drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <linux/clk.h>
  33 #include <linux/component.h>
  34 #include <linux/of_device.h>
  35
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_fb_cma_helper.h>
  40 #include <drm/drm_print.h>
  41 #include <drm/drm_probe_helper.h>
  42 #include <drm/drm_vblank.h>
  43
  44 #include "vc4_drv.h"
  45 #include "vc4_regs.h"
  46
  47 struct vc4_crtc_state {
  48         struct drm_crtc_state base;
  49         /* Dlist area for this CRTC configuration. */
  50         struct drm_mm_node mm;
  51         bool feed_txp;
  52         bool txp_armed;
  53
  54         struct {
  55                 unsigned int left;
  56                 unsigned int right;
  57                 unsigned int top;
  58                 unsigned int bottom;
  59         } margins;
  60 };
  61
  62 static inline struct vc4_crtc_state *
  63 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
  64 {
  65         return (struct vc4_crtc_state *)crtc_state;
  66 }
  67
  68 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  69 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  70
  71 static const struct debugfs_reg32 crtc_regs[] = {
  72         VC4_REG32(PV_CONTROL),
  73         VC4_REG32(PV_V_CONTROL),
  74         VC4_REG32(PV_VSYNCD_EVEN),
  75         VC4_REG32(PV_HORZA),
  76         VC4_REG32(PV_HORZB),
  77         VC4_REG32(PV_VERTA),
  78         VC4_REG32(PV_VERTB),
  79         VC4_REG32(PV_VERTA_EVEN),
  80         VC4_REG32(PV_VERTB_EVEN),
  81         VC4_REG32(PV_INTEN),
  82         VC4_REG32(PV_INTSTAT),
  83         VC4_REG32(PV_STAT),
  84         VC4_REG32(PV_HACT_ACT),
  85 };
  86
  87 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
  88                                           bool in_vblank_irq,
  89                                           int *vpos, int *hpos,
  90                                           ktime_t *stime, ktime_t *etime,
  91                                           const struct drm_display_mode *mode)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct vc4_dev *vc4 = to_vc4_dev(dev);
  95         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  96         u32 val;
  97         int fifo_lines;
  98         int vblank_lines;
  99         bool ret = false;
 100
 101         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 102
 103         /* Get optional system timestamp before query. */
 104         if (stime)
 105                 *stime = ktime_get();
 106
 107         /*
 108          * Read vertical scanline which is currently composed for our
 109          * pixelvalve by the HVS, and also the scaler status.
 110          */
 111         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
 112
 113         /* Get optional system timestamp after query. */
 114         if (etime)
 115                 *etime = ktime_get();
 116
 117         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 118
 119         /* Vertical position of hvs composed scanline. */
 120         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 121         *hpos = 0;
 122
 123         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 124                 *vpos /= 2;
 125
 126                 /* Use hpos to correct for field offset in interlaced mode. */
 127                 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
 128                         *hpos += mode->crtc_htotal / 2;
 129         }
 130
 131         /* This is the offset we need for translating hvs -> pv scanout pos. */
 132         fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
 133
 134         if (fifo_lines > 0)
 135                 ret = true;
 136
 137         /* HVS more than fifo_lines into frame for compositing? */
 138         if (*vpos > fifo_lines) {
 139                 /*
 140                  * We are in active scanout and can get some meaningful results
 141                  * from HVS. The actual PV scanout can not trail behind more
 142                  * than fifo_lines as that is the fifo's capacity. Assume that
 143                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 144                  * refilling the fifo and PV consuming from the fifo, ie.
 145                  * whenever the PV consumes and frees up a scanline in the
 146                  * fifo, the HVS will immediately refill it, therefore
 147                  * incrementing vpos. Therefore we choose HVS read position -
 148                  * fifo size in scanlines as a estimate of the real scanout
 149                  * position of the PV.
 150                  */
 151                 *vpos -= fifo_lines + 1;
 152
 153                 return ret;
 154         }
 155
 156         /*
 157          * Less: This happens when we are in vblank and the HVS, after getting
 158          * the VSTART restart signal from the PV, just started refilling its
 159          * fifo with new lines from the top-most lines of the new framebuffers.
 160          * The PV does not scan out in vblank, so does not remove lines from
 161          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 162          * We can't get meaningful readings wrt. scanline position of the PV
 163          * and need to make things up in a approximative but consistent way.
 164          */
 165         vblank_lines = mode->vtotal - mode->vdisplay;
 166
 167         if (in_vblank_irq) {
 168                 /*
 169                  * Assume the irq handler got called close to first
 170                  * line of vblank, so PV has about a full vblank
 171                  * scanlines to go, and as a base timestamp use the
 172                  * one taken at entry into vblank irq handler, so it
 173                  * is not affected by random delays due to lock
 174                  * contention on event_lock or vblank_time lock in
 175                  * the core.
 176                  */
 177                 *vpos = -vblank_lines;
 178
 179                 if (stime)
 180                         *stime = vc4_crtc->t_vblank;
 181                 if (etime)
 182                         *etime = vc4_crtc->t_vblank;
 183
 184                 /*
 185                  * If the HVS fifo is not yet full then we know for certain
 186                  * we are at the very beginning of vblank, as the hvs just
 187                  * started refilling, and the stime and etime timestamps
 188                  * truly correspond to start of vblank.
 189                  *
 190                  * Unfortunately there's no way to report this to upper levels
 191                  * and make it more useful.
 192                  */
 193         } else {
 194                 /*
 195                  * No clue where we are inside vblank. Return a vpos of zero,
 196                  * which will cause calling code to just return the etime
 197                  * timestamp uncorrected. At least this is no worse than the
 198                  * standard fallback.
 199                  */
 200                 *vpos = 0;
 201         }
 202
 203         return ret;
 204 }
 205
 206 static void vc4_crtc_destroy(struct drm_crtc *crtc)
 207 {
 208         drm_crtc_cleanup(crtc);
 209 }
 210
 211 static void
 212 vc4_crtc_lut_load(struct drm_crtc *crtc)
 213 {
 214         struct drm_device *dev = crtc->dev;
 215         struct vc4_dev *vc4 = to_vc4_dev(dev);
 216         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 217         u32 i;
 218
 219         /* The LUT memory is laid out with each HVS channel in order,
 220          * each of which takes 256 writes for R, 256 for G, then 256
 221          * for B.
 222          */
 223         HVS_WRITE(SCALER_GAMADDR,
 224                   SCALER_GAMADDR_AUTOINC |
 225                   (vc4_crtc->channel * 3 * crtc->gamma_size));
 226
 227         for (i = 0; i < crtc->gamma_size; i++)
 228                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
 229         for (i = 0; i < crtc->gamma_size; i++)
 230                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
 231         for (i = 0; i < crtc->gamma_size; i++)
 232                 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
 233 }
 234
 235 static void
 236 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc)
 237 {
 238         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 239         struct drm_color_lut *lut = crtc->state->gamma_lut->data;
 240         u32 length = drm_color_lut_size(crtc->state->gamma_lut);
 241         u32 i;
 242
 243         for (i = 0; i < length; i++) {
 244                 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8);
 245                 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8);
 246                 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8);
 247         }
 248
 249         vc4_crtc_lut_load(crtc);
 250 }
 251
 252 static u32 vc4_get_fifo_full_level(u32 format)
 253 {
 254         static const u32 fifo_len_bytes = 64;
 255         static const u32 hvs_latency_pix = 6;
 256
 257         switch (format) {
 258         case PV_CONTROL_FORMAT_DSIV_16:
 259         case PV_CONTROL_FORMAT_DSIC_16:
 260                 return fifo_len_bytes - 2 * hvs_latency_pix;
 261         case PV_CONTROL_FORMAT_DSIV_18:
 262                 return fifo_len_bytes - 14;
 263         case PV_CONTROL_FORMAT_24:
 264         case PV_CONTROL_FORMAT_DSIV_24:
 265         default:
 266                 return fifo_len_bytes - 3 * hvs_latency_pix;
 267         }
 268 }
 269
 270 /*
 271  * Returns the encoder attached to the CRTC.
 272  *
 273  * VC4 can only scan out to one encoder at a time, while the DRM core
 274  * allows drivers to push pixels to more than one encoder from the
 275  * same CRTC.
 276  */
 277 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
 278 {
 279         struct drm_connector *connector;
 280         struct drm_connector_list_iter conn_iter;
 281
 282         drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 283         drm_for_each_connector_iter(connector, &conn_iter) {
 284                 if (connector->state->crtc == crtc) {
 285                         drm_connector_list_iter_end(&conn_iter);
 286                         return connector->encoder;
 287                 }
 288         }
 289         drm_connector_list_iter_end(&conn_iter);
 290
 291         return NULL;
 292 }
 293
 294 static void vc4_crtc_config_pv(struct drm_crtc *crtc)
 295 {
 296         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
 297         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 298         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 299         struct drm_crtc_state *state = crtc->state;
 300         struct drm_display_mode *mode = &state->adjusted_mode;
 301         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 302         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 303         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 304                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 305         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 306
 307         /* Reset the PV fifo. */
 308         CRTC_WRITE(PV_CONTROL, 0);
 309         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
 310         CRTC_WRITE(PV_CONTROL, 0);
 311
 312         CRTC_WRITE(PV_HORZA,
 313                    VC4_SET_FIELD((mode->htotal -
 314                                   mode->hsync_end) * pixel_rep,
 315                                  PV_HORZA_HBP) |
 316                    VC4_SET_FIELD((mode->hsync_end -
 317                                   mode->hsync_start) * pixel_rep,
 318                                  PV_HORZA_HSYNC));
 319         CRTC_WRITE(PV_HORZB,
 320                    VC4_SET_FIELD((mode->hsync_start -
 321                                   mode->hdisplay) * pixel_rep,
 322                                  PV_HORZB_HFP) |
 323                    VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
 324
 325         CRTC_WRITE(PV_VERTA,
 326                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 327                                  PV_VERTA_VBP) |
 328                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 329                                  PV_VERTA_VSYNC));
 330         CRTC_WRITE(PV_VERTB,
 331                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 332                                  PV_VERTB_VFP) |
 333                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 334
 335         if (interlace) {
 336                 CRTC_WRITE(PV_VERTA_EVEN,
 337                            VC4_SET_FIELD(mode->crtc_vtotal -
 338                                          mode->crtc_vsync_end - 1,
 339                                          PV_VERTA_VBP) |
 340                            VC4_SET_FIELD(mode->crtc_vsync_end -
 341                                          mode->crtc_vsync_start,
 342                                          PV_VERTA_VSYNC));
 343                 CRTC_WRITE(PV_VERTB_EVEN,
 344                            VC4_SET_FIELD(mode->crtc_vsync_start -
 345                                          mode->crtc_vdisplay,
 346                                          PV_VERTB_VFP) |
 347                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 348
 349                 /* We set up first field even mode for HDMI.  VEC's
 350                  * NTSC mode would want first field odd instead, once
 351                  * we support it (to do so, set ODD_FIRST and put the
 352                  * delay in VSYNCD_EVEN instead).
 353                  */
 354                 CRTC_WRITE(PV_V_CONTROL,
 355                            PV_VCONTROL_CONTINUOUS |
 356                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 357                            PV_VCONTROL_INTERLACE |
 358                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 359                                          PV_VCONTROL_ODD_DELAY));
 360                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 361         } else {
 362                 CRTC_WRITE(PV_V_CONTROL,
 363                            PV_VCONTROL_CONTINUOUS |
 364                            (is_dsi ? PV_VCONTROL_DSI : 0));
 365         }
 366
 367         CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 368
 369         CRTC_WRITE(PV_CONTROL,
 370                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 371                    VC4_SET_FIELD(vc4_get_fifo_full_level(format),
 372                                  PV_CONTROL_FIFO_LEVEL) |
 373                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 374                    PV_CONTROL_CLR_AT_START |
 375                    PV_CONTROL_TRIGGER_UNDERFLOW |
 376                    PV_CONTROL_WAIT_HSTART |
 377                    VC4_SET_FIELD(vc4_encoder->clock_select,
 378                                  PV_CONTROL_CLK_SELECT) |
 379                    PV_CONTROL_FIFO_CLR |
 380                    PV_CONTROL_EN);
 381 }
 382
 383 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
 384 {
 385         struct drm_device *dev = crtc->dev;
 386         struct vc4_dev *vc4 = to_vc4_dev(dev);
 387         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 388         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 389         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 390         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 391         bool debug_dump_regs = false;
 392
 393         if (debug_dump_regs) {
 394                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 395                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 396                          drm_crtc_index(crtc));
 397                 drm_print_regset32(&p, &vc4_crtc->regset);
 398         }
 399
 400         if (vc4_crtc->channel == 2) {
 401                 u32 dispctrl;
 402                 u32 dsp3_mux;
 403
 404                 /*
 405                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 406                  * FIFO X'.
 407                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 408                  *
 409                  * DSP3 is connected to FIFO2 unless the transposer is
 410                  * enabled. In this case, FIFO 2 is directly accessed by the
 411                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 412                  * route.
 413                  */
 414                 if (vc4_state->feed_txp)
 415                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 416                 else
 417                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 418
 419                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 420                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 421                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 422         }
 423
 424         if (!vc4_state->feed_txp)
 425                 vc4_crtc_config_pv(crtc);
 426
 427         HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 428                   SCALER_DISPBKGND_AUTOHS |
 429                   SCALER_DISPBKGND_GAMMA |
 430                   (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
 431
 432         /* Reload the LUT, since the SRAMs would have been disabled if
 433          * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
 434          */
 435         vc4_crtc_lut_load(crtc);
 436
 437         if (debug_dump_regs) {
 438                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 439                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 440                          drm_crtc_index(crtc));
 441                 drm_print_regset32(&p, &vc4_crtc->regset);
 442         }
 443 }
 444
 445 static void require_hvs_enabled(struct drm_device *dev)
 446 {
 447         struct vc4_dev *vc4 = to_vc4_dev(dev);
 448
 449         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 450                      SCALER_DISPCTRL_ENABLE);
 451 }
 452
 453 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 454                                     struct drm_crtc_state *old_state)
 455 {
 456         struct drm_device *dev = crtc->dev;
 457         struct vc4_dev *vc4 = to_vc4_dev(dev);
 458         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 459         u32 chan = vc4_crtc->channel;
 460         int ret;
 461         require_hvs_enabled(dev);
 462
 463         /* Disable vblank irq handling before crtc is disabled. */
 464         drm_crtc_vblank_off(crtc);
 465
 466         CRTC_WRITE(PV_V_CONTROL,
 467                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 468         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 469         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 470
 471         if (HVS_READ(SCALER_DISPCTRLX(chan)) &
 472             SCALER_DISPCTRLX_ENABLE) {
 473                 HVS_WRITE(SCALER_DISPCTRLX(chan),
 474                           SCALER_DISPCTRLX_RESET);
 475
 476                 /* While the docs say that reset is self-clearing, it
 477                  * seems it doesn't actually.
 478                  */
 479                 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
 480         }
 481
 482         /* Once we leave, the scaler should be disabled and its fifo empty. */
 483
 484         WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
 485
 486         WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
 487                                    SCALER_DISPSTATX_MODE) !=
 488                      SCALER_DISPSTATX_MODE_DISABLED);
 489
 490         WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
 491                       (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
 492                      SCALER_DISPSTATX_EMPTY);
 493
 494         /*
 495          * Make sure we issue a vblank event after disabling the CRTC if
 496          * someone was waiting it.
 497          */
 498         if (crtc->state->event) {
 499                 unsigned long flags;
 500
 501                 spin_lock_irqsave(&dev->event_lock, flags);
 502                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 503                 crtc->state->event = NULL;
 504                 spin_unlock_irqrestore(&dev->event_lock, flags);
 505         }
 506 }
 507
 508 void vc4_crtc_txp_armed(struct drm_crtc_state *state)
 509 {
 510         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 511
 512         vc4_state->txp_armed = true;
 513 }
 514
 515 static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
 516 {
 517         struct drm_device *dev = crtc->dev;
 518         struct vc4_dev *vc4 = to_vc4_dev(dev);
 519         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 520         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 521
 522         if (crtc->state->event) {
 523                 unsigned long flags;
 524
 525                 crtc->state->event->pipe = drm_crtc_index(crtc);
 526
 527                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 528
 529                 spin_lock_irqsave(&dev->event_lock, flags);
 530
 531                 if (!vc4_state->feed_txp || vc4_state->txp_armed) {
 532                         vc4_crtc->event = crtc->state->event;
 533                         crtc->state->event = NULL;
 534                 }
 535
 536                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 537                           vc4_state->mm.start);
 538
 539                 spin_unlock_irqrestore(&dev->event_lock, flags);
 540         } else {
 541                 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
 542                           vc4_state->mm.start);
 543         }
 544 }
 545
 546 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 547                                    struct drm_crtc_state *old_state)
 548 {
 549         struct drm_device *dev = crtc->dev;
 550         struct vc4_dev *vc4 = to_vc4_dev(dev);
 551         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 552         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 553         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 554
 555         require_hvs_enabled(dev);
 556
 557         /* Enable vblank irq handling before crtc is started otherwise
 558          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 559          */
 560         drm_crtc_vblank_on(crtc);
 561         vc4_crtc_update_dlist(crtc);
 562
 563         /* Turn on the scaler, which will wait for vstart to start
 564          * compositing.
 565          * When feeding the transposer, we should operate in oneshot
 566          * mode.
 567          */
 568         HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
 569                   VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
 570                   VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
 571                   SCALER_DISPCTRLX_ENABLE |
 572                   (vc4_state->feed_txp ? SCALER_DISPCTRLX_ONESHOT : 0));
 573
 574         /* When feeding the transposer block the pixelvalve is unneeded and
 575          * should not be enabled.
 576          */
 577         if (!vc4_state->feed_txp)
 578                 CRTC_WRITE(PV_V_CONTROL,
 579                            CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 580 }
 581
 582 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 583                                                 const struct drm_display_mode *mode)
 584 {
 585         /* Do not allow doublescan modes from user space */
 586         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 587                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 588                               crtc->base.id);
 589                 return MODE_NO_DBLESCAN;
 590         }
 591
 592         return MODE_OK;
 593 }
 594
 595 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 596                           unsigned int *left, unsigned int *right,
 597                           unsigned int *top, unsigned int *bottom)
 598 {
 599         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 600         struct drm_connector_state *conn_state;
 601         struct drm_connector *conn;
 602         int i;
 603
 604         *left = vc4_state->margins.left;
 605         *right = vc4_state->margins.right;
 606         *top = vc4_state->margins.top;
 607         *bottom = vc4_state->margins.bottom;
 608
 609         /* We have to interate over all new connector states because
 610          * vc4_crtc_get_margins() might be called before
 611          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 612          * might be outdated.
 613          */
 614         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 615                 if (conn_state->crtc != state->crtc)
 616                         continue;
 617
 618                 *left = conn_state->tv.margins.left;
 619                 *right = conn_state->tv.margins.right;
 620                 *top = conn_state->tv.margins.top;
 621                 *bottom = conn_state->tv.margins.bottom;
 622                 break;
 623         }
 624 }
 625
 626 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 627                                  struct drm_crtc_state *state)
 628 {
 629         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 630         struct drm_device *dev = crtc->dev;
 631         struct vc4_dev *vc4 = to_vc4_dev(dev);
 632         struct drm_plane *plane;
 633         unsigned long flags;
 634         const struct drm_plane_state *plane_state;
 635         struct drm_connector *conn;
 636         struct drm_connector_state *conn_state;
 637         u32 dlist_count = 0;
 638         int ret, i;
 639
 640         /* The pixelvalve can only feed one encoder (and encoders are
 641          * 1:1 with connectors.)
 642          */
 643         if (hweight32(state->connector_mask) > 1)
 644                 return -EINVAL;
 645
 646         drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
 647                 dlist_count += vc4_plane_dlist_size(plane_state);
 648
 649         dlist_count++; /* Account for SCALER_CTL0_END. */
 650
 651         spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
 652         ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
 653                                  dlist_count);
 654         spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
 655         if (ret)
 656                 return ret;
 657
 658         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 659                 if (conn_state->crtc != crtc)
 660                         continue;
 661
 662                 /* The writeback connector is implemented using the transposer
 663                  * block which is directly taking its data from the HVS FIFO.
 664                  */
 665                 if (conn->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) {
 666                         state->no_vblank = true;
 667                         vc4_state->feed_txp = true;
 668                 } else {
 669                         state->no_vblank = false;
 670                         vc4_state->feed_txp = false;
 671                 }
 672
 673                 vc4_state->margins.left = conn_state->tv.margins.left;
 674                 vc4_state->margins.right = conn_state->tv.margins.right;
 675                 vc4_state->margins.top = conn_state->tv.margins.top;
 676                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 677                 break;
 678         }
 679
 680         return 0;
 681 }
 682
 683 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
 684                                   struct drm_crtc_state *old_state)
 685 {
 686         struct drm_device *dev = crtc->dev;
 687         struct vc4_dev *vc4 = to_vc4_dev(dev);
 688         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 689         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 690         struct drm_plane *plane;
 691         struct vc4_plane_state *vc4_plane_state;
 692         bool debug_dump_regs = false;
 693         bool enable_bg_fill = false;
 694         u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
 695         u32 __iomem *dlist_next = dlist_start;
 696
 697         if (debug_dump_regs) {
 698                 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
 699                 vc4_hvs_dump_state(dev);
 700         }
 701
 702         /* Copy all the active planes' dlist contents to the hardware dlist. */
 703         drm_atomic_crtc_for_each_plane(plane, crtc) {
 704                 /* Is this the first active plane? */
 705                 if (dlist_next == dlist_start) {
 706                         /* We need to enable background fill when a plane
 707                          * could be alpha blending from the background, i.e.
 708                          * where no other plane is underneath. It suffices to
 709                          * consider the first active plane here since we set
 710                          * needs_bg_fill such that either the first plane
 711                          * already needs it or all planes on top blend from
 712                          * the first or a lower plane.
 713                          */
 714                         vc4_plane_state = to_vc4_plane_state(plane->state);
 715                         enable_bg_fill = vc4_plane_state->needs_bg_fill;
 716                 }
 717
 718                 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
 719         }
 720
 721         writel(SCALER_CTL0_END, dlist_next);
 722         dlist_next++;
 723
 724         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
 725
 726         if (enable_bg_fill)
 727                 /* This sets a black background color fill, as is the case
 728                  * with other DRM drivers.
 729                  */
 730                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
 731                           HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
 732                           SCALER_DISPBKGND_FILL);
 733
 734         /* Only update DISPLIST if the CRTC was already running and is not
 735          * being disabled.
 736          * vc4_crtc_enable() takes care of updating the dlist just after
 737          * re-enabling VBLANK interrupts and before enabling the engine.
 738          * If the CRTC is being disabled, there's no point in updating this
 739          * information.
 740          */
 741         if (crtc->state->active && old_state->active)
 742                 vc4_crtc_update_dlist(crtc);
 743
 744         if (crtc->state->color_mgmt_changed) {
 745                 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel));
 746
 747                 if (crtc->state->gamma_lut) {
 748                         vc4_crtc_update_gamma_lut(crtc);
 749                         dispbkgndx |= SCALER_DISPBKGND_GAMMA;
 750                 } else {
 751                         /* Unsetting DISPBKGND_GAMMA skips the gamma lut step
 752                          * in hardware, which is the same as a linear lut that
 753                          * DRM expects us to use in absence of a user lut.
 754                          */
 755                         dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
 756                 }
 757                 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx);
 758         }
 759
 760         if (debug_dump_regs) {
 761                 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
 762                 vc4_hvs_dump_state(dev);
 763         }
 764 }
 765
 766 static int vc4_enable_vblank(struct drm_crtc *crtc)
 767 {
 768         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 769
 770         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 771
 772         return 0;
 773 }
 774
 775 static void vc4_disable_vblank(struct drm_crtc *crtc)
 776 {
 777         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 778
 779         CRTC_WRITE(PV_INTEN, 0);
 780 }
 781
 782 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 783 {
 784         struct drm_crtc *crtc = &vc4_crtc->base;
 785         struct drm_device *dev = crtc->dev;
 786         struct vc4_dev *vc4 = to_vc4_dev(dev);
 787         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 788         u32 chan = vc4_crtc->channel;
 789         unsigned long flags;
 790
 791         spin_lock_irqsave(&dev->event_lock, flags);
 792         if (vc4_crtc->event &&
 793             (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) ||
 794              vc4_state->feed_txp)) {
 795                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 796                 vc4_crtc->event = NULL;
 797                 drm_crtc_vblank_put(crtc);
 798
 799                 /* Wait for the page flip to unmask the underrun to ensure that
 800                  * the display list was updated by the hardware. Before that
 801                  * happens, the HVS will be using the previous display list with
 802                  * the CRTC and encoder already reconfigured, leading to
 803                  * underruns. This can be seen when reconfiguring the CRTC.
 804                  */
 805                 vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);
 806         }
 807         spin_unlock_irqrestore(&dev->event_lock, flags);
 808 }
 809
 810 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 811 {
 812         crtc->t_vblank = ktime_get();
 813         drm_crtc_handle_vblank(&crtc->base);
 814         vc4_crtc_handle_page_flip(crtc);
 815 }
 816
 817 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 818 {
 819         struct vc4_crtc *vc4_crtc = data;
 820         u32 stat = CRTC_READ(PV_INTSTAT);
 821         irqreturn_t ret = IRQ_NONE;
 822
 823         if (stat & PV_INT_VFP_START) {
 824                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 825                 vc4_crtc_handle_vblank(vc4_crtc);
 826                 ret = IRQ_HANDLED;
 827         }
 828
 829         return ret;
 830 }
 831
 832 struct vc4_async_flip_state {
 833         struct drm_crtc *crtc;
 834         struct drm_framebuffer *fb;
 835         struct drm_framebuffer *old_fb;
 836         struct drm_pending_vblank_event *event;
 837
 838         struct vc4_seqno_cb cb;
 839 };
 840
 841 /* Called when the V3D execution for the BO being flipped to is done, so that
 842  * we can actually update the plane's address to point to it.
 843  */
 844 static void
 845 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
 846 {
 847         struct vc4_async_flip_state *flip_state =
 848                 container_of(cb, struct vc4_async_flip_state, cb);
 849         struct drm_crtc *crtc = flip_state->crtc;
 850         struct drm_device *dev = crtc->dev;
 851         struct vc4_dev *vc4 = to_vc4_dev(dev);
 852         struct drm_plane *plane = crtc->primary;
 853
 854         vc4_plane_async_set_fb(plane, flip_state->fb);
 855         if (flip_state->event) {
 856                 unsigned long flags;
 857
 858                 spin_lock_irqsave(&dev->event_lock, flags);
 859                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 860                 spin_unlock_irqrestore(&dev->event_lock, flags);
 861         }
 862
 863         drm_crtc_vblank_put(crtc);
 864         drm_framebuffer_put(flip_state->fb);
 865
 866         /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
 867          * when the planes are updated through the async update path.
 868          * FIXME: we should move to generic async-page-flip when it's
 869          * available, so that we can get rid of this hand-made cleanup_fb()
 870          * logic.
 871          */
 872         if (flip_state->old_fb) {
 873                 struct drm_gem_cma_object *cma_bo;
 874                 struct vc4_bo *bo;
 875
 876                 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 877                 bo = to_vc4_bo(&cma_bo->base);
 878                 vc4_bo_dec_usecnt(bo);
 879                 drm_framebuffer_put(flip_state->old_fb);
 880         }
 881
 882         kfree(flip_state);
 883
 884         up(&vc4->async_modeset);
 885 }
 886
 887 /* Implements async (non-vblank-synced) page flips.
 888  *
 889  * The page flip ioctl needs to return immediately, so we grab the
 890  * modeset semaphore on the pipe, and queue the address update for
 891  * when V3D is done with the BO being flipped to.
 892  */
 893 static int vc4_async_page_flip(struct drm_crtc *crtc,
 894                                struct drm_framebuffer *fb,
 895                                struct drm_pending_vblank_event *event,
 896                                uint32_t flags)
 897 {
 898         struct drm_device *dev = crtc->dev;
 899         struct vc4_dev *vc4 = to_vc4_dev(dev);
 900         struct drm_plane *plane = crtc->primary;
 901         int ret = 0;
 902         struct vc4_async_flip_state *flip_state;
 903         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 904         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 905
 906         /* Increment the BO usecnt here, so that we never end up with an
 907          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 908          * plane is later updated through the non-async path.
 909          * FIXME: we should move to generic async-page-flip when it's
 910          * available, so that we can get rid of this hand-made prepare_fb()
 911          * logic.
 912          */
 913         ret = vc4_bo_inc_usecnt(bo);
 914         if (ret)
 915                 return ret;
 916
 917         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 918         if (!flip_state) {
 919                 vc4_bo_dec_usecnt(bo);
 920                 return -ENOMEM;
 921         }
 922
 923         drm_framebuffer_get(fb);
 924         flip_state->fb = fb;
 925         flip_state->crtc = crtc;
 926         flip_state->event = event;
 927
 928         /* Make sure all other async modesetes have landed. */
 929         ret = down_interruptible(&vc4->async_modeset);
 930         if (ret) {
 931                 drm_framebuffer_put(fb);
 932                 vc4_bo_dec_usecnt(bo);
 933                 kfree(flip_state);
 934                 return ret;
 935         }
 936
 937         /* Save the current FB before it's replaced by the new one in
 938          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 939          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 940          * it consistent.
 941          * FIXME: we should move to generic async-page-flip when it's
 942          * available, so that we can get rid of this hand-made cleanup_fb()
 943          * logic.
 944          */
 945         flip_state->old_fb = plane->state->fb;
 946         if (flip_state->old_fb)
 947                 drm_framebuffer_get(flip_state->old_fb);
 948
 949         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 950
 951         /* Immediately update the plane's legacy fb pointer, so that later
 952          * modeset prep sees the state that will be present when the semaphore
 953          * is released.
 954          */
 955         drm_atomic_set_fb_for_plane(plane->state, fb);
 956
 957         vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
 958                            vc4_async_page_flip_complete);
 959
 960         /* Driver takes ownership of state on successful async commit. */
 961         return 0;
 962 }
 963
 964 static int vc4_page_flip(struct drm_crtc *crtc,
 965                          struct drm_framebuffer *fb,
 966                          struct drm_pending_vblank_event *event,
 967                          uint32_t flags,
 968                          struct drm_modeset_acquire_ctx *ctx)
 969 {
 970         if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
 971                 return vc4_async_page_flip(crtc, fb, event, flags);
 972         else
 973                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 974 }
 975
 976 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 977 {
 978         struct vc4_crtc_state *vc4_state, *old_vc4_state;
 979
 980         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 981         if (!vc4_state)
 982                 return NULL;
 983
 984         old_vc4_state = to_vc4_crtc_state(crtc->state);
 985         vc4_state->feed_txp = old_vc4_state->feed_txp;
 986         vc4_state->margins = old_vc4_state->margins;
 987
 988         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
 989         return &vc4_state->base;
 990 }
 991
 992 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
 993                                    struct drm_crtc_state *state)
 994 {
 995         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
 996         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 997
 998         if (drm_mm_node_allocated(&vc4_state->mm)) {
 999                 unsigned long flags;
1000
1001                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1002                 drm_mm_remove_node(&vc4_state->mm);
1003                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1004
1005         }
1006
1007         drm_atomic_helper_crtc_destroy_state(crtc, state);
1008 }
1009
1010 static void
1011 vc4_crtc_reset(struct drm_crtc *crtc)
1012 {
1013         if (crtc->state)
1014                 vc4_crtc_destroy_state(crtc, crtc->state);
1015
1016         crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
1017         if (crtc->state)
1018                 crtc->state->crtc = crtc;
1019 }
1020
1021 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1022         .set_config = drm_atomic_helper_set_config,
1023         .destroy = vc4_crtc_destroy,
1024         .page_flip = vc4_page_flip,
1025         .set_property = NULL,
1026         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1027         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1028         .reset = vc4_crtc_reset,
1029         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1030         .atomic_destroy_state = vc4_crtc_destroy_state,
1031         .gamma_set = drm_atomic_helper_legacy_gamma_set,
1032         .enable_vblank = vc4_enable_vblank,
1033         .disable_vblank = vc4_disable_vblank,
1034         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1035 };
1036
1037 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1038         .mode_set_nofb = vc4_crtc_mode_set_nofb,
1039         .mode_valid = vc4_crtc_mode_valid,
1040         .atomic_check = vc4_crtc_atomic_check,
1041         .atomic_flush = vc4_crtc_atomic_flush,
1042         .atomic_enable = vc4_crtc_atomic_enable,
1043         .atomic_disable = vc4_crtc_atomic_disable,
1044         .get_scanout_position = vc4_crtc_get_scanout_position,
1045 };
1046
1047 static const struct vc4_crtc_data pv0_data = {
1048         .hvs_channel = 0,
1049         .debugfs_name = "crtc0_regs",
1050         .encoder_types = {
1051                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1052                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1053         },
1054 };
1055
1056 static const struct vc4_crtc_data pv1_data = {
1057         .hvs_channel = 2,
1058         .debugfs_name = "crtc1_regs",
1059         .encoder_types = {
1060                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1061                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1062         },
1063 };
1064
1065 static const struct vc4_crtc_data pv2_data = {
1066         .hvs_channel = 1,
1067         .debugfs_name = "crtc2_regs",
1068         .encoder_types = {
1069                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
1070                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1071         },
1072 };
1073
1074 static const struct of_device_id vc4_crtc_dt_match[] = {
1075         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
1076         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
1077         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
1078         {}
1079 };
1080
1081 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1082                                         struct drm_crtc *crtc)
1083 {
1084         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1085         const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1086         const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1087         struct drm_encoder *encoder;
1088
1089         drm_for_each_encoder(encoder, drm) {
1090                 struct vc4_encoder *vc4_encoder;
1091                 int i;
1092
1093                 /* HVS FIFO2 can feed the TXP IP. */
1094                 if (crtc_data->hvs_channel == 2 &&
1095                     encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
1096                         encoder->possible_crtcs |= drm_crtc_mask(crtc);
1097                         continue;
1098                 }
1099
1100                 vc4_encoder = to_vc4_encoder(encoder);
1101                 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1102                         if (vc4_encoder->type == encoder_types[i]) {
1103                                 vc4_encoder->clock_select = i;
1104                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1105                                 break;
1106                         }
1107                 }
1108         }
1109 }
1110
1111 static void
1112 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1113 {
1114         struct drm_device *drm = vc4_crtc->base.dev;
1115         struct vc4_dev *vc4 = to_vc4_dev(drm);
1116         u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1117         /* Top/base are supposed to be 4-pixel aligned, but the
1118          * Raspberry Pi firmware fills the low bits (which are
1119          * presumably ignored).
1120          */
1121         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1122         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1123
1124         vc4_crtc->cob_size = top - base + 4;
1125 }
1126
1127 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1128 {
1129         struct platform_device *pdev = to_platform_device(dev);
1130         struct drm_device *drm = dev_get_drvdata(master);
1131         struct vc4_crtc *vc4_crtc;
1132         struct drm_crtc *crtc;
1133         struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1134         const struct of_device_id *match;
1135         int ret, i;
1136
1137         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1138         if (!vc4_crtc)
1139                 return -ENOMEM;
1140         crtc = &vc4_crtc->base;
1141
1142         match = of_match_device(vc4_crtc_dt_match, dev);
1143         if (!match)
1144                 return -ENODEV;
1145         vc4_crtc->data = match->data;
1146         vc4_crtc->pdev = pdev;
1147
1148         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1149         if (IS_ERR(vc4_crtc->regs))
1150                 return PTR_ERR(vc4_crtc->regs);
1151
1152         vc4_crtc->regset.base = vc4_crtc->regs;
1153         vc4_crtc->regset.regs = crtc_regs;
1154         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1155
1156         /* For now, we create just the primary and the legacy cursor
1157          * planes.  We should be able to stack more planes on easily,
1158          * but to do that we would need to compute the bandwidth
1159          * requirement of the plane configuration, and reject ones
1160          * that will take too much.
1161          */
1162         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1163         if (IS_ERR(primary_plane)) {
1164                 dev_err(dev, "failed to construct primary plane\n");
1165                 ret = PTR_ERR(primary_plane);
1166                 goto err;
1167         }
1168
1169         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1170                                   &vc4_crtc_funcs, NULL);
1171         drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1172         vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1173         drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1174         drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1175
1176         /* We support CTM, but only for one CRTC at a time. It's therefore
1177          * implemented as private driver state in vc4_kms, not here.
1178          */
1179         drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1180
1181         /* Set up some arbitrary number of planes.  We're not limited
1182          * by a set number of physical registers, just the space in
1183          * the HVS (16k) and how small an plane can be (28 bytes).
1184          * However, each plane we set up takes up some memory, and
1185          * increases the cost of looping over planes, which atomic
1186          * modesetting does quite a bit.  As a result, we pick a
1187          * modest number of planes to expose, that should hopefully
1188          * still cover any sane usecase.
1189          */
1190         for (i = 0; i < 8; i++) {
1191                 struct drm_plane *plane =
1192                         vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1193
1194                 if (IS_ERR(plane))
1195                         continue;
1196
1197                 plane->possible_crtcs = drm_crtc_mask(crtc);
1198         }
1199
1200         /* Set up the legacy cursor after overlay initialization,
1201          * since we overlay planes on the CRTC in the order they were
1202          * initialized.
1203          */
1204         cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1205         if (!IS_ERR(cursor_plane)) {
1206                 cursor_plane->possible_crtcs = drm_crtc_mask(crtc);
1207                 crtc->cursor = cursor_plane;
1208         }
1209
1210         vc4_crtc_get_cob_allocation(vc4_crtc);
1211
1212         CRTC_WRITE(PV_INTEN, 0);
1213         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1214         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1215                                vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1216         if (ret)
1217                 goto err_destroy_planes;
1218
1219         vc4_set_crtc_possible_masks(drm, crtc);
1220
1221         for (i = 0; i < crtc->gamma_size; i++) {
1222                 vc4_crtc->lut_r[i] = i;
1223                 vc4_crtc->lut_g[i] = i;
1224                 vc4_crtc->lut_b[i] = i;
1225         }
1226
1227         platform_set_drvdata(pdev, vc4_crtc);
1228
1229         vc4_debugfs_add_regset32(drm, vc4_crtc->data->debugfs_name,
1230                                  &vc4_crtc->regset);
1231
1232         return 0;
1233
1234 err_destroy_planes:
1235         list_for_each_entry_safe(destroy_plane, temp,
1236                                  &drm->mode_config.plane_list, head) {
1237                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1238                     destroy_plane->funcs->destroy(destroy_plane);
1239         }
1240 err:
1241         return ret;
1242 }
1243
1244 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1245                             void *data)
1246 {
1247         struct platform_device *pdev = to_platform_device(dev);
1248         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1249
1250         vc4_crtc_destroy(&vc4_crtc->base);
1251
1252         CRTC_WRITE(PV_INTEN, 0);
1253
1254         platform_set_drvdata(pdev, NULL);
1255 }
1256
1257 static const struct component_ops vc4_crtc_ops = {
1258         .bind   = vc4_crtc_bind,
1259         .unbind = vc4_crtc_unbind,
1260 };
1261
1262 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1263 {
1264         return component_add(&pdev->dev, &vc4_crtc_ops);
1265 }
1266
1267 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1268 {
1269         component_del(&pdev->dev, &vc4_crtc_ops);
1270         return 0;
1271 }
1272
1273 struct platform_driver vc4_crtc_driver = {
1274         .probe = vc4_crtc_dev_probe,
1275         .remove = vc4_crtc_dev_remove,
1276         .driver = {
1277                 .name = "vc4_crtc",
1278                 .of_match_table = vc4_crtc_dt_match,
1279         },
1280 };