drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/debugfs.h>
  25 #include <linux/list.h>
  26 #include <linux/module.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/reboot.h>
  29 #include <linux/syscalls.h>
  30
  31 #include "amdgpu.h"
  32 #include "amdgpu_ras.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_xgmi.h"
  35 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
  36
  37 static const char *RAS_FS_NAME = "ras";
  38
  39 const char *ras_error_string[] = {
  40         "none",
  41         "parity",
  42         "single_correctable",
  43         "multi_uncorrectable",
  44         "poison",
  45 };
  46
  47 const char *ras_block_string[] = {
  48         "umc",
  49         "sdma",
  50         "gfx",
  51         "mmhub",
  52         "athub",
  53         "pcie_bif",
  54         "hdp",
  55         "xgmi_wafl",
  56         "df",
  57         "smn",
  58         "sem",
  59         "mp0",
  60         "mp1",
  61         "fuse",
  62 };
  63
  64 #define ras_err_str(i) (ras_error_string[ffs(i)])
  65 #define ras_block_str(i) (ras_block_string[i])
  66
  67 #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
  68
  69 /* inject address is 52 bits */
  70 #define RAS_UMC_INJECT_ADDR_LIMIT       (0x1ULL << 52)
  71
  72 /* typical ECC bad page rate(1 bad page per 100MB VRAM) */
  73 #define RAS_BAD_PAGE_RATE               (100 * 1024 * 1024ULL)
  74
  75 enum amdgpu_ras_retire_page_reservation {
  76         AMDGPU_RAS_RETIRE_PAGE_RESERVED,
  77         AMDGPU_RAS_RETIRE_PAGE_PENDING,
  78         AMDGPU_RAS_RETIRE_PAGE_FAULT,
  79 };
  80
  81 atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
  82
  83 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
  84                                 uint64_t addr);
  85 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
  86                                 uint64_t addr);
  87
  88 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
  89 {
  90         if (adev && amdgpu_ras_get_context(adev))
  91                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
  92 }
  93
  94 static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
  95 {
  96         if (adev && amdgpu_ras_get_context(adev))
  97                 return amdgpu_ras_get_context(adev)->error_query_ready;
  98
  99         return false;
 100 }
 101
 102 static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
 103 {
 104         struct ras_err_data err_data = {0, 0, 0, NULL};
 105         struct eeprom_table_record err_rec;
 106
 107         if ((address >= adev->gmc.mc_vram_size) ||
 108             (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 109                 dev_warn(adev->dev,
 110                          "RAS WARN: input address 0x%llx is invalid.\n",
 111                          address);
 112                 return -EINVAL;
 113         }
 114
 115         if (amdgpu_ras_check_bad_page(adev, address)) {
 116                 dev_warn(adev->dev,
 117                          "RAS WARN: 0x%llx has been marked as bad page!\n",
 118                          address);
 119                 return 0;
 120         }
 121
 122         memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
 123
 124         err_rec.address = address;
 125         err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT;
 126         err_rec.ts = (uint64_t)ktime_get_real_seconds();
 127         err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
 128
 129         err_data.err_addr = &err_rec;
 130         err_data.err_addr_cnt = 1;
 131
 132         if (amdgpu_bad_page_threshold != 0) {
 133                 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
 134                                          err_data.err_addr_cnt);
 135                 amdgpu_ras_save_bad_pages(adev);
 136         }
 137
 138         dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
 139         dev_warn(adev->dev, "Clear EEPROM:\n");
 140         dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
 141
 142         return 0;
 143 }
 144
 145 static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
 146                                         size_t size, loff_t *pos)
 147 {
 148         struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
 149         struct ras_query_if info = {
 150                 .head = obj->head,
 151         };
 152         ssize_t s;
 153         char val[128];
 154
 155         if (amdgpu_ras_query_error_status(obj->adev, &info))
 156                 return -EINVAL;
 157
 158         s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
 159                         "ue", info.ue_count,
 160                         "ce", info.ce_count);
 161         if (*pos >= s)
 162                 return 0;
 163
 164         s -= *pos;
 165         s = min_t(u64, s, size);
 166
 167
 168         if (copy_to_user(buf, &val[*pos], s))
 169                 return -EINVAL;
 170
 171         *pos += s;
 172
 173         return s;
 174 }
 175
 176 static const struct file_operations amdgpu_ras_debugfs_ops = {
 177         .owner = THIS_MODULE,
 178         .read = amdgpu_ras_debugfs_read,
 179         .write = NULL,
 180         .llseek = default_llseek
 181 };
 182
 183 static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
 184 {
 185         int i;
 186
 187         for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
 188                 *block_id = i;
 189                 if (strcmp(name, ras_block_str(i)) == 0)
 190                         return 0;
 191         }
 192         return -EINVAL;
 193 }
 194
 195 static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
 196                 const char __user *buf, size_t size,
 197                 loff_t *pos, struct ras_debug_if *data)
 198 {
 199         ssize_t s = min_t(u64, 64, size);
 200         char str[65];
 201         char block_name[33];
 202         char err[9] = "ue";
 203         int op = -1;
 204         int block_id;
 205         uint32_t sub_block;
 206         u64 address, value;
 207
 208         if (*pos)
 209                 return -EINVAL;
 210         *pos = size;
 211
 212         memset(str, 0, sizeof(str));
 213         memset(data, 0, sizeof(*data));
 214
 215         if (copy_from_user(str, buf, s))
 216                 return -EINVAL;
 217
 218         if (sscanf(str, "disable %32s", block_name) == 1)
 219                 op = 0;
 220         else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
 221                 op = 1;
 222         else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
 223                 op = 2;
 224         else if (sscanf(str, "retire_page") == 0)
 225                 op = 3;
 226         else if (str[0] && str[1] && str[2] && str[3])
 227                 /* ascii string, but commands are not matched. */
 228                 return -EINVAL;
 229
 230         if (op != -1) {
 231
 232                 if (op == 3) {
 233                         if (sscanf(str, "%*s %llx", &address) != 1)
 234                                 return -EINVAL;
 235
 236                         data->op = op;
 237                         data->inject.address = address;
 238
 239                         return 0;
 240                 }
 241
 242                 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
 243                         return -EINVAL;
 244
 245                 data->head.block = block_id;
 246                 /* only ue and ce errors are supported */
 247                 if (!memcmp("ue", err, 2))
 248                         data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
 249                 else if (!memcmp("ce", err, 2))
 250                         data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
 251                 else
 252                         return -EINVAL;
 253
 254                 data->op = op;
 255
 256                 if (op == 2) {
 257                         if (sscanf(str, "%*s %*s %*s %x %llx %llx",
 258                                    &sub_block, &address, &value) != 3)
 259                                 return -EINVAL;
 260                         data->head.sub_block_index = sub_block;
 261                         data->inject.address = address;
 262                         data->inject.value = value;
 263                 }
 264         } else {
 265                 if (size < sizeof(*data))
 266                         return -EINVAL;
 267
 268                 if (copy_from_user(data, buf, sizeof(*data)))
 269                         return -EINVAL;
 270         }
 271
 272         return 0;
 273 }
 274
 275 /**
 276  * DOC: AMDGPU RAS debugfs control interface
 277  *
 278  * It accepts struct ras_debug_if who has two members.
 279  *
 280  * First member: ras_debug_if::head or ras_debug_if::inject.
 281  *
 282  * head is used to indicate which IP block will be under control.
 283  *
 284  * head has four members, they are block, type, sub_block_index, name.
 285  * block: which IP will be under control.
 286  * type: what kind of error will be enabled/disabled/injected.
 287  * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
 288  * name: the name of IP.
 289  *
 290  * inject has two more members than head, they are address, value.
 291  * As their names indicate, inject operation will write the
 292  * value to the address.
 293  *
 294  * The second member: struct ras_debug_if::op.
 295  * It has three kinds of operations.
 296  *
 297  * - 0: disable RAS on the block. Take ::head as its data.
 298  * - 1: enable RAS on the block. Take ::head as its data.
 299  * - 2: inject errors on the block. Take ::inject as its data.
 300  *
 301  * How to use the interface?
 302  *
 303  * Programs
 304  *
 305  * Copy the struct ras_debug_if in your codes and initialize it.
 306  * Write the struct to the control node.
 307  *
 308  * Shells
 309  *
 310  * .. code-block:: bash
 311  *
 312  *      echo op block [error [sub_block address value]] > .../ras/ras_ctrl
 313  *
 314  * Parameters:
 315  *
 316  * op: disable, enable, inject
 317  *      disable: only block is needed
 318  *      enable: block and error are needed
 319  *      inject: error, address, value are needed
 320  * block: umc, sdma, gfx, .........
 321  *      see ras_block_string[] for details
 322  * error: ue, ce
 323  *      ue: multi_uncorrectable
 324  *      ce: single_correctable
 325  * sub_block:
 326  *      sub block index, pass 0 if there is no sub block
 327  *
 328  * here are some examples for bash commands:
 329  *
 330  * .. code-block:: bash
 331  *
 332  *      echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 333  *      echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
 334  *      echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
 335  *
 336  * How to check the result?
 337  *
 338  * For disable/enable, please check ras features at
 339  * /sys/class/drm/card[0/1/2...]/device/ras/features
 340  *
 341  * For inject, please check corresponding err count at
 342  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 343  *
 344  * .. note::
 345  *      Operations are only allowed on blocks which are supported.
 346  *      Please check ras mask at /sys/module/amdgpu/parameters/ras_mask
 347  *      to see which blocks support RAS on a particular asic.
 348  *
 349  */
 350 static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf,
 351                 size_t size, loff_t *pos)
 352 {
 353         struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
 354         struct ras_debug_if data;
 355         int ret = 0;
 356
 357         if (!amdgpu_ras_get_error_query_ready(adev)) {
 358                 dev_warn(adev->dev, "RAS WARN: error injection "
 359                                 "currently inaccessible\n");
 360                 return size;
 361         }
 362
 363         ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
 364         if (ret)
 365                 return -EINVAL;
 366
 367         if (data.op == 3)
 368         {
 369                 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
 370
 371                 if (ret)
 372                         return size;
 373                 else
 374                         return ret;
 375         }
 376
 377         if (!amdgpu_ras_is_supported(adev, data.head.block))
 378                 return -EINVAL;
 379
 380         switch (data.op) {
 381         case 0:
 382                 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
 383                 break;
 384         case 1:
 385                 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
 386                 break;
 387         case 2:
 388                 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
 389                     (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
 390                         dev_warn(adev->dev, "RAS WARN: input address "
 391                                         "0x%llx is invalid.",
 392                                         data.inject.address);
 393                         ret = -EINVAL;
 394                         break;
 395                 }
 396
 397                 /* umc ce/ue error injection for a bad page is not allowed */
 398                 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
 399                     amdgpu_ras_check_bad_page(adev, data.inject.address)) {
 400                         dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked "
 401                                         "as bad before error injection!\n",
 402                                         data.inject.address);
 403                         break;
 404                 }
 405
 406                 /* data.inject.address is offset instead of absolute gpu address */
 407                 ret = amdgpu_ras_error_inject(adev, &data.inject);
 408                 break;
 409         default:
 410                 ret = -EINVAL;
 411                 break;
 412         }
 413
 414         if (ret)
 415                 return -EINVAL;
 416
 417         return size;
 418 }
 419
 420 /**
 421  * DOC: AMDGPU RAS debugfs EEPROM table reset interface
 422  *
 423  * Some boards contain an EEPROM which is used to persistently store a list of
 424  * bad pages which experiences ECC errors in vram.  This interface provides
 425  * a way to reset the EEPROM, e.g., after testing error injection.
 426  *
 427  * Usage:
 428  *
 429  * .. code-block:: bash
 430  *
 431  *      echo 1 > ../ras/ras_eeprom_reset
 432  *
 433  * will reset EEPROM table to 0 entries.
 434  *
 435  */
 436 static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf,
 437                 size_t size, loff_t *pos)
 438 {
 439         struct amdgpu_device *adev =
 440                 (struct amdgpu_device *)file_inode(f)->i_private;
 441         int ret;
 442
 443         ret = amdgpu_ras_eeprom_reset_table(
 444                         &(amdgpu_ras_get_context(adev)->eeprom_control));
 445
 446         if (ret == 1) {
 447                 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
 448                 return size;
 449         } else {
 450                 return -EIO;
 451         }
 452 }
 453
 454 static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
 455         .owner = THIS_MODULE,
 456         .read = NULL,
 457         .write = amdgpu_ras_debugfs_ctrl_write,
 458         .llseek = default_llseek
 459 };
 460
 461 static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
 462         .owner = THIS_MODULE,
 463         .read = NULL,
 464         .write = amdgpu_ras_debugfs_eeprom_write,
 465         .llseek = default_llseek
 466 };
 467
 468 /**
 469  * DOC: AMDGPU RAS sysfs Error Count Interface
 470  *
 471  * It allows the user to read the error count for each IP block on the gpu through
 472  * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
 473  *
 474  * It outputs the multiple lines which report the uncorrected (ue) and corrected
 475  * (ce) error counts.
 476  *
 477  * The format of one line is below,
 478  *
 479  * [ce|ue]: count
 480  *
 481  * Example:
 482  *
 483  * .. code-block:: bash
 484  *
 485  *      ue: 0
 486  *      ce: 1
 487  *
 488  */
 489 static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
 490                 struct device_attribute *attr, char *buf)
 491 {
 492         struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
 493         struct ras_query_if info = {
 494                 .head = obj->head,
 495         };
 496
 497         if (!amdgpu_ras_get_error_query_ready(obj->adev))
 498                 return sysfs_emit(buf, "Query currently inaccessible\n");
 499
 500         if (amdgpu_ras_query_error_status(obj->adev, &info))
 501                 return -EINVAL;
 502
 503         return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
 504                           "ce", info.ce_count);
 505 }
 506
 507 /* obj begin */
 508
 509 #define get_obj(obj) do { (obj)->use++; } while (0)
 510 #define alive_obj(obj) ((obj)->use)
 511
 512 static inline void put_obj(struct ras_manager *obj)
 513 {
 514         if (obj && (--obj->use == 0))
 515                 list_del(&obj->node);
 516         if (obj && (obj->use < 0))
 517                 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name);
 518 }
 519
 520 /* make one obj and return it. */
 521 static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
 522                 struct ras_common_if *head)
 523 {
 524         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 525         struct ras_manager *obj;
 526
 527         if (!adev->ras_features || !con)
 528                 return NULL;
 529
 530         if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 531                 return NULL;
 532
 533         obj = &con->objs[head->block];
 534         /* already exist. return obj? */
 535         if (alive_obj(obj))
 536                 return NULL;
 537
 538         obj->head = *head;
 539         obj->adev = adev;
 540         list_add(&obj->node, &con->head);
 541         get_obj(obj);
 542
 543         return obj;
 544 }
 545
 546 /* return an obj equal to head, or the first when head is NULL */
 547 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 548                 struct ras_common_if *head)
 549 {
 550         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 551         struct ras_manager *obj;
 552         int i;
 553
 554         if (!adev->ras_features || !con)
 555                 return NULL;
 556
 557         if (head) {
 558                 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
 559                         return NULL;
 560
 561                 obj = &con->objs[head->block];
 562
 563                 if (alive_obj(obj)) {
 564                         WARN_ON(head->block != obj->head.block);
 565                         return obj;
 566                 }
 567         } else {
 568                 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
 569                         obj = &con->objs[i];
 570                         if (alive_obj(obj)) {
 571                                 WARN_ON(i != obj->head.block);
 572                                 return obj;
 573                         }
 574                 }
 575         }
 576
 577         return NULL;
 578 }
 579 /* obj end */
 580
 581 static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
 582                                          const char* invoke_type,
 583                                          const char* block_name,
 584                                          enum ta_ras_status ret)
 585 {
 586         switch (ret) {
 587         case TA_RAS_STATUS__SUCCESS:
 588                 return;
 589         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
 590                 dev_warn(adev->dev,
 591                         "RAS WARN: %s %s currently unavailable\n",
 592                         invoke_type,
 593                         block_name);
 594                 break;
 595         default:
 596                 dev_err(adev->dev,
 597                         "RAS ERROR: %s %s error failed ret 0x%X\n",
 598                         invoke_type,
 599                         block_name,
 600                         ret);
 601         }
 602 }
 603
 604 /* feature ctl begin */
 605 static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
 606                 struct ras_common_if *head)
 607 {
 608         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 609
 610         return con->hw_supported & BIT(head->block);
 611 }
 612
 613 static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
 614                 struct ras_common_if *head)
 615 {
 616         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 617
 618         return con->features & BIT(head->block);
 619 }
 620
 621 /*
 622  * if obj is not created, then create one.
 623  * set feature enable flag.
 624  */
 625 static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 626                 struct ras_common_if *head, int enable)
 627 {
 628         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 629         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
 630
 631         /* If hardware does not support ras, then do not create obj.
 632          * But if hardware support ras, we can create the obj.
 633          * Ras framework checks con->hw_supported to see if it need do
 634          * corresponding initialization.
 635          * IP checks con->support to see if it need disable ras.
 636          */
 637         if (!amdgpu_ras_is_feature_allowed(adev, head))
 638                 return 0;
 639         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head)))
 640                 return 0;
 641
 642         if (enable) {
 643                 if (!obj) {
 644                         obj = amdgpu_ras_create_obj(adev, head);
 645                         if (!obj)
 646                                 return -EINVAL;
 647                 } else {
 648                         /* In case we create obj somewhere else */
 649                         get_obj(obj);
 650                 }
 651                 con->features |= BIT(head->block);
 652         } else {
 653                 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
 654                         /* skip clean gfx ras context feature for VEGA20 Gaming.
 655                          * will clean later
 656                          */
 657                         if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)))
 658                                 con->features &= ~BIT(head->block);
 659                         put_obj(obj);
 660                 }
 661         }
 662
 663         return 0;
 664 }
 665
 666 /* wrapper of psp_ras_enable_features */
 667 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 668                 struct ras_common_if *head, bool enable)
 669 {
 670         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 671         union ta_ras_cmd_input *info;
 672         int ret;
 673
 674         if (!con)
 675                 return -EINVAL;
 676
 677         info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
 678         if (!info)
 679                 return -ENOMEM;
 680
 681         if (!enable) {
 682                 info->disable_features = (struct ta_ras_disable_features_input) {
 683                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 684                         .error_type = amdgpu_ras_error_to_ta(head->type),
 685                 };
 686         } else {
 687                 info->enable_features = (struct ta_ras_enable_features_input) {
 688                         .block_id =  amdgpu_ras_block_to_ta(head->block),
 689                         .error_type = amdgpu_ras_error_to_ta(head->type),
 690                 };
 691         }
 692
 693         /* Do not enable if it is not allowed. */
 694         WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
 695         /* Are we alerady in that state we are going to set? */
 696         if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) {
 697                 ret = 0;
 698                 goto out;
 699         }
 700
 701         if (!amdgpu_ras_intr_triggered()) {
 702                 ret = psp_ras_enable_features(&adev->psp, info, enable);
 703                 if (ret) {
 704                         amdgpu_ras_parse_status_code(adev,
 705                                                      enable ? "enable":"disable",
 706                                                      ras_block_str(head->block),
 707                                                     (enum ta_ras_status)ret);
 708                         if (ret == TA_RAS_STATUS__RESET_NEEDED)
 709                                 ret = -EAGAIN;
 710                         else
 711                                 ret = -EINVAL;
 712
 713                         goto out;
 714                 }
 715         }
 716
 717         /* setup the obj */
 718         __amdgpu_ras_feature_enable(adev, head, enable);
 719         ret = 0;
 720 out:
 721         kfree(info);
 722         return ret;
 723 }
 724
 725 /* Only used in device probe stage and called only once. */
 726 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 727                 struct ras_common_if *head, bool enable)
 728 {
 729         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 730         int ret;
 731
 732         if (!con)
 733                 return -EINVAL;
 734
 735         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
 736                 if (enable) {
 737                         /* There is no harm to issue a ras TA cmd regardless of
 738                          * the currecnt ras state.
 739                          * If current state == target state, it will do nothing
 740                          * But sometimes it requests driver to reset and repost
 741                          * with error code -EAGAIN.
 742                          */
 743                         ret = amdgpu_ras_feature_enable(adev, head, 1);
 744                         /* With old ras TA, we might fail to enable ras.
 745                          * Log it and just setup the object.
 746                          * TODO need remove this WA in the future.
 747                          */
 748                         if (ret == -EINVAL) {
 749                                 ret = __amdgpu_ras_feature_enable(adev, head, 1);
 750                                 if (!ret)
 751                                         dev_info(adev->dev,
 752                                                 "RAS INFO: %s setup object\n",
 753                                                 ras_block_str(head->block));
 754                         }
 755                 } else {
 756                         /* setup the object then issue a ras TA disable cmd.*/
 757                         ret = __amdgpu_ras_feature_enable(adev, head, 1);
 758                         if (ret)
 759                                 return ret;
 760
 761                         /* gfx block ras dsiable cmd must send to ras-ta */
 762                         if (head->block == AMDGPU_RAS_BLOCK__GFX)
 763                                 con->features |= BIT(head->block);
 764
 765                         ret = amdgpu_ras_feature_enable(adev, head, 0);
 766                 }
 767         } else
 768                 ret = amdgpu_ras_feature_enable(adev, head, enable);
 769
 770         return ret;
 771 }
 772
 773 static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
 774                 bool bypass)
 775 {
 776         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 777         struct ras_manager *obj, *tmp;
 778
 779         list_for_each_entry_safe(obj, tmp, &con->head, node) {
 780                 /* bypass psp.
 781                  * aka just release the obj and corresponding flags
 782                  */
 783                 if (bypass) {
 784                         if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
 785                                 break;
 786                 } else {
 787                         if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
 788                                 break;
 789                 }
 790         }
 791
 792         return con->features;
 793 }
 794
 795 static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
 796                 bool bypass)
 797 {
 798         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
 799         int ras_block_count = AMDGPU_RAS_BLOCK_COUNT;
 800         int i;
 801         const enum amdgpu_ras_error_type default_ras_type =
 802                 AMDGPU_RAS_ERROR__NONE;
 803
 804         for (i = 0; i < ras_block_count; i++) {
 805                 struct ras_common_if head = {
 806                         .block = i,
 807                         .type = default_ras_type,
 808                         .sub_block_index = 0,
 809                 };
 810                 strcpy(head.name, ras_block_str(i));
 811                 if (bypass) {
 812                         /*
 813                          * bypass psp. vbios enable ras for us.
 814                          * so just create the obj
 815                          */
 816                         if (__amdgpu_ras_feature_enable(adev, &head, 1))
 817                                 break;
 818                 } else {
 819                         if (amdgpu_ras_feature_enable(adev, &head, 1))
 820                                 break;
 821                 }
 822         }
 823
 824         return con->features;
 825 }
 826 /* feature ctl end */
 827
 828 /* query/inject/cure begin */
 829 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 830         struct ras_query_if *info)
 831 {
 832         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 833         struct ras_err_data err_data = {0, 0, 0, NULL};
 834         int i;
 835
 836         if (!obj)
 837                 return -EINVAL;
 838
 839         switch (info->head.block) {
 840         case AMDGPU_RAS_BLOCK__UMC:
 841                 if (adev->umc.ras_funcs &&
 842                     adev->umc.ras_funcs->query_ras_error_count)
 843                         adev->umc.ras_funcs->query_ras_error_count(adev, &err_data);
 844                 /* umc query_ras_error_address is also responsible for clearing
 845                  * error status
 846                  */
 847                 if (adev->umc.ras_funcs &&
 848                     adev->umc.ras_funcs->query_ras_error_address)
 849                         adev->umc.ras_funcs->query_ras_error_address(adev, &err_data);
 850                 break;
 851         case AMDGPU_RAS_BLOCK__SDMA:
 852                 if (adev->sdma.funcs->query_ras_error_count) {
 853                         for (i = 0; i < adev->sdma.num_instances; i++)
 854                                 adev->sdma.funcs->query_ras_error_count(adev, i,
 855                                                                         &err_data);
 856                 }
 857                 break;
 858         case AMDGPU_RAS_BLOCK__GFX:
 859                 if (adev->gfx.ras_funcs &&
 860                     adev->gfx.ras_funcs->query_ras_error_count)
 861                         adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data);
 862
 863                 if (adev->gfx.ras_funcs &&
 864                     adev->gfx.ras_funcs->query_ras_error_status)
 865                         adev->gfx.ras_funcs->query_ras_error_status(adev);
 866                 break;
 867         case AMDGPU_RAS_BLOCK__MMHUB:
 868                 if (adev->mmhub.ras_funcs &&
 869                     adev->mmhub.ras_funcs->query_ras_error_count)
 870                         adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data);
 871
 872                 if (adev->mmhub.ras_funcs &&
 873                     adev->mmhub.ras_funcs->query_ras_error_status)
 874                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
 875                 break;
 876         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 877                 if (adev->nbio.ras_funcs &&
 878                     adev->nbio.ras_funcs->query_ras_error_count)
 879                         adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
 880                 break;
 881         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 882                 if (adev->gmc.xgmi.ras_funcs &&
 883                     adev->gmc.xgmi.ras_funcs->query_ras_error_count)
 884                         adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
 885                 break;
 886         default:
 887                 break;
 888         }
 889
 890         obj->err_data.ue_count += err_data.ue_count;
 891         obj->err_data.ce_count += err_data.ce_count;
 892
 893         info->ue_count = obj->err_data.ue_count;
 894         info->ce_count = obj->err_data.ce_count;
 895
 896         if (err_data.ce_count) {
 897                 dev_info(adev->dev, "%ld correctable hardware errors "
 898                                         "detected in %s block, no user "
 899                                         "action is needed.\n",
 900                                         obj->err_data.ce_count,
 901                                         ras_block_str(info->head.block));
 902         }
 903         if (err_data.ue_count) {
 904                 dev_info(adev->dev, "%ld uncorrectable hardware errors "
 905                                         "detected in %s block\n",
 906                                         obj->err_data.ue_count,
 907                                         ras_block_str(info->head.block));
 908         }
 909
 910         return 0;
 911 }
 912
 913 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 914                 enum amdgpu_ras_block block)
 915 {
 916         if (!amdgpu_ras_is_supported(adev, block))
 917                 return -EINVAL;
 918
 919         switch (block) {
 920         case AMDGPU_RAS_BLOCK__GFX:
 921                 if (adev->gfx.ras_funcs &&
 922                     adev->gfx.ras_funcs->reset_ras_error_count)
 923                         adev->gfx.ras_funcs->reset_ras_error_count(adev);
 924
 925                 if (adev->gfx.ras_funcs &&
 926                     adev->gfx.ras_funcs->reset_ras_error_status)
 927                         adev->gfx.ras_funcs->reset_ras_error_status(adev);
 928                 break;
 929         case AMDGPU_RAS_BLOCK__MMHUB:
 930                 if (adev->mmhub.ras_funcs &&
 931                     adev->mmhub.ras_funcs->reset_ras_error_count)
 932                         adev->mmhub.ras_funcs->reset_ras_error_count(adev);
 933                 break;
 934         case AMDGPU_RAS_BLOCK__SDMA:
 935                 if (adev->sdma.funcs->reset_ras_error_count)
 936                         adev->sdma.funcs->reset_ras_error_count(adev);
 937                 break;
 938         default:
 939                 break;
 940         }
 941
 942         return 0;
 943 }
 944
 945 /* Trigger XGMI/WAFL error */
 946 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
 947                                  struct ta_ras_trigger_error_input *block_info)
 948 {
 949         int ret;
 950
 951         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
 952                 dev_warn(adev->dev, "Failed to disallow df cstate");
 953
 954         if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
 955                 dev_warn(adev->dev, "Failed to disallow XGMI power down");
 956
 957         ret = psp_ras_trigger_error(&adev->psp, block_info);
 958
 959         if (amdgpu_ras_intr_triggered())
 960                 return ret;
 961
 962         if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
 963                 dev_warn(adev->dev, "Failed to allow XGMI power down");
 964
 965         if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
 966                 dev_warn(adev->dev, "Failed to allow df cstate");
 967
 968         return ret;
 969 }
 970
 971 /* wrapper of psp_ras_trigger_error */
 972 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 973                 struct ras_inject_if *info)
 974 {
 975         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
 976         struct ta_ras_trigger_error_input block_info = {
 977                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
 978                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
 979                 .sub_block_index = info->head.sub_block_index,
 980                 .address = info->address,
 981                 .value = info->value,
 982         };
 983         int ret = 0;
 984
 985         if (!obj)
 986                 return -EINVAL;
 987
 988         /* Calculate XGMI relative offset */
 989         if (adev->gmc.xgmi.num_physical_nodes > 1) {
 990                 block_info.address =
 991                         amdgpu_xgmi_get_relative_phy_addr(adev,
 992                                                           block_info.address);
 993         }
 994
 995         switch (info->head.block) {
 996         case AMDGPU_RAS_BLOCK__GFX:
 997                 if (adev->gfx.ras_funcs &&
 998                     adev->gfx.ras_funcs->ras_error_inject)
 999                         ret = adev->gfx.ras_funcs->ras_error_inject(adev, info);
1000                 else
1001                         ret = -EINVAL;
1002                 break;
1003         case AMDGPU_RAS_BLOCK__UMC:
1004         case AMDGPU_RAS_BLOCK__SDMA:
1005         case AMDGPU_RAS_BLOCK__MMHUB:
1006         case AMDGPU_RAS_BLOCK__PCIE_BIF:
1007                 ret = psp_ras_trigger_error(&adev->psp, &block_info);
1008                 break;
1009         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1010                 ret = amdgpu_ras_error_inject_xgmi(adev, &block_info);
1011                 break;
1012         default:
1013                 dev_info(adev->dev, "%s error injection is not supported yet\n",
1014                          ras_block_str(info->head.block));
1015                 ret = -EINVAL;
1016         }
1017
1018         amdgpu_ras_parse_status_code(adev,
1019                                      "inject",
1020                                      ras_block_str(info->head.block),
1021                                      (enum ta_ras_status)ret);
1022
1023         return ret;
1024 }
1025
1026 /* get the total error counts on all IPs */
1027 unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1028                 bool is_ce)
1029 {
1030         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1031         struct ras_manager *obj;
1032         struct ras_err_data data = {0, 0};
1033
1034         if (!adev->ras_features || !con)
1035                 return 0;
1036
1037         list_for_each_entry(obj, &con->head, node) {
1038                 struct ras_query_if info = {
1039                         .head = obj->head,
1040                 };
1041
1042                 if (amdgpu_ras_query_error_status(adev, &info))
1043                         return 0;
1044
1045                 data.ce_count += info.ce_count;
1046                 data.ue_count += info.ue_count;
1047         }
1048
1049         return is_ce ? data.ce_count : data.ue_count;
1050 }
1051 /* query/inject/cure end */
1052
1053
1054 /* sysfs begin */
1055
1056 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1057                 struct ras_badpage **bps, unsigned int *count);
1058
1059 static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1060 {
1061         switch (flags) {
1062         case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
1063                 return "R";
1064         case AMDGPU_RAS_RETIRE_PAGE_PENDING:
1065                 return "P";
1066         case AMDGPU_RAS_RETIRE_PAGE_FAULT:
1067         default:
1068                 return "F";
1069         }
1070 }
1071
1072 /**
1073  * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
1074  *
1075  * It allows user to read the bad pages of vram on the gpu through
1076  * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1077  *
1078  * It outputs multiple lines, and each line stands for one gpu page.
1079  *
1080  * The format of one line is below,
1081  * gpu pfn : gpu page size : flags
1082  *
1083  * gpu pfn and gpu page size are printed in hex format.
1084  * flags can be one of below character,
1085  *
1086  * R: reserved, this gpu page is reserved and not able to use.
1087  *
1088  * P: pending for reserve, this gpu page is marked as bad, will be reserved
1089  * in next window of page_reserve.
1090  *
1091  * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1092  *
1093  * Examples:
1094  *
1095  * .. code-block:: bash
1096  *
1097  *      0x00000001 : 0x00001000 : R
1098  *      0x00000002 : 0x00001000 : P
1099  *
1100  */
1101
1102 static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1103                 struct kobject *kobj, struct bin_attribute *attr,
1104                 char *buf, loff_t ppos, size_t count)
1105 {
1106         struct amdgpu_ras *con =
1107                 container_of(attr, struct amdgpu_ras, badpages_attr);
1108         struct amdgpu_device *adev = con->adev;
1109         const unsigned int element_size =
1110                 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
1111         unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1112         unsigned int end = div64_ul(ppos + count - 1, element_size);
1113         ssize_t s = 0;
1114         struct ras_badpage *bps = NULL;
1115         unsigned int bps_count = 0;
1116
1117         memset(buf, 0, count);
1118
1119         if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1120                 return 0;
1121
1122         for (; start < end && start < bps_count; start++)
1123                 s += scnprintf(&buf[s], element_size + 1,
1124                                 "0x%08x : 0x%08x : %1s\n",
1125                                 bps[start].bp,
1126                                 bps[start].size,
1127                                 amdgpu_ras_badpage_flags_str(bps[start].flags));
1128
1129         kfree(bps);
1130
1131         return s;
1132 }
1133
1134 static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1135                 struct device_attribute *attr, char *buf)
1136 {
1137         struct amdgpu_ras *con =
1138                 container_of(attr, struct amdgpu_ras, features_attr);
1139
1140         return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
1141 }
1142
1143 static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1144 {
1145         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1146
1147         sysfs_remove_file_from_group(&adev->dev->kobj,
1148                                 &con->badpages_attr.attr,
1149                                 RAS_FS_NAME);
1150 }
1151
1152 static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1153 {
1154         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1155         struct attribute *attrs[] = {
1156                 &con->features_attr.attr,
1157                 NULL
1158         };
1159         struct attribute_group group = {
1160                 .name = RAS_FS_NAME,
1161                 .attrs = attrs,
1162         };
1163
1164         sysfs_remove_group(&adev->dev->kobj, &group);
1165
1166         return 0;
1167 }
1168
1169 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
1170                 struct ras_fs_if *head)
1171 {
1172         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1173
1174         if (!obj || obj->attr_inuse)
1175                 return -EINVAL;
1176
1177         get_obj(obj);
1178
1179         memcpy(obj->fs_data.sysfs_name,
1180                         head->sysfs_name,
1181                         sizeof(obj->fs_data.sysfs_name));
1182
1183         obj->sysfs_attr = (struct device_attribute){
1184                 .attr = {
1185                         .name = obj->fs_data.sysfs_name,
1186                         .mode = S_IRUGO,
1187                 },
1188                         .show = amdgpu_ras_sysfs_read,
1189         };
1190         sysfs_attr_init(&obj->sysfs_attr.attr);
1191
1192         if (sysfs_add_file_to_group(&adev->dev->kobj,
1193                                 &obj->sysfs_attr.attr,
1194                                 RAS_FS_NAME)) {
1195                 put_obj(obj);
1196                 return -EINVAL;
1197         }
1198
1199         obj->attr_inuse = 1;
1200
1201         return 0;
1202 }
1203
1204 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1205                 struct ras_common_if *head)
1206 {
1207         struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1208
1209         if (!obj || !obj->attr_inuse)
1210                 return -EINVAL;
1211
1212         sysfs_remove_file_from_group(&adev->dev->kobj,
1213                                 &obj->sysfs_attr.attr,
1214                                 RAS_FS_NAME);
1215         obj->attr_inuse = 0;
1216         put_obj(obj);
1217
1218         return 0;
1219 }
1220
1221 static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1222 {
1223         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1224         struct ras_manager *obj, *tmp;
1225
1226         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1227                 amdgpu_ras_sysfs_remove(adev, &obj->head);
1228         }
1229
1230         if (amdgpu_bad_page_threshold != 0)
1231                 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1232
1233         amdgpu_ras_sysfs_remove_feature_node(adev);
1234
1235         return 0;
1236 }
1237 /* sysfs end */
1238
1239 /**
1240  * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1241  *
1242  * Normally when there is an uncorrectable error, the driver will reset
1243  * the GPU to recover.  However, in the event of an unrecoverable error,
1244  * the driver provides an interface to reboot the system automatically
1245  * in that event.
1246  *
1247  * The following file in debugfs provides that interface:
1248  * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1249  *
1250  * Usage:
1251  *
1252  * .. code-block:: bash
1253  *
1254  *      echo true > .../ras/auto_reboot
1255  *
1256  */
1257 /* debugfs begin */
1258 static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1259 {
1260         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1261         struct dentry *dir;
1262         struct drm_minor *minor = adev_to_drm(adev)->primary;
1263
1264         dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1265         debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1266                             &amdgpu_ras_debugfs_ctrl_ops);
1267         debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1268                             &amdgpu_ras_debugfs_eeprom_ops);
1269
1270         /*
1271          * After one uncorrectable error happens, usually GPU recovery will
1272          * be scheduled. But due to the known problem in GPU recovery failing
1273          * to bring GPU back, below interface provides one direct way to
1274          * user to reboot system automatically in such case within
1275          * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1276          * will never be called.
1277          */
1278         debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
1279
1280         /*
1281          * User could set this not to clean up hardware's error count register
1282          * of RAS IPs during ras recovery.
1283          */
1284         debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1285                             &con->disable_ras_err_cnt_harvest);
1286         return dir;
1287 }
1288
1289 static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
1290                                       struct ras_fs_if *head,
1291                                       struct dentry *dir)
1292 {
1293         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
1294
1295         if (!obj || !dir)
1296                 return;
1297
1298         get_obj(obj);
1299
1300         memcpy(obj->fs_data.debugfs_name,
1301                         head->debugfs_name,
1302                         sizeof(obj->fs_data.debugfs_name));
1303
1304         debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1305                             obj, &amdgpu_ras_debugfs_ops);
1306 }
1307
1308 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1309 {
1310         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1311         struct dentry *dir;
1312         struct ras_manager *obj;
1313         struct ras_fs_if fs_info;
1314
1315         /*
1316          * it won't be called in resume path, no need to check
1317          * suspend and gpu reset status
1318          */
1319         if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
1320                 return;
1321
1322         dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
1323
1324         list_for_each_entry(obj, &con->head, node) {
1325                 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1326                         (obj->attr_inuse == 1)) {
1327                         sprintf(fs_info.debugfs_name, "%s_err_inject",
1328                                         ras_block_str(obj->head.block));
1329                         fs_info.head = obj->head;
1330                         amdgpu_ras_debugfs_create(adev, &fs_info, dir);
1331                 }
1332         }
1333 }
1334
1335 /* debugfs end */
1336
1337 /* ras fs */
1338 static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1339                 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1340 static DEVICE_ATTR(features, S_IRUGO,
1341                 amdgpu_ras_sysfs_features_read, NULL);
1342 static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1343 {
1344         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1345         struct attribute_group group = {
1346                 .name = RAS_FS_NAME,
1347         };
1348         struct attribute *attrs[] = {
1349                 &con->features_attr.attr,
1350                 NULL
1351         };
1352         struct bin_attribute *bin_attrs[] = {
1353                 NULL,
1354                 NULL,
1355         };
1356         int r;
1357
1358         /* add features entry */
1359         con->features_attr = dev_attr_features;
1360         group.attrs = attrs;
1361         sysfs_attr_init(attrs[0]);
1362
1363         if (amdgpu_bad_page_threshold != 0) {
1364                 /* add bad_page_features entry */
1365                 bin_attr_gpu_vram_bad_pages.private = NULL;
1366                 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1367                 bin_attrs[0] = &con->badpages_attr;
1368                 group.bin_attrs = bin_attrs;
1369                 sysfs_bin_attr_init(bin_attrs[0]);
1370         }
1371
1372         r = sysfs_create_group(&adev->dev->kobj, &group);
1373         if (r)
1374                 dev_err(adev->dev, "Failed to create RAS sysfs group!");
1375
1376         return 0;
1377 }
1378
1379 static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1380 {
1381         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1382         struct ras_manager *con_obj, *ip_obj, *tmp;
1383
1384         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1385                 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1386                         ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1387                         if (ip_obj)
1388                                 put_obj(ip_obj);
1389                 }
1390         }
1391
1392         amdgpu_ras_sysfs_remove_all(adev);
1393         return 0;
1394 }
1395 /* ras fs end */
1396
1397 /* ih begin */
1398 static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1399 {
1400         struct ras_ih_data *data = &obj->ih_data;
1401         struct amdgpu_iv_entry entry;
1402         int ret;
1403         struct ras_err_data err_data = {0, 0, 0, NULL};
1404
1405         while (data->rptr != data->wptr) {
1406                 rmb();
1407                 memcpy(&entry, &data->ring[data->rptr],
1408                                 data->element_size);
1409
1410                 wmb();
1411                 data->rptr = (data->aligned_element_size +
1412                                 data->rptr) % data->ring_size;
1413
1414                 /* Let IP handle its data, maybe we need get the output
1415                  * from the callback to udpate the error type/count, etc
1416                  */
1417                 if (data->cb) {
1418                         ret = data->cb(obj->adev, &err_data, &entry);
1419                         /* ue will trigger an interrupt, and in that case
1420                          * we need do a reset to recovery the whole system.
1421                          * But leave IP do that recovery, here we just dispatch
1422                          * the error.
1423                          */
1424                         if (ret == AMDGPU_RAS_SUCCESS) {
1425                                 /* these counts could be left as 0 if
1426                                  * some blocks do not count error number
1427                                  */
1428                                 obj->err_data.ue_count += err_data.ue_count;
1429                                 obj->err_data.ce_count += err_data.ce_count;
1430                         }
1431                 }
1432         }
1433 }
1434
1435 static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1436 {
1437         struct ras_ih_data *data =
1438                 container_of(work, struct ras_ih_data, ih_work);
1439         struct ras_manager *obj =
1440                 container_of(data, struct ras_manager, ih_data);
1441
1442         amdgpu_ras_interrupt_handler(obj);
1443 }
1444
1445 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1446                 struct ras_dispatch_if *info)
1447 {
1448         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1449         struct ras_ih_data *data = &obj->ih_data;
1450
1451         if (!obj)
1452                 return -EINVAL;
1453
1454         if (data->inuse == 0)
1455                 return 0;
1456
1457         /* Might be overflow... */
1458         memcpy(&data->ring[data->wptr], info->entry,
1459                         data->element_size);
1460
1461         wmb();
1462         data->wptr = (data->aligned_element_size +
1463                         data->wptr) % data->ring_size;
1464
1465         schedule_work(&data->ih_work);
1466
1467         return 0;
1468 }
1469
1470 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
1471                 struct ras_ih_if *info)
1472 {
1473         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1474         struct ras_ih_data *data;
1475
1476         if (!obj)
1477                 return -EINVAL;
1478
1479         data = &obj->ih_data;
1480         if (data->inuse == 0)
1481                 return 0;
1482
1483         cancel_work_sync(&data->ih_work);
1484
1485         kfree(data->ring);
1486         memset(data, 0, sizeof(*data));
1487         put_obj(obj);
1488
1489         return 0;
1490 }
1491
1492 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
1493                 struct ras_ih_if *info)
1494 {
1495         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1496         struct ras_ih_data *data;
1497
1498         if (!obj) {
1499                 /* in case we registe the IH before enable ras feature */
1500                 obj = amdgpu_ras_create_obj(adev, &info->head);
1501                 if (!obj)
1502                         return -EINVAL;
1503         } else
1504                 get_obj(obj);
1505
1506         data = &obj->ih_data;
1507         /* add the callback.etc */
1508         *data = (struct ras_ih_data) {
1509                 .inuse = 0,
1510                 .cb = info->cb,
1511                 .element_size = sizeof(struct amdgpu_iv_entry),
1512                 .rptr = 0,
1513                 .wptr = 0,
1514         };
1515
1516         INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1517
1518         data->aligned_element_size = ALIGN(data->element_size, 8);
1519         /* the ring can store 64 iv entries. */
1520         data->ring_size = 64 * data->aligned_element_size;
1521         data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1522         if (!data->ring) {
1523                 put_obj(obj);
1524                 return -ENOMEM;
1525         }
1526
1527         /* IH is ready */
1528         data->inuse = 1;
1529
1530         return 0;
1531 }
1532
1533 static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1534 {
1535         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1536         struct ras_manager *obj, *tmp;
1537
1538         list_for_each_entry_safe(obj, tmp, &con->head, node) {
1539                 struct ras_ih_if info = {
1540                         .head = obj->head,
1541                 };
1542                 amdgpu_ras_interrupt_remove_handler(adev, &info);
1543         }
1544
1545         return 0;
1546 }
1547 /* ih end */
1548
1549 /* traversal all IPs except NBIO to query error counter */
1550 static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1551 {
1552         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1553         struct ras_manager *obj;
1554
1555         if (!adev->ras_features || !con)
1556                 return;
1557
1558         list_for_each_entry(obj, &con->head, node) {
1559                 struct ras_query_if info = {
1560                         .head = obj->head,
1561                 };
1562
1563                 /*
1564                  * PCIE_BIF IP has one different isr by ras controller
1565                  * interrupt, the specific ras counter query will be
1566                  * done in that isr. So skip such block from common
1567                  * sync flood interrupt isr calling.
1568                  */
1569                 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1570                         continue;
1571
1572                 amdgpu_ras_query_error_status(adev, &info);
1573         }
1574 }
1575
1576 /* Parse RdRspStatus and WrRspStatus */
1577 static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1578                                           struct ras_query_if *info)
1579 {
1580         /*
1581          * Only two block need to query read/write
1582          * RspStatus at current state
1583          */
1584         switch (info->head.block) {
1585         case AMDGPU_RAS_BLOCK__GFX:
1586                 if (adev->gfx.ras_funcs &&
1587                     adev->gfx.ras_funcs->query_ras_error_status)
1588                         adev->gfx.ras_funcs->query_ras_error_status(adev);
1589                 break;
1590         case AMDGPU_RAS_BLOCK__MMHUB:
1591                 if (adev->mmhub.ras_funcs &&
1592                     adev->mmhub.ras_funcs->query_ras_error_status)
1593                         adev->mmhub.ras_funcs->query_ras_error_status(adev);
1594                 break;
1595         default:
1596                 break;
1597         }
1598 }
1599
1600 static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1601 {
1602         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1603         struct ras_manager *obj;
1604
1605         if (!adev->ras_features || !con)
1606                 return;
1607
1608         list_for_each_entry(obj, &con->head, node) {
1609                 struct ras_query_if info = {
1610                         .head = obj->head,
1611                 };
1612
1613                 amdgpu_ras_error_status_query(adev, &info);
1614         }
1615 }
1616
1617 /* recovery begin */
1618
1619 /* return 0 on success.
1620  * caller need free bps.
1621  */
1622 static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1623                 struct ras_badpage **bps, unsigned int *count)
1624 {
1625         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1626         struct ras_err_handler_data *data;
1627         int i = 0;
1628         int ret = 0, status;
1629
1630         if (!con || !con->eh_data || !bps || !count)
1631                 return -EINVAL;
1632
1633         mutex_lock(&con->recovery_lock);
1634         data = con->eh_data;
1635         if (!data || data->count == 0) {
1636                 *bps = NULL;
1637                 ret = -EINVAL;
1638                 goto out;
1639         }
1640
1641         *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1642         if (!*bps) {
1643                 ret = -ENOMEM;
1644                 goto out;
1645         }
1646
1647         for (; i < data->count; i++) {
1648                 (*bps)[i] = (struct ras_badpage){
1649                         .bp = data->bps[i].retired_page,
1650                         .size = AMDGPU_GPU_PAGE_SIZE,
1651                         .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
1652                 };
1653                 status = amdgpu_vram_mgr_query_page_status(
1654                                 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1655                                 data->bps[i].retired_page);
1656                 if (status == -EBUSY)
1657                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
1658                 else if (status == -ENOENT)
1659                         (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
1660         }
1661
1662         *count = data->count;
1663 out:
1664         mutex_unlock(&con->recovery_lock);
1665         return ret;
1666 }
1667
1668 static void amdgpu_ras_do_recovery(struct work_struct *work)
1669 {
1670         struct amdgpu_ras *ras =
1671                 container_of(work, struct amdgpu_ras, recovery_work);
1672         struct amdgpu_device *remote_adev = NULL;
1673         struct amdgpu_device *adev = ras->adev;
1674         struct list_head device_list, *device_list_handle =  NULL;
1675
1676         if (!ras->disable_ras_err_cnt_harvest) {
1677                 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1678
1679                 /* Build list of devices to query RAS related errors */
1680                 if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1681                         device_list_handle = &hive->device_list;
1682                 } else {
1683                         INIT_LIST_HEAD(&device_list);
1684                         list_add_tail(&adev->gmc.xgmi.head, &device_list);
1685                         device_list_handle = &device_list;
1686                 }
1687
1688                 list_for_each_entry(remote_adev,
1689                                 device_list_handle, gmc.xgmi.head) {
1690                         amdgpu_ras_query_err_status(remote_adev);
1691                         amdgpu_ras_log_on_err_counter(remote_adev);
1692                 }
1693
1694                 amdgpu_put_xgmi_hive(hive);
1695         }
1696
1697         if (amdgpu_device_should_recover_gpu(ras->adev))
1698                 amdgpu_device_gpu_recover(ras->adev, NULL);
1699         atomic_set(&ras->in_recovery, 0);
1700 }
1701
1702 /* alloc/realloc bps array */
1703 static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1704                 struct ras_err_handler_data *data, int pages)
1705 {
1706         unsigned int old_space = data->count + data->space_left;
1707         unsigned int new_space = old_space + pages;
1708         unsigned int align_space = ALIGN(new_space, 512);
1709         void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
1710
1711         if (!bps) {
1712                 kfree(bps);
1713                 return -ENOMEM;
1714         }
1715
1716         if (data->bps) {
1717                 memcpy(bps, data->bps,
1718                                 data->count * sizeof(*data->bps));
1719                 kfree(data->bps);
1720         }
1721
1722         data->bps = bps;
1723         data->space_left += align_space - old_space;
1724         return 0;
1725 }
1726
1727 /* it deal with vram only. */
1728 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
1729                 struct eeprom_table_record *bps, int pages)
1730 {
1731         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1732         struct ras_err_handler_data *data;
1733         int ret = 0;
1734         uint32_t i;
1735
1736         if (!con || !con->eh_data || !bps || pages <= 0)
1737                 return 0;
1738
1739         mutex_lock(&con->recovery_lock);
1740         data = con->eh_data;
1741         if (!data)
1742                 goto out;
1743
1744         for (i = 0; i < pages; i++) {
1745                 if (amdgpu_ras_check_bad_page_unlock(con,
1746                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1747                         continue;
1748
1749                 if (!data->space_left &&
1750                         amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
1751                         ret = -ENOMEM;
1752                         goto out;
1753                 }
1754
1755                 amdgpu_vram_mgr_reserve_range(
1756                         ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM),
1757                         bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1758                         AMDGPU_GPU_PAGE_SIZE);
1759
1760                 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1761                 data->count++;
1762                 data->space_left--;
1763         }
1764 out:
1765         mutex_unlock(&con->recovery_lock);
1766
1767         return ret;
1768 }
1769
1770 /*
1771  * write error record array to eeprom, the function should be
1772  * protected by recovery_lock
1773  */
1774 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
1775 {
1776         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1777         struct ras_err_handler_data *data;
1778         struct amdgpu_ras_eeprom_control *control;
1779         int save_count;
1780
1781         if (!con || !con->eh_data)
1782                 return 0;
1783
1784         control = &con->eeprom_control;
1785         data = con->eh_data;
1786         save_count = data->count - control->num_recs;
1787         /* only new entries are saved */
1788         if (save_count > 0) {
1789                 if (amdgpu_ras_eeprom_process_recods(control,
1790                                                         &data->bps[control->num_recs],
1791                                                         true,
1792                                                         save_count)) {
1793                         dev_err(adev->dev, "Failed to save EEPROM table data!");
1794                         return -EIO;
1795                 }
1796
1797                 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
1798         }
1799
1800         return 0;
1801 }
1802
1803 /*
1804  * read error record array in eeprom and reserve enough space for
1805  * storing new bad pages
1806  */
1807 static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
1808 {
1809         struct amdgpu_ras_eeprom_control *control =
1810                                         &adev->psp.ras.ras->eeprom_control;
1811         struct eeprom_table_record *bps = NULL;
1812         int ret = 0;
1813
1814         /* no bad page record, skip eeprom access */
1815         if (!control->num_recs || (amdgpu_bad_page_threshold == 0))
1816                 return ret;
1817
1818         bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL);
1819         if (!bps)
1820                 return -ENOMEM;
1821
1822         if (amdgpu_ras_eeprom_process_recods(control, bps, false,
1823                 control->num_recs)) {
1824                 dev_err(adev->dev, "Failed to load EEPROM table records!");
1825                 ret = -EIO;
1826                 goto out;
1827         }
1828
1829         ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs);
1830
1831 out:
1832         kfree(bps);
1833         return ret;
1834 }
1835
1836 static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
1837                                 uint64_t addr)
1838 {
1839         struct ras_err_handler_data *data = con->eh_data;
1840         int i;
1841
1842         addr >>= AMDGPU_GPU_PAGE_SHIFT;
1843         for (i = 0; i < data->count; i++)
1844                 if (addr == data->bps[i].retired_page)
1845                         return true;
1846
1847         return false;
1848 }
1849
1850 /*
1851  * check if an address belongs to bad page
1852  *
1853  * Note: this check is only for umc block
1854  */
1855 static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
1856                                 uint64_t addr)
1857 {
1858         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1859         bool ret = false;
1860
1861         if (!con || !con->eh_data)
1862                 return ret;
1863
1864         mutex_lock(&con->recovery_lock);
1865         ret = amdgpu_ras_check_bad_page_unlock(con, addr);
1866         mutex_unlock(&con->recovery_lock);
1867         return ret;
1868 }
1869
1870 static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
1871                                         uint32_t max_length)
1872 {
1873         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1874         int tmp_threshold = amdgpu_bad_page_threshold;
1875         u64 val;
1876
1877         /*
1878          * Justification of value bad_page_cnt_threshold in ras structure
1879          *
1880          * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
1881          * in eeprom, and introduce two scenarios accordingly.
1882          *
1883          * Bad page retirement enablement:
1884          *    - If amdgpu_bad_page_threshold = -1,
1885          *      bad_page_cnt_threshold = typical value by formula.
1886          *
1887          *    - When the value from user is 0 < amdgpu_bad_page_threshold <
1888          *      max record length in eeprom, use it directly.
1889          *
1890          * Bad page retirement disablement:
1891          *    - If amdgpu_bad_page_threshold = 0, bad page retirement
1892          *      functionality is disabled, and bad_page_cnt_threshold will
1893          *      take no effect.
1894          */
1895
1896         if (tmp_threshold < -1)
1897                 tmp_threshold = -1;
1898         else if (tmp_threshold > max_length)
1899                 tmp_threshold = max_length;
1900
1901         if (tmp_threshold == -1) {
1902                 val = adev->gmc.mc_vram_size;
1903                 do_div(val, RAS_BAD_PAGE_RATE);
1904                 con->bad_page_cnt_threshold = min(lower_32_bits(val),
1905                                                 max_length);
1906         } else {
1907                 con->bad_page_cnt_threshold = tmp_threshold;
1908         }
1909 }
1910
1911 int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
1912 {
1913         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1914         struct ras_err_handler_data **data;
1915         uint32_t max_eeprom_records_len = 0;
1916         bool exc_err_limit = false;
1917         int ret;
1918
1919         if (adev->ras_features && con)
1920                 data = &con->eh_data;
1921         else
1922                 return 0;
1923
1924         *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
1925         if (!*data) {
1926                 ret = -ENOMEM;
1927                 goto out;
1928         }
1929
1930         mutex_init(&con->recovery_lock);
1931         INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
1932         atomic_set(&con->in_recovery, 0);
1933         con->adev = adev;
1934
1935         max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length();
1936         amdgpu_ras_validate_threshold(adev, max_eeprom_records_len);
1937
1938         /* Todo: During test the SMU might fail to read the eeprom through I2C
1939          * when the GPU is pending on XGMI reset during probe time
1940          * (Mostly after second bus reset), skip it now
1941          */
1942         if (adev->gmc.xgmi.pending_reset)
1943                 return 0;
1944         ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
1945         /*
1946          * This calling fails when exc_err_limit is true or
1947          * ret != 0.
1948          */
1949         if (exc_err_limit || ret)
1950                 goto free;
1951
1952         if (con->eeprom_control.num_recs) {
1953                 ret = amdgpu_ras_load_bad_pages(adev);
1954                 if (ret)
1955                         goto free;
1956         }
1957
1958         return 0;
1959
1960 free:
1961         kfree((*data)->bps);
1962         kfree(*data);
1963         con->eh_data = NULL;
1964 out:
1965         dev_warn(adev->dev, "Failed to initialize ras recovery!\n");
1966
1967         /*
1968          * Except error threshold exceeding case, other failure cases in this
1969          * function would not fail amdgpu driver init.
1970          */
1971         if (!exc_err_limit)
1972                 ret = 0;
1973         else
1974                 ret = -EINVAL;
1975
1976         return ret;
1977 }
1978
1979 static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
1980 {
1981         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1982         struct ras_err_handler_data *data = con->eh_data;
1983
1984         /* recovery_init failed to init it, fini is useless */
1985         if (!data)
1986                 return 0;
1987
1988         cancel_work_sync(&con->recovery_work);
1989
1990         mutex_lock(&con->recovery_lock);
1991         con->eh_data = NULL;
1992         kfree(data->bps);
1993         kfree(data);
1994         mutex_unlock(&con->recovery_lock);
1995
1996         return 0;
1997 }
1998 /* recovery end */
1999
2000 /* return 0 if ras will reset gpu and repost.*/
2001 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
2002                 unsigned int block)
2003 {
2004         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2005
2006         if (!ras)
2007                 return -EINVAL;
2008
2009         ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2010         return 0;
2011 }
2012
2013 static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2014 {
2015         return adev->asic_type == CHIP_VEGA10 ||
2016                 adev->asic_type == CHIP_VEGA20 ||
2017                 adev->asic_type == CHIP_ARCTURUS ||
2018                 adev->asic_type == CHIP_ALDEBARAN ||
2019                 adev->asic_type == CHIP_SIENNA_CICHLID;
2020 }
2021
2022 /*
2023  * check hardware's ras ability which will be saved in hw_supported.
2024  * if hardware does not support ras, we can skip some ras initializtion and
2025  * forbid some ras operations from IP.
2026  * if software itself, say boot parameter, limit the ras ability. We still
2027  * need allow IP do some limited operations, like disable. In such case,
2028  * we have to initialize ras as normal. but need check if operation is
2029  * allowed or not in each function.
2030  */
2031 static void amdgpu_ras_check_supported(struct amdgpu_device *adev,
2032                 uint32_t *hw_supported, uint32_t *supported)
2033 {
2034         *hw_supported = 0;
2035         *supported = 0;
2036
2037         if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw ||
2038             !amdgpu_ras_asic_supported(adev))
2039                 return;
2040
2041         if (!adev->gmc.xgmi.connected_to_cpu) {
2042                 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2043                         dev_info(adev->dev, "MEM ECC is active.\n");
2044                         *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC |
2045                                         1 << AMDGPU_RAS_BLOCK__DF);
2046                 } else {
2047                         dev_info(adev->dev, "MEM ECC is not presented.\n");
2048                 }
2049
2050                 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2051                         dev_info(adev->dev, "SRAM ECC is active.\n");
2052                         *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2053                                         1 << AMDGPU_RAS_BLOCK__DF);
2054                 } else {
2055                         dev_info(adev->dev, "SRAM ECC is not presented.\n");
2056                 }
2057         } else {
2058                 /* driver only manages a few IP blocks RAS feature
2059                  * when GPU is connected cpu through XGMI */
2060                 *hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX |
2061                                 1 << AMDGPU_RAS_BLOCK__SDMA |
2062                                 1 << AMDGPU_RAS_BLOCK__MMHUB);
2063         }
2064
2065         /* hw_supported needs to be aligned with RAS block mask. */
2066         *hw_supported &= AMDGPU_RAS_BLOCK_MASK;
2067
2068         *supported = amdgpu_ras_enable == 0 ?
2069                         0 : *hw_supported & amdgpu_ras_mask;
2070         adev->ras_features = *supported;
2071 }
2072
2073 int amdgpu_ras_init(struct amdgpu_device *adev)
2074 {
2075         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2076         int r;
2077
2078         if (con)
2079                 return 0;
2080
2081         con = kmalloc(sizeof(struct amdgpu_ras) +
2082                         sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT,
2083                         GFP_KERNEL|__GFP_ZERO);
2084         if (!con)
2085                 return -ENOMEM;
2086
2087         con->objs = (struct ras_manager *)(con + 1);
2088
2089         amdgpu_ras_set_context(adev, con);
2090
2091         amdgpu_ras_check_supported(adev, &con->hw_supported,
2092                         &con->supported);
2093         if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) {
2094                 /* set gfx block ras context feature for VEGA20 Gaming
2095                  * send ras disable cmd to ras ta during ras late init.
2096                  */
2097                 if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) {
2098                         con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2099
2100                         return 0;
2101                 }
2102
2103                 r = 0;
2104                 goto release_con;
2105         }
2106
2107         con->features = 0;
2108         INIT_LIST_HEAD(&con->head);
2109         /* Might need get this flag from vbios. */
2110         con->flags = RAS_DEFAULT_FLAGS;
2111
2112         /* initialize nbio ras function ahead of any other
2113          * ras functions so hardware fatal error interrupt
2114          * can be enabled as early as possible */
2115         switch (adev->asic_type) {
2116         case CHIP_VEGA20:
2117         case CHIP_ARCTURUS:
2118         case CHIP_ALDEBARAN:
2119                 if (!adev->gmc.xgmi.connected_to_cpu)
2120                         adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs;
2121                 break;
2122         default:
2123                 /* nbio ras is not available */
2124                 break;
2125         }
2126
2127         if (adev->nbio.ras_funcs &&
2128             adev->nbio.ras_funcs->init_ras_controller_interrupt) {
2129                 r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev);
2130                 if (r)
2131                         goto release_con;
2132         }
2133
2134         if (adev->nbio.ras_funcs &&
2135             adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) {
2136                 r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev);
2137                 if (r)
2138                         goto release_con;
2139         }
2140
2141         if (amdgpu_ras_fs_init(adev)) {
2142                 r = -EINVAL;
2143                 goto release_con;
2144         }
2145
2146         dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
2147                         "hardware ability[%x] ras_mask[%x]\n",
2148                         con->hw_supported, con->supported);
2149         return 0;
2150 release_con:
2151         amdgpu_ras_set_context(adev, NULL);
2152         kfree(con);
2153
2154         return r;
2155 }
2156
2157 static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2158 {
2159         if (adev->gmc.xgmi.connected_to_cpu)
2160                 return 1;
2161         return 0;
2162 }
2163
2164 static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2165                                         struct ras_common_if *ras_block)
2166 {
2167         struct ras_query_if info = {
2168                 .head = *ras_block,
2169         };
2170
2171         if (!amdgpu_persistent_edc_harvesting_supported(adev))
2172                 return 0;
2173
2174         if (amdgpu_ras_query_error_status(adev, &info) != 0)
2175                 DRM_WARN("RAS init harvest failure");
2176
2177         if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2178                 DRM_WARN("RAS init harvest reset failure");
2179
2180         return 0;
2181 }
2182
2183 /* helper function to handle common stuff in ip late init phase */
2184 int amdgpu_ras_late_init(struct amdgpu_device *adev,
2185                          struct ras_common_if *ras_block,
2186                          struct ras_fs_if *fs_info,
2187                          struct ras_ih_if *ih_info)
2188 {
2189         int r;
2190
2191         /* disable RAS feature per IP block if it is not supported */
2192         if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2193                 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2194                 return 0;
2195         }
2196
2197         r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2198         if (r) {
2199                 if (r == -EAGAIN) {
2200                         /* request gpu reset. will run again */
2201                         amdgpu_ras_request_reset_on_boot(adev,
2202                                         ras_block->block);
2203                         return 0;
2204                 } else if (adev->in_suspend || amdgpu_in_reset(adev)) {
2205                         /* in resume phase, if fail to enable ras,
2206                          * clean up all ras fs nodes, and disable ras */
2207                         goto cleanup;
2208                 } else
2209                         return r;
2210         }
2211
2212         /* check for errors on warm reset edc persisant supported ASIC */
2213         amdgpu_persistent_edc_harvesting(adev, ras_block);
2214
2215         /* in resume phase, no need to create ras fs node */
2216         if (adev->in_suspend || amdgpu_in_reset(adev))
2217                 return 0;
2218
2219         if (ih_info->cb) {
2220                 r = amdgpu_ras_interrupt_add_handler(adev, ih_info);
2221                 if (r)
2222                         goto interrupt;
2223         }
2224
2225         r = amdgpu_ras_sysfs_create(adev, fs_info);
2226         if (r)
2227                 goto sysfs;
2228
2229         return 0;
2230 cleanup:
2231         amdgpu_ras_sysfs_remove(adev, ras_block);
2232 sysfs:
2233         if (ih_info->cb)
2234                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2235 interrupt:
2236         amdgpu_ras_feature_enable(adev, ras_block, 0);
2237         return r;
2238 }
2239
2240 /* helper function to remove ras fs node and interrupt handler */
2241 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
2242                           struct ras_common_if *ras_block,
2243                           struct ras_ih_if *ih_info)
2244 {
2245         if (!ras_block || !ih_info)
2246                 return;
2247
2248         amdgpu_ras_sysfs_remove(adev, ras_block);
2249         if (ih_info->cb)
2250                 amdgpu_ras_interrupt_remove_handler(adev, ih_info);
2251         amdgpu_ras_feature_enable(adev, ras_block, 0);
2252 }
2253
2254 /* do some init work after IP late init as dependence.
2255  * and it runs in resume/gpu reset/booting up cases.
2256  */
2257 void amdgpu_ras_resume(struct amdgpu_device *adev)
2258 {
2259         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2260         struct ras_manager *obj, *tmp;
2261
2262         if (!adev->ras_features || !con) {
2263                 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2264                 amdgpu_release_ras_context(adev);
2265
2266                 return;
2267         }
2268
2269         if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
2270                 /* Set up all other IPs which are not implemented. There is a
2271                  * tricky thing that IP's actual ras error type should be
2272                  * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2273                  * ERROR_NONE make sense anyway.
2274                  */
2275                 amdgpu_ras_enable_all_features(adev, 1);
2276
2277                 /* We enable ras on all hw_supported block, but as boot
2278                  * parameter might disable some of them and one or more IP has
2279                  * not implemented yet. So we disable them on behalf.
2280                  */
2281                 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2282                         if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2283                                 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2284                                 /* there should be no any reference. */
2285                                 WARN_ON(alive_obj(obj));
2286                         }
2287                 }
2288         }
2289
2290         if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) {
2291                 con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET;
2292                 /* setup ras obj state as disabled.
2293                  * for init_by_vbios case.
2294                  * if we want to enable ras, just enable it in a normal way.
2295                  * If we want do disable it, need setup ras obj as enabled,
2296                  * then issue another TA disable cmd.
2297                  * See feature_enable_on_boot
2298                  */
2299                 amdgpu_ras_disable_all_features(adev, 1);
2300                 amdgpu_ras_reset_gpu(adev);
2301         }
2302 }
2303
2304 void amdgpu_ras_suspend(struct amdgpu_device *adev)
2305 {
2306         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2307
2308         if (!adev->ras_features || !con)
2309                 return;
2310
2311         amdgpu_ras_disable_all_features(adev, 0);
2312         /* Make sure all ras objects are disabled. */
2313         if (con->features)
2314                 amdgpu_ras_disable_all_features(adev, 1);
2315 }
2316
2317 /* do some fini work before IP fini as dependence */
2318 int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2319 {
2320         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2321
2322         if (!adev->ras_features || !con)
2323                 return 0;
2324
2325         /* Need disable ras on all IPs here before ip [hw/sw]fini */
2326         amdgpu_ras_disable_all_features(adev, 0);
2327         amdgpu_ras_recovery_fini(adev);
2328         return 0;
2329 }
2330
2331 int amdgpu_ras_fini(struct amdgpu_device *adev)
2332 {
2333         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2334
2335         if (!adev->ras_features || !con)
2336                 return 0;
2337
2338         amdgpu_ras_fs_fini(adev);
2339         amdgpu_ras_interrupt_remove_all(adev);
2340
2341         WARN(con->features, "Feature mask is not cleared");
2342
2343         if (con->features)
2344                 amdgpu_ras_disable_all_features(adev, 1);
2345
2346         amdgpu_ras_set_context(adev, NULL);
2347         kfree(con);
2348
2349         return 0;
2350 }
2351
2352 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2353 {
2354         uint32_t hw_supported, supported;
2355
2356         amdgpu_ras_check_supported(adev, &hw_supported, &supported);
2357         if (!hw_supported)
2358                 return;
2359
2360         if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2361                 dev_info(adev->dev, "uncorrectable hardware error"
2362                         "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
2363
2364                 amdgpu_ras_reset_gpu(adev);
2365         }
2366 }
2367
2368 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2369 {
2370         if (adev->asic_type == CHIP_VEGA20 &&
2371             adev->pm.fw_version <= 0x283400) {
2372                 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2373                                 amdgpu_ras_intr_triggered();
2374         }
2375
2376         return false;
2377 }
2378
2379 void amdgpu_release_ras_context(struct amdgpu_device *adev)
2380 {
2381         struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2382
2383         if (!con)
2384                 return;
2385
2386         if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
2387                 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2388                 amdgpu_ras_set_context(adev, NULL);
2389                 kfree(con);
2390         }
2391 }