drivers/staging/wilc1000/wilc_spi.c

   1 /* ////////////////////////////////////////////////////////////////////////// */
   2 /*  */
   3 /* Copyright (c) Atmel Corporation.  All rights reserved. */
   4 /*  */
   5 /* Module Name:  wilc_spi.c */
   6 /*  */
   7 /*  */
   8 /* //////////////////////////////////////////////////////////////////////////// */
   9 #include <linux/module.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/fs.h>
  13 #include <linux/slab.h>
  14 #include <linux/types.h>
  15 #include <linux/cdev.h>
  16 #include <linux/uaccess.h>
  17 #include <linux/device.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/of_gpio.h>
  20
  21 #include "linux_wlan_common.h"
  22 #include <linux/string.h>
  23 #include "wilc_wlan_if.h"
  24 #include "wilc_wlan.h"
  25 #include "wilc_wfi_netdevice.h"
  26
  27 typedef struct {
  28         int crc_off;
  29         int nint;
  30         int has_thrpt_enh;
  31 } wilc_spi_t;
  32
  33 static wilc_spi_t g_spi;
  34
  35 static int wilc_spi_read(struct wilc *wilc, u32, u8 *, u32);
  36 static int wilc_spi_write(struct wilc *wilc, u32, u8 *, u32);
  37
  38 /********************************************
  39  *
  40  *      Crc7
  41  *
  42  ********************************************/
  43
  44 static const u8 crc7_syndrome_table[256] = {
  45         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  46         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  47         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  48         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  49         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  50         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  51         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  52         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  53         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  54         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  55         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  56         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  57         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  58         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  59         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  60         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  61         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  62         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  63         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  64         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  65         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  66         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  67         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  68         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  69         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  70         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  71         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  72         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  73         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  74         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  75         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  76         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  77 };
  78
  79 static u8 crc7_byte(u8 crc, u8 data)
  80 {
  81         return crc7_syndrome_table[(crc << 1) ^ data];
  82 }
  83
  84 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
  85 {
  86         while (len--)
  87                 crc = crc7_byte(crc, *buffer++);
  88         return crc;
  89 }
  90
  91 /********************************************
  92  *
  93  *      Spi protocol Function
  94  *
  95  ********************************************/
  96
  97 #define CMD_DMA_WRITE                           0xc1
  98 #define CMD_DMA_READ                            0xc2
  99 #define CMD_INTERNAL_WRITE              0xc3
 100 #define CMD_INTERNAL_READ               0xc4
 101 #define CMD_TERMINATE                           0xc5
 102 #define CMD_REPEAT                                      0xc6
 103 #define CMD_DMA_EXT_WRITE               0xc7
 104 #define CMD_DMA_EXT_READ                0xc8
 105 #define CMD_SINGLE_WRITE                        0xc9
 106 #define CMD_SINGLE_READ                 0xca
 107 #define CMD_RESET                                               0xcf
 108
 109 #define N_OK                                                            1
 110 #define N_FAIL                                                          0
 111 #define N_RESET                                                 -1
 112 #define N_RETRY                                                 -2
 113
 114 #define DATA_PKT_SZ_256                         256
 115 #define DATA_PKT_SZ_512                 512
 116 #define DATA_PKT_SZ_1K                          1024
 117 #define DATA_PKT_SZ_4K                          (4 * 1024)
 118 #define DATA_PKT_SZ_8K                          (8 * 1024)
 119 #define DATA_PKT_SZ                                     DATA_PKT_SZ_8K
 120
 121 #define USE_SPI_DMA     0
 122
 123 static const struct wilc1000_ops wilc1000_spi_ops;
 124
 125 static int wilc_bus_probe(struct spi_device *spi)
 126 {
 127         int ret, gpio;
 128         struct wilc *wilc;
 129
 130         gpio = of_get_gpio(spi->dev.of_node, 0);
 131         if (gpio < 0)
 132                 gpio = GPIO_NUM;
 133
 134         ret = wilc_netdev_init(&wilc, NULL, HIF_SPI, GPIO_NUM, &wilc_hif_spi);
 135         if (ret)
 136                 return ret;
 137
 138         spi_set_drvdata(spi, wilc);
 139         wilc->dev = &spi->dev;
 140
 141         return 0;
 142 }
 143
 144 static int wilc_bus_remove(struct spi_device *spi)
 145 {
 146         wilc_netdev_cleanup(spi_get_drvdata(spi));
 147         return 0;
 148 }
 149
 150 static const struct of_device_id wilc1000_of_match[] = {
 151         { .compatible = "atmel,wilc_spi", },
 152         {}
 153 };
 154 MODULE_DEVICE_TABLE(of, wilc1000_of_match);
 155
 156 struct spi_driver wilc1000_spi_driver = {
 157         .driver = {
 158                 .name = MODALIAS,
 159                 .of_match_table = wilc1000_of_match,
 160         },
 161         .probe =  wilc_bus_probe,
 162         .remove = wilc_bus_remove,
 163 };
 164 module_spi_driver(wilc1000_spi_driver);
 165 MODULE_LICENSE("GPL");
 166
 167 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
 168 {
 169         struct spi_device *spi = to_spi_device(wilc->dev);
 170         int ret;
 171         struct spi_message msg;
 172
 173         if (len > 0 && b) {
 174                 struct spi_transfer tr = {
 175                         .tx_buf = b,
 176                         .len = len,
 177                         .delay_usecs = 0,
 178                 };
 179                 char *r_buffer = kzalloc(len, GFP_KERNEL);
 180
 181                 if (!r_buffer)
 182                         return -ENOMEM;
 183
 184                 tr.rx_buf = r_buffer;
 185                 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
 186
 187                 memset(&msg, 0, sizeof(msg));
 188                 spi_message_init(&msg);
 189                 msg.spi = spi;
 190                 msg.is_dma_mapped = USE_SPI_DMA;
 191                 spi_message_add_tail(&tr, &msg);
 192
 193                 ret = spi_sync(spi, &msg);
 194                 if (ret < 0)
 195                         dev_err(&spi->dev, "SPI transaction failed\n");
 196
 197                 kfree(r_buffer);
 198         } else {
 199                 dev_err(&spi->dev,
 200                         "can't write data with the following length: %d\n",
 201                         len);
 202                 dev_err(&spi->dev,
 203                         "FAILED due to NULL buffer or ZERO length check the following length: %d\n",
 204                         len);
 205                 ret = -EINVAL;
 206         }
 207
 208         return ret;
 209 }
 210
 211 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
 212 {
 213         struct spi_device *spi = to_spi_device(wilc->dev);
 214         int ret;
 215
 216         if (rlen > 0) {
 217                 struct spi_message msg;
 218                 struct spi_transfer tr = {
 219                         .rx_buf = rb,
 220                         .len = rlen,
 221                         .delay_usecs = 0,
 222
 223                 };
 224                 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
 225
 226                 if (!t_buffer)
 227                         return -ENOMEM;
 228
 229                 tr.tx_buf = t_buffer;
 230
 231                 memset(&msg, 0, sizeof(msg));
 232                 spi_message_init(&msg);
 233                 msg.spi = spi;
 234                 msg.is_dma_mapped = USE_SPI_DMA;
 235                 spi_message_add_tail(&tr, &msg);
 236
 237                 ret = spi_sync(spi, &msg);
 238                 if (ret < 0)
 239                         dev_err(&spi->dev, "SPI transaction failed\n");
 240                 kfree(t_buffer);
 241         } else {
 242                 dev_err(&spi->dev,
 243                         "can't read data with the following length: %u\n",
 244                         rlen);
 245                 ret = -EINVAL;
 246         }
 247
 248         return ret;
 249 }
 250
 251 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
 252 {
 253         struct spi_device *spi = to_spi_device(wilc->dev);
 254         int ret;
 255
 256         if (rlen > 0) {
 257                 struct spi_message msg;
 258                 struct spi_transfer tr = {
 259                         .rx_buf = rb,
 260                         .tx_buf = wb,
 261                         .len = rlen,
 262                         .bits_per_word = 8,
 263                         .delay_usecs = 0,
 264
 265                 };
 266
 267                 memset(&msg, 0, sizeof(msg));
 268                 spi_message_init(&msg);
 269                 msg.spi = spi;
 270                 msg.is_dma_mapped = USE_SPI_DMA;
 271
 272                 spi_message_add_tail(&tr, &msg);
 273                 ret = spi_sync(spi, &msg);
 274                 if (ret < 0)
 275                         dev_err(&spi->dev, "SPI transaction failed\n");
 276         } else {
 277                 dev_err(&spi->dev,
 278                         "can't read data with the following length: %u\n",
 279                         rlen);
 280                 ret = -EINVAL;
 281         }
 282
 283         return ret;
 284 }
 285
 286 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
 287                             u8 clockless)
 288 {
 289         struct spi_device *spi = to_spi_device(wilc->dev);
 290         u8 wb[32], rb[32];
 291         u8 wix, rix;
 292         u32 len2;
 293         u8 rsp;
 294         int len = 0;
 295         int result = N_OK;
 296
 297         wb[0] = cmd;
 298         switch (cmd) {
 299         case CMD_SINGLE_READ:                           /* single word (4 bytes) read */
 300                 wb[1] = (u8)(adr >> 16);
 301                 wb[2] = (u8)(adr >> 8);
 302                 wb[3] = (u8)adr;
 303                 len = 5;
 304                 break;
 305
 306         case CMD_INTERNAL_READ:                 /* internal register read */
 307                 wb[1] = (u8)(adr >> 8);
 308                 if (clockless == 1)
 309                         wb[1] |= BIT(7);
 310                 wb[2] = (u8)adr;
 311                 wb[3] = 0x00;
 312                 len = 5;
 313                 break;
 314
 315         case CMD_TERMINATE:                                     /* termination */
 316                 wb[1] = 0x00;
 317                 wb[2] = 0x00;
 318                 wb[3] = 0x00;
 319                 len = 5;
 320                 break;
 321
 322         case CMD_REPEAT:                                                /* repeat */
 323                 wb[1] = 0x00;
 324                 wb[2] = 0x00;
 325                 wb[3] = 0x00;
 326                 len = 5;
 327                 break;
 328
 329         case CMD_RESET:                                                 /* reset */
 330                 wb[1] = 0xff;
 331                 wb[2] = 0xff;
 332                 wb[3] = 0xff;
 333                 len = 5;
 334                 break;
 335
 336         case CMD_DMA_WRITE:                                     /* dma write */
 337         case CMD_DMA_READ:                                      /* dma read */
 338                 wb[1] = (u8)(adr >> 16);
 339                 wb[2] = (u8)(adr >> 8);
 340                 wb[3] = (u8)adr;
 341                 wb[4] = (u8)(sz >> 8);
 342                 wb[5] = (u8)(sz);
 343                 len = 7;
 344                 break;
 345
 346         case CMD_DMA_EXT_WRITE:         /* dma extended write */
 347         case CMD_DMA_EXT_READ:                  /* dma extended read */
 348                 wb[1] = (u8)(adr >> 16);
 349                 wb[2] = (u8)(adr >> 8);
 350                 wb[3] = (u8)adr;
 351                 wb[4] = (u8)(sz >> 16);
 352                 wb[5] = (u8)(sz >> 8);
 353                 wb[6] = (u8)(sz);
 354                 len = 8;
 355                 break;
 356
 357         case CMD_INTERNAL_WRITE:                /* internal register write */
 358                 wb[1] = (u8)(adr >> 8);
 359                 if (clockless == 1)
 360                         wb[1] |= BIT(7);
 361                 wb[2] = (u8)(adr);
 362                 wb[3] = b[3];
 363                 wb[4] = b[2];
 364                 wb[5] = b[1];
 365                 wb[6] = b[0];
 366                 len = 8;
 367                 break;
 368
 369         case CMD_SINGLE_WRITE:                  /* single word write */
 370                 wb[1] = (u8)(adr >> 16);
 371                 wb[2] = (u8)(adr >> 8);
 372                 wb[3] = (u8)(adr);
 373                 wb[4] = b[3];
 374                 wb[5] = b[2];
 375                 wb[6] = b[1];
 376                 wb[7] = b[0];
 377                 len = 9;
 378                 break;
 379
 380         default:
 381                 result = N_FAIL;
 382                 break;
 383         }
 384
 385         if (result != N_OK) {
 386                 return result;
 387         }
 388
 389         if (!g_spi.crc_off)
 390                 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
 391         else
 392                 len -= 1;
 393
 394 #define NUM_SKIP_BYTES (1)
 395 #define NUM_RSP_BYTES (2)
 396 #define NUM_DATA_HDR_BYTES (1)
 397 #define NUM_DATA_BYTES (4)
 398 #define NUM_CRC_BYTES (2)
 399 #define NUM_DUMMY_BYTES (3)
 400         if ((cmd == CMD_RESET) ||
 401             (cmd == CMD_TERMINATE) ||
 402             (cmd == CMD_REPEAT)) {
 403                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 404         } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 405                 if (!g_spi.crc_off) {
 406                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 407                                       + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
 408                 } else {
 409                         len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 410                                       + NUM_DUMMY_BYTES);
 411                 }
 412         } else {
 413                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 414         }
 415 #undef NUM_DUMMY_BYTES
 416
 417         if (len2 > ARRAY_SIZE(wb)) {
 418                 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
 419                          len2, ARRAY_SIZE(wb));
 420                 result = N_FAIL;
 421                 return result;
 422         }
 423         /* zero spi write buffers. */
 424         for (wix = len; wix < len2; wix++) {
 425                 wb[wix] = 0;
 426         }
 427         rix = len;
 428
 429         if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
 430                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 431                 result = N_FAIL;
 432                 return result;
 433         }
 434
 435         /**
 436          * Command/Control response
 437          **/
 438         if ((cmd == CMD_RESET) ||
 439             (cmd == CMD_TERMINATE) ||
 440             (cmd == CMD_REPEAT)) {
 441                 rix++;         /* skip 1 byte */
 442         }
 443
 444         /* do { */
 445         rsp = rb[rix++];
 446         /*      if(rsp == cmd) break; */
 447         /* } while(&rptr[1] <= &rb[len2]); */
 448
 449         if (rsp != cmd) {
 450                 dev_err(&spi->dev, "Failed cmd response, cmd (%02x)"
 451                          ", resp (%02x)\n", cmd, rsp);
 452                 result = N_FAIL;
 453                 return result;
 454         }
 455
 456         /**
 457          * State response
 458          **/
 459         rsp = rb[rix++];
 460         if (rsp != 0x00) {
 461                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 462                         rsp);
 463                 result = N_FAIL;
 464                 return result;
 465         }
 466
 467         if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
 468             || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 469                 int retry;
 470                 /* u16 crc1, crc2; */
 471                 u8 crc[2];
 472                 /**
 473                  * Data Respnose header
 474                  **/
 475                 retry = 100;
 476                 do {
 477                         /* ensure there is room in buffer later to read data and crc */
 478                         if (rix < len2) {
 479                                 rsp = rb[rix++];
 480                         } else {
 481                                 retry = 0;
 482                                 break;
 483                         }
 484                         if (((rsp >> 4) & 0xf) == 0xf)
 485                                 break;
 486                 } while (retry--);
 487
 488                 if (retry <= 0) {
 489                         dev_err(&spi->dev,
 490                                 "Error, data read response (%02x)\n", rsp);
 491                         result = N_RESET;
 492                         return result;
 493                 }
 494
 495                 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
 496                         /**
 497                          * Read bytes
 498                          **/
 499                         if ((rix + 3) < len2) {
 500                                 b[0] = rb[rix++];
 501                                 b[1] = rb[rix++];
 502                                 b[2] = rb[rix++];
 503                                 b[3] = rb[rix++];
 504                         } else {
 505                                 dev_err(&spi->dev,
 506                                         "buffer overrun when reading data.\n");
 507                                 result = N_FAIL;
 508                                 return result;
 509                         }
 510
 511                         if (!g_spi.crc_off) {
 512                                 /**
 513                                  * Read Crc
 514                                  **/
 515                                 if ((rix + 1) < len2) {
 516                                         crc[0] = rb[rix++];
 517                                         crc[1] = rb[rix++];
 518                                 } else {
 519                                         dev_err(&spi->dev,"buffer overrun when reading crc.\n");
 520                                         result = N_FAIL;
 521                                         return result;
 522                                 }
 523                         }
 524                 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 525                         int ix;
 526
 527                         /* some data may be read in response to dummy bytes. */
 528                         for (ix = 0; (rix < len2) && (ix < sz); ) {
 529                                 b[ix++] = rb[rix++];
 530                         }
 531
 532                         sz -= ix;
 533
 534                         if (sz > 0) {
 535                                 int nbytes;
 536
 537                                 if (sz <= (DATA_PKT_SZ - ix))
 538                                         nbytes = sz;
 539                                 else
 540                                         nbytes = DATA_PKT_SZ - ix;
 541
 542                                 /**
 543                                  * Read bytes
 544                                  **/
 545                                 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 546                                         dev_err(&spi->dev, "Failed data block read, bus error...\n");
 547                                         result = N_FAIL;
 548                                         goto _error_;
 549                                 }
 550
 551                                 /**
 552                                  * Read Crc
 553                                  **/
 554                                 if (!g_spi.crc_off) {
 555                                         if (wilc_spi_rx(wilc, crc, 2)) {
 556                                                 dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
 557                                                 result = N_FAIL;
 558                                                 goto _error_;
 559                                         }
 560                                 }
 561
 562
 563                                 ix += nbytes;
 564                                 sz -= nbytes;
 565                         }
 566
 567                         /*  if any data in left unread, then read the rest using normal DMA code.*/
 568                         while (sz > 0) {
 569                                 int nbytes;
 570
 571                                 if (sz <= DATA_PKT_SZ)
 572                                         nbytes = sz;
 573                                 else
 574                                         nbytes = DATA_PKT_SZ;
 575
 576                                 /**
 577                                  * read data response only on the next DMA cycles not
 578                                  * the first DMA since data response header is already
 579                                  * handled above for the first DMA.
 580                                  **/
 581                                 /**
 582                                  * Data Respnose header
 583                                  **/
 584                                 retry = 10;
 585                                 do {
 586                                         if (wilc_spi_rx(wilc, &rsp, 1)) {
 587                                                 dev_err(&spi->dev, "Failed data response read, bus error...\n");
 588                                                 result = N_FAIL;
 589                                                 break;
 590                                         }
 591                                         if (((rsp >> 4) & 0xf) == 0xf)
 592                                                 break;
 593                                 } while (retry--);
 594
 595                                 if (result == N_FAIL)
 596                                         break;
 597
 598
 599                                 /**
 600                                  * Read bytes
 601                                  **/
 602                                 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 603                                         dev_err(&spi->dev, "Failed data block read, bus error...\n");
 604                                         result = N_FAIL;
 605                                         break;
 606                                 }
 607
 608                                 /**
 609                                  * Read Crc
 610                                  **/
 611                                 if (!g_spi.crc_off) {
 612                                         if (wilc_spi_rx(wilc, crc, 2)) {
 613                                                 dev_err(&spi->dev, "Failed data block crc read, bus error...\n");
 614                                                 result = N_FAIL;
 615                                                 break;
 616                                         }
 617                                 }
 618
 619                                 ix += nbytes;
 620                                 sz -= nbytes;
 621                         }
 622                 }
 623         }
 624 _error_:
 625         return result;
 626 }
 627
 628 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
 629 {
 630         struct spi_device *spi = to_spi_device(wilc->dev);
 631         int ix, nbytes;
 632         int result = 1;
 633         u8 cmd, order, crc[2] = {0};
 634         /* u8 rsp; */
 635
 636         /**
 637          *      Data
 638          **/
 639         ix = 0;
 640         do {
 641                 if (sz <= DATA_PKT_SZ)
 642                         nbytes = sz;
 643                 else
 644                         nbytes = DATA_PKT_SZ;
 645
 646                 /**
 647                  *      Write command
 648                  **/
 649                 cmd = 0xf0;
 650                 if (ix == 0) {
 651                         if (sz <= DATA_PKT_SZ)
 652
 653                                 order = 0x3;
 654                         else
 655                                 order = 0x1;
 656                 } else {
 657                         if (sz <= DATA_PKT_SZ)
 658                                 order = 0x3;
 659                         else
 660                                 order = 0x2;
 661                 }
 662                 cmd |= order;
 663                 if (wilc_spi_tx(wilc, &cmd, 1)) {
 664                         dev_err(&spi->dev,
 665                                 "Failed data block cmd write, bus error...\n");
 666                         result = N_FAIL;
 667                         break;
 668                 }
 669
 670                 /**
 671                  *      Write data
 672                  **/
 673                 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
 674                         dev_err(&spi->dev,
 675                                 "Failed data block write, bus error...\n");
 676                         result = N_FAIL;
 677                         break;
 678                 }
 679
 680                 /**
 681                  *      Write Crc
 682                  **/
 683                 if (!g_spi.crc_off) {
 684                         if (wilc_spi_tx(wilc, crc, 2)) {
 685                                 dev_err(&spi->dev,"Failed data block crc write, bus error...\n");
 686                                 result = N_FAIL;
 687                                 break;
 688                         }
 689                 }
 690
 691                 /**
 692                  *      No need to wait for response
 693                  **/
 694                 ix += nbytes;
 695                 sz -= nbytes;
 696         } while (sz);
 697
 698
 699         return result;
 700 }
 701
 702 /********************************************
 703  *
 704  *      Spi Internal Read/Write Function
 705  *
 706  ********************************************/
 707
 708 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
 709 {
 710         struct spi_device *spi = to_spi_device(wilc->dev);
 711         int result;
 712
 713         dat = cpu_to_le32(dat);
 714         result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
 715                                   0);
 716         if (result != N_OK) {
 717                 dev_err(&spi->dev, "Failed internal write cmd...\n");
 718         }
 719
 720         return result;
 721 }
 722
 723 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
 724 {
 725         struct spi_device *spi = to_spi_device(wilc->dev);
 726         int result;
 727
 728         result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
 729                                   0);
 730         if (result != N_OK) {
 731                 dev_err(&spi->dev, "Failed internal read cmd...\n");
 732                 return 0;
 733         }
 734
 735         *data = cpu_to_le32(*data);
 736
 737         return 1;
 738 }
 739
 740 /********************************************
 741  *
 742  *      Spi interfaces
 743  *
 744  ********************************************/
 745
 746 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
 747 {
 748         struct spi_device *spi = to_spi_device(wilc->dev);
 749         int result = N_OK;
 750         u8 cmd = CMD_SINGLE_WRITE;
 751         u8 clockless = 0;
 752
 753         data = cpu_to_le32(data);
 754         if (addr < 0x30) {
 755                 /* Clockless register*/
 756                 cmd = CMD_INTERNAL_WRITE;
 757                 clockless = 1;
 758         }
 759
 760         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
 761         if (result != N_OK) {
 762                 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
 763         }
 764
 765         return result;
 766 }
 767
 768 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 769 {
 770         struct spi_device *spi = to_spi_device(wilc->dev);
 771         int result;
 772         u8 cmd = CMD_DMA_EXT_WRITE;
 773
 774         /**
 775          *      has to be greated than 4
 776          **/
 777         if (size <= 4)
 778                 return 0;
 779
 780         result = spi_cmd_complete(wilc, cmd, addr, NULL, size, 0);
 781         if (result != N_OK) {
 782                 dev_err(&spi->dev,
 783                         "Failed cmd, write block (%08x)...\n", addr);
 784                 return 0;
 785         }
 786
 787         /**
 788          *      Data
 789          **/
 790         result = spi_data_write(wilc, buf, size);
 791         if (result != N_OK) {
 792                 dev_err(&spi->dev, "Failed block data write...\n");
 793         }
 794
 795         return 1;
 796 }
 797
 798 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
 799 {
 800         struct spi_device *spi = to_spi_device(wilc->dev);
 801         int result = N_OK;
 802         u8 cmd = CMD_SINGLE_READ;
 803         u8 clockless = 0;
 804
 805         if (addr < 0x30) {
 806                 /* dev_err(&spi->dev, "***** read addr %d\n\n", addr); */
 807                 /* Clockless register*/
 808                 cmd = CMD_INTERNAL_READ;
 809                 clockless = 1;
 810         }
 811
 812         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
 813         if (result != N_OK) {
 814                 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
 815                 return 0;
 816         }
 817
 818         *data = cpu_to_le32(*data);
 819
 820         return 1;
 821 }
 822
 823 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 824 {
 825         struct spi_device *spi = to_spi_device(wilc->dev);
 826         u8 cmd = CMD_DMA_EXT_READ;
 827         int result;
 828
 829         if (size <= 4)
 830                 return 0;
 831
 832         result = spi_cmd_complete(wilc, cmd, addr, buf, size, 0);
 833         if (result != N_OK) {
 834                 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
 835                 return 0;
 836         }
 837
 838         return 1;
 839 }
 840
 841 /********************************************
 842  *
 843  *      Bus interfaces
 844  *
 845  ********************************************/
 846
 847 static int _wilc_spi_deinit(struct wilc *wilc)
 848 {
 849         /**
 850          *      TODO:
 851          **/
 852         return 1;
 853 }
 854
 855 static int wilc_spi_init(struct wilc *wilc)
 856 {
 857         struct spi_device *spi = to_spi_device(wilc->dev);
 858         u32 reg;
 859         u32 chipid;
 860
 861         static int isinit;
 862
 863         if (isinit) {
 864
 865                 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 866                         dev_err(&spi->dev, "Fail cmd read chip id...\n");
 867                         return 0;
 868                 }
 869                 return 1;
 870         }
 871
 872         memset(&g_spi, 0, sizeof(wilc_spi_t));
 873
 874         /**
 875          *      configure protocol
 876          **/
 877         g_spi.crc_off = 0;
 878
 879         /* TODO: We can remove the CRC trials if there is a definite way to reset */
 880         /* the SPI to it's initial value. */
 881         if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 882                 /* Read failed. Try with CRC off. This might happen when module
 883                  * is removed but chip isn't reset*/
 884                 g_spi.crc_off = 1;
 885                 dev_err(&spi->dev, "Failed internal read protocol with CRC on, retyring with CRC off...\n");
 886                 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 887                         /* Reaad failed with both CRC on and off, something went bad */
 888                         dev_err(&spi->dev,
 889                                 "Failed internal read protocol...\n");
 890                         return 0;
 891                 }
 892         }
 893         if (g_spi.crc_off == 0) {
 894                 reg &= ~0xc;    /* disable crc checking */
 895                 reg &= ~0x70;
 896                 reg |= (0x5 << 4);
 897                 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
 898                         dev_err(&spi->dev, "[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
 899                         return 0;
 900                 }
 901                 g_spi.crc_off = 1;
 902         }
 903
 904
 905         /**
 906          *      make sure can read back chip id correctly
 907          **/
 908         if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 909                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
 910                 return 0;
 911         }
 912         /* dev_err(&spi->dev, "chipid (%08x)\n", chipid); */
 913
 914         g_spi.has_thrpt_enh = 1;
 915
 916         isinit = 1;
 917
 918         return 1;
 919 }
 920
 921 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
 922 {
 923         struct spi_device *spi = to_spi_device(wilc->dev);
 924         int ret;
 925
 926         if (g_spi.has_thrpt_enh) {
 927                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 928                                         size);
 929                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
 930         } else {
 931                 u32 tmp;
 932                 u32 byte_cnt;
 933
 934                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 935                                         &byte_cnt);
 936                 if (!ret) {
 937                         dev_err(&spi->dev,
 938                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 939                         goto _fail_;
 940                 }
 941                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 942                 *size = tmp;
 943         }
 944
 945
 946
 947 _fail_:
 948         return ret;
 949 }
 950
 951
 952
 953 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
 954 {
 955         struct spi_device *spi = to_spi_device(wilc->dev);
 956         int ret;
 957
 958         if (g_spi.has_thrpt_enh) {
 959                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 960                                         int_status);
 961         } else {
 962                 u32 tmp;
 963                 u32 byte_cnt;
 964
 965                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 966                                         &byte_cnt);
 967                 if (!ret) {
 968                         dev_err(&spi->dev,
 969                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 970                         goto _fail_;
 971                 }
 972                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 973
 974                 {
 975                         int happended, j;
 976
 977                         j = 0;
 978                         do {
 979                                 u32 irq_flags;
 980
 981                                 happended = 0;
 982
 983                                 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
 984                                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
 985
 986                                 if (g_spi.nint > 5) {
 987                                         wilc_spi_read_reg(wilc, 0x1a94,
 988                                                           &irq_flags);
 989                                         tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
 990                                 }
 991
 992                                 {
 993                                         u32 unkmown_mask;
 994
 995                                         unkmown_mask = ~((1ul << g_spi.nint) - 1);
 996
 997                                         if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
 998                                                 dev_err(&spi->dev, "Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
 999                                                 happended = 1;
1000                                         }
1001                                 }
1002                                 j++;
1003                         } while (happended);
1004                 }
1005
1006                 *int_status = tmp;
1007
1008         }
1009
1010 _fail_:
1011         return ret;
1012 }
1013
1014 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1015 {
1016         struct spi_device *spi = to_spi_device(wilc->dev);
1017         int ret;
1018
1019         if (g_spi.has_thrpt_enh) {
1020                 ret = spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
1021                                          val);
1022         } else {
1023                 u32 flags;
1024
1025                 flags = val & (BIT(MAX_NUM_INT) - 1);
1026                 if (flags) {
1027                         int i;
1028
1029                         ret = 1;
1030                         for (i = 0; i < g_spi.nint; i++) {
1031                                 /* No matter what you write 1 or 0, it will clear interrupt. */
1032                                 if (flags & 1)
1033                                         ret = wilc_spi_write_reg(wilc, 0x10c8 + i * 4, 1);
1034                                 if (!ret)
1035                                         break;
1036                                 flags >>= 1;
1037                         }
1038                         if (!ret) {
1039                                 dev_err(&spi->dev,
1040                                         "Failed wilc_spi_write_reg, set reg %x ...\n",
1041                                         0x10c8 + i * 4);
1042                                 goto _fail_;
1043                         }
1044                         for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1045                                 if (flags & 1)
1046                                         dev_err(&spi->dev,
1047                                                 "Unexpected interrupt cleared %d...\n",
1048                                                 i);
1049                                 flags >>= 1;
1050                         }
1051                 }
1052
1053                 {
1054                         u32 tbl_ctl;
1055
1056                         tbl_ctl = 0;
1057                         /* select VMM table 0 */
1058                         if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1059                                 tbl_ctl |= BIT(0);
1060                         /* select VMM table 1 */
1061                         if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1062                                 tbl_ctl |= BIT(1);
1063
1064                         ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL,
1065                                                  tbl_ctl);
1066                         if (!ret) {
1067                                 dev_err(&spi->dev,
1068                                         "fail write reg vmm_tbl_ctl...\n");
1069                                 goto _fail_;
1070                         }
1071
1072                         if ((val & EN_VMM) == EN_VMM) {
1073                                 /**
1074                                  *      enable vmm transfer.
1075                                  **/
1076                                 ret = wilc_spi_write_reg(wilc,
1077                                                          WILC_VMM_CORE_CTL, 1);
1078                                 if (!ret) {
1079                                         dev_err(&spi->dev,"fail write reg vmm_core_ctl...\n");
1080                                         goto _fail_;
1081                                 }
1082                         }
1083                 }
1084         }
1085 _fail_:
1086         return ret;
1087 }
1088
1089 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1090 {
1091         struct spi_device *spi = to_spi_device(wilc->dev);
1092         u32 reg;
1093         int ret, i;
1094
1095         if (nint > MAX_NUM_INT) {
1096                 dev_err(&spi->dev, "Too many interupts (%d)...\n", nint);
1097                 return 0;
1098         }
1099
1100         g_spi.nint = nint;
1101
1102         /**
1103          *      interrupt pin mux select
1104          **/
1105         ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1106         if (!ret) {
1107                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1108                         WILC_PIN_MUX_0);
1109                 return 0;
1110         }
1111         reg |= BIT(8);
1112         ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1113         if (!ret) {
1114                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1115                         WILC_PIN_MUX_0);
1116                 return 0;
1117         }
1118
1119         /**
1120          *      interrupt enable
1121          **/
1122         ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1123         if (!ret) {
1124                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1125                         WILC_INTR_ENABLE);
1126                 return 0;
1127         }
1128
1129         for (i = 0; (i < 5) && (nint > 0); i++, nint--) {
1130                 reg |= (BIT((27 + i)));
1131         }
1132         ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1133         if (!ret) {
1134                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1135                         WILC_INTR_ENABLE);
1136                 return 0;
1137         }
1138         if (nint) {
1139                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1140                 if (!ret) {
1141                         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1142                                 WILC_INTR2_ENABLE);
1143                         return 0;
1144                 }
1145
1146                 for (i = 0; (i < 3) && (nint > 0); i++, nint--) {
1147                         reg |= BIT(i);
1148                 }
1149
1150                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1151                 if (!ret) {
1152                         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1153                                 WILC_INTR2_ENABLE);
1154                         return 0;
1155                 }
1156         }
1157
1158         return 1;
1159 }
1160 /********************************************
1161  *
1162  *      Global spi HIF function table
1163  *
1164  ********************************************/
1165 const struct wilc_hif_func wilc_hif_spi = {
1166         .hif_init = wilc_spi_init,
1167         .hif_deinit = _wilc_spi_deinit,
1168         .hif_read_reg = wilc_spi_read_reg,
1169         .hif_write_reg = wilc_spi_write_reg,
1170         .hif_block_rx = wilc_spi_read,
1171         .hif_block_tx = wilc_spi_write,
1172         .hif_read_int = wilc_spi_read_int,
1173         .hif_clear_int_ext = wilc_spi_clear_int_ext,
1174         .hif_read_size = wilc_spi_read_size,
1175         .hif_block_tx_ext = wilc_spi_write,
1176         .hif_block_rx_ext = wilc_spi_read,
1177         .hif_sync_ext = wilc_spi_sync_ext,
1178 };