drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/module.h>
   8 #include <linux/of.h>
   9 #include <linux/usb/of.h>
  10 #include <linux/pci_ids.h>
  11 #include <linux/pci.h>
  12
  13 #include "core.h"
  14
  15 #define PCI_PRODUCT_ID_HAPS_HSOTG       0xabc0
  16 #define PCI_DEVICE_ID_LOONGSON_DWC2     0x7a04
  17
  18 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  19 {
  20         struct dwc2_core_params *p = &hsotg->params;
  21
  22         p->host_rx_fifo_size = 774;
  23         p->max_transfer_size = 65535;
  24         p->max_packet_count = 511;
  25         p->ahbcfg = 0x10;
  26         p->no_clock_gating = true;
  27 }
  28
  29 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  30 {
  31         struct dwc2_core_params *p = &hsotg->params;
  32
  33         p->otg_caps.hnp_support = false;
  34         p->otg_caps.srp_support = false;
  35         p->speed = DWC2_SPEED_PARAM_HIGH;
  36         p->host_rx_fifo_size = 512;
  37         p->host_nperio_tx_fifo_size = 512;
  38         p->host_perio_tx_fifo_size = 512;
  39         p->max_transfer_size = 65535;
  40         p->max_packet_count = 511;
  41         p->host_channels = 16;
  42         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  43         p->phy_utmi_width = 8;
  44         p->i2c_enable = false;
  45         p->reload_ctl = false;
  46         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  47                 GAHBCFG_HBSTLEN_SHIFT;
  48         p->change_speed_quirk = true;
  49         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
  50 }
  51
  52 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg)
  53 {
  54         struct dwc2_core_params *p = &hsotg->params;
  55
  56         p->otg_caps.hnp_support = false;
  57         p->speed = DWC2_SPEED_PARAM_HIGH;
  58         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  59         p->phy_utmi_width = 16;
  60         p->activate_ingenic_overcurrent_detection =
  61                 !device_property_read_bool(hsotg->dev, "disable-over-current");
  62 }
  63
  64 static void dwc2_set_loongson_params(struct dwc2_hsotg *hsotg)
  65 {
  66         struct dwc2_core_params *p = &hsotg->params;
  67
  68         p->phy_utmi_width = 8;
  69         p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL;
  70 }
  71
  72 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg)
  73 {
  74         struct dwc2_core_params *p = &hsotg->params;
  75
  76         p->otg_caps.hnp_support = false;
  77         p->speed = DWC2_SPEED_PARAM_HIGH;
  78         p->host_channels = 16;
  79         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  80         p->phy_utmi_width = 16;
  81         p->activate_ingenic_overcurrent_detection =
  82                 !device_property_read_bool(hsotg->dev, "disable-over-current");
  83 }
  84
  85 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg)
  86 {
  87         struct dwc2_core_params *p = &hsotg->params;
  88
  89         p->otg_caps.hnp_support = false;
  90         p->speed = DWC2_SPEED_PARAM_HIGH;
  91         p->host_rx_fifo_size = 1024;
  92         p->host_nperio_tx_fifo_size = 1024;
  93         p->host_perio_tx_fifo_size = 1024;
  94         p->host_channels = 16;
  95         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  96         p->phy_utmi_width = 16;
  97         p->activate_ingenic_overcurrent_detection =
  98                 !device_property_read_bool(hsotg->dev, "disable-over-current");
  99 }
 100
 101 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
 102 {
 103         struct dwc2_core_params *p = &hsotg->params;
 104
 105         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 106         p->no_clock_gating = true;
 107         p->phy_utmi_width = 8;
 108 }
 109
 110 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
 111 {
 112         struct dwc2_core_params *p = &hsotg->params;
 113
 114         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 115         p->no_clock_gating = true;
 116 }
 117
 118 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
 119 {
 120         struct dwc2_core_params *p = &hsotg->params;
 121
 122         p->otg_caps.hnp_support = false;
 123         p->otg_caps.srp_support = false;
 124         p->host_rx_fifo_size = 525;
 125         p->host_nperio_tx_fifo_size = 128;
 126         p->host_perio_tx_fifo_size = 256;
 127         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 128                 GAHBCFG_HBSTLEN_SHIFT;
 129         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 130         p->lpm = false;
 131         p->lpm_clock_gating = false;
 132         p->besl = false;
 133         p->hird_threshold_en = false;
 134         p->no_clock_gating = true;
 135 }
 136
 137 static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)
 138 {
 139         struct dwc2_core_params *p = &hsotg->params;
 140
 141         p->otg_caps.hnp_support = false;
 142         p->otg_caps.srp_support = false;
 143 }
 144
 145 static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)
 146 {
 147         struct dwc2_core_params *p = &hsotg->params;
 148
 149         p->otg_caps.hnp_support = false;
 150         p->otg_caps.srp_support = false;
 151         p->host_rx_fifo_size = 288;
 152         p->host_nperio_tx_fifo_size = 128;
 153         p->host_perio_tx_fifo_size = 96;
 154         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
 155                 GAHBCFG_HBSTLEN_SHIFT;
 156 }
 157
 158 static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)
 159 {
 160         struct dwc2_core_params *p = &hsotg->params;
 161
 162         p->otg_caps.hnp_support = false;
 163         p->otg_caps.srp_support = false;
 164         p->host_rx_fifo_size = 288;
 165         p->host_nperio_tx_fifo_size = 128;
 166         p->host_perio_tx_fifo_size = 136;
 167 }
 168
 169 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 170 {
 171         struct dwc2_core_params *p = &hsotg->params;
 172
 173         p->otg_caps.hnp_support = false;
 174         p->otg_caps.srp_support = false;
 175         p->speed = DWC2_SPEED_PARAM_HIGH;
 176         p->host_rx_fifo_size = 512;
 177         p->host_nperio_tx_fifo_size = 500;
 178         p->host_perio_tx_fifo_size = 500;
 179         p->host_channels = 16;
 180         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 181         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 182                 GAHBCFG_HBSTLEN_SHIFT;
 183         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 184 }
 185
 186 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
 187 {
 188         struct dwc2_core_params *p = &hsotg->params;
 189
 190         p->lpm = false;
 191         p->lpm_clock_gating = false;
 192         p->besl = false;
 193         p->hird_threshold_en = false;
 194 }
 195
 196 static void dwc2_set_amlogic_a1_params(struct dwc2_hsotg *hsotg)
 197 {
 198         struct dwc2_core_params *p = &hsotg->params;
 199
 200         p->otg_caps.hnp_support = false;
 201         p->otg_caps.srp_support = false;
 202         p->speed = DWC2_SPEED_PARAM_HIGH;
 203         p->host_rx_fifo_size = 192;
 204         p->host_nperio_tx_fifo_size = 128;
 205         p->host_perio_tx_fifo_size = 128;
 206         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 207         p->phy_utmi_width = 8;
 208         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT;
 209         p->lpm = false;
 210         p->lpm_clock_gating = false;
 211         p->besl = false;
 212         p->hird_threshold_en = false;
 213 }
 214
 215 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 216 {
 217         struct dwc2_core_params *p = &hsotg->params;
 218
 219         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 220 }
 221
 222 static void dwc2_set_cv1800_params(struct dwc2_hsotg *hsotg)
 223 {
 224         struct dwc2_core_params *p = &hsotg->params;
 225
 226         p->otg_caps.hnp_support = false;
 227         p->otg_caps.srp_support = false;
 228         p->host_dma = false;
 229         p->g_dma = false;
 230         p->speed = DWC2_SPEED_PARAM_HIGH;
 231         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 232         p->phy_utmi_width = 16;
 233         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 234         p->lpm = false;
 235         p->lpm_clock_gating = false;
 236         p->besl = false;
 237         p->hird_threshold_en = false;
 238         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 239 }
 240
 241 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 242 {
 243         struct dwc2_core_params *p = &hsotg->params;
 244
 245         p->otg_caps.hnp_support = false;
 246         p->otg_caps.srp_support = false;
 247         p->speed = DWC2_SPEED_PARAM_FULL;
 248         p->host_rx_fifo_size = 128;
 249         p->host_nperio_tx_fifo_size = 96;
 250         p->host_perio_tx_fifo_size = 96;
 251         p->max_packet_count = 256;
 252         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 253         p->i2c_enable = false;
 254         p->activate_stm_fs_transceiver = true;
 255 }
 256
 257 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 258 {
 259         struct dwc2_core_params *p = &hsotg->params;
 260
 261         p->host_rx_fifo_size = 622;
 262         p->host_nperio_tx_fifo_size = 128;
 263         p->host_perio_tx_fifo_size = 256;
 264 }
 265
 266 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
 267 {
 268         struct dwc2_core_params *p = &hsotg->params;
 269
 270         p->otg_caps.hnp_support = false;
 271         p->otg_caps.srp_support = false;
 272         p->otg_caps.otg_rev = 0x200;
 273         p->speed = DWC2_SPEED_PARAM_FULL;
 274         p->host_rx_fifo_size = 128;
 275         p->host_nperio_tx_fifo_size = 96;
 276         p->host_perio_tx_fifo_size = 96;
 277         p->max_packet_count = 256;
 278         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 279         p->i2c_enable = false;
 280         p->activate_stm_fs_transceiver = true;
 281         p->activate_stm_id_vb_detection = true;
 282         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 283         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 284         p->host_support_fs_ls_low_power = true;
 285         p->host_ls_low_power_phy_clk = true;
 286 }
 287
 288 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
 289 {
 290         struct dwc2_core_params *p = &hsotg->params;
 291
 292         p->otg_caps.hnp_support = false;
 293         p->otg_caps.srp_support = false;
 294         p->otg_caps.otg_rev = 0x200;
 295         p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
 296         p->host_rx_fifo_size = 440;
 297         p->host_nperio_tx_fifo_size = 256;
 298         p->host_perio_tx_fifo_size = 256;
 299         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 300         p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 301         p->lpm = false;
 302         p->lpm_clock_gating = false;
 303         p->besl = false;
 304         p->hird_threshold_en = false;
 305 }
 306
 307 const struct of_device_id dwc2_of_match_table[] = {
 308         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 309         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
 310         { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params },
 311         { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params },
 312         { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params },
 313         { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params },
 314         { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params },
 315         { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params },
 316         { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params },
 317         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 318         { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
 319         { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
 320         { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
 321         { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
 322         { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
 323         { .compatible = "snps,dwc2" },
 324         { .compatible = "samsung,s3c6400-hsotg",
 325           .data = dwc2_set_s3c6400_params },
 326         { .compatible = "amlogic,meson8-usb",
 327           .data = dwc2_set_amlogic_params },
 328         { .compatible = "amlogic,meson8b-usb",
 329           .data = dwc2_set_amlogic_params },
 330         { .compatible = "amlogic,meson-gxbb-usb",
 331           .data = dwc2_set_amlogic_params },
 332         { .compatible = "amlogic,meson-g12a-usb",
 333           .data = dwc2_set_amlogic_g12a_params },
 334         { .compatible = "amlogic,meson-a1-usb",
 335           .data = dwc2_set_amlogic_a1_params },
 336         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 337         { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
 338         { .compatible = "sophgo,cv1800-usb",
 339           .data = dwc2_set_cv1800_params },
 340         { .compatible = "st,stm32f4x9-fsotg",
 341           .data = dwc2_set_stm32f4x9_fsotg_params },
 342         { .compatible = "st,stm32f4x9-hsotg" },
 343         { .compatible = "st,stm32f7-hsotg",
 344           .data = dwc2_set_stm32f7_hsotg_params },
 345         { .compatible = "st,stm32mp15-fsotg",
 346           .data = dwc2_set_stm32mp15_fsotg_params },
 347         { .compatible = "st,stm32mp15-hsotg",
 348           .data = dwc2_set_stm32mp15_hsotg_params },
 349         { .compatible = "intel,socfpga-agilex-hsotg",
 350           .data = dwc2_set_socfpga_agilex_params },
 351         {},
 352 };
 353 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 354
 355 const struct acpi_device_id dwc2_acpi_match[] = {
 356         /* This ID refers to the same USB IP as of_device_id brcm,bcm2835-usb */
 357         { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params },
 358         { },
 359 };
 360 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match);
 361
 362 const struct pci_device_id dwc2_pci_ids[] = {
 363         {
 364                 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_PRODUCT_ID_HAPS_HSOTG),
 365         },
 366         {
 367                 PCI_DEVICE(PCI_VENDOR_ID_STMICRO,
 368                            PCI_DEVICE_ID_STMICRO_USB_OTG),
 369         },
 370         {
 371                 PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DWC2),
 372                 .driver_data = (unsigned long)dwc2_set_loongson_params,
 373         },
 374         { /* end: all zeroes */ }
 375 };
 376 MODULE_DEVICE_TABLE(pci, dwc2_pci_ids);
 377 EXPORT_SYMBOL_GPL(dwc2_pci_ids);
 378
 379 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 380 {
 381         switch (hsotg->hw_params.op_mode) {
 382         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 383                 hsotg->params.otg_caps.hnp_support = true;
 384                 hsotg->params.otg_caps.srp_support = true;
 385                 break;
 386         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 387         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 388         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 389                 hsotg->params.otg_caps.hnp_support = false;
 390                 hsotg->params.otg_caps.srp_support = true;
 391                 break;
 392         default:
 393                 hsotg->params.otg_caps.hnp_support = false;
 394                 hsotg->params.otg_caps.srp_support = false;
 395                 break;
 396         }
 397 }
 398
 399 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 400 {
 401         int val;
 402         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 403
 404         val = DWC2_PHY_TYPE_PARAM_FS;
 405         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 406                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 407                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 408                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 409                 else
 410                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 411         }
 412
 413         if (dwc2_is_fs_iot(hsotg))
 414                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 415
 416         hsotg->params.phy_type = val;
 417 }
 418
 419 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 420 {
 421         int val;
 422
 423         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 424                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 425
 426         if (dwc2_is_fs_iot(hsotg))
 427                 val = DWC2_SPEED_PARAM_FULL;
 428
 429         if (dwc2_is_hs_iot(hsotg))
 430                 val = DWC2_SPEED_PARAM_HIGH;
 431
 432         hsotg->params.speed = val;
 433 }
 434
 435 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 436 {
 437         int val;
 438
 439         val = (hsotg->hw_params.utmi_phy_data_width ==
 440                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 441
 442         if (hsotg->phy) {
 443                 /*
 444                  * If using the generic PHY framework, check if the PHY bus
 445                  * width is 8-bit and set the phyif appropriately.
 446                  */
 447                 if (phy_get_bus_width(hsotg->phy) == 8)
 448                         val = 8;
 449         }
 450
 451         hsotg->params.phy_utmi_width = val;
 452 }
 453
 454 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 455 {
 456         struct dwc2_core_params *p = &hsotg->params;
 457         int depth_average;
 458         int fifo_count;
 459         int i;
 460
 461         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 462
 463         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 464         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 465         for (i = 1; i <= fifo_count; i++)
 466                 p->g_tx_fifo_size[i] = depth_average;
 467 }
 468
 469 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 470 {
 471         int val;
 472
 473         if (hsotg->hw_params.hibernation)
 474                 val = DWC2_POWER_DOWN_PARAM_HIBERNATION;
 475         else if (hsotg->hw_params.power_optimized)
 476                 val = DWC2_POWER_DOWN_PARAM_PARTIAL;
 477         else
 478                 val = DWC2_POWER_DOWN_PARAM_NONE;
 479
 480         hsotg->params.power_down = val;
 481 }
 482
 483 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
 484 {
 485         struct dwc2_core_params *p = &hsotg->params;
 486
 487         p->lpm = hsotg->hw_params.lpm_mode;
 488         if (p->lpm) {
 489                 p->lpm_clock_gating = true;
 490                 p->besl = true;
 491                 p->hird_threshold_en = true;
 492                 p->hird_threshold = 4;
 493         } else {
 494                 p->lpm_clock_gating = false;
 495                 p->besl = false;
 496                 p->hird_threshold_en = false;
 497         }
 498 }
 499
 500 /**
 501  * dwc2_set_default_params() - Set all core parameters to their
 502  * auto-detected default values.
 503  *
 504  * @hsotg: Programming view of the DWC_otg controller
 505  *
 506  */
 507 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 508 {
 509         struct dwc2_hw_params *hw = &hsotg->hw_params;
 510         struct dwc2_core_params *p = &hsotg->params;
 511         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 512
 513         dwc2_set_param_otg_cap(hsotg);
 514         dwc2_set_param_phy_type(hsotg);
 515         dwc2_set_param_speed(hsotg);
 516         dwc2_set_param_phy_utmi_width(hsotg);
 517         dwc2_set_param_power_down(hsotg);
 518         dwc2_set_param_lpm(hsotg);
 519         p->phy_ulpi_ddr = false;
 520         p->phy_ulpi_ext_vbus = false;
 521         p->eusb2_disc = false;
 522
 523         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 524         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 525         p->i2c_enable = hw->i2c_enable;
 526         p->acg_enable = hw->acg_enable;
 527         p->ulpi_fs_ls = false;
 528         p->ts_dline = false;
 529         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 530         p->uframe_sched = true;
 531         p->external_id_pin_ctl = false;
 532         p->ipg_isoc_en = false;
 533         p->service_interval = false;
 534         p->max_packet_count = hw->max_packet_count;
 535         p->max_transfer_size = hw->max_transfer_size;
 536         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 537         p->ref_clk_per = 33333;
 538         p->sof_cnt_wkup_alert = 100;
 539
 540         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 541             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 542                 p->host_dma = dma_capable;
 543                 p->dma_desc_enable = false;
 544                 p->dma_desc_fs_enable = false;
 545                 p->host_support_fs_ls_low_power = false;
 546                 p->host_ls_low_power_phy_clk = false;
 547                 p->host_channels = hw->host_channels;
 548                 p->host_rx_fifo_size = hw->rx_fifo_size;
 549                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 550                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 551         }
 552
 553         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 554             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 555                 p->g_dma = dma_capable;
 556                 p->g_dma_desc = hw->dma_desc_enable;
 557
 558                 /*
 559                  * The values for g_rx_fifo_size (2048) and
 560                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 561                  * gadget driver. These defaults have been hard-coded
 562                  * for some time so many platforms depend on these
 563                  * values. Leave them as defaults for now and only
 564                  * auto-detect if the hardware does not support the
 565                  * default.
 566                  */
 567                 p->g_rx_fifo_size = 2048;
 568                 p->g_np_tx_fifo_size = 1024;
 569                 dwc2_set_param_tx_fifo_sizes(hsotg);
 570         }
 571 }
 572
 573 /**
 574  * dwc2_get_device_properties() - Read in device properties.
 575  *
 576  * @hsotg: Programming view of the DWC_otg controller
 577  *
 578  * Read in the device properties and adjust core parameters if needed.
 579  */
 580 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 581 {
 582         struct dwc2_core_params *p = &hsotg->params;
 583         int num;
 584
 585         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 586             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 587                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 588                                          &p->g_rx_fifo_size);
 589
 590                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 591                                          &p->g_np_tx_fifo_size);
 592
 593                 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
 594                 if (num > 0) {
 595                         num = min(num, 15);
 596                         memset(p->g_tx_fifo_size, 0,
 597                                sizeof(p->g_tx_fifo_size));
 598                         device_property_read_u32_array(hsotg->dev,
 599                                                        "g-tx-fifo-size",
 600                                                        &p->g_tx_fifo_size[1],
 601                                                        num);
 602                 }
 603
 604                 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps);
 605         }
 606
 607         p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current");
 608 }
 609
 610 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 611 {
 612         int valid = 1;
 613
 614         if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) {
 615                 /* check HNP && SRP capable */
 616                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 617                         valid = 0;
 618         } else if (!hsotg->params.otg_caps.hnp_support) {
 619                 /* check SRP only capable */
 620                 if (hsotg->params.otg_caps.srp_support) {
 621                         switch (hsotg->hw_params.op_mode) {
 622                         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 623                         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 624                         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 625                         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 626                                 break;
 627                         default:
 628                                 valid = 0;
 629                                 break;
 630                         }
 631                 }
 632                 /* else: NO HNP && NO SRP capable: always valid */
 633         } else {
 634                 valid = 0;
 635         }
 636
 637         if (!valid)
 638                 dwc2_set_param_otg_cap(hsotg);
 639 }
 640
 641 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 642 {
 643         int valid = 0;
 644         u32 hs_phy_type;
 645         u32 fs_phy_type;
 646
 647         hs_phy_type = hsotg->hw_params.hs_phy_type;
 648         fs_phy_type = hsotg->hw_params.fs_phy_type;
 649
 650         switch (hsotg->params.phy_type) {
 651         case DWC2_PHY_TYPE_PARAM_FS:
 652                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 653                         valid = 1;
 654                 break;
 655         case DWC2_PHY_TYPE_PARAM_UTMI:
 656                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 657                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 658                         valid = 1;
 659                 break;
 660         case DWC2_PHY_TYPE_PARAM_ULPI:
 661                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 662                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 663                         valid = 1;
 664                 break;
 665         default:
 666                 break;
 667         }
 668
 669         if (!valid)
 670                 dwc2_set_param_phy_type(hsotg);
 671 }
 672
 673 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 674 {
 675         int valid = 1;
 676         int phy_type = hsotg->params.phy_type;
 677         int speed = hsotg->params.speed;
 678
 679         switch (speed) {
 680         case DWC2_SPEED_PARAM_HIGH:
 681                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 682                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 683                         valid = 0;
 684                 break;
 685         case DWC2_SPEED_PARAM_FULL:
 686         case DWC2_SPEED_PARAM_LOW:
 687                 break;
 688         default:
 689                 valid = 0;
 690                 break;
 691         }
 692
 693         if (!valid)
 694                 dwc2_set_param_speed(hsotg);
 695 }
 696
 697 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 698 {
 699         int valid = 0;
 700         int param = hsotg->params.phy_utmi_width;
 701         int width = hsotg->hw_params.utmi_phy_data_width;
 702
 703         switch (width) {
 704         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 705                 valid = (param == 8);
 706                 break;
 707         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 708                 valid = (param == 16);
 709                 break;
 710         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 711                 valid = (param == 8 || param == 16);
 712                 break;
 713         }
 714
 715         if (!valid)
 716                 dwc2_set_param_phy_utmi_width(hsotg);
 717 }
 718
 719 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 720 {
 721         int param = hsotg->params.power_down;
 722
 723         switch (param) {
 724         case DWC2_POWER_DOWN_PARAM_NONE:
 725                 break;
 726         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 727                 if (hsotg->hw_params.power_optimized)
 728                         break;
 729                 dev_dbg(hsotg->dev,
 730                         "Partial power down isn't supported by HW\n");
 731                 param = DWC2_POWER_DOWN_PARAM_NONE;
 732                 break;
 733         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 734                 if (hsotg->hw_params.hibernation)
 735                         break;
 736                 dev_dbg(hsotg->dev,
 737                         "Hibernation isn't supported by HW\n");
 738                 param = DWC2_POWER_DOWN_PARAM_NONE;
 739                 break;
 740         default:
 741                 dev_err(hsotg->dev,
 742                         "%s: Invalid parameter power_down=%d\n",
 743                         __func__, param);
 744                 param = DWC2_POWER_DOWN_PARAM_NONE;
 745                 break;
 746         }
 747
 748         hsotg->params.power_down = param;
 749 }
 750
 751 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 752 {
 753         int fifo_count;
 754         int fifo;
 755         int min;
 756         u32 total = 0;
 757         u32 dptxfszn;
 758
 759         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 760         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 761
 762         for (fifo = 1; fifo <= fifo_count; fifo++)
 763                 total += hsotg->params.g_tx_fifo_size[fifo];
 764
 765         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 766                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 767                          __func__);
 768                 dwc2_set_param_tx_fifo_sizes(hsotg);
 769         }
 770
 771         for (fifo = 1; fifo <= fifo_count; fifo++) {
 772                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 773
 774                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 775                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 776                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 777                                  __func__, fifo,
 778                                  hsotg->params.g_tx_fifo_size[fifo]);
 779                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 780                 }
 781         }
 782 }
 783
 784 static void dwc2_check_param_eusb2_disc(struct dwc2_hsotg *hsotg)
 785 {
 786         u32 gsnpsid;
 787
 788         if (!hsotg->params.eusb2_disc)
 789                 return;
 790         gsnpsid = dwc2_readl(hsotg, GSNPSID);
 791         /*
 792          * eusb2_disc not supported by FS IOT devices.
 793          * For other cores, it supported starting from version 5.00a
 794          */
 795         if ((gsnpsid & ~DWC2_CORE_REV_MASK) == DWC2_FS_IOT_ID ||
 796             (gsnpsid & DWC2_CORE_REV_MASK) <
 797             (DWC2_CORE_REV_5_00a & DWC2_CORE_REV_MASK)) {
 798                 hsotg->params.eusb2_disc = false;
 799                 return;
 800         }
 801 }
 802
 803 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 804                 if ((int)(hsotg->params._param) < (_min) ||             \
 805                     (hsotg->params._param) > (_max)) {                  \
 806                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 807                                  __func__, #_param, hsotg->params._param); \
 808                         hsotg->params._param = (_def);                  \
 809                 }                                                       \
 810         } while (0)
 811
 812 #define CHECK_BOOL(_param, _check) do {                                 \
 813                 if (hsotg->params._param && !(_check)) {                \
 814                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 815                                  __func__, #_param, hsotg->params._param); \
 816                         hsotg->params._param = false;                   \
 817                 }                                                       \
 818         } while (0)
 819
 820 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 821 {
 822         struct dwc2_hw_params *hw = &hsotg->hw_params;
 823         struct dwc2_core_params *p = &hsotg->params;
 824         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 825
 826         dwc2_check_param_otg_cap(hsotg);
 827         dwc2_check_param_phy_type(hsotg);
 828         dwc2_check_param_speed(hsotg);
 829         dwc2_check_param_phy_utmi_width(hsotg);
 830         dwc2_check_param_power_down(hsotg);
 831         dwc2_check_param_eusb2_disc(hsotg);
 832
 833         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 834         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 835         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 836         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 837         CHECK_BOOL(acg_enable, hw->acg_enable);
 838         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 839         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 840         CHECK_BOOL(lpm, hw->lpm_mode);
 841         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 842         CHECK_BOOL(besl, hsotg->params.lpm);
 843         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 844         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 845         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 846         CHECK_BOOL(service_interval, hw->service_interval_mode);
 847         CHECK_RANGE(max_packet_count,
 848                     15, hw->max_packet_count,
 849                     hw->max_packet_count);
 850         CHECK_RANGE(max_transfer_size,
 851                     2047, hw->max_transfer_size,
 852                     hw->max_transfer_size);
 853
 854         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 855             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 856                 CHECK_BOOL(host_dma, dma_capable);
 857                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 858                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 859                 CHECK_BOOL(host_ls_low_power_phy_clk,
 860                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 861                 CHECK_RANGE(host_channels,
 862                             1, hw->host_channels,
 863                             hw->host_channels);
 864                 CHECK_RANGE(host_rx_fifo_size,
 865                             16, hw->rx_fifo_size,
 866                             hw->rx_fifo_size);
 867                 CHECK_RANGE(host_nperio_tx_fifo_size,
 868                             16, hw->host_nperio_tx_fifo_size,
 869                             hw->host_nperio_tx_fifo_size);
 870                 CHECK_RANGE(host_perio_tx_fifo_size,
 871                             16, hw->host_perio_tx_fifo_size,
 872                             hw->host_perio_tx_fifo_size);
 873         }
 874
 875         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 876             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 877                 CHECK_BOOL(g_dma, dma_capable);
 878                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 879                 CHECK_RANGE(g_rx_fifo_size,
 880                             16, hw->rx_fifo_size,
 881                             hw->rx_fifo_size);
 882                 CHECK_RANGE(g_np_tx_fifo_size,
 883                             16, hw->dev_nperio_tx_fifo_size,
 884                             hw->dev_nperio_tx_fifo_size);
 885                 dwc2_check_param_tx_fifo_sizes(hsotg);
 886         }
 887 }
 888
 889 /*
 890  * Gets host hardware parameters. Forces host mode if not currently in
 891  * host mode. Should be called immediately after a core soft reset in
 892  * order to get the reset values.
 893  */
 894 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 895 {
 896         struct dwc2_hw_params *hw = &hsotg->hw_params;
 897         u32 gnptxfsiz;
 898         u32 hptxfsiz;
 899
 900         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 901                 return;
 902
 903         dwc2_force_mode(hsotg, true);
 904
 905         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 906         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 907
 908         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 909                                        FIFOSIZE_DEPTH_SHIFT;
 910         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 911                                       FIFOSIZE_DEPTH_SHIFT;
 912 }
 913
 914 /*
 915  * Gets device hardware parameters. Forces device mode if not
 916  * currently in device mode. Should be called immediately after a core
 917  * soft reset in order to get the reset values.
 918  */
 919 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 920 {
 921         struct dwc2_hw_params *hw = &hsotg->hw_params;
 922         u32 gnptxfsiz;
 923         int fifo, fifo_count;
 924
 925         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 926                 return;
 927
 928         dwc2_force_mode(hsotg, false);
 929
 930         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 931
 932         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 933
 934         for (fifo = 1; fifo <= fifo_count; fifo++) {
 935                 hw->g_tx_fifo_size[fifo] =
 936                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 937                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 938         }
 939
 940         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 941                                        FIFOSIZE_DEPTH_SHIFT;
 942 }
 943
 944 /**
 945  * dwc2_get_hwparams() - During device initialization, read various hardware
 946  *                       configuration registers and interpret the contents.
 947  *
 948  * @hsotg: Programming view of the DWC_otg controller
 949  *
 950  */
 951 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 952 {
 953         struct dwc2_hw_params *hw = &hsotg->hw_params;
 954         unsigned int width;
 955         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 956         u32 grxfsiz;
 957
 958         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 959         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 960         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 961         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 962         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 963
 964         /* hwcfg1 */
 965         hw->dev_ep_dirs = hwcfg1;
 966
 967         /* hwcfg2 */
 968         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 969                       GHWCFG2_OP_MODE_SHIFT;
 970         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 971                    GHWCFG2_ARCHITECTURE_SHIFT;
 972         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 973         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 974                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 975         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 976                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 977         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 978                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 979         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 980                          GHWCFG2_NUM_DEV_EP_SHIFT;
 981         hw->nperio_tx_q_depth =
 982                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 983                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 984         hw->host_perio_tx_q_depth =
 985                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 986                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 987         hw->dev_token_q_depth =
 988                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 989                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 990
 991         /* hwcfg3 */
 992         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 993                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 994         hw->max_transfer_size = (1 << (width + 11)) - 1;
 995         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 996                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 997         hw->max_packet_count = (1 << (width + 4)) - 1;
 998         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 999         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
1000                               GHWCFG3_DFIFO_DEPTH_SHIFT;
1001         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
1002
1003         /* hwcfg4 */
1004         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
1005         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
1006                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
1007         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
1008                              GHWCFG4_NUM_IN_EPS_SHIFT;
1009         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
1010         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
1011         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
1012         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
1013                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
1014         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
1015         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
1016         hw->service_interval_mode = !!(hwcfg4 &
1017                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
1018
1019         /* fifo sizes */
1020         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
1021                                 GRXFSIZ_DEPTH_SHIFT;
1022         /*
1023          * Host specific hardware parameters. Reading these parameters
1024          * requires the controller to be in host mode. The mode will
1025          * be forced, if necessary, to read these values.
1026          */
1027         dwc2_get_host_hwparams(hsotg);
1028         dwc2_get_dev_hwparams(hsotg);
1029
1030         return 0;
1031 }
1032
1033 typedef void (*set_params_cb)(struct dwc2_hsotg *data);
1034
1035 int dwc2_init_params(struct dwc2_hsotg *hsotg)
1036 {
1037         set_params_cb set_params;
1038
1039         dwc2_set_default_params(hsotg);
1040         dwc2_get_device_properties(hsotg);
1041
1042         set_params = device_get_match_data(hsotg->dev);
1043         if (set_params) {
1044                 set_params(hsotg);
1045         } else {
1046                 const struct pci_device_id *pmatch =
1047                         pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent));
1048
1049                 if (pmatch && pmatch->driver_data) {
1050                         set_params = (set_params_cb)pmatch->driver_data;
1051                         set_params(hsotg);
1052                 }
1053         }
1054
1055         dwc2_check_params(hsotg);
1056
1057         return 0;
1058 }