drivers/pinctrl/pinctrl-rockchip.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl driver for Rockchip SoCs
   4  *
   5  * Copyright (c) 2013 MundoReader S.L.
   6  * Author: Heiko Stuebner <[email protected]>
   7  *
   8  * With some ideas taken from pinctrl-samsung:
   9  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  10  *              http://www.samsung.com
  11  * Copyright (c) 2012 Linaro Ltd
  12  *              https://www.linaro.org
  13  *
  14  * and pinctrl-at91:
  15  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22 #include <linux/bitops.h>
  23 #include <linux/gpio/driver.h>
  24 #include <linux/of.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/pinctrl/machine.h>
  27 #include <linux/pinctrl/pinconf.h>
  28 #include <linux/pinctrl/pinctrl.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/pinctrl/pinconf-generic.h>
  31 #include <linux/irqchip/chained_irq.h>
  32 #include <linux/clk.h>
  33 #include <linux/regmap.h>
  34 #include <linux/mfd/syscon.h>
  35 #include <linux/string_helpers.h>
  36
  37 #include <dt-bindings/pinctrl/rockchip.h>
  38
  39 #include "core.h"
  40 #include "pinconf.h"
  41 #include "pinctrl-rockchip.h"
  42
  43 /*
  44  * Generate a bitmask for setting a value (v) with a write mask bit in hiword
  45  * register 31:16 area.
  46  */
  47 #define WRITE_MASK_VAL(h, l, v) \
  48         (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
  49
  50 /*
  51  * Encode variants of iomux registers into a type variable
  52  */
  53 #define IOMUX_GPIO_ONLY         BIT(0)
  54 #define IOMUX_WIDTH_4BIT        BIT(1)
  55 #define IOMUX_SOURCE_PMU        BIT(2)
  56 #define IOMUX_UNROUTED          BIT(3)
  57 #define IOMUX_WIDTH_3BIT        BIT(4)
  58 #define IOMUX_WIDTH_2BIT        BIT(5)
  59 #define IOMUX_L_SOURCE_PMU      BIT(6)
  60
  61 #define PIN_BANK(id, pins, label)                       \
  62         {                                               \
  63                 .bank_num       = id,                   \
  64                 .nr_pins        = pins,                 \
  65                 .name           = label,                \
  66                 .iomux          = {                     \
  67                         { .offset = -1 },               \
  68                         { .offset = -1 },               \
  69                         { .offset = -1 },               \
  70                         { .offset = -1 },               \
  71                 },                                      \
  72         }
  73
  74 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
  75         {                                                               \
  76                 .bank_num       = id,                                   \
  77                 .nr_pins        = pins,                                 \
  78                 .name           = label,                                \
  79                 .iomux          = {                                     \
  80                         { .type = iom0, .offset = -1 },                 \
  81                         { .type = iom1, .offset = -1 },                 \
  82                         { .type = iom2, .offset = -1 },                 \
  83                         { .type = iom3, .offset = -1 },                 \
  84                 },                                                      \
  85         }
  86
  87 #define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0,   \
  88                                                iom1, iom2, iom3,        \
  89                                                offset0, offset1,        \
  90                                                offset2, offset3, pull0, \
  91                                                pull1, pull2, pull3)     \
  92         {                                                               \
  93                 .bank_num       = id,                                   \
  94                 .nr_pins        = pins,                                 \
  95                 .name           = label,                                \
  96                 .iomux          = {                                     \
  97                         { .type = iom0, .offset = offset0 },            \
  98                         { .type = iom1, .offset = offset1 },            \
  99                         { .type = iom2, .offset = offset2 },            \
 100                         { .type = iom3, .offset = offset3 },            \
 101                 },                                                      \
 102                 .pull_type[0] = pull0,                                  \
 103                 .pull_type[1] = pull1,                                  \
 104                 .pull_type[2] = pull2,                                  \
 105                 .pull_type[3] = pull3,                                  \
 106         }
 107
 108 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 109         {                                                               \
 110                 .bank_num       = id,                                   \
 111                 .nr_pins        = pins,                                 \
 112                 .name           = label,                                \
 113                 .iomux          = {                                     \
 114                         { .offset = -1 },                               \
 115                         { .offset = -1 },                               \
 116                         { .offset = -1 },                               \
 117                         { .offset = -1 },                               \
 118                 },                                                      \
 119                 .drv            = {                                     \
 120                         { .drv_type = type0, .offset = -1 },            \
 121                         { .drv_type = type1, .offset = -1 },            \
 122                         { .drv_type = type2, .offset = -1 },            \
 123                         { .drv_type = type3, .offset = -1 },            \
 124                 },                                                      \
 125         }
 126
 127 #define PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(id, pins, label, iom0, iom1,    \
 128                                         iom2, iom3, pull0, pull1,       \
 129                                         pull2, pull3)                   \
 130         {                                                               \
 131                 .bank_num       = id,                                   \
 132                 .nr_pins        = pins,                                 \
 133                 .name           = label,                                \
 134                 .iomux          = {                                     \
 135                         { .type = iom0, .offset = -1 },                 \
 136                         { .type = iom1, .offset = -1 },                 \
 137                         { .type = iom2, .offset = -1 },                 \
 138                         { .type = iom3, .offset = -1 },                 \
 139                 },                                                      \
 140                 .pull_type[0] = pull0,                                  \
 141                 .pull_type[1] = pull1,                                  \
 142                 .pull_type[2] = pull2,                                  \
 143                 .pull_type[3] = pull3,                                  \
 144         }
 145
 146 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 147                                       drv2, drv3, pull0, pull1,         \
 148                                       pull2, pull3)                     \
 149         {                                                               \
 150                 .bank_num       = id,                                   \
 151                 .nr_pins        = pins,                                 \
 152                 .name           = label,                                \
 153                 .iomux          = {                                     \
 154                         { .offset = -1 },                               \
 155                         { .offset = -1 },                               \
 156                         { .offset = -1 },                               \
 157                         { .offset = -1 },                               \
 158                 },                                                      \
 159                 .drv            = {                                     \
 160                         { .drv_type = drv0, .offset = -1 },             \
 161                         { .drv_type = drv1, .offset = -1 },             \
 162                         { .drv_type = drv2, .offset = -1 },             \
 163                         { .drv_type = drv3, .offset = -1 },             \
 164                 },                                                      \
 165                 .pull_type[0] = pull0,                                  \
 166                 .pull_type[1] = pull1,                                  \
 167                 .pull_type[2] = pull2,                                  \
 168                 .pull_type[3] = pull3,                                  \
 169         }
 170
 171 #define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2,  \
 172                                     iom3, offset0, offset1, offset2,    \
 173                                     offset3)                            \
 174         {                                                               \
 175                 .bank_num       = id,                                   \
 176                 .nr_pins        = pins,                                 \
 177                 .name           = label,                                \
 178                 .iomux          = {                                     \
 179                         { .type = iom0, .offset = offset0 },            \
 180                         { .type = iom1, .offset = offset1 },            \
 181                         { .type = iom2, .offset = offset2 },            \
 182                         { .type = iom3, .offset = offset3 },            \
 183                 },                                                      \
 184         }
 185
 186 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 187                                         iom2, iom3, drv0, drv1, drv2,   \
 188                                         drv3, offset0, offset1,         \
 189                                         offset2, offset3)               \
 190         {                                                               \
 191                 .bank_num       = id,                                   \
 192                 .nr_pins        = pins,                                 \
 193                 .name           = label,                                \
 194                 .iomux          = {                                     \
 195                         { .type = iom0, .offset = -1 },                 \
 196                         { .type = iom1, .offset = -1 },                 \
 197                         { .type = iom2, .offset = -1 },                 \
 198                         { .type = iom3, .offset = -1 },                 \
 199                 },                                                      \
 200                 .drv            = {                                     \
 201                         { .drv_type = drv0, .offset = offset0 },        \
 202                         { .drv_type = drv1, .offset = offset1 },        \
 203                         { .drv_type = drv2, .offset = offset2 },        \
 204                         { .drv_type = drv3, .offset = offset3 },        \
 205                 },                                                      \
 206         }
 207
 208 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 209                                               label, iom0, iom1, iom2,  \
 210                                               iom3, drv0, drv1, drv2,   \
 211                                               drv3, offset0, offset1,   \
 212                                               offset2, offset3, pull0,  \
 213                                               pull1, pull2, pull3)      \
 214         {                                                               \
 215                 .bank_num       = id,                                   \
 216                 .nr_pins        = pins,                                 \
 217                 .name           = label,                                \
 218                 .iomux          = {                                     \
 219                         { .type = iom0, .offset = -1 },                 \
 220                         { .type = iom1, .offset = -1 },                 \
 221                         { .type = iom2, .offset = -1 },                 \
 222                         { .type = iom3, .offset = -1 },                 \
 223                 },                                                      \
 224                 .drv            = {                                     \
 225                         { .drv_type = drv0, .offset = offset0 },        \
 226                         { .drv_type = drv1, .offset = offset1 },        \
 227                         { .drv_type = drv2, .offset = offset2 },        \
 228                         { .drv_type = drv3, .offset = offset3 },        \
 229                 },                                                      \
 230                 .pull_type[0] = pull0,                                  \
 231                 .pull_type[1] = pull1,                                  \
 232                 .pull_type[2] = pull2,                                  \
 233                 .pull_type[3] = pull3,                                  \
 234         }
 235
 236 #define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG)         \
 237         {                                                               \
 238                 .bank_num       = ID,                                   \
 239                 .pin            = PIN,                                  \
 240                 .func           = FUNC,                                 \
 241                 .route_offset   = REG,                                  \
 242                 .route_val      = VAL,                                  \
 243                 .route_location = FLAG,                                 \
 244         }
 245
 246 #define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL)       \
 247         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
 248
 249 #define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL)        \
 250         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
 251
 252 #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL)        \
 253         PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
 254
 255 #define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P)                     \
 256         PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
 257
 258 static struct regmap_config rockchip_regmap_config = {
 259         .reg_bits = 32,
 260         .val_bits = 32,
 261         .reg_stride = 4,
 262 };
 263
 264 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 265                                         const struct rockchip_pinctrl *info,
 266                                         const char *name)
 267 {
 268         int i;
 269
 270         for (i = 0; i < info->ngroups; i++) {
 271                 if (!strcmp(info->groups[i].name, name))
 272                         return &info->groups[i];
 273         }
 274
 275         return NULL;
 276 }
 277
 278 /*
 279  * given a pin number that is local to a pin controller, find out the pin bank
 280  * and the register base of the pin bank.
 281  */
 282 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 283                                                                 unsigned pin)
 284 {
 285         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 286
 287         while (pin >= (b->pin_base + b->nr_pins))
 288                 b++;
 289
 290         return b;
 291 }
 292
 293 static struct rockchip_pin_bank *bank_num_to_bank(
 294                                         struct rockchip_pinctrl *info,
 295                                         unsigned num)
 296 {
 297         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 298         int i;
 299
 300         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 301                 if (b->bank_num == num)
 302                         return b;
 303         }
 304
 305         return ERR_PTR(-EINVAL);
 306 }
 307
 308 /*
 309  * Pinctrl_ops handling
 310  */
 311
 312 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 313 {
 314         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 315
 316         return info->ngroups;
 317 }
 318
 319 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 320                                                         unsigned selector)
 321 {
 322         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 323
 324         return info->groups[selector].name;
 325 }
 326
 327 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 328                                       unsigned selector, const unsigned **pins,
 329                                       unsigned *npins)
 330 {
 331         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 332
 333         if (selector >= info->ngroups)
 334                 return -EINVAL;
 335
 336         *pins = info->groups[selector].pins;
 337         *npins = info->groups[selector].npins;
 338
 339         return 0;
 340 }
 341
 342 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 343                                  struct device_node *np,
 344                                  struct pinctrl_map **map, unsigned *num_maps)
 345 {
 346         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 347         const struct rockchip_pin_group *grp;
 348         struct device *dev = info->dev;
 349         struct pinctrl_map *new_map;
 350         struct device_node *parent;
 351         int map_num = 1;
 352         int i;
 353
 354         /*
 355          * first find the group of this node and check if we need to create
 356          * config maps for pins
 357          */
 358         grp = pinctrl_name_to_group(info, np->name);
 359         if (!grp) {
 360                 dev_err(dev, "unable to find group for node %pOFn\n", np);
 361                 return -EINVAL;
 362         }
 363
 364         map_num += grp->npins;
 365
 366         new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 367         if (!new_map)
 368                 return -ENOMEM;
 369
 370         *map = new_map;
 371         *num_maps = map_num;
 372
 373         /* create mux map */
 374         parent = of_get_parent(np);
 375         if (!parent) {
 376                 kfree(new_map);
 377                 return -EINVAL;
 378         }
 379         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 380         new_map[0].data.mux.function = parent->name;
 381         new_map[0].data.mux.group = np->name;
 382         of_node_put(parent);
 383
 384         /* create config map */
 385         new_map++;
 386         for (i = 0; i < grp->npins; i++) {
 387                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 388                 new_map[i].data.configs.group_or_pin =
 389                                 pin_get_name(pctldev, grp->pins[i]);
 390                 new_map[i].data.configs.configs = grp->data[i].configs;
 391                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 392         }
 393
 394         dev_dbg(dev, "maps: function %s group %s num %d\n",
 395                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 396
 397         return 0;
 398 }
 399
 400 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 401                                     struct pinctrl_map *map, unsigned num_maps)
 402 {
 403         kfree(map);
 404 }
 405
 406 static const struct pinctrl_ops rockchip_pctrl_ops = {
 407         .get_groups_count       = rockchip_get_groups_count,
 408         .get_group_name         = rockchip_get_group_name,
 409         .get_group_pins         = rockchip_get_group_pins,
 410         .dt_node_to_map         = rockchip_dt_node_to_map,
 411         .dt_free_map            = rockchip_dt_free_map,
 412 };
 413
 414 /*
 415  * Hardware access
 416  */
 417
 418 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
 419         {
 420                 .num = 1,
 421                 .pin = 0,
 422                 .reg = 0x418,
 423                 .bit = 0,
 424                 .mask = 0x3
 425         }, {
 426                 .num = 1,
 427                 .pin = 1,
 428                 .reg = 0x418,
 429                 .bit = 2,
 430                 .mask = 0x3
 431         }, {
 432                 .num = 1,
 433                 .pin = 2,
 434                 .reg = 0x418,
 435                 .bit = 4,
 436                 .mask = 0x3
 437         }, {
 438                 .num = 1,
 439                 .pin = 3,
 440                 .reg = 0x418,
 441                 .bit = 6,
 442                 .mask = 0x3
 443         }, {
 444                 .num = 1,
 445                 .pin = 4,
 446                 .reg = 0x418,
 447                 .bit = 8,
 448                 .mask = 0x3
 449         }, {
 450                 .num = 1,
 451                 .pin = 5,
 452                 .reg = 0x418,
 453                 .bit = 10,
 454                 .mask = 0x3
 455         }, {
 456                 .num = 1,
 457                 .pin = 6,
 458                 .reg = 0x418,
 459                 .bit = 12,
 460                 .mask = 0x3
 461         }, {
 462                 .num = 1,
 463                 .pin = 7,
 464                 .reg = 0x418,
 465                 .bit = 14,
 466                 .mask = 0x3
 467         }, {
 468                 .num = 1,
 469                 .pin = 8,
 470                 .reg = 0x41c,
 471                 .bit = 0,
 472                 .mask = 0x3
 473         }, {
 474                 .num = 1,
 475                 .pin = 9,
 476                 .reg = 0x41c,
 477                 .bit = 2,
 478                 .mask = 0x3
 479         },
 480 };
 481
 482 static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
 483         {
 484                 .num = 0,
 485                 .pin = 20,
 486                 .reg = 0x10000,
 487                 .bit = 0,
 488                 .mask = 0xf
 489         },
 490         {
 491                 .num = 0,
 492                 .pin = 21,
 493                 .reg = 0x10000,
 494                 .bit = 4,
 495                 .mask = 0xf
 496         },
 497         {
 498                 .num = 0,
 499                 .pin = 22,
 500                 .reg = 0x10000,
 501                 .bit = 8,
 502                 .mask = 0xf
 503         },
 504         {
 505                 .num = 0,
 506                 .pin = 23,
 507                 .reg = 0x10000,
 508                 .bit = 12,
 509                 .mask = 0xf
 510         },
 511 };
 512
 513 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
 514         {
 515                 .num = 2,
 516                 .pin = 20,
 517                 .reg = 0xe8,
 518                 .bit = 0,
 519                 .mask = 0x7
 520         }, {
 521                 .num = 2,
 522                 .pin = 21,
 523                 .reg = 0xe8,
 524                 .bit = 4,
 525                 .mask = 0x7
 526         }, {
 527                 .num = 2,
 528                 .pin = 22,
 529                 .reg = 0xe8,
 530                 .bit = 8,
 531                 .mask = 0x7
 532         }, {
 533                 .num = 2,
 534                 .pin = 23,
 535                 .reg = 0xe8,
 536                 .bit = 12,
 537                 .mask = 0x7
 538         }, {
 539                 .num = 2,
 540                 .pin = 24,
 541                 .reg = 0xd4,
 542                 .bit = 12,
 543                 .mask = 0x7
 544         },
 545 };
 546
 547 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
 548         {
 549                 /* gpio1b6_sel */
 550                 .num = 1,
 551                 .pin = 14,
 552                 .reg = 0x28,
 553                 .bit = 12,
 554                 .mask = 0xf
 555         }, {
 556                 /* gpio1b7_sel */
 557                 .num = 1,
 558                 .pin = 15,
 559                 .reg = 0x2c,
 560                 .bit = 0,
 561                 .mask = 0x3
 562         }, {
 563                 /* gpio1c2_sel */
 564                 .num = 1,
 565                 .pin = 18,
 566                 .reg = 0x30,
 567                 .bit = 4,
 568                 .mask = 0xf
 569         }, {
 570                 /* gpio1c3_sel */
 571                 .num = 1,
 572                 .pin = 19,
 573                 .reg = 0x30,
 574                 .bit = 8,
 575                 .mask = 0xf
 576         }, {
 577                 /* gpio1c4_sel */
 578                 .num = 1,
 579                 .pin = 20,
 580                 .reg = 0x30,
 581                 .bit = 12,
 582                 .mask = 0xf
 583         }, {
 584                 /* gpio1c5_sel */
 585                 .num = 1,
 586                 .pin = 21,
 587                 .reg = 0x34,
 588                 .bit = 0,
 589                 .mask = 0xf
 590         }, {
 591                 /* gpio1c6_sel */
 592                 .num = 1,
 593                 .pin = 22,
 594                 .reg = 0x34,
 595                 .bit = 4,
 596                 .mask = 0xf
 597         }, {
 598                 /* gpio1c7_sel */
 599                 .num = 1,
 600                 .pin = 23,
 601                 .reg = 0x34,
 602                 .bit = 8,
 603                 .mask = 0xf
 604         }, {
 605                 /* gpio2a2_sel */
 606                 .num = 2,
 607                 .pin = 2,
 608                 .reg = 0x40,
 609                 .bit = 4,
 610                 .mask = 0x3
 611         }, {
 612                 /* gpio2a3_sel */
 613                 .num = 2,
 614                 .pin = 3,
 615                 .reg = 0x40,
 616                 .bit = 6,
 617                 .mask = 0x3
 618         }, {
 619                 /* gpio2c0_sel */
 620                 .num = 2,
 621                 .pin = 16,
 622                 .reg = 0x50,
 623                 .bit = 0,
 624                 .mask = 0x3
 625         }, {
 626                 /* gpio3b2_sel */
 627                 .num = 3,
 628                 .pin = 10,
 629                 .reg = 0x68,
 630                 .bit = 4,
 631                 .mask = 0x3
 632         }, {
 633                 /* gpio3b3_sel */
 634                 .num = 3,
 635                 .pin = 11,
 636                 .reg = 0x68,
 637                 .bit = 6,
 638                 .mask = 0x3
 639         }, {
 640                 /* gpio3b4_sel */
 641                 .num = 3,
 642                 .pin = 12,
 643                 .reg = 0x68,
 644                 .bit = 8,
 645                 .mask = 0xf
 646         }, {
 647                 /* gpio3b5_sel */
 648                 .num = 3,
 649                 .pin = 13,
 650                 .reg = 0x68,
 651                 .bit = 12,
 652                 .mask = 0xf
 653         },
 654 };
 655
 656 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 657         {
 658                 /* gpio2_b7_sel */
 659                 .num = 2,
 660                 .pin = 15,
 661                 .reg = 0x28,
 662                 .bit = 0,
 663                 .mask = 0x7
 664         }, {
 665                 /* gpio2_c7_sel */
 666                 .num = 2,
 667                 .pin = 23,
 668                 .reg = 0x30,
 669                 .bit = 14,
 670                 .mask = 0x3
 671         }, {
 672                 /* gpio3_b1_sel */
 673                 .num = 3,
 674                 .pin = 9,
 675                 .reg = 0x44,
 676                 .bit = 2,
 677                 .mask = 0x3
 678         }, {
 679                 /* gpio3_b2_sel */
 680                 .num = 3,
 681                 .pin = 10,
 682                 .reg = 0x44,
 683                 .bit = 4,
 684                 .mask = 0x3
 685         }, {
 686                 /* gpio3_b3_sel */
 687                 .num = 3,
 688                 .pin = 11,
 689                 .reg = 0x44,
 690                 .bit = 6,
 691                 .mask = 0x3
 692         }, {
 693                 /* gpio3_b4_sel */
 694                 .num = 3,
 695                 .pin = 12,
 696                 .reg = 0x44,
 697                 .bit = 8,
 698                 .mask = 0x3
 699         }, {
 700                 /* gpio3_b5_sel */
 701                 .num = 3,
 702                 .pin = 13,
 703                 .reg = 0x44,
 704                 .bit = 10,
 705                 .mask = 0x3
 706         }, {
 707                 /* gpio3_b6_sel */
 708                 .num = 3,
 709                 .pin = 14,
 710                 .reg = 0x44,
 711                 .bit = 12,
 712                 .mask = 0x3
 713         }, {
 714                 /* gpio3_b7_sel */
 715                 .num = 3,
 716                 .pin = 15,
 717                 .reg = 0x44,
 718                 .bit = 14,
 719                 .mask = 0x3
 720         },
 721 };
 722
 723 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
 724                                       int *reg, u8 *bit, int *mask)
 725 {
 726         struct rockchip_pinctrl *info = bank->drvdata;
 727         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 728         struct rockchip_mux_recalced_data *data;
 729         int i;
 730
 731         for (i = 0; i < ctrl->niomux_recalced; i++) {
 732                 data = &ctrl->iomux_recalced[i];
 733                 if (data->num == bank->bank_num &&
 734                     data->pin == pin)
 735                         break;
 736         }
 737
 738         if (i >= ctrl->niomux_recalced)
 739                 return;
 740
 741         *reg = data->reg;
 742         *mask = data->mask;
 743         *bit = data->bit;
 744 }
 745
 746 static struct rockchip_mux_route_data px30_mux_route_data[] = {
 747         RK_MUXROUTE_SAME(2, RK_PB4, 1, 0x184, BIT(16 + 7)), /* cif-d0m0 */
 748         RK_MUXROUTE_SAME(3, RK_PA1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d0m1 */
 749         RK_MUXROUTE_SAME(2, RK_PB6, 1, 0x184, BIT(16 + 7)), /* cif-d1m0 */
 750         RK_MUXROUTE_SAME(3, RK_PA2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d1m1 */
 751         RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
 752         RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
 753         RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x184, BIT(16 + 7)), /* cif-d3m0 */
 754         RK_MUXROUTE_SAME(3, RK_PA5, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d3m1 */
 755         RK_MUXROUTE_SAME(2, RK_PA2, 1, 0x184, BIT(16 + 7)), /* cif-d4m0 */
 756         RK_MUXROUTE_SAME(3, RK_PA7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d4m1 */
 757         RK_MUXROUTE_SAME(2, RK_PA3, 1, 0x184, BIT(16 + 7)), /* cif-d5m0 */
 758         RK_MUXROUTE_SAME(3, RK_PB0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d5m1 */
 759         RK_MUXROUTE_SAME(2, RK_PA4, 1, 0x184, BIT(16 + 7)), /* cif-d6m0 */
 760         RK_MUXROUTE_SAME(3, RK_PB1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d6m1 */
 761         RK_MUXROUTE_SAME(2, RK_PA5, 1, 0x184, BIT(16 + 7)), /* cif-d7m0 */
 762         RK_MUXROUTE_SAME(3, RK_PB4, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d7m1 */
 763         RK_MUXROUTE_SAME(2, RK_PA6, 1, 0x184, BIT(16 + 7)), /* cif-d8m0 */
 764         RK_MUXROUTE_SAME(3, RK_PB6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d8m1 */
 765         RK_MUXROUTE_SAME(2, RK_PA7, 1, 0x184, BIT(16 + 7)), /* cif-d9m0 */
 766         RK_MUXROUTE_SAME(3, RK_PB7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d9m1 */
 767         RK_MUXROUTE_SAME(2, RK_PB7, 1, 0x184, BIT(16 + 7)), /* cif-d10m0 */
 768         RK_MUXROUTE_SAME(3, RK_PC6, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d10m1 */
 769         RK_MUXROUTE_SAME(2, RK_PC0, 1, 0x184, BIT(16 + 7)), /* cif-d11m0 */
 770         RK_MUXROUTE_SAME(3, RK_PC7, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d11m1 */
 771         RK_MUXROUTE_SAME(2, RK_PB0, 1, 0x184, BIT(16 + 7)), /* cif-vsyncm0 */
 772         RK_MUXROUTE_SAME(3, RK_PD1, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-vsyncm1 */
 773         RK_MUXROUTE_SAME(2, RK_PB1, 1, 0x184, BIT(16 + 7)), /* cif-hrefm0 */
 774         RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-hrefm1 */
 775         RK_MUXROUTE_SAME(2, RK_PB2, 1, 0x184, BIT(16 + 7)), /* cif-clkinm0 */
 776         RK_MUXROUTE_SAME(3, RK_PD3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkinm1 */
 777         RK_MUXROUTE_SAME(2, RK_PB3, 1, 0x184, BIT(16 + 7)), /* cif-clkoutm0 */
 778         RK_MUXROUTE_SAME(3, RK_PD0, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-clkoutm1 */
 779         RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
 780         RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
 781         RK_MUXROUTE_SAME(3, RK_PD3, 2, 0x184, BIT(16 + 8)), /* pdm-sdi0m0 */
 782         RK_MUXROUTE_SAME(2, RK_PC5, 2, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-sdi0m1 */
 783         RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
 784         RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
 785         RK_MUXROUTE_SAME(1, RK_PD2, 2, 0x184, BIT(16 + 10)), /* uart2-txm0 */
 786         RK_MUXROUTE_SAME(2, RK_PB4, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-txm1 */
 787         RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
 788         RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
 789         RK_MUXROUTE_SAME(0, RK_PC0, 2, 0x184, BIT(16 + 9)), /* uart3-txm0 */
 790         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-txm1 */
 791         RK_MUXROUTE_SAME(0, RK_PC2, 2, 0x184, BIT(16 + 9)), /* uart3-ctsm0 */
 792         RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-ctsm1 */
 793         RK_MUXROUTE_SAME(0, RK_PC3, 2, 0x184, BIT(16 + 9)), /* uart3-rtsm0 */
 794         RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rtsm1 */
 795 };
 796
 797 static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
 798         RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
 799         RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
 800
 801         RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
 802         RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
 803         RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
 804
 805         RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
 806         RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
 807
 808         RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
 809         RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
 810
 811         RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
 812         RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
 813
 814         RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
 815         RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
 816         RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
 817
 818         RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
 819         RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
 820
 821         RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
 822         RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
 823         RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
 824
 825         RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
 826         RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
 827         RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
 828
 829         RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
 830         RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
 831
 832         RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
 833         RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
 834
 835         RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
 836         RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
 837
 838         RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
 839         RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
 840
 841         RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
 842         RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
 843
 844         RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
 845         RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
 846
 847         RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
 848         RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
 849
 850         RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
 851         RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
 852         RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
 853
 854         RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
 855         RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
 856         RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
 857
 858         RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
 859         RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
 860         RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
 861
 862         RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
 863         RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
 864
 865         RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
 866         RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
 867
 868         RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
 869         RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
 870
 871         RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
 872         RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
 873
 874         RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
 875         RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
 876
 877         RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
 878         RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
 879
 880         RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
 881         RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
 882
 883         RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
 884         RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
 885
 886         RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
 887         RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
 888         RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
 889
 890         RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
 891         RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
 892 };
 893
 894 static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
 895         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
 896         RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
 897         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
 898         RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
 899         RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
 900         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
 901         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
 902 };
 903
 904 static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
 905         RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
 906         RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on emmc-clk */
 907 };
 908
 909 static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
 910         RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
 911         RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
 912         RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
 913         RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
 914         RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
 915         RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
 916         RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
 917         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
 918         RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
 919         RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
 920         RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
 921         RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
 922         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
 923         RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
 924         RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
 925         RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
 926         RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
 927         RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
 928 };
 929
 930 static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
 931         RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
 932         RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
 933 };
 934
 935 static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
 936         RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
 937         RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
 938         RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
 939         RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x314, BIT(16 + 4)), /* i2c3_sdam0 */
 940         RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x314, BIT(16 + 4) | BIT(4)), /* i2c3_sdam1 */
 941         RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
 942         RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
 943         RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
 944         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
 945         RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
 946         RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
 947         RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
 948         RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
 949 };
 950
 951 static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
 952         RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
 953         RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
 954         RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
 955         RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
 956         RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
 957         RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
 958         RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
 959         RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
 960         RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
 961         RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
 962         RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
 963         RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
 964 };
 965
 966 static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
 967         RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
 968         RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
 969         RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
 970         RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
 971         RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
 972 };
 973
 974 static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
 975         RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
 976         RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
 977         RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
 978         RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
 979         RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
 980         RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
 981         RK_MUXROUTE_GRF(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
 982         RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
 983         RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
 984         RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
 985         RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
 986         RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
 987         RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
 988         RK_MUXROUTE_GRF(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
 989         RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
 990         RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
 991         RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
 992         RK_MUXROUTE_GRF(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
 993         RK_MUXROUTE_GRF(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
 994         RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
 995         RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
 996         RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
 997         RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
 998         RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
 999         RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1000         RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1001         RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1002         RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1003         RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1004         RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1005         RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1006         RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1007         RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1008         RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1009         RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1010         RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1011         RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1012         RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1013         RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1014         RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1015         RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1016         RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1017         RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1018         RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1019         RK_MUXROUTE_GRF(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1020         RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1021         RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1022         RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1023         RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1024         RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1025         RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1026         RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1027         RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1028         RK_MUXROUTE_GRF(3, RK_PD6, 4, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1029         RK_MUXROUTE_GRF(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1030         RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1031         RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1032         RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1033         RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1034         RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1035         RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1036         RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1037         RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1038         RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1039         RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1040         RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1041         RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1042         RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1043         RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1044         RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1045         RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1046         RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1047         RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1048         RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1049         RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1050         RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1051         RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1052         RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1053         RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1054         RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1055         RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1056         RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1057         RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1058         RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1059         RK_MUXROUTE_GRF(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1060         RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1061         RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1062         RK_MUXROUTE_GRF(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1063         RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1064         RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1065         RK_MUXROUTE_GRF(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1066         RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1067         RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1068 };
1069
1070 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1071                                    int mux, u32 *loc, u32 *reg, u32 *value)
1072 {
1073         struct rockchip_pinctrl *info = bank->drvdata;
1074         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1075         struct rockchip_mux_route_data *data;
1076         int i;
1077
1078         for (i = 0; i < ctrl->niomux_routes; i++) {
1079                 data = &ctrl->iomux_routes[i];
1080                 if ((data->bank_num == bank->bank_num) &&
1081                     (data->pin == pin) && (data->func == mux))
1082                         break;
1083         }
1084
1085         if (i >= ctrl->niomux_routes)
1086                 return false;
1087
1088         *loc = data->route_location;
1089         *reg = data->route_offset;
1090         *value = data->route_val;
1091
1092         return true;
1093 }
1094
1095 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1096 {
1097         struct rockchip_pinctrl *info = bank->drvdata;
1098         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1099         int iomux_num = (pin / 8);
1100         struct regmap *regmap;
1101         unsigned int val;
1102         int reg, ret, mask, mux_type;
1103         u8 bit;
1104
1105         if (iomux_num > 3)
1106                 return -EINVAL;
1107
1108         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1109                 dev_err(info->dev, "pin %d is unrouted\n", pin);
1110                 return -EINVAL;
1111         }
1112
1113         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1114                 return RK_FUNC_GPIO;
1115
1116         if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1117                 regmap = info->regmap_pmu;
1118         else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1119                 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1120         else
1121                 regmap = info->regmap_base;
1122
1123         /* get basic quadrupel of mux registers and the correct reg inside */
1124         mux_type = bank->iomux[iomux_num].type;
1125         reg = bank->iomux[iomux_num].offset;
1126         if (mux_type & IOMUX_WIDTH_4BIT) {
1127                 if ((pin % 8) >= 4)
1128                         reg += 0x4;
1129                 bit = (pin % 4) * 4;
1130                 mask = 0xf;
1131         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1132                 if ((pin % 8) >= 5)
1133                         reg += 0x4;
1134                 bit = (pin % 8 % 5) * 3;
1135                 mask = 0x7;
1136         } else {
1137                 bit = (pin % 8) * 2;
1138                 mask = 0x3;
1139         }
1140
1141         if (bank->recalced_mask & BIT(pin))
1142                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1143
1144         if (ctrl->type == RK3576) {
1145                 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1146                         reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1147         }
1148
1149         if (ctrl->type == RK3588) {
1150                 if (bank->bank_num == 0) {
1151                         if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1152                                 u32 reg0 = 0;
1153
1154                                 reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1155                                 ret = regmap_read(regmap, reg0, &val);
1156                                 if (ret)
1157                                         return ret;
1158
1159                                 if (!(val & BIT(8)))
1160                                         return ((val >> bit) & mask);
1161
1162                                 reg = reg + 0x8000; /* BUS_IOC_BASE */
1163                                 regmap = info->regmap_base;
1164                         }
1165                 } else if (bank->bank_num > 0) {
1166                         reg += 0x8000; /* BUS_IOC_BASE */
1167                 }
1168         }
1169
1170         ret = regmap_read(regmap, reg, &val);
1171         if (ret)
1172                 return ret;
1173
1174         return ((val >> bit) & mask);
1175 }
1176
1177 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1178                                int pin, int mux)
1179 {
1180         struct rockchip_pinctrl *info = bank->drvdata;
1181         struct device *dev = info->dev;
1182         int iomux_num = (pin / 8);
1183
1184         if (iomux_num > 3)
1185                 return -EINVAL;
1186
1187         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1188                 dev_err(dev, "pin %d is unrouted\n", pin);
1189                 return -EINVAL;
1190         }
1191
1192         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1193                 if (mux != RK_FUNC_GPIO) {
1194                         dev_err(dev, "pin %d only supports a gpio mux\n", pin);
1195                         return -ENOTSUPP;
1196                 }
1197         }
1198
1199         return 0;
1200 }
1201
1202 /*
1203  * Set a new mux function for a pin.
1204  *
1205  * The register is divided into the upper and lower 16 bit. When changing
1206  * a value, the previous register value is not read and changed. Instead
1207  * it seems the changed bits are marked in the upper 16 bit, while the
1208  * changed value gets set in the same offset in the lower 16 bit.
1209  * All pin settings seem to be 2 bit wide in both the upper and lower
1210  * parts.
1211  * @bank: pin bank to change
1212  * @pin: pin to change
1213  * @mux: new mux function to set
1214  */
1215 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
1216 {
1217         struct rockchip_pinctrl *info = bank->drvdata;
1218         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1219         struct device *dev = info->dev;
1220         int iomux_num = (pin / 8);
1221         struct regmap *regmap;
1222         int reg, ret, mask, mux_type;
1223         u8 bit;
1224         u32 data, rmask, route_location, route_reg, route_val;
1225
1226         ret = rockchip_verify_mux(bank, pin, mux);
1227         if (ret < 0)
1228                 return ret;
1229
1230         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1231                 return 0;
1232
1233         dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
1234
1235         if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1236                 regmap = info->regmap_pmu;
1237         else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
1238                 regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
1239         else
1240                 regmap = info->regmap_base;
1241
1242         /* get basic quadrupel of mux registers and the correct reg inside */
1243         mux_type = bank->iomux[iomux_num].type;
1244         reg = bank->iomux[iomux_num].offset;
1245         if (mux_type & IOMUX_WIDTH_4BIT) {
1246                 if ((pin % 8) >= 4)
1247                         reg += 0x4;
1248                 bit = (pin % 4) * 4;
1249                 mask = 0xf;
1250         } else if (mux_type & IOMUX_WIDTH_3BIT) {
1251                 if ((pin % 8) >= 5)
1252                         reg += 0x4;
1253                 bit = (pin % 8 % 5) * 3;
1254                 mask = 0x7;
1255         } else {
1256                 bit = (pin % 8) * 2;
1257                 mask = 0x3;
1258         }
1259
1260         if (bank->recalced_mask & BIT(pin))
1261                 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
1262
1263         if (ctrl->type == RK3576) {
1264                 if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
1265                         reg += 0x1ff4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
1266         }
1267
1268         if (ctrl->type == RK3588) {
1269                 if (bank->bank_num == 0) {
1270                         if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
1271                                 if (mux < 8) {
1272                                         reg += 0x4000 - 0xC; /* PMU2_IOC_BASE */
1273                                         data = (mask << (bit + 16));
1274                                         rmask = data | (data >> 16);
1275                                         data |= (mux & mask) << bit;
1276                                         ret = regmap_update_bits(regmap, reg, rmask, data);
1277                                 } else {
1278                                         u32 reg0 = 0;
1279
1280                                         reg0 = reg + 0x4000 - 0xC; /* PMU2_IOC_BASE */
1281                                         data = (mask << (bit + 16));
1282                                         rmask = data | (data >> 16);
1283                                         data |= 8 << bit;
1284                                         ret = regmap_update_bits(regmap, reg0, rmask, data);
1285
1286                                         reg0 = reg + 0x8000; /* BUS_IOC_BASE */
1287                                         data = (mask << (bit + 16));
1288                                         rmask = data | (data >> 16);
1289                                         data |= mux << bit;
1290                                         regmap = info->regmap_base;
1291                                         ret |= regmap_update_bits(regmap, reg0, rmask, data);
1292                                 }
1293                         } else {
1294                                 data = (mask << (bit + 16));
1295                                 rmask = data | (data >> 16);
1296                                 data |= (mux & mask) << bit;
1297                                 ret = regmap_update_bits(regmap, reg, rmask, data);
1298                         }
1299                         return ret;
1300                 } else if (bank->bank_num > 0) {
1301                         reg += 0x8000; /* BUS_IOC_BASE */
1302                 }
1303         }
1304
1305         if (mux > mask)
1306                 return -EINVAL;
1307
1308         if (bank->route_mask & BIT(pin)) {
1309                 if (rockchip_get_mux_route(bank, pin, mux, &route_location,
1310                                            &route_reg, &route_val)) {
1311                         struct regmap *route_regmap = regmap;
1312
1313                         /* handle special locations */
1314                         switch (route_location) {
1315                         case ROCKCHIP_ROUTE_PMU:
1316                                 route_regmap = info->regmap_pmu;
1317                                 break;
1318                         case ROCKCHIP_ROUTE_GRF:
1319                                 route_regmap = info->regmap_base;
1320                                 break;
1321                         }
1322
1323                         ret = regmap_write(route_regmap, route_reg, route_val);
1324                         if (ret)
1325                                 return ret;
1326                 }
1327         }
1328
1329         data = (mask << (bit + 16));
1330         rmask = data | (data >> 16);
1331         data |= (mux & mask) << bit;
1332         ret = regmap_update_bits(regmap, reg, rmask, data);
1333
1334         return ret;
1335 }
1336
1337 #define PX30_PULL_PMU_OFFSET            0x10
1338 #define PX30_PULL_GRF_OFFSET            0x60
1339 #define PX30_PULL_BITS_PER_PIN          2
1340 #define PX30_PULL_PINS_PER_REG          8
1341 #define PX30_PULL_BANK_STRIDE           16
1342
1343 static int px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1344                                       int pin_num, struct regmap **regmap,
1345                                       int *reg, u8 *bit)
1346 {
1347         struct rockchip_pinctrl *info = bank->drvdata;
1348
1349         /* The first 32 pins of the first bank are located in PMU */
1350         if (bank->bank_num == 0) {
1351                 *regmap = info->regmap_pmu;
1352                 *reg = PX30_PULL_PMU_OFFSET;
1353         } else {
1354                 *regmap = info->regmap_base;
1355                 *reg = PX30_PULL_GRF_OFFSET;
1356
1357                 /* correct the offset, as we're starting with the 2nd bank */
1358                 *reg -= 0x10;
1359                 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
1360         }
1361
1362         *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
1363         *bit = (pin_num % PX30_PULL_PINS_PER_REG);
1364         *bit *= PX30_PULL_BITS_PER_PIN;
1365
1366         return 0;
1367 }
1368
1369 #define PX30_DRV_PMU_OFFSET             0x20
1370 #define PX30_DRV_GRF_OFFSET             0xf0
1371 #define PX30_DRV_BITS_PER_PIN           2
1372 #define PX30_DRV_PINS_PER_REG           8
1373 #define PX30_DRV_BANK_STRIDE            16
1374
1375 static int px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1376                                      int pin_num, struct regmap **regmap,
1377                                      int *reg, u8 *bit)
1378 {
1379         struct rockchip_pinctrl *info = bank->drvdata;
1380
1381         /* The first 32 pins of the first bank are located in PMU */
1382         if (bank->bank_num == 0) {
1383                 *regmap = info->regmap_pmu;
1384                 *reg = PX30_DRV_PMU_OFFSET;
1385         } else {
1386                 *regmap = info->regmap_base;
1387                 *reg = PX30_DRV_GRF_OFFSET;
1388
1389                 /* correct the offset, as we're starting with the 2nd bank */
1390                 *reg -= 0x10;
1391                 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
1392         }
1393
1394         *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
1395         *bit = (pin_num % PX30_DRV_PINS_PER_REG);
1396         *bit *= PX30_DRV_BITS_PER_PIN;
1397
1398         return 0;
1399 }
1400
1401 #define PX30_SCHMITT_PMU_OFFSET                 0x38
1402 #define PX30_SCHMITT_GRF_OFFSET                 0xc0
1403 #define PX30_SCHMITT_PINS_PER_PMU_REG           16
1404 #define PX30_SCHMITT_BANK_STRIDE                16
1405 #define PX30_SCHMITT_PINS_PER_GRF_REG           8
1406
1407 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1408                                          int pin_num,
1409                                          struct regmap **regmap,
1410                                          int *reg, u8 *bit)
1411 {
1412         struct rockchip_pinctrl *info = bank->drvdata;
1413         int pins_per_reg;
1414
1415         if (bank->bank_num == 0) {
1416                 *regmap = info->regmap_pmu;
1417                 *reg = PX30_SCHMITT_PMU_OFFSET;
1418                 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
1419         } else {
1420                 *regmap = info->regmap_base;
1421                 *reg = PX30_SCHMITT_GRF_OFFSET;
1422                 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
1423                 *reg += (bank->bank_num  - 1) * PX30_SCHMITT_BANK_STRIDE;
1424         }
1425
1426         *reg += ((pin_num / pins_per_reg) * 4);
1427         *bit = pin_num % pins_per_reg;
1428
1429         return 0;
1430 }
1431
1432 #define RV1108_PULL_PMU_OFFSET          0x10
1433 #define RV1108_PULL_OFFSET              0x110
1434 #define RV1108_PULL_PINS_PER_REG        8
1435 #define RV1108_PULL_BITS_PER_PIN        2
1436 #define RV1108_PULL_BANK_STRIDE         16
1437
1438 static int rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1439                                         int pin_num, struct regmap **regmap,
1440                                         int *reg, u8 *bit)
1441 {
1442         struct rockchip_pinctrl *info = bank->drvdata;
1443
1444         /* The first 24 pins of the first bank are located in PMU */
1445         if (bank->bank_num == 0) {
1446                 *regmap = info->regmap_pmu;
1447                 *reg = RV1108_PULL_PMU_OFFSET;
1448         } else {
1449                 *reg = RV1108_PULL_OFFSET;
1450                 *regmap = info->regmap_base;
1451                 /* correct the offset, as we're starting with the 2nd bank */
1452                 *reg -= 0x10;
1453                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
1454         }
1455
1456         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1457         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1458         *bit *= RV1108_PULL_BITS_PER_PIN;
1459
1460         return 0;
1461 }
1462
1463 #define RV1108_DRV_PMU_OFFSET           0x20
1464 #define RV1108_DRV_GRF_OFFSET           0x210
1465 #define RV1108_DRV_BITS_PER_PIN         2
1466 #define RV1108_DRV_PINS_PER_REG         8
1467 #define RV1108_DRV_BANK_STRIDE          16
1468
1469 static int rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1470                                        int pin_num, struct regmap **regmap,
1471                                        int *reg, u8 *bit)
1472 {
1473         struct rockchip_pinctrl *info = bank->drvdata;
1474
1475         /* The first 24 pins of the first bank are located in PMU */
1476         if (bank->bank_num == 0) {
1477                 *regmap = info->regmap_pmu;
1478                 *reg = RV1108_DRV_PMU_OFFSET;
1479         } else {
1480                 *regmap = info->regmap_base;
1481                 *reg = RV1108_DRV_GRF_OFFSET;
1482
1483                 /* correct the offset, as we're starting with the 2nd bank */
1484                 *reg -= 0x10;
1485                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
1486         }
1487
1488         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1489         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1490         *bit *= RV1108_DRV_BITS_PER_PIN;
1491
1492         return 0;
1493 }
1494
1495 #define RV1108_SCHMITT_PMU_OFFSET               0x30
1496 #define RV1108_SCHMITT_GRF_OFFSET               0x388
1497 #define RV1108_SCHMITT_BANK_STRIDE              8
1498 #define RV1108_SCHMITT_PINS_PER_GRF_REG         16
1499 #define RV1108_SCHMITT_PINS_PER_PMU_REG         8
1500
1501 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1502                                            int pin_num,
1503                                            struct regmap **regmap,
1504                                            int *reg, u8 *bit)
1505 {
1506         struct rockchip_pinctrl *info = bank->drvdata;
1507         int pins_per_reg;
1508
1509         if (bank->bank_num == 0) {
1510                 *regmap = info->regmap_pmu;
1511                 *reg = RV1108_SCHMITT_PMU_OFFSET;
1512                 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1513         } else {
1514                 *regmap = info->regmap_base;
1515                 *reg = RV1108_SCHMITT_GRF_OFFSET;
1516                 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1517                 *reg += (bank->bank_num  - 1) * RV1108_SCHMITT_BANK_STRIDE;
1518         }
1519         *reg += ((pin_num / pins_per_reg) * 4);
1520         *bit = pin_num % pins_per_reg;
1521
1522         return 0;
1523 }
1524
1525 #define RV1126_PULL_PMU_OFFSET          0x40
1526 #define RV1126_PULL_GRF_GPIO1A0_OFFSET  0x10108
1527 #define RV1126_PULL_PINS_PER_REG        8
1528 #define RV1126_PULL_BITS_PER_PIN        2
1529 #define RV1126_PULL_BANK_STRIDE         16
1530 #define RV1126_GPIO_C4_D7(p)            (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
1531
1532 static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1533                                         int pin_num, struct regmap **regmap,
1534                                         int *reg, u8 *bit)
1535 {
1536         struct rockchip_pinctrl *info = bank->drvdata;
1537
1538         /* The first 24 pins of the first bank are located in PMU */
1539         if (bank->bank_num == 0) {
1540                 if (RV1126_GPIO_C4_D7(pin_num)) {
1541                         *regmap = info->regmap_base;
1542                         *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1543                         *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
1544                         *bit = pin_num % RV1126_PULL_PINS_PER_REG;
1545                         *bit *= RV1126_PULL_BITS_PER_PIN;
1546                         return 0;
1547                 }
1548                 *regmap = info->regmap_pmu;
1549                 *reg = RV1126_PULL_PMU_OFFSET;
1550         } else {
1551                 *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
1552                 *regmap = info->regmap_base;
1553                 *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
1554         }
1555
1556         *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
1557         *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
1558         *bit *= RV1126_PULL_BITS_PER_PIN;
1559
1560         return 0;
1561 }
1562
1563 #define RV1126_DRV_PMU_OFFSET           0x20
1564 #define RV1126_DRV_GRF_GPIO1A0_OFFSET   0x10090
1565 #define RV1126_DRV_BITS_PER_PIN         4
1566 #define RV1126_DRV_PINS_PER_REG         4
1567 #define RV1126_DRV_BANK_STRIDE          32
1568
1569 static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1570                                        int pin_num, struct regmap **regmap,
1571                                        int *reg, u8 *bit)
1572 {
1573         struct rockchip_pinctrl *info = bank->drvdata;
1574
1575         /* The first 24 pins of the first bank are located in PMU */
1576         if (bank->bank_num == 0) {
1577                 if (RV1126_GPIO_C4_D7(pin_num)) {
1578                         *regmap = info->regmap_base;
1579                         *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1580                         *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
1581                         *reg -= 0x4;
1582                         *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1583                         *bit *= RV1126_DRV_BITS_PER_PIN;
1584                         return 0;
1585                 }
1586                 *regmap = info->regmap_pmu;
1587                 *reg = RV1126_DRV_PMU_OFFSET;
1588         } else {
1589                 *regmap = info->regmap_base;
1590                 *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
1591                 *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
1592         }
1593
1594         *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
1595         *bit = pin_num % RV1126_DRV_PINS_PER_REG;
1596         *bit *= RV1126_DRV_BITS_PER_PIN;
1597
1598         return 0;
1599 }
1600
1601 #define RV1126_SCHMITT_PMU_OFFSET               0x60
1602 #define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET       0x10188
1603 #define RV1126_SCHMITT_BANK_STRIDE              16
1604 #define RV1126_SCHMITT_PINS_PER_GRF_REG         8
1605 #define RV1126_SCHMITT_PINS_PER_PMU_REG         8
1606
1607 static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1608                                            int pin_num,
1609                                            struct regmap **regmap,
1610                                            int *reg, u8 *bit)
1611 {
1612         struct rockchip_pinctrl *info = bank->drvdata;
1613         int pins_per_reg;
1614
1615         if (bank->bank_num == 0) {
1616                 if (RV1126_GPIO_C4_D7(pin_num)) {
1617                         *regmap = info->regmap_base;
1618                         *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1619                         *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
1620                         *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
1621                         return 0;
1622                 }
1623                 *regmap = info->regmap_pmu;
1624                 *reg = RV1126_SCHMITT_PMU_OFFSET;
1625                 pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
1626         } else {
1627                 *regmap = info->regmap_base;
1628                 *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
1629                 pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
1630                 *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
1631         }
1632         *reg += ((pin_num / pins_per_reg) * 4);
1633         *bit = pin_num % pins_per_reg;
1634
1635         return 0;
1636 }
1637
1638 #define RK3308_SCHMITT_PINS_PER_REG             8
1639 #define RK3308_SCHMITT_BANK_STRIDE              16
1640 #define RK3308_SCHMITT_GRF_OFFSET               0x1a0
1641
1642 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1643                                     int pin_num, struct regmap **regmap,
1644                                     int *reg, u8 *bit)
1645 {
1646         struct rockchip_pinctrl *info = bank->drvdata;
1647
1648         *regmap = info->regmap_base;
1649         *reg = RK3308_SCHMITT_GRF_OFFSET;
1650
1651         *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
1652         *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
1653         *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
1654
1655         return 0;
1656 }
1657
1658 #define RK2928_PULL_OFFSET              0x118
1659 #define RK2928_PULL_PINS_PER_REG        16
1660 #define RK2928_PULL_BANK_STRIDE         8
1661
1662 static int rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1663                                         int pin_num, struct regmap **regmap,
1664                                         int *reg, u8 *bit)
1665 {
1666         struct rockchip_pinctrl *info = bank->drvdata;
1667
1668         *regmap = info->regmap_base;
1669         *reg = RK2928_PULL_OFFSET;
1670         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1671         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1672
1673         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1674
1675         return 0;
1676 };
1677
1678 #define RK3128_PULL_OFFSET      0x118
1679
1680 static int rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1681                                         int pin_num, struct regmap **regmap,
1682                                         int *reg, u8 *bit)
1683 {
1684         struct rockchip_pinctrl *info = bank->drvdata;
1685
1686         *regmap = info->regmap_base;
1687         *reg = RK3128_PULL_OFFSET;
1688         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1689         *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1690
1691         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1692
1693         return 0;
1694 }
1695
1696 #define RK3188_PULL_OFFSET              0x164
1697 #define RK3188_PULL_BITS_PER_PIN        2
1698 #define RK3188_PULL_PINS_PER_REG        8
1699 #define RK3188_PULL_BANK_STRIDE         16
1700 #define RK3188_PULL_PMU_OFFSET          0x64
1701
1702 static int rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1703                                         int pin_num, struct regmap **regmap,
1704                                         int *reg, u8 *bit)
1705 {
1706         struct rockchip_pinctrl *info = bank->drvdata;
1707
1708         /* The first 12 pins of the first bank are located elsewhere */
1709         if (bank->bank_num == 0 && pin_num < 12) {
1710                 *regmap = info->regmap_pmu ? info->regmap_pmu
1711                                            : bank->regmap_pull;
1712                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
1713                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1714                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1715                 *bit *= RK3188_PULL_BITS_PER_PIN;
1716         } else {
1717                 *regmap = info->regmap_pull ? info->regmap_pull
1718                                             : info->regmap_base;
1719                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1720
1721                 /* correct the offset, as it is the 2nd pull register */
1722                 *reg -= 4;
1723                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1724                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1725
1726                 /*
1727                  * The bits in these registers have an inverse ordering
1728                  * with the lowest pin being in bits 15:14 and the highest
1729                  * pin in bits 1:0
1730                  */
1731                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1732                 *bit *= RK3188_PULL_BITS_PER_PIN;
1733         }
1734
1735         return 0;
1736 }
1737
1738 #define RK3288_PULL_OFFSET              0x140
1739 static int rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1740                                         int pin_num, struct regmap **regmap,
1741                                         int *reg, u8 *bit)
1742 {
1743         struct rockchip_pinctrl *info = bank->drvdata;
1744
1745         /* The first 24 pins of the first bank are located in PMU */
1746         if (bank->bank_num == 0) {
1747                 *regmap = info->regmap_pmu;
1748                 *reg = RK3188_PULL_PMU_OFFSET;
1749
1750                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1751                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1752                 *bit *= RK3188_PULL_BITS_PER_PIN;
1753         } else {
1754                 *regmap = info->regmap_base;
1755                 *reg = RK3288_PULL_OFFSET;
1756
1757                 /* correct the offset, as we're starting with the 2nd bank */
1758                 *reg -= 0x10;
1759                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1760                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1761
1762                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1763                 *bit *= RK3188_PULL_BITS_PER_PIN;
1764         }
1765
1766         return 0;
1767 }
1768
1769 #define RK3288_DRV_PMU_OFFSET           0x70
1770 #define RK3288_DRV_GRF_OFFSET           0x1c0
1771 #define RK3288_DRV_BITS_PER_PIN         2
1772 #define RK3288_DRV_PINS_PER_REG         8
1773 #define RK3288_DRV_BANK_STRIDE          16
1774
1775 static int rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1776                                        int pin_num, struct regmap **regmap,
1777                                        int *reg, u8 *bit)
1778 {
1779         struct rockchip_pinctrl *info = bank->drvdata;
1780
1781         /* The first 24 pins of the first bank are located in PMU */
1782         if (bank->bank_num == 0) {
1783                 *regmap = info->regmap_pmu;
1784                 *reg = RK3288_DRV_PMU_OFFSET;
1785
1786                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1787                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1788                 *bit *= RK3288_DRV_BITS_PER_PIN;
1789         } else {
1790                 *regmap = info->regmap_base;
1791                 *reg = RK3288_DRV_GRF_OFFSET;
1792
1793                 /* correct the offset, as we're starting with the 2nd bank */
1794                 *reg -= 0x10;
1795                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1796                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1797
1798                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1799                 *bit *= RK3288_DRV_BITS_PER_PIN;
1800         }
1801
1802         return 0;
1803 }
1804
1805 #define RK3228_PULL_OFFSET              0x100
1806
1807 static int rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1808                                         int pin_num, struct regmap **regmap,
1809                                         int *reg, u8 *bit)
1810 {
1811         struct rockchip_pinctrl *info = bank->drvdata;
1812
1813         *regmap = info->regmap_base;
1814         *reg = RK3228_PULL_OFFSET;
1815         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1816         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1817
1818         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1819         *bit *= RK3188_PULL_BITS_PER_PIN;
1820
1821         return 0;
1822 }
1823
1824 #define RK3228_DRV_GRF_OFFSET           0x200
1825
1826 static int rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1827                                        int pin_num, struct regmap **regmap,
1828                                        int *reg, u8 *bit)
1829 {
1830         struct rockchip_pinctrl *info = bank->drvdata;
1831
1832         *regmap = info->regmap_base;
1833         *reg = RK3228_DRV_GRF_OFFSET;
1834         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1835         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1836
1837         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1838         *bit *= RK3288_DRV_BITS_PER_PIN;
1839
1840         return 0;
1841 }
1842
1843 #define RK3308_PULL_OFFSET              0xa0
1844
1845 static int rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1846                                         int pin_num, struct regmap **regmap,
1847                                         int *reg, u8 *bit)
1848 {
1849         struct rockchip_pinctrl *info = bank->drvdata;
1850
1851         *regmap = info->regmap_base;
1852         *reg = RK3308_PULL_OFFSET;
1853         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1854         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1855
1856         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1857         *bit *= RK3188_PULL_BITS_PER_PIN;
1858
1859         return 0;
1860 }
1861
1862 #define RK3308_DRV_GRF_OFFSET           0x100
1863
1864 static int rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1865                                        int pin_num, struct regmap **regmap,
1866                                        int *reg, u8 *bit)
1867 {
1868         struct rockchip_pinctrl *info = bank->drvdata;
1869
1870         *regmap = info->regmap_base;
1871         *reg = RK3308_DRV_GRF_OFFSET;
1872         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1873         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1874
1875         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1876         *bit *= RK3288_DRV_BITS_PER_PIN;
1877
1878         return 0;
1879 }
1880
1881 #define RK3368_PULL_GRF_OFFSET          0x100
1882 #define RK3368_PULL_PMU_OFFSET          0x10
1883
1884 static int rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1885                                         int pin_num, struct regmap **regmap,
1886                                         int *reg, u8 *bit)
1887 {
1888         struct rockchip_pinctrl *info = bank->drvdata;
1889
1890         /* The first 32 pins of the first bank are located in PMU */
1891         if (bank->bank_num == 0) {
1892                 *regmap = info->regmap_pmu;
1893                 *reg = RK3368_PULL_PMU_OFFSET;
1894
1895                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1896                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1897                 *bit *= RK3188_PULL_BITS_PER_PIN;
1898         } else {
1899                 *regmap = info->regmap_base;
1900                 *reg = RK3368_PULL_GRF_OFFSET;
1901
1902                 /* correct the offset, as we're starting with the 2nd bank */
1903                 *reg -= 0x10;
1904                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1905                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1906
1907                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1908                 *bit *= RK3188_PULL_BITS_PER_PIN;
1909         }
1910
1911         return 0;
1912 }
1913
1914 #define RK3368_DRV_PMU_OFFSET           0x20
1915 #define RK3368_DRV_GRF_OFFSET           0x200
1916
1917 static int rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1918                                        int pin_num, struct regmap **regmap,
1919                                        int *reg, u8 *bit)
1920 {
1921         struct rockchip_pinctrl *info = bank->drvdata;
1922
1923         /* The first 32 pins of the first bank are located in PMU */
1924         if (bank->bank_num == 0) {
1925                 *regmap = info->regmap_pmu;
1926                 *reg = RK3368_DRV_PMU_OFFSET;
1927
1928                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1929                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1930                 *bit *= RK3288_DRV_BITS_PER_PIN;
1931         } else {
1932                 *regmap = info->regmap_base;
1933                 *reg = RK3368_DRV_GRF_OFFSET;
1934
1935                 /* correct the offset, as we're starting with the 2nd bank */
1936                 *reg -= 0x10;
1937                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1938                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1939
1940                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1941                 *bit *= RK3288_DRV_BITS_PER_PIN;
1942         }
1943
1944         return 0;
1945 }
1946
1947 #define RK3399_PULL_GRF_OFFSET          0xe040
1948 #define RK3399_PULL_PMU_OFFSET          0x40
1949 #define RK3399_DRV_3BITS_PER_PIN        3
1950
1951 static int rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1952                                         int pin_num, struct regmap **regmap,
1953                                         int *reg, u8 *bit)
1954 {
1955         struct rockchip_pinctrl *info = bank->drvdata;
1956
1957         /* The bank0:16 and bank1:32 pins are located in PMU */
1958         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1959                 *regmap = info->regmap_pmu;
1960                 *reg = RK3399_PULL_PMU_OFFSET;
1961
1962                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1963
1964                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1965                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1966                 *bit *= RK3188_PULL_BITS_PER_PIN;
1967         } else {
1968                 *regmap = info->regmap_base;
1969                 *reg = RK3399_PULL_GRF_OFFSET;
1970
1971                 /* correct the offset, as we're starting with the 3rd bank */
1972                 *reg -= 0x20;
1973                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1974                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1975
1976                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1977                 *bit *= RK3188_PULL_BITS_PER_PIN;
1978         }
1979
1980         return 0;
1981 }
1982
1983 static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1984                                        int pin_num, struct regmap **regmap,
1985                                        int *reg, u8 *bit)
1986 {
1987         struct rockchip_pinctrl *info = bank->drvdata;
1988         int drv_num = (pin_num / 8);
1989
1990         /*  The bank0:16 and bank1:32 pins are located in PMU */
1991         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1992                 *regmap = info->regmap_pmu;
1993         else
1994                 *regmap = info->regmap_base;
1995
1996         *reg = bank->drv[drv_num].offset;
1997         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1998             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1999                 *bit = (pin_num % 8) * 3;
2000         else
2001                 *bit = (pin_num % 8) * 2;
2002
2003         return 0;
2004 }
2005
2006 #define RK3568_PULL_PMU_OFFSET          0x20
2007 #define RK3568_PULL_GRF_OFFSET          0x80
2008 #define RK3568_PULL_BITS_PER_PIN        2
2009 #define RK3568_PULL_PINS_PER_REG        8
2010 #define RK3568_PULL_BANK_STRIDE         0x10
2011
2012 static int rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2013                                         int pin_num, struct regmap **regmap,
2014                                         int *reg, u8 *bit)
2015 {
2016         struct rockchip_pinctrl *info = bank->drvdata;
2017
2018         if (bank->bank_num == 0) {
2019                 *regmap = info->regmap_pmu;
2020                 *reg = RK3568_PULL_PMU_OFFSET;
2021                 *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
2022                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2023
2024                 *bit = pin_num % RK3568_PULL_PINS_PER_REG;
2025                 *bit *= RK3568_PULL_BITS_PER_PIN;
2026         } else {
2027                 *regmap = info->regmap_base;
2028                 *reg = RK3568_PULL_GRF_OFFSET;
2029                 *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
2030                 *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2031
2032                 *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2033                 *bit *= RK3568_PULL_BITS_PER_PIN;
2034         }
2035
2036         return 0;
2037 }
2038
2039 #define RK3568_DRV_PMU_OFFSET           0x70
2040 #define RK3568_DRV_GRF_OFFSET           0x200
2041 #define RK3568_DRV_BITS_PER_PIN         8
2042 #define RK3568_DRV_PINS_PER_REG         2
2043 #define RK3568_DRV_BANK_STRIDE          0x40
2044
2045 static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2046                                        int pin_num, struct regmap **regmap,
2047                                        int *reg, u8 *bit)
2048 {
2049         struct rockchip_pinctrl *info = bank->drvdata;
2050
2051         /* The first 32 pins of the first bank are located in PMU */
2052         if (bank->bank_num == 0) {
2053                 *regmap = info->regmap_pmu;
2054                 *reg = RK3568_DRV_PMU_OFFSET;
2055                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2056
2057                 *bit = pin_num % RK3568_DRV_PINS_PER_REG;
2058                 *bit *= RK3568_DRV_BITS_PER_PIN;
2059         } else {
2060                 *regmap = info->regmap_base;
2061                 *reg = RK3568_DRV_GRF_OFFSET;
2062                 *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2063                 *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2064
2065                 *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2066                 *bit *= RK3568_DRV_BITS_PER_PIN;
2067         }
2068
2069         return 0;
2070 }
2071
2072 #define RK3576_DRV_BITS_PER_PIN         4
2073 #define RK3576_DRV_PINS_PER_REG         4
2074 #define RK3576_DRV_GPIO0_AL_OFFSET      0x10
2075 #define RK3576_DRV_GPIO0_BH_OFFSET      0x2014
2076 #define RK3576_DRV_GPIO1_OFFSET         0x6020
2077 #define RK3576_DRV_GPIO2_OFFSET         0x6040
2078 #define RK3576_DRV_GPIO3_OFFSET         0x6060
2079 #define RK3576_DRV_GPIO4_AL_OFFSET      0x6080
2080 #define RK3576_DRV_GPIO4_CL_OFFSET      0xA090
2081 #define RK3576_DRV_GPIO4_DL_OFFSET      0xB098
2082
2083 static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2084                                         int pin_num, struct regmap **regmap,
2085                                         int *reg, u8 *bit)
2086 {
2087         struct rockchip_pinctrl *info = bank->drvdata;
2088
2089         *regmap = info->regmap_base;
2090
2091         if (bank->bank_num == 0 && pin_num < 12)
2092                 *reg = RK3576_DRV_GPIO0_AL_OFFSET;
2093         else if (bank->bank_num == 0)
2094                 *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
2095         else if (bank->bank_num == 1)
2096                 *reg = RK3576_DRV_GPIO1_OFFSET;
2097         else if (bank->bank_num == 2)
2098                 *reg = RK3576_DRV_GPIO2_OFFSET;
2099         else if (bank->bank_num == 3)
2100                 *reg = RK3576_DRV_GPIO3_OFFSET;
2101         else if (bank->bank_num == 4 && pin_num < 16)
2102                 *reg = RK3576_DRV_GPIO4_AL_OFFSET;
2103         else if (bank->bank_num == 4 && pin_num < 24)
2104                 *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
2105         else if (bank->bank_num == 4)
2106                 *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
2107         else
2108                 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2109
2110         *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
2111         *bit = pin_num % RK3576_DRV_PINS_PER_REG;
2112         *bit *= RK3576_DRV_BITS_PER_PIN;
2113
2114         return 0;
2115 }
2116
2117 #define RK3576_PULL_BITS_PER_PIN        2
2118 #define RK3576_PULL_PINS_PER_REG        8
2119 #define RK3576_PULL_GPIO0_AL_OFFSET     0x20
2120 #define RK3576_PULL_GPIO0_BH_OFFSET     0x2028
2121 #define RK3576_PULL_GPIO1_OFFSET        0x6110
2122 #define RK3576_PULL_GPIO2_OFFSET        0x6120
2123 #define RK3576_PULL_GPIO3_OFFSET        0x6130
2124 #define RK3576_PULL_GPIO4_AL_OFFSET     0x6140
2125 #define RK3576_PULL_GPIO4_CL_OFFSET     0xA148
2126 #define RK3576_PULL_GPIO4_DL_OFFSET     0xB14C
2127
2128 static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2129                                          int pin_num, struct regmap **regmap,
2130                                          int *reg, u8 *bit)
2131 {
2132         struct rockchip_pinctrl *info = bank->drvdata;
2133
2134         *regmap = info->regmap_base;
2135
2136         if (bank->bank_num == 0 && pin_num < 12)
2137                 *reg = RK3576_PULL_GPIO0_AL_OFFSET;
2138         else if (bank->bank_num == 0)
2139                 *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
2140         else if (bank->bank_num == 1)
2141                 *reg = RK3576_PULL_GPIO1_OFFSET;
2142         else if (bank->bank_num == 2)
2143                 *reg = RK3576_PULL_GPIO2_OFFSET;
2144         else if (bank->bank_num == 3)
2145                 *reg = RK3576_PULL_GPIO3_OFFSET;
2146         else if (bank->bank_num == 4 && pin_num < 16)
2147                 *reg = RK3576_PULL_GPIO4_AL_OFFSET;
2148         else if (bank->bank_num == 4 && pin_num < 24)
2149                 *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
2150         else if (bank->bank_num == 4)
2151                 *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
2152         else
2153                 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2154
2155         *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
2156         *bit = pin_num % RK3576_PULL_PINS_PER_REG;
2157         *bit *= RK3576_PULL_BITS_PER_PIN;
2158
2159         return 0;
2160 }
2161
2162 #define RK3576_SMT_BITS_PER_PIN         1
2163 #define RK3576_SMT_PINS_PER_REG         8
2164 #define RK3576_SMT_GPIO0_AL_OFFSET      0x30
2165 #define RK3576_SMT_GPIO0_BH_OFFSET      0x2040
2166 #define RK3576_SMT_GPIO1_OFFSET         0x6210
2167 #define RK3576_SMT_GPIO2_OFFSET         0x6220
2168 #define RK3576_SMT_GPIO3_OFFSET         0x6230
2169 #define RK3576_SMT_GPIO4_AL_OFFSET      0x6240
2170 #define RK3576_SMT_GPIO4_CL_OFFSET      0xA248
2171 #define RK3576_SMT_GPIO4_DL_OFFSET      0xB24C
2172
2173 static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2174                                            int pin_num,
2175                                            struct regmap **regmap,
2176                                            int *reg, u8 *bit)
2177 {
2178         struct rockchip_pinctrl *info = bank->drvdata;
2179
2180         *regmap = info->regmap_base;
2181
2182         if (bank->bank_num == 0 && pin_num < 12)
2183                 *reg = RK3576_SMT_GPIO0_AL_OFFSET;
2184         else if (bank->bank_num == 0)
2185                 *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
2186         else if (bank->bank_num == 1)
2187                 *reg = RK3576_SMT_GPIO1_OFFSET;
2188         else if (bank->bank_num == 2)
2189                 *reg = RK3576_SMT_GPIO2_OFFSET;
2190         else if (bank->bank_num == 3)
2191                 *reg = RK3576_SMT_GPIO3_OFFSET;
2192         else if (bank->bank_num == 4 && pin_num < 16)
2193                 *reg = RK3576_SMT_GPIO4_AL_OFFSET;
2194         else if (bank->bank_num == 4 && pin_num < 24)
2195                 *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
2196         else if (bank->bank_num == 4)
2197                 *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
2198         else
2199                 dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
2200
2201         *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
2202         *bit = pin_num % RK3576_SMT_PINS_PER_REG;
2203         *bit *= RK3576_SMT_BITS_PER_PIN;
2204
2205         return 0;
2206 }
2207
2208 #define RK3588_PMU1_IOC_REG             (0x0000)
2209 #define RK3588_PMU2_IOC_REG             (0x4000)
2210 #define RK3588_BUS_IOC_REG              (0x8000)
2211 #define RK3588_VCCIO1_4_IOC_REG         (0x9000)
2212 #define RK3588_VCCIO3_5_IOC_REG         (0xA000)
2213 #define RK3588_VCCIO2_IOC_REG           (0xB000)
2214 #define RK3588_VCCIO6_IOC_REG           (0xC000)
2215 #define RK3588_EMMC_IOC_REG             (0xD000)
2216
2217 static const u32 rk3588_ds_regs[][2] = {
2218         {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0010},
2219         {RK_GPIO0_A4, RK3588_PMU1_IOC_REG + 0x0014},
2220         {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0018},
2221         {RK_GPIO0_B4, RK3588_PMU2_IOC_REG + 0x0014},
2222         {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0018},
2223         {RK_GPIO0_C4, RK3588_PMU2_IOC_REG + 0x001C},
2224         {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0020},
2225         {RK_GPIO0_D4, RK3588_PMU2_IOC_REG + 0x0024},
2226         {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0020},
2227         {RK_GPIO1_A4, RK3588_VCCIO1_4_IOC_REG + 0x0024},
2228         {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0028},
2229         {RK_GPIO1_B4, RK3588_VCCIO1_4_IOC_REG + 0x002C},
2230         {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0030},
2231         {RK_GPIO1_C4, RK3588_VCCIO1_4_IOC_REG + 0x0034},
2232         {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x0038},
2233         {RK_GPIO1_D4, RK3588_VCCIO1_4_IOC_REG + 0x003C},
2234         {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0040},
2235         {RK_GPIO2_A4, RK3588_VCCIO3_5_IOC_REG + 0x0044},
2236         {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0048},
2237         {RK_GPIO2_B4, RK3588_VCCIO3_5_IOC_REG + 0x004C},
2238         {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0050},
2239         {RK_GPIO2_C4, RK3588_VCCIO3_5_IOC_REG + 0x0054},
2240         {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x0058},
2241         {RK_GPIO2_D4, RK3588_EMMC_IOC_REG + 0x005C},
2242         {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0060},
2243         {RK_GPIO3_A4, RK3588_VCCIO3_5_IOC_REG + 0x0064},
2244         {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0068},
2245         {RK_GPIO3_B4, RK3588_VCCIO3_5_IOC_REG + 0x006C},
2246         {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0070},
2247         {RK_GPIO3_C4, RK3588_VCCIO3_5_IOC_REG + 0x0074},
2248         {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x0078},
2249         {RK_GPIO3_D4, RK3588_VCCIO3_5_IOC_REG + 0x007C},
2250         {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0080},
2251         {RK_GPIO4_A4, RK3588_VCCIO6_IOC_REG + 0x0084},
2252         {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0088},
2253         {RK_GPIO4_B4, RK3588_VCCIO6_IOC_REG + 0x008C},
2254         {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0090},
2255         {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0090},
2256         {RK_GPIO4_C4, RK3588_VCCIO3_5_IOC_REG + 0x0094},
2257         {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x0098},
2258         {RK_GPIO4_D4, RK3588_VCCIO2_IOC_REG + 0x009C},
2259 };
2260
2261 static const u32 rk3588_p_regs[][2] = {
2262         {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0020},
2263         {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0024},
2264         {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0028},
2265         {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x002C},
2266         {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0030},
2267         {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0110},
2268         {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0114},
2269         {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0118},
2270         {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x011C},
2271         {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0120},
2272         {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0120},
2273         {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0124},
2274         {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0128},
2275         {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x012C},
2276         {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0130},
2277         {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0134},
2278         {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0138},
2279         {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x013C},
2280         {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0140},
2281         {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0144},
2282         {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0148},
2283         {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0148},
2284         {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x014C},
2285 };
2286
2287 static const u32 rk3588_smt_regs[][2] = {
2288         {RK_GPIO0_A0, RK3588_PMU1_IOC_REG + 0x0030},
2289         {RK_GPIO0_B0, RK3588_PMU1_IOC_REG + 0x0034},
2290         {RK_GPIO0_B5, RK3588_PMU2_IOC_REG + 0x0040},
2291         {RK_GPIO0_C0, RK3588_PMU2_IOC_REG + 0x0044},
2292         {RK_GPIO0_D0, RK3588_PMU2_IOC_REG + 0x0048},
2293         {RK_GPIO1_A0, RK3588_VCCIO1_4_IOC_REG + 0x0210},
2294         {RK_GPIO1_B0, RK3588_VCCIO1_4_IOC_REG + 0x0214},
2295         {RK_GPIO1_C0, RK3588_VCCIO1_4_IOC_REG + 0x0218},
2296         {RK_GPIO1_D0, RK3588_VCCIO1_4_IOC_REG + 0x021C},
2297         {RK_GPIO2_A0, RK3588_EMMC_IOC_REG + 0x0220},
2298         {RK_GPIO2_A6, RK3588_VCCIO3_5_IOC_REG + 0x0220},
2299         {RK_GPIO2_B0, RK3588_VCCIO3_5_IOC_REG + 0x0224},
2300         {RK_GPIO2_C0, RK3588_VCCIO3_5_IOC_REG + 0x0228},
2301         {RK_GPIO2_D0, RK3588_EMMC_IOC_REG + 0x022C},
2302         {RK_GPIO3_A0, RK3588_VCCIO3_5_IOC_REG + 0x0230},
2303         {RK_GPIO3_B0, RK3588_VCCIO3_5_IOC_REG + 0x0234},
2304         {RK_GPIO3_C0, RK3588_VCCIO3_5_IOC_REG + 0x0238},
2305         {RK_GPIO3_D0, RK3588_VCCIO3_5_IOC_REG + 0x023C},
2306         {RK_GPIO4_A0, RK3588_VCCIO6_IOC_REG + 0x0240},
2307         {RK_GPIO4_B0, RK3588_VCCIO6_IOC_REG + 0x0244},
2308         {RK_GPIO4_C0, RK3588_VCCIO6_IOC_REG + 0x0248},
2309         {RK_GPIO4_C2, RK3588_VCCIO3_5_IOC_REG + 0x0248},
2310         {RK_GPIO4_D0, RK3588_VCCIO2_IOC_REG + 0x024C},
2311 };
2312
2313 #define RK3588_PULL_BITS_PER_PIN                2
2314 #define RK3588_PULL_PINS_PER_REG                8
2315
2316 static int rk3588_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2317                                         int pin_num, struct regmap **regmap,
2318                                         int *reg, u8 *bit)
2319 {
2320         struct rockchip_pinctrl *info = bank->drvdata;
2321         u8 bank_num = bank->bank_num;
2322         u32 pin = bank_num * 32 + pin_num;
2323         int i;
2324
2325         for (i = ARRAY_SIZE(rk3588_p_regs) - 1; i >= 0; i--) {
2326                 if (pin >= rk3588_p_regs[i][0]) {
2327                         *reg = rk3588_p_regs[i][1];
2328                         *regmap = info->regmap_base;
2329                         *bit = pin_num % RK3588_PULL_PINS_PER_REG;
2330                         *bit *= RK3588_PULL_BITS_PER_PIN;
2331                         return 0;
2332                 }
2333         }
2334
2335         return -EINVAL;
2336 }
2337
2338 #define RK3588_DRV_BITS_PER_PIN         4
2339 #define RK3588_DRV_PINS_PER_REG         4
2340
2341 static int rk3588_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2342                                        int pin_num, struct regmap **regmap,
2343                                        int *reg, u8 *bit)
2344 {
2345         struct rockchip_pinctrl *info = bank->drvdata;
2346         u8 bank_num = bank->bank_num;
2347         u32 pin = bank_num * 32 + pin_num;
2348         int i;
2349
2350         for (i = ARRAY_SIZE(rk3588_ds_regs) - 1; i >= 0; i--) {
2351                 if (pin >= rk3588_ds_regs[i][0]) {
2352                         *reg = rk3588_ds_regs[i][1];
2353                         *regmap = info->regmap_base;
2354                         *bit = pin_num % RK3588_DRV_PINS_PER_REG;
2355                         *bit *= RK3588_DRV_BITS_PER_PIN;
2356                         return 0;
2357                 }
2358         }
2359
2360         return -EINVAL;
2361 }
2362
2363 #define RK3588_SMT_BITS_PER_PIN         1
2364 #define RK3588_SMT_PINS_PER_REG         8
2365
2366 static int rk3588_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2367                                            int pin_num,
2368                                            struct regmap **regmap,
2369                                            int *reg, u8 *bit)
2370 {
2371         struct rockchip_pinctrl *info = bank->drvdata;
2372         u8 bank_num = bank->bank_num;
2373         u32 pin = bank_num * 32 + pin_num;
2374         int i;
2375
2376         for (i = ARRAY_SIZE(rk3588_smt_regs) - 1; i >= 0; i--) {
2377                 if (pin >= rk3588_smt_regs[i][0]) {
2378                         *reg = rk3588_smt_regs[i][1];
2379                         *regmap = info->regmap_base;
2380                         *bit = pin_num % RK3588_SMT_PINS_PER_REG;
2381                         *bit *= RK3588_SMT_BITS_PER_PIN;
2382                         return 0;
2383                 }
2384         }
2385
2386         return -EINVAL;
2387 }
2388
2389 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
2390         { 2, 4, 8, 12, -1, -1, -1, -1 },
2391         { 3, 6, 9, 12, -1, -1, -1, -1 },
2392         { 5, 10, 15, 20, -1, -1, -1, -1 },
2393         { 4, 6, 8, 10, 12, 14, 16, 18 },
2394         { 4, 7, 10, 13, 16, 19, 22, 26 }
2395 };
2396
2397 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
2398                                      int pin_num)
2399 {
2400         struct rockchip_pinctrl *info = bank->drvdata;
2401         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2402         struct device *dev = info->dev;
2403         struct regmap *regmap;
2404         int reg, ret;
2405         u32 data, temp, rmask_bits;
2406         u8 bit;
2407         int drv_type = bank->drv[pin_num / 8].drv_type;
2408
2409         ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2410         if (ret)
2411                 return ret;
2412
2413         switch (drv_type) {
2414         case DRV_TYPE_IO_1V8_3V0_AUTO:
2415         case DRV_TYPE_IO_3V3_ONLY:
2416                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2417                 switch (bit) {
2418                 case 0 ... 12:
2419                         /* regular case, nothing to do */
2420                         break;
2421                 case 15:
2422                         /*
2423                          * drive-strength offset is special, as it is
2424                          * spread over 2 registers
2425                          */
2426                         ret = regmap_read(regmap, reg, &data);
2427                         if (ret)
2428                                 return ret;
2429
2430                         ret = regmap_read(regmap, reg + 0x4, &temp);
2431                         if (ret)
2432                                 return ret;
2433
2434                         /*
2435                          * the bit data[15] contains bit 0 of the value
2436                          * while temp[1:0] contains bits 2 and 1
2437                          */
2438                         data >>= 15;
2439                         temp &= 0x3;
2440                         temp <<= 1;
2441                         data |= temp;
2442
2443                         return rockchip_perpin_drv_list[drv_type][data];
2444                 case 18 ... 21:
2445                         /* setting fully enclosed in the second register */
2446                         reg += 4;
2447                         bit -= 16;
2448                         break;
2449                 default:
2450                         dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2451                                 bit, drv_type);
2452                         return -EINVAL;
2453                 }
2454
2455                 break;
2456         case DRV_TYPE_IO_DEFAULT:
2457         case DRV_TYPE_IO_1V8_OR_3V0:
2458         case DRV_TYPE_IO_1V8_ONLY:
2459                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2460                 break;
2461         default:
2462                 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2463                 return -EINVAL;
2464         }
2465
2466         ret = regmap_read(regmap, reg, &data);
2467         if (ret)
2468                 return ret;
2469
2470         data >>= bit;
2471         data &= (1 << rmask_bits) - 1;
2472
2473         return rockchip_perpin_drv_list[drv_type][data];
2474 }
2475
2476 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
2477                                      int pin_num, int strength)
2478 {
2479         struct rockchip_pinctrl *info = bank->drvdata;
2480         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2481         struct device *dev = info->dev;
2482         struct regmap *regmap;
2483         int reg, ret, i;
2484         u32 data, rmask, rmask_bits, temp;
2485         u8 bit;
2486         int drv_type = bank->drv[pin_num / 8].drv_type;
2487
2488         dev_dbg(dev, "setting drive of GPIO%d-%d to %d\n",
2489                 bank->bank_num, pin_num, strength);
2490
2491         ret = ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2492         if (ret)
2493                 return ret;
2494         if (ctrl->type == RK3588) {
2495                 rmask_bits = RK3588_DRV_BITS_PER_PIN;
2496                 ret = strength;
2497                 goto config;
2498         } else if (ctrl->type == RK3568) {
2499                 rmask_bits = RK3568_DRV_BITS_PER_PIN;
2500                 ret = (1 << (strength + 1)) - 1;
2501                 goto config;
2502         } else if (ctrl->type == RK3576) {
2503                 rmask_bits = RK3576_DRV_BITS_PER_PIN;
2504                 ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
2505                 goto config;
2506         }
2507
2508         if (ctrl->type == RV1126) {
2509                 rmask_bits = RV1126_DRV_BITS_PER_PIN;
2510                 ret = strength;
2511                 goto config;
2512         }
2513
2514         ret = -EINVAL;
2515         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
2516                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
2517                         ret = i;
2518                         break;
2519                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
2520                         ret = rockchip_perpin_drv_list[drv_type][i];
2521                         break;
2522                 }
2523         }
2524
2525         if (ret < 0) {
2526                 dev_err(dev, "unsupported driver strength %d\n", strength);
2527                 return ret;
2528         }
2529
2530         switch (drv_type) {
2531         case DRV_TYPE_IO_1V8_3V0_AUTO:
2532         case DRV_TYPE_IO_3V3_ONLY:
2533                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
2534                 switch (bit) {
2535                 case 0 ... 12:
2536                         /* regular case, nothing to do */
2537                         break;
2538                 case 15:
2539                         /*
2540                          * drive-strength offset is special, as it is spread
2541                          * over 2 registers, the bit data[15] contains bit 0
2542                          * of the value while temp[1:0] contains bits 2 and 1
2543                          */
2544                         data = (ret & 0x1) << 15;
2545                         temp = (ret >> 0x1) & 0x3;
2546
2547                         rmask = BIT(15) | BIT(31);
2548                         data |= BIT(31);
2549                         ret = regmap_update_bits(regmap, reg, rmask, data);
2550                         if (ret)
2551                                 return ret;
2552
2553                         rmask = 0x3 | (0x3 << 16);
2554                         temp |= (0x3 << 16);
2555                         reg += 0x4;
2556                         ret = regmap_update_bits(regmap, reg, rmask, temp);
2557
2558                         return ret;
2559                 case 18 ... 21:
2560                         /* setting fully enclosed in the second register */
2561                         reg += 4;
2562                         bit -= 16;
2563                         break;
2564                 default:
2565                         dev_err(dev, "unsupported bit: %d for pinctrl drive type: %d\n",
2566                                 bit, drv_type);
2567                         return -EINVAL;
2568                 }
2569                 break;
2570         case DRV_TYPE_IO_DEFAULT:
2571         case DRV_TYPE_IO_1V8_OR_3V0:
2572         case DRV_TYPE_IO_1V8_ONLY:
2573                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
2574                 break;
2575         default:
2576                 dev_err(dev, "unsupported pinctrl drive type: %d\n", drv_type);
2577                 return -EINVAL;
2578         }
2579
2580 config:
2581         /* enable the write to the equivalent lower bits */
2582         data = ((1 << rmask_bits) - 1) << (bit + 16);
2583         rmask = data | (data >> 16);
2584         data |= (ret << bit);
2585
2586         ret = regmap_update_bits(regmap, reg, rmask, data);
2587
2588         return ret;
2589 }
2590
2591 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
2592         {
2593                 PIN_CONFIG_BIAS_DISABLE,
2594                 PIN_CONFIG_BIAS_PULL_UP,
2595                 PIN_CONFIG_BIAS_PULL_DOWN,
2596                 PIN_CONFIG_BIAS_BUS_HOLD
2597         },
2598         {
2599                 PIN_CONFIG_BIAS_DISABLE,
2600                 PIN_CONFIG_BIAS_PULL_DOWN,
2601                 PIN_CONFIG_BIAS_DISABLE,
2602                 PIN_CONFIG_BIAS_PULL_UP
2603         },
2604 };
2605
2606 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
2607 {
2608         struct rockchip_pinctrl *info = bank->drvdata;
2609         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2610         struct device *dev = info->dev;
2611         struct regmap *regmap;
2612         int reg, ret, pull_type;
2613         u8 bit;
2614         u32 data;
2615
2616         /* rk3066b does support any pulls */
2617         if (ctrl->type == RK3066B)
2618                 return PIN_CONFIG_BIAS_DISABLE;
2619
2620         ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2621         if (ret)
2622                 return ret;
2623
2624         ret = regmap_read(regmap, reg, &data);
2625         if (ret)
2626                 return ret;
2627
2628         switch (ctrl->type) {
2629         case RK2928:
2630         case RK3128:
2631                 return !(data & BIT(bit))
2632                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
2633                                 : PIN_CONFIG_BIAS_DISABLE;
2634         case PX30:
2635         case RV1108:
2636         case RK3188:
2637         case RK3288:
2638         case RK3308:
2639         case RK3328:
2640         case RK3368:
2641         case RK3399:
2642         case RK3568:
2643         case RK3576:
2644         case RK3588:
2645                 pull_type = bank->pull_type[pin_num / 8];
2646                 data >>= bit;
2647                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
2648                 /*
2649                  * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2650                  * where that pull up value becomes 3.
2651                  */
2652                 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2653                         if (data == 3)
2654                                 data = 1;
2655                 }
2656
2657                 return rockchip_pull_list[pull_type][data];
2658         default:
2659                 dev_err(dev, "unsupported pinctrl type\n");
2660                 return -EINVAL;
2661         };
2662 }
2663
2664 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
2665                                         int pin_num, int pull)
2666 {
2667         struct rockchip_pinctrl *info = bank->drvdata;
2668         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2669         struct device *dev = info->dev;
2670         struct regmap *regmap;
2671         int reg, ret, i, pull_type;
2672         u8 bit;
2673         u32 data, rmask;
2674
2675         dev_dbg(dev, "setting pull of GPIO%d-%d to %d\n", bank->bank_num, pin_num, pull);
2676
2677         /* rk3066b does support any pulls */
2678         if (ctrl->type == RK3066B)
2679                 return pull ? -EINVAL : 0;
2680
2681         ret = ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2682         if (ret)
2683                 return ret;
2684
2685         switch (ctrl->type) {
2686         case RK2928:
2687         case RK3128:
2688                 data = BIT(bit + 16);
2689                 if (pull == PIN_CONFIG_BIAS_DISABLE)
2690                         data |= BIT(bit);
2691                 ret = regmap_write(regmap, reg, data);
2692                 break;
2693         case PX30:
2694         case RV1108:
2695         case RV1126:
2696         case RK3188:
2697         case RK3288:
2698         case RK3308:
2699         case RK3328:
2700         case RK3368:
2701         case RK3399:
2702         case RK3568:
2703         case RK3576:
2704         case RK3588:
2705                 pull_type = bank->pull_type[pin_num / 8];
2706                 ret = -EINVAL;
2707                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
2708                         i++) {
2709                         if (rockchip_pull_list[pull_type][i] == pull) {
2710                                 ret = i;
2711                                 break;
2712                         }
2713                 }
2714                 /*
2715                  * In the TRM, pull-up being 1 for everything except the GPIO0_D3-D6,
2716                  * where that pull up value becomes 3.
2717                  */
2718                 if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2719                         if (ret == 1)
2720                                 ret = 3;
2721                 }
2722
2723                 if (ret < 0) {
2724                         dev_err(dev, "unsupported pull setting %d\n", pull);
2725                         return ret;
2726                 }
2727
2728                 /* enable the write to the equivalent lower bits */
2729                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
2730                 rmask = data | (data >> 16);
2731                 data |= (ret << bit);
2732
2733                 ret = regmap_update_bits(regmap, reg, rmask, data);
2734                 break;
2735         default:
2736                 dev_err(dev, "unsupported pinctrl type\n");
2737                 return -EINVAL;
2738         }
2739
2740         return ret;
2741 }
2742
2743 #define RK3328_SCHMITT_BITS_PER_PIN             1
2744 #define RK3328_SCHMITT_PINS_PER_REG             16
2745 #define RK3328_SCHMITT_BANK_STRIDE              8
2746 #define RK3328_SCHMITT_GRF_OFFSET               0x380
2747
2748 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2749                                            int pin_num,
2750                                            struct regmap **regmap,
2751                                            int *reg, u8 *bit)
2752 {
2753         struct rockchip_pinctrl *info = bank->drvdata;
2754
2755         *regmap = info->regmap_base;
2756         *reg = RK3328_SCHMITT_GRF_OFFSET;
2757
2758         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
2759         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
2760         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
2761
2762         return 0;
2763 }
2764
2765 #define RK3568_SCHMITT_BITS_PER_PIN             2
2766 #define RK3568_SCHMITT_PINS_PER_REG             8
2767 #define RK3568_SCHMITT_BANK_STRIDE              0x10
2768 #define RK3568_SCHMITT_GRF_OFFSET               0xc0
2769 #define RK3568_SCHMITT_PMUGRF_OFFSET            0x30
2770
2771 static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2772                                            int pin_num,
2773                                            struct regmap **regmap,
2774                                            int *reg, u8 *bit)
2775 {
2776         struct rockchip_pinctrl *info = bank->drvdata;
2777
2778         if (bank->bank_num == 0) {
2779                 *regmap = info->regmap_pmu;
2780                 *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
2781         } else {
2782                 *regmap = info->regmap_base;
2783                 *reg = RK3568_SCHMITT_GRF_OFFSET;
2784                 *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
2785         }
2786
2787         *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
2788         *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
2789         *bit *= RK3568_SCHMITT_BITS_PER_PIN;
2790
2791         return 0;
2792 }
2793
2794 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
2795 {
2796         struct rockchip_pinctrl *info = bank->drvdata;
2797         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2798         struct regmap *regmap;
2799         int reg, ret;
2800         u8 bit;
2801         u32 data;
2802
2803         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2804         if (ret)
2805                 return ret;
2806
2807         ret = regmap_read(regmap, reg, &data);
2808         if (ret)
2809                 return ret;
2810
2811         data >>= bit;
2812         switch (ctrl->type) {
2813         case RK3568:
2814                 return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2815         default:
2816                 break;
2817         }
2818
2819         return data & 0x1;
2820 }
2821
2822 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
2823                                 int pin_num, int enable)
2824 {
2825         struct rockchip_pinctrl *info = bank->drvdata;
2826         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2827         struct device *dev = info->dev;
2828         struct regmap *regmap;
2829         int reg, ret;
2830         u8 bit;
2831         u32 data, rmask;
2832
2833         dev_dbg(dev, "setting input schmitt of GPIO%d-%d to %d\n",
2834                 bank->bank_num, pin_num, enable);
2835
2836         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2837         if (ret)
2838                 return ret;
2839
2840         /* enable the write to the equivalent lower bits */
2841         switch (ctrl->type) {
2842         case RK3568:
2843                 data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2844                 rmask = data | (data >> 16);
2845                 data |= ((enable ? 0x2 : 0x1) << bit);
2846                 break;
2847         default:
2848                 data = BIT(bit + 16) | (enable << bit);
2849                 rmask = BIT(bit + 16) | BIT(bit);
2850                 break;
2851         }
2852
2853         return regmap_update_bits(regmap, reg, rmask, data);
2854 }
2855
2856 /*
2857  * Pinmux_ops handling
2858  */
2859
2860 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
2861 {
2862         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2863
2864         return info->nfunctions;
2865 }
2866
2867 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
2868                                           unsigned selector)
2869 {
2870         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2871
2872         return info->functions[selector].name;
2873 }
2874
2875 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
2876                                 unsigned selector, const char * const **groups,
2877                                 unsigned * const num_groups)
2878 {
2879         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2880
2881         *groups = info->functions[selector].groups;
2882         *num_groups = info->functions[selector].ngroups;
2883
2884         return 0;
2885 }
2886
2887 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
2888                             unsigned group)
2889 {
2890         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2891         const unsigned int *pins = info->groups[group].pins;
2892         const struct rockchip_pin_config *data = info->groups[group].data;
2893         struct device *dev = info->dev;
2894         struct rockchip_pin_bank *bank;
2895         int cnt, ret = 0;
2896
2897         dev_dbg(dev, "enable function %s group %s\n",
2898                 info->functions[selector].name, info->groups[group].name);
2899
2900         /*
2901          * for each pin in the pin group selected, program the corresponding
2902          * pin function number in the config register.
2903          */
2904         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
2905                 bank = pin_to_bank(info, pins[cnt]);
2906                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
2907                                        data[cnt].func);
2908                 if (ret)
2909                         break;
2910         }
2911
2912         if (ret) {
2913                 /* revert the already done pin settings */
2914                 for (cnt--; cnt >= 0; cnt--) {
2915                         bank = pin_to_bank(info, pins[cnt]);
2916                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
2917                 }
2918
2919                 return ret;
2920         }
2921
2922         return 0;
2923 }
2924
2925 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2926                                            struct pinctrl_gpio_range *range,
2927                                            unsigned offset,
2928                                            bool input)
2929 {
2930         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2931         struct rockchip_pin_bank *bank;
2932
2933         bank = pin_to_bank(info, offset);
2934         return rockchip_set_mux(bank, offset - bank->pin_base, RK_FUNC_GPIO);
2935 }
2936
2937 static const struct pinmux_ops rockchip_pmx_ops = {
2938         .get_functions_count    = rockchip_pmx_get_funcs_count,
2939         .get_function_name      = rockchip_pmx_get_func_name,
2940         .get_function_groups    = rockchip_pmx_get_groups,
2941         .set_mux                = rockchip_pmx_set,
2942         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
2943 };
2944
2945 /*
2946  * Pinconf_ops handling
2947  */
2948
2949 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2950                                         enum pin_config_param pull)
2951 {
2952         switch (ctrl->type) {
2953         case RK2928:
2954         case RK3128:
2955                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2956                                         pull == PIN_CONFIG_BIAS_DISABLE);
2957         case RK3066B:
2958                 return pull ? false : true;
2959         case PX30:
2960         case RV1108:
2961         case RV1126:
2962         case RK3188:
2963         case RK3288:
2964         case RK3308:
2965         case RK3328:
2966         case RK3368:
2967         case RK3399:
2968         case RK3568:
2969         case RK3576:
2970         case RK3588:
2971                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
2972         }
2973
2974         return false;
2975 }
2976
2977 static int rockchip_pinconf_defer_pin(struct rockchip_pin_bank *bank,
2978                                          unsigned int pin, u32 param, u32 arg)
2979 {
2980         struct rockchip_pin_deferred *cfg;
2981
2982         cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2983         if (!cfg)
2984                 return -ENOMEM;
2985
2986         cfg->pin = pin;
2987         cfg->param = param;
2988         cfg->arg = arg;
2989
2990         list_add_tail(&cfg->head, &bank->deferred_pins);
2991
2992         return 0;
2993 }
2994
2995 /* set the pin config settings for a specified pin */
2996 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2997                                 unsigned long *configs, unsigned num_configs)
2998 {
2999         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3000         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3001         struct gpio_chip *gpio = &bank->gpio_chip;
3002         enum pin_config_param param;
3003         u32 arg;
3004         int i;
3005         int rc;
3006
3007         for (i = 0; i < num_configs; i++) {
3008                 param = pinconf_to_config_param(configs[i]);
3009                 arg = pinconf_to_config_argument(configs[i]);
3010
3011                 if (param == PIN_CONFIG_OUTPUT || param == PIN_CONFIG_INPUT_ENABLE) {
3012                         /*
3013                          * Check for gpio driver not being probed yet.
3014                          * The lock makes sure that either gpio-probe has completed
3015                          * or the gpio driver hasn't probed yet.
3016                          */
3017                         mutex_lock(&bank->deferred_lock);
3018                         if (!gpio || !gpio->direction_output) {
3019                                 rc = rockchip_pinconf_defer_pin(bank, pin - bank->pin_base, param,
3020                                                                 arg);
3021                                 mutex_unlock(&bank->deferred_lock);
3022                                 if (rc)
3023                                         return rc;
3024
3025                                 break;
3026                         }
3027                         mutex_unlock(&bank->deferred_lock);
3028                 }
3029
3030                 switch (param) {
3031                 case PIN_CONFIG_BIAS_DISABLE:
3032                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
3033                                 param);
3034                         if (rc)
3035                                 return rc;
3036                         break;
3037                 case PIN_CONFIG_BIAS_PULL_UP:
3038                 case PIN_CONFIG_BIAS_PULL_DOWN:
3039                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3040                 case PIN_CONFIG_BIAS_BUS_HOLD:
3041                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
3042                                 return -ENOTSUPP;
3043
3044                         if (!arg)
3045                                 return -EINVAL;
3046
3047                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
3048                                 param);
3049                         if (rc)
3050                                 return rc;
3051                         break;
3052                 case PIN_CONFIG_OUTPUT:
3053                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
3054                                               RK_FUNC_GPIO);
3055                         if (rc != RK_FUNC_GPIO)
3056                                 return -EINVAL;
3057
3058                         rc = gpio->direction_output(gpio, pin - bank->pin_base,
3059                                                     arg);
3060                         if (rc)
3061                                 return rc;
3062                         break;
3063                 case PIN_CONFIG_INPUT_ENABLE:
3064                         rc = rockchip_set_mux(bank, pin - bank->pin_base,
3065                                               RK_FUNC_GPIO);
3066                         if (rc != RK_FUNC_GPIO)
3067                                 return -EINVAL;
3068
3069                         rc = gpio->direction_input(gpio, pin - bank->pin_base);
3070                         if (rc)
3071                                 return rc;
3072                         break;
3073                 case PIN_CONFIG_DRIVE_STRENGTH:
3074                         /* rk3288 is the first with per-pin drive-strength */
3075                         if (!info->ctrl->drv_calc_reg)
3076                                 return -ENOTSUPP;
3077
3078                         rc = rockchip_set_drive_perpin(bank,
3079                                                 pin - bank->pin_base, arg);
3080                         if (rc < 0)
3081                                 return rc;
3082                         break;
3083                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3084                         if (!info->ctrl->schmitt_calc_reg)
3085                                 return -ENOTSUPP;
3086
3087                         rc = rockchip_set_schmitt(bank,
3088                                                   pin - bank->pin_base, arg);
3089                         if (rc < 0)
3090                                 return rc;
3091                         break;
3092                 default:
3093                         return -ENOTSUPP;
3094                         break;
3095                 }
3096         } /* for each config */
3097
3098         return 0;
3099 }
3100
3101 /* get the pin config settings for a specified pin */
3102 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
3103                                                         unsigned long *config)
3104 {
3105         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
3106         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
3107         struct gpio_chip *gpio = &bank->gpio_chip;
3108         enum pin_config_param param = pinconf_to_config_param(*config);
3109         u16 arg;
3110         int rc;
3111
3112         switch (param) {
3113         case PIN_CONFIG_BIAS_DISABLE:
3114                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
3115                         return -EINVAL;
3116
3117                 arg = 0;
3118                 break;
3119         case PIN_CONFIG_BIAS_PULL_UP:
3120         case PIN_CONFIG_BIAS_PULL_DOWN:
3121         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
3122         case PIN_CONFIG_BIAS_BUS_HOLD:
3123                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
3124                         return -ENOTSUPP;
3125
3126                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
3127                         return -EINVAL;
3128
3129                 arg = 1;
3130                 break;
3131         case PIN_CONFIG_OUTPUT:
3132                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
3133                 if (rc != RK_FUNC_GPIO)
3134                         return -EINVAL;
3135
3136                 if (!gpio || !gpio->get) {
3137                         arg = 0;
3138                         break;
3139                 }
3140
3141                 rc = gpio->get(gpio, pin - bank->pin_base);
3142                 if (rc < 0)
3143                         return rc;
3144
3145                 arg = rc ? 1 : 0;
3146                 break;
3147         case PIN_CONFIG_DRIVE_STRENGTH:
3148                 /* rk3288 is the first with per-pin drive-strength */
3149                 if (!info->ctrl->drv_calc_reg)
3150                         return -ENOTSUPP;
3151
3152                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
3153                 if (rc < 0)
3154                         return rc;
3155
3156                 arg = rc;
3157                 break;
3158         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3159                 if (!info->ctrl->schmitt_calc_reg)
3160                         return -ENOTSUPP;
3161
3162                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
3163                 if (rc < 0)
3164                         return rc;
3165
3166                 arg = rc;
3167                 break;
3168         default:
3169                 return -ENOTSUPP;
3170                 break;
3171         }
3172
3173         *config = pinconf_to_config_packed(param, arg);
3174
3175         return 0;
3176 }
3177
3178 static const struct pinconf_ops rockchip_pinconf_ops = {
3179         .pin_config_get                 = rockchip_pinconf_get,
3180         .pin_config_set                 = rockchip_pinconf_set,
3181         .is_generic                     = true,
3182 };
3183
3184 static const struct of_device_id rockchip_bank_match[] = {
3185         { .compatible = "rockchip,gpio-bank" },
3186         { .compatible = "rockchip,rk3188-gpio-bank0" },
3187         {},
3188 };
3189
3190 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
3191                                                 struct device_node *np)
3192 {
3193         struct device_node *child;
3194
3195         for_each_child_of_node(np, child) {
3196                 if (of_match_node(rockchip_bank_match, child))
3197                         continue;
3198
3199                 info->nfunctions++;
3200                 info->ngroups += of_get_child_count(child);
3201         }
3202 }
3203
3204 static int rockchip_pinctrl_parse_groups(struct device_node *np,
3205                                               struct rockchip_pin_group *grp,
3206                                               struct rockchip_pinctrl *info,
3207                                               u32 index)
3208 {
3209         struct device *dev = info->dev;
3210         struct rockchip_pin_bank *bank;
3211         int size;
3212         const __be32 *list;
3213         int num;
3214         int i, j;
3215         int ret;
3216
3217         dev_dbg(dev, "group(%d): %pOFn\n", index, np);
3218
3219         /* Initialise group */
3220         grp->name = np->name;
3221
3222         /*
3223          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
3224          * do sanity check and calculate pins number
3225          */
3226         list = of_get_property(np, "rockchip,pins", &size);
3227         /* we do not check return since it's safe node passed down */
3228         size /= sizeof(*list);
3229         if (!size || size % 4)
3230                 return dev_err_probe(dev, -EINVAL, "wrong pins number or pins and configs should be by 4\n");
3231
3232         grp->npins = size / 4;
3233
3234         grp->pins = devm_kcalloc(dev, grp->npins, sizeof(*grp->pins), GFP_KERNEL);
3235         grp->data = devm_kcalloc(dev, grp->npins, sizeof(*grp->data), GFP_KERNEL);
3236         if (!grp->pins || !grp->data)
3237                 return -ENOMEM;
3238
3239         for (i = 0, j = 0; i < size; i += 4, j++) {
3240                 const __be32 *phandle;
3241                 struct device_node *np_config;
3242
3243                 num = be32_to_cpu(*list++);
3244                 bank = bank_num_to_bank(info, num);
3245                 if (IS_ERR(bank))
3246                         return PTR_ERR(bank);
3247
3248                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
3249                 grp->data[j].func = be32_to_cpu(*list++);
3250
3251                 phandle = list++;
3252                 if (!phandle)
3253                         return -EINVAL;
3254
3255                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
3256                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
3257                                 &grp->data[j].configs, &grp->data[j].nconfigs);
3258                 of_node_put(np_config);
3259                 if (ret)
3260                         return ret;
3261         }
3262
3263         return 0;
3264 }
3265
3266 static int rockchip_pinctrl_parse_functions(struct device_node *np,
3267                                                 struct rockchip_pinctrl *info,
3268                                                 u32 index)
3269 {
3270         struct device *dev = info->dev;
3271         struct rockchip_pmx_func *func;
3272         struct rockchip_pin_group *grp;
3273         int ret;
3274         static u32 grp_index;
3275         u32 i = 0;
3276
3277         dev_dbg(dev, "parse function(%d): %pOFn\n", index, np);
3278
3279         func = &info->functions[index];
3280
3281         /* Initialise function */
3282         func->name = np->name;
3283         func->ngroups = of_get_child_count(np);
3284         if (func->ngroups <= 0)
3285                 return 0;
3286
3287         func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
3288         if (!func->groups)
3289                 return -ENOMEM;
3290
3291         for_each_child_of_node_scoped(np, child) {
3292                 func->groups[i] = child->name;
3293                 grp = &info->groups[grp_index++];
3294                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
3295                 if (ret)
3296                         return ret;
3297         }
3298
3299         return 0;
3300 }
3301
3302 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
3303                                               struct rockchip_pinctrl *info)
3304 {
3305         struct device *dev = &pdev->dev;
3306         struct device_node *np = dev->of_node;
3307         int ret;
3308         int i;
3309
3310         rockchip_pinctrl_child_count(info, np);
3311
3312         dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
3313         dev_dbg(dev, "ngroups = %d\n", info->ngroups);
3314
3315         info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
3316         if (!info->functions)
3317                 return -ENOMEM;
3318
3319         info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
3320         if (!info->groups)
3321                 return -ENOMEM;
3322
3323         i = 0;
3324
3325         for_each_child_of_node_scoped(np, child) {
3326                 if (of_match_node(rockchip_bank_match, child))
3327                         continue;
3328
3329                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
3330                 if (ret) {
3331                         dev_err(dev, "failed to parse function\n");
3332                         return ret;
3333                 }
3334         }
3335
3336         return 0;
3337 }
3338
3339 static int rockchip_pinctrl_register(struct platform_device *pdev,
3340                                         struct rockchip_pinctrl *info)
3341 {
3342         struct pinctrl_desc *ctrldesc = &info->pctl;
3343         struct pinctrl_pin_desc *pindesc, *pdesc;
3344         struct rockchip_pin_bank *pin_bank;
3345         struct device *dev = &pdev->dev;
3346         char **pin_names;
3347         int pin, bank, ret;
3348         int k;
3349
3350         ctrldesc->name = "rockchip-pinctrl";
3351         ctrldesc->owner = THIS_MODULE;
3352         ctrldesc->pctlops = &rockchip_pctrl_ops;
3353         ctrldesc->pmxops = &rockchip_pmx_ops;
3354         ctrldesc->confops = &rockchip_pinconf_ops;
3355
3356         pindesc = devm_kcalloc(dev, info->ctrl->nr_pins, sizeof(*pindesc), GFP_KERNEL);
3357         if (!pindesc)
3358                 return -ENOMEM;
3359
3360         ctrldesc->pins = pindesc;
3361         ctrldesc->npins = info->ctrl->nr_pins;
3362
3363         pdesc = pindesc;
3364         for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
3365                 pin_bank = &info->ctrl->pin_banks[bank];
3366
3367                 pin_names = devm_kasprintf_strarray(dev, pin_bank->name, pin_bank->nr_pins);
3368                 if (IS_ERR(pin_names))
3369                         return PTR_ERR(pin_names);
3370
3371                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
3372                         pdesc->number = k;
3373                         pdesc->name = pin_names[pin];
3374                         pdesc++;
3375                 }
3376
3377                 INIT_LIST_HEAD(&pin_bank->deferred_pins);
3378                 mutex_init(&pin_bank->deferred_lock);
3379         }
3380
3381         ret = rockchip_pinctrl_parse_dt(pdev, info);
3382         if (ret)
3383                 return ret;
3384
3385         info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
3386         if (IS_ERR(info->pctl_dev))
3387                 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
3388
3389         return 0;
3390 }
3391
3392 static const struct of_device_id rockchip_pinctrl_dt_match[];
3393
3394 /* retrieve the soc specific data */
3395 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
3396                                                 struct rockchip_pinctrl *d,
3397                                                 struct platform_device *pdev)
3398 {
3399         struct device *dev = &pdev->dev;
3400         struct device_node *node = dev->of_node;
3401         const struct of_device_id *match;
3402         struct rockchip_pin_ctrl *ctrl;
3403         struct rockchip_pin_bank *bank;
3404         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
3405
3406         match = of_match_node(rockchip_pinctrl_dt_match, node);
3407         ctrl = (struct rockchip_pin_ctrl *)match->data;
3408
3409         grf_offs = ctrl->grf_mux_offset;
3410         pmu_offs = ctrl->pmu_mux_offset;
3411         drv_pmu_offs = ctrl->pmu_drv_offset;
3412         drv_grf_offs = ctrl->grf_drv_offset;
3413         bank = ctrl->pin_banks;
3414         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
3415                 int bank_pins = 0;
3416
3417                 raw_spin_lock_init(&bank->slock);
3418                 bank->drvdata = d;
3419                 bank->pin_base = ctrl->nr_pins;
3420                 ctrl->nr_pins += bank->nr_pins;
3421
3422                 /* calculate iomux and drv offsets */
3423                 for (j = 0; j < 4; j++) {
3424                         struct rockchip_iomux *iom = &bank->iomux[j];
3425                         struct rockchip_drv *drv = &bank->drv[j];
3426                         int inc;
3427
3428                         if (bank_pins >= bank->nr_pins)
3429                                 break;
3430
3431                         /* preset iomux offset value, set new start value */
3432                         if (iom->offset >= 0) {
3433                                 if ((iom->type & IOMUX_SOURCE_PMU) ||
3434                                     (iom->type & IOMUX_L_SOURCE_PMU))
3435                                         pmu_offs = iom->offset;
3436                                 else
3437                                         grf_offs = iom->offset;
3438                         } else { /* set current iomux offset */
3439                                 iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
3440                                                (iom->type & IOMUX_L_SOURCE_PMU)) ?
3441                                                         pmu_offs : grf_offs;
3442                         }
3443
3444                         /* preset drv offset value, set new start value */
3445                         if (drv->offset >= 0) {
3446                                 if (iom->type & IOMUX_SOURCE_PMU)
3447                                         drv_pmu_offs = drv->offset;
3448                                 else
3449                                         drv_grf_offs = drv->offset;
3450                         } else { /* set current drv offset */
3451                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3452                                                 drv_pmu_offs : drv_grf_offs;
3453                         }
3454
3455                         dev_dbg(dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3456                                 i, j, iom->offset, drv->offset);
3457
3458                         /*
3459                          * Increase offset according to iomux width.
3460                          * 4bit iomux'es are spread over two registers.
3461                          */
3462                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
3463                                             IOMUX_WIDTH_3BIT |
3464                                             IOMUX_WIDTH_2BIT)) ? 8 : 4;
3465                         if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
3466                                 pmu_offs += inc;
3467                         else
3468                                 grf_offs += inc;
3469
3470                         /*
3471                          * Increase offset according to drv width.
3472                          * 3bit drive-strenth'es are spread over two registers.
3473                          */
3474                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3475                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3476                                 inc = 8;
3477                         else
3478                                 inc = 4;
3479
3480                         if (iom->type & IOMUX_SOURCE_PMU)
3481                                 drv_pmu_offs += inc;
3482                         else
3483                                 drv_grf_offs += inc;
3484
3485                         bank_pins += 8;
3486                 }
3487
3488                 /* calculate the per-bank recalced_mask */
3489                 for (j = 0; j < ctrl->niomux_recalced; j++) {
3490                         int pin = 0;
3491
3492                         if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3493                                 pin = ctrl->iomux_recalced[j].pin;
3494                                 bank->recalced_mask |= BIT(pin);
3495                         }
3496                 }
3497
3498                 /* calculate the per-bank route_mask */
3499                 for (j = 0; j < ctrl->niomux_routes; j++) {
3500                         int pin = 0;
3501
3502                         if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3503                                 pin = ctrl->iomux_routes[j].pin;
3504                                 bank->route_mask |= BIT(pin);
3505                         }
3506                 }
3507         }
3508
3509         return ctrl;
3510 }
3511
3512 #define RK3288_GRF_GPIO6C_IOMUX         0x64
3513 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
3514
3515 static u32 rk3288_grf_gpio6c_iomux;
3516
3517 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3518 {
3519         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3520         int ret = pinctrl_force_sleep(info->pctl_dev);
3521
3522         if (ret)
3523                 return ret;
3524
3525         /*
3526          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3527          * the setting here, and restore it at resume.
3528          */
3529         if (info->ctrl->type == RK3288) {
3530                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3531                                   &rk3288_grf_gpio6c_iomux);
3532                 if (ret) {
3533                         pinctrl_force_default(info->pctl_dev);
3534                         return ret;
3535                 }
3536         }
3537
3538         return 0;
3539 }
3540
3541 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3542 {
3543         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
3544         int ret;
3545
3546         if (info->ctrl->type == RK3288) {
3547                 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3548                                    rk3288_grf_gpio6c_iomux |
3549                                    GPIO6C6_SEL_WRITE_ENABLE);
3550                 if (ret)
3551                         return ret;
3552         }
3553
3554         return pinctrl_force_default(info->pctl_dev);
3555 }
3556
3557 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3558                          rockchip_pinctrl_resume);
3559
3560 static int rockchip_pinctrl_probe(struct platform_device *pdev)
3561 {
3562         struct rockchip_pinctrl *info;
3563         struct device *dev = &pdev->dev;
3564         struct device_node *np = dev->of_node, *node;
3565         struct rockchip_pin_ctrl *ctrl;
3566         struct resource *res;
3567         void __iomem *base;
3568         int ret;
3569
3570         if (!dev->of_node)
3571                 return dev_err_probe(dev, -ENODEV, "device tree node not found\n");
3572
3573         info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
3574         if (!info)
3575                 return -ENOMEM;
3576
3577         info->dev = dev;
3578
3579         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3580         if (!ctrl)
3581                 return dev_err_probe(dev, -EINVAL, "driver data not available\n");
3582         info->ctrl = ctrl;
3583
3584         node = of_parse_phandle(np, "rockchip,grf", 0);
3585         if (node) {
3586                 info->regmap_base = syscon_node_to_regmap(node);
3587                 of_node_put(node);
3588                 if (IS_ERR(info->regmap_base))
3589                         return PTR_ERR(info->regmap_base);
3590         } else {
3591                 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
3592                 if (IS_ERR(base))
3593                         return PTR_ERR(base);
3594
3595                 rockchip_regmap_config.max_register = resource_size(res) - 4;
3596                 rockchip_regmap_config.name = "rockchip,pinctrl";
3597                 info->regmap_base =
3598                         devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3599
3600                 /* to check for the old dt-bindings */
3601                 info->reg_size = resource_size(res);
3602
3603                 /* Honor the old binding, with pull registers as 2nd resource */
3604                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3605                         base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
3606                         if (IS_ERR(base))
3607                                 return PTR_ERR(base);
3608
3609                         rockchip_regmap_config.max_register = resource_size(res) - 4;
3610                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3611                         info->regmap_pull =
3612                                 devm_regmap_init_mmio(dev, base, &rockchip_regmap_config);
3613                 }
3614         }
3615
3616         /* try to find the optional reference to the pmu syscon */
3617         node = of_parse_phandle(np, "rockchip,pmu", 0);
3618         if (node) {
3619                 info->regmap_pmu = syscon_node_to_regmap(node);
3620                 of_node_put(node);
3621                 if (IS_ERR(info->regmap_pmu))
3622                         return PTR_ERR(info->regmap_pmu);
3623         }
3624
3625         ret = rockchip_pinctrl_register(pdev, info);
3626         if (ret)
3627                 return ret;
3628
3629         platform_set_drvdata(pdev, info);
3630
3631         ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
3632         if (ret)
3633                 return dev_err_probe(dev, ret, "failed to register gpio device\n");
3634
3635         return 0;
3636 }
3637
3638 static void rockchip_pinctrl_remove(struct platform_device *pdev)
3639 {
3640         struct rockchip_pinctrl *info = platform_get_drvdata(pdev);
3641         struct rockchip_pin_bank *bank;
3642         struct rockchip_pin_deferred *cfg;
3643         int i;
3644
3645         of_platform_depopulate(&pdev->dev);
3646
3647         for (i = 0; i < info->ctrl->nr_banks; i++) {
3648                 bank = &info->ctrl->pin_banks[i];
3649
3650                 mutex_lock(&bank->deferred_lock);
3651                 while (!list_empty(&bank->deferred_pins)) {
3652                         cfg = list_first_entry(&bank->deferred_pins,
3653                                                struct rockchip_pin_deferred, head);
3654                         list_del(&cfg->head);
3655                         kfree(cfg);
3656                 }
3657                 mutex_unlock(&bank->deferred_lock);
3658         }
3659 }
3660
3661 static struct rockchip_pin_bank px30_pin_banks[] = {
3662         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3663                                              IOMUX_SOURCE_PMU,
3664                                              IOMUX_SOURCE_PMU,
3665                                              IOMUX_SOURCE_PMU
3666                             ),
3667         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
3668                                              IOMUX_WIDTH_4BIT,
3669                                              IOMUX_WIDTH_4BIT,
3670                                              IOMUX_WIDTH_4BIT
3671                             ),
3672         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
3673                                              IOMUX_WIDTH_4BIT,
3674                                              IOMUX_WIDTH_4BIT,
3675                                              IOMUX_WIDTH_4BIT
3676                             ),
3677         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
3678                                              IOMUX_WIDTH_4BIT,
3679                                              IOMUX_WIDTH_4BIT,
3680                                              IOMUX_WIDTH_4BIT
3681                             ),
3682 };
3683
3684 static struct rockchip_pin_ctrl px30_pin_ctrl = {
3685                 .pin_banks              = px30_pin_banks,
3686                 .nr_banks               = ARRAY_SIZE(px30_pin_banks),
3687                 .label                  = "PX30-GPIO",
3688                 .type                   = PX30,
3689                 .grf_mux_offset         = 0x0,
3690                 .pmu_mux_offset         = 0x0,
3691                 .iomux_routes           = px30_mux_route_data,
3692                 .niomux_routes          = ARRAY_SIZE(px30_mux_route_data),
3693                 .pull_calc_reg          = px30_calc_pull_reg_and_bit,
3694                 .drv_calc_reg           = px30_calc_drv_reg_and_bit,
3695                 .schmitt_calc_reg       = px30_calc_schmitt_reg_and_bit,
3696 };
3697
3698 static struct rockchip_pin_bank rv1108_pin_banks[] = {
3699         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3700                                              IOMUX_SOURCE_PMU,
3701                                              IOMUX_SOURCE_PMU,
3702                                              IOMUX_SOURCE_PMU),
3703         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3704         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3705         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3706 };
3707
3708 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3709         .pin_banks              = rv1108_pin_banks,
3710         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
3711         .label                  = "RV1108-GPIO",
3712         .type                   = RV1108,
3713         .grf_mux_offset         = 0x10,
3714         .pmu_mux_offset         = 0x0,
3715         .iomux_recalced         = rv1108_mux_recalced_data,
3716         .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
3717         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
3718         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
3719         .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,
3720 };
3721
3722 static struct rockchip_pin_bank rv1126_pin_banks[] = {
3723         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
3724                              IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3725                              IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
3726                              IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
3727                              IOMUX_WIDTH_4BIT),
3728         PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
3729                                     IOMUX_WIDTH_4BIT,
3730                                     IOMUX_WIDTH_4BIT,
3731                                     IOMUX_WIDTH_4BIT,
3732                                     IOMUX_WIDTH_4BIT,
3733                                     0x10010, 0x10018, 0x10020, 0x10028),
3734         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
3735                              IOMUX_WIDTH_4BIT,
3736                              IOMUX_WIDTH_4BIT,
3737                              IOMUX_WIDTH_4BIT,
3738                              IOMUX_WIDTH_4BIT),
3739         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3740                              IOMUX_WIDTH_4BIT,
3741                              IOMUX_WIDTH_4BIT,
3742                              IOMUX_WIDTH_4BIT,
3743                              IOMUX_WIDTH_4BIT),
3744         PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
3745                              IOMUX_WIDTH_4BIT, 0, 0, 0),
3746 };
3747
3748 static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
3749         .pin_banks              = rv1126_pin_banks,
3750         .nr_banks               = ARRAY_SIZE(rv1126_pin_banks),
3751         .label                  = "RV1126-GPIO",
3752         .type                   = RV1126,
3753         .grf_mux_offset         = 0x10004, /* mux offset from GPIO0_D0 */
3754         .pmu_mux_offset         = 0x0,
3755         .iomux_routes           = rv1126_mux_route_data,
3756         .niomux_routes          = ARRAY_SIZE(rv1126_mux_route_data),
3757         .iomux_recalced         = rv1126_mux_recalced_data,
3758         .niomux_recalced        = ARRAY_SIZE(rv1126_mux_recalced_data),
3759         .pull_calc_reg          = rv1126_calc_pull_reg_and_bit,
3760         .drv_calc_reg           = rv1126_calc_drv_reg_and_bit,
3761         .schmitt_calc_reg       = rv1126_calc_schmitt_reg_and_bit,
3762 };
3763
3764 static struct rockchip_pin_bank rk2928_pin_banks[] = {
3765         PIN_BANK(0, 32, "gpio0"),
3766         PIN_BANK(1, 32, "gpio1"),
3767         PIN_BANK(2, 32, "gpio2"),
3768         PIN_BANK(3, 32, "gpio3"),
3769 };
3770
3771 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3772                 .pin_banks              = rk2928_pin_banks,
3773                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
3774                 .label                  = "RK2928-GPIO",
3775                 .type                   = RK2928,
3776                 .grf_mux_offset         = 0xa8,
3777                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3778 };
3779
3780 static struct rockchip_pin_bank rk3036_pin_banks[] = {
3781         PIN_BANK(0, 32, "gpio0"),
3782         PIN_BANK(1, 32, "gpio1"),
3783         PIN_BANK(2, 32, "gpio2"),
3784 };
3785
3786 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3787                 .pin_banks              = rk3036_pin_banks,
3788                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
3789                 .label                  = "RK3036-GPIO",
3790                 .type                   = RK2928,
3791                 .grf_mux_offset         = 0xa8,
3792                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3793 };
3794
3795 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3796         PIN_BANK(0, 32, "gpio0"),
3797         PIN_BANK(1, 32, "gpio1"),
3798         PIN_BANK(2, 32, "gpio2"),
3799         PIN_BANK(3, 32, "gpio3"),
3800         PIN_BANK(4, 32, "gpio4"),
3801         PIN_BANK(6, 16, "gpio6"),
3802 };
3803
3804 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3805                 .pin_banks              = rk3066a_pin_banks,
3806                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
3807                 .label                  = "RK3066a-GPIO",
3808                 .type                   = RK2928,
3809                 .grf_mux_offset         = 0xa8,
3810                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
3811 };
3812
3813 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3814         PIN_BANK(0, 32, "gpio0"),
3815         PIN_BANK(1, 32, "gpio1"),
3816         PIN_BANK(2, 32, "gpio2"),
3817         PIN_BANK(3, 32, "gpio3"),
3818 };
3819
3820 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3821                 .pin_banks      = rk3066b_pin_banks,
3822                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
3823                 .label          = "RK3066b-GPIO",
3824                 .type           = RK3066B,
3825                 .grf_mux_offset = 0x60,
3826 };
3827
3828 static struct rockchip_pin_bank rk3128_pin_banks[] = {
3829         PIN_BANK(0, 32, "gpio0"),
3830         PIN_BANK(1, 32, "gpio1"),
3831         PIN_BANK(2, 32, "gpio2"),
3832         PIN_BANK(3, 32, "gpio3"),
3833 };
3834
3835 static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3836                 .pin_banks              = rk3128_pin_banks,
3837                 .nr_banks               = ARRAY_SIZE(rk3128_pin_banks),
3838                 .label                  = "RK3128-GPIO",
3839                 .type                   = RK3128,
3840                 .grf_mux_offset         = 0xa8,
3841                 .iomux_recalced         = rk3128_mux_recalced_data,
3842                 .niomux_recalced        = ARRAY_SIZE(rk3128_mux_recalced_data),
3843                 .iomux_routes           = rk3128_mux_route_data,
3844                 .niomux_routes          = ARRAY_SIZE(rk3128_mux_route_data),
3845                 .pull_calc_reg          = rk3128_calc_pull_reg_and_bit,
3846 };
3847
3848 static struct rockchip_pin_bank rk3188_pin_banks[] = {
3849         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
3850         PIN_BANK(1, 32, "gpio1"),
3851         PIN_BANK(2, 32, "gpio2"),
3852         PIN_BANK(3, 32, "gpio3"),
3853 };
3854
3855 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3856                 .pin_banks              = rk3188_pin_banks,
3857                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
3858                 .label                  = "RK3188-GPIO",
3859                 .type                   = RK3188,
3860                 .grf_mux_offset         = 0x60,
3861                 .iomux_routes           = rk3188_mux_route_data,
3862                 .niomux_routes          = ARRAY_SIZE(rk3188_mux_route_data),
3863                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
3864 };
3865
3866 static struct rockchip_pin_bank rk3228_pin_banks[] = {
3867         PIN_BANK(0, 32, "gpio0"),
3868         PIN_BANK(1, 32, "gpio1"),
3869         PIN_BANK(2, 32, "gpio2"),
3870         PIN_BANK(3, 32, "gpio3"),
3871 };
3872
3873 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3874                 .pin_banks              = rk3228_pin_banks,
3875                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
3876                 .label                  = "RK3228-GPIO",
3877                 .type                   = RK3288,
3878                 .grf_mux_offset         = 0x0,
3879                 .iomux_routes           = rk3228_mux_route_data,
3880                 .niomux_routes          = ARRAY_SIZE(rk3228_mux_route_data),
3881                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3882                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3883 };
3884
3885 static struct rockchip_pin_bank rk3288_pin_banks[] = {
3886         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3887                                              IOMUX_SOURCE_PMU,
3888                                              IOMUX_SOURCE_PMU,
3889                                              IOMUX_UNROUTED
3890                             ),
3891         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3892                                              IOMUX_UNROUTED,
3893                                              IOMUX_UNROUTED,
3894                                              0
3895                             ),
3896         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3897         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3898         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3899                                              IOMUX_WIDTH_4BIT,
3900                                              0,
3901                                              0
3902                             ),
3903         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3904                                              0,
3905                                              0,
3906                                              IOMUX_UNROUTED
3907                             ),
3908         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3909         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3910                                              0,
3911                                              IOMUX_WIDTH_4BIT,
3912                                              IOMUX_UNROUTED
3913                             ),
3914         PIN_BANK(8, 16, "gpio8"),
3915 };
3916
3917 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3918                 .pin_banks              = rk3288_pin_banks,
3919                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
3920                 .label                  = "RK3288-GPIO",
3921                 .type                   = RK3288,
3922                 .grf_mux_offset         = 0x0,
3923                 .pmu_mux_offset         = 0x84,
3924                 .iomux_routes           = rk3288_mux_route_data,
3925                 .niomux_routes          = ARRAY_SIZE(rk3288_mux_route_data),
3926                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
3927                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
3928 };
3929
3930 static struct rockchip_pin_bank rk3308_pin_banks[] = {
3931         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,
3932                                              IOMUX_WIDTH_2BIT,
3933                                              IOMUX_WIDTH_2BIT,
3934                                              IOMUX_WIDTH_2BIT),
3935         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,
3936                                              IOMUX_WIDTH_2BIT,
3937                                              IOMUX_WIDTH_2BIT,
3938                                              IOMUX_WIDTH_2BIT),
3939         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,
3940                                              IOMUX_WIDTH_2BIT,
3941                                              IOMUX_WIDTH_2BIT,
3942                                              IOMUX_WIDTH_2BIT),
3943         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,
3944                                              IOMUX_WIDTH_2BIT,
3945                                              IOMUX_WIDTH_2BIT,
3946                                              IOMUX_WIDTH_2BIT),
3947         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,
3948                                              IOMUX_WIDTH_2BIT,
3949                                              IOMUX_WIDTH_2BIT,
3950                                              IOMUX_WIDTH_2BIT),
3951 };
3952
3953 static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
3954                 .pin_banks              = rk3308_pin_banks,
3955                 .nr_banks               = ARRAY_SIZE(rk3308_pin_banks),
3956                 .label                  = "RK3308-GPIO",
3957                 .type                   = RK3308,
3958                 .grf_mux_offset         = 0x0,
3959                 .iomux_recalced         = rk3308_mux_recalced_data,
3960                 .niomux_recalced        = ARRAY_SIZE(rk3308_mux_recalced_data),
3961                 .iomux_routes           = rk3308_mux_route_data,
3962                 .niomux_routes          = ARRAY_SIZE(rk3308_mux_route_data),
3963                 .pull_calc_reg          = rk3308_calc_pull_reg_and_bit,
3964                 .drv_calc_reg           = rk3308_calc_drv_reg_and_bit,
3965                 .schmitt_calc_reg       = rk3308_calc_schmitt_reg_and_bit,
3966 };
3967
3968 static struct rockchip_pin_bank rk3328_pin_banks[] = {
3969         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3970         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3971         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
3972                              IOMUX_WIDTH_2BIT,
3973                              IOMUX_WIDTH_3BIT,
3974                              0),
3975         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3976                              IOMUX_WIDTH_3BIT,
3977                              IOMUX_WIDTH_3BIT,
3978                              0,
3979                              0),
3980 };
3981
3982 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3983                 .pin_banks              = rk3328_pin_banks,
3984                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
3985                 .label                  = "RK3328-GPIO",
3986                 .type                   = RK3328,
3987                 .grf_mux_offset         = 0x0,
3988                 .iomux_recalced         = rk3328_mux_recalced_data,
3989                 .niomux_recalced        = ARRAY_SIZE(rk3328_mux_recalced_data),
3990                 .iomux_routes           = rk3328_mux_route_data,
3991                 .niomux_routes          = ARRAY_SIZE(rk3328_mux_route_data),
3992                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
3993                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
3994                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
3995 };
3996
3997 static struct rockchip_pin_bank rk3368_pin_banks[] = {
3998         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3999                                              IOMUX_SOURCE_PMU,
4000                                              IOMUX_SOURCE_PMU,
4001                                              IOMUX_SOURCE_PMU
4002                             ),
4003         PIN_BANK(1, 32, "gpio1"),
4004         PIN_BANK(2, 32, "gpio2"),
4005         PIN_BANK(3, 32, "gpio3"),
4006 };
4007
4008 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
4009                 .pin_banks              = rk3368_pin_banks,
4010                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
4011                 .label                  = "RK3368-GPIO",
4012                 .type                   = RK3368,
4013                 .grf_mux_offset         = 0x0,
4014                 .pmu_mux_offset         = 0x0,
4015                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
4016                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
4017 };
4018
4019 static struct rockchip_pin_bank rk3399_pin_banks[] = {
4020         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
4021                                                          IOMUX_SOURCE_PMU,
4022                                                          IOMUX_SOURCE_PMU,
4023                                                          IOMUX_SOURCE_PMU,
4024                                                          IOMUX_SOURCE_PMU,
4025                                                          DRV_TYPE_IO_1V8_ONLY,
4026                                                          DRV_TYPE_IO_1V8_ONLY,
4027                                                          DRV_TYPE_IO_DEFAULT,
4028                                                          DRV_TYPE_IO_DEFAULT,
4029                                                          0x80,
4030                                                          0x88,
4031                                                          -1,
4032                                                          -1,
4033                                                          PULL_TYPE_IO_1V8_ONLY,
4034                                                          PULL_TYPE_IO_1V8_ONLY,
4035                                                          PULL_TYPE_IO_DEFAULT,
4036                                                          PULL_TYPE_IO_DEFAULT
4037                                                         ),
4038         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
4039                                         IOMUX_SOURCE_PMU,
4040                                         IOMUX_SOURCE_PMU,
4041                                         IOMUX_SOURCE_PMU,
4042                                         DRV_TYPE_IO_1V8_OR_3V0,
4043                                         DRV_TYPE_IO_1V8_OR_3V0,
4044                                         DRV_TYPE_IO_1V8_OR_3V0,
4045                                         DRV_TYPE_IO_1V8_OR_3V0,
4046                                         0xa0,
4047                                         0xa8,
4048                                         0xb0,
4049                                         0xb8
4050                                         ),
4051         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
4052                                       DRV_TYPE_IO_1V8_OR_3V0,
4053                                       DRV_TYPE_IO_1V8_ONLY,
4054                                       DRV_TYPE_IO_1V8_ONLY,
4055                                       PULL_TYPE_IO_DEFAULT,
4056                                       PULL_TYPE_IO_DEFAULT,
4057                                       PULL_TYPE_IO_1V8_ONLY,
4058                                       PULL_TYPE_IO_1V8_ONLY
4059                                       ),
4060         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
4061                            DRV_TYPE_IO_3V3_ONLY,
4062                            DRV_TYPE_IO_3V3_ONLY,
4063                            DRV_TYPE_IO_1V8_OR_3V0
4064                            ),
4065         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
4066                            DRV_TYPE_IO_1V8_3V0_AUTO,
4067                            DRV_TYPE_IO_1V8_OR_3V0,
4068                            DRV_TYPE_IO_1V8_OR_3V0
4069                            ),
4070 };
4071
4072 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
4073                 .pin_banks              = rk3399_pin_banks,
4074                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
4075                 .label                  = "RK3399-GPIO",
4076                 .type                   = RK3399,
4077                 .grf_mux_offset         = 0xe000,
4078                 .pmu_mux_offset         = 0x0,
4079                 .grf_drv_offset         = 0xe100,
4080                 .pmu_drv_offset         = 0x80,
4081                 .iomux_routes           = rk3399_mux_route_data,
4082                 .niomux_routes          = ARRAY_SIZE(rk3399_mux_route_data),
4083                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
4084                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
4085 };
4086
4087 static struct rockchip_pin_bank rk3568_pin_banks[] = {
4088         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4089                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4090                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4091                                              IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
4092         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4093                                              IOMUX_WIDTH_4BIT,
4094                                              IOMUX_WIDTH_4BIT,
4095                                              IOMUX_WIDTH_4BIT),
4096         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4097                                              IOMUX_WIDTH_4BIT,
4098                                              IOMUX_WIDTH_4BIT,
4099                                              IOMUX_WIDTH_4BIT),
4100         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4101                                              IOMUX_WIDTH_4BIT,
4102                                              IOMUX_WIDTH_4BIT,
4103                                              IOMUX_WIDTH_4BIT),
4104         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4105                                              IOMUX_WIDTH_4BIT,
4106                                              IOMUX_WIDTH_4BIT,
4107                                              IOMUX_WIDTH_4BIT),
4108 };
4109
4110 static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
4111         .pin_banks              = rk3568_pin_banks,
4112         .nr_banks               = ARRAY_SIZE(rk3568_pin_banks),
4113         .label                  = "RK3568-GPIO",
4114         .type                   = RK3568,
4115         .grf_mux_offset         = 0x0,
4116         .pmu_mux_offset         = 0x0,
4117         .grf_drv_offset         = 0x0200,
4118         .pmu_drv_offset         = 0x0070,
4119         .iomux_routes           = rk3568_mux_route_data,
4120         .niomux_routes          = ARRAY_SIZE(rk3568_mux_route_data),
4121         .pull_calc_reg          = rk3568_calc_pull_reg_and_bit,
4122         .drv_calc_reg           = rk3568_calc_drv_reg_and_bit,
4123         .schmitt_calc_reg       = rk3568_calc_schmitt_reg_and_bit,
4124 };
4125
4126 #define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3)  \
4127         PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL,           \
4128                                                IOMUX_WIDTH_4BIT,        \
4129                                                IOMUX_WIDTH_4BIT,        \
4130                                                IOMUX_WIDTH_4BIT,        \
4131                                                IOMUX_WIDTH_4BIT,        \
4132                                                OFFSET0, OFFSET1,        \
4133                                                OFFSET2, OFFSET3,        \
4134                                                PULL_TYPE_IO_1V8_ONLY,   \
4135                                                PULL_TYPE_IO_1V8_ONLY,   \
4136                                                PULL_TYPE_IO_1V8_ONLY,   \
4137                                                PULL_TYPE_IO_1V8_ONLY)
4138
4139 static struct rockchip_pin_bank rk3576_pin_banks[] = {
4140         RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
4141         RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
4142         RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
4143         RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
4144         RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
4145 };
4146
4147 static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
4148         .pin_banks              = rk3576_pin_banks,
4149         .nr_banks               = ARRAY_SIZE(rk3576_pin_banks),
4150         .label                  = "RK3576-GPIO",
4151         .type                   = RK3576,
4152         .pull_calc_reg          = rk3576_calc_pull_reg_and_bit,
4153         .drv_calc_reg           = rk3576_calc_drv_reg_and_bit,
4154         .schmitt_calc_reg       = rk3576_calc_schmitt_reg_and_bit,
4155 };
4156
4157 static struct rockchip_pin_bank rk3588_pin_banks[] = {
4158         RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
4159                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4160         RK3588_PIN_BANK_FLAGS(1, 32, "gpio1",
4161                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4162         RK3588_PIN_BANK_FLAGS(2, 32, "gpio2",
4163                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4164         RK3588_PIN_BANK_FLAGS(3, 32, "gpio3",
4165                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4166         RK3588_PIN_BANK_FLAGS(4, 32, "gpio4",
4167                               IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
4168 };
4169
4170 static struct rockchip_pin_ctrl rk3588_pin_ctrl = {
4171         .pin_banks              = rk3588_pin_banks,
4172         .nr_banks               = ARRAY_SIZE(rk3588_pin_banks),
4173         .label                  = "RK3588-GPIO",
4174         .type                   = RK3588,
4175         .pull_calc_reg          = rk3588_calc_pull_reg_and_bit,
4176         .drv_calc_reg           = rk3588_calc_drv_reg_and_bit,
4177         .schmitt_calc_reg       = rk3588_calc_schmitt_reg_and_bit,
4178 };
4179
4180 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
4181         { .compatible = "rockchip,px30-pinctrl",
4182                 .data = &px30_pin_ctrl },
4183         { .compatible = "rockchip,rv1108-pinctrl",
4184                 .data = &rv1108_pin_ctrl },
4185         { .compatible = "rockchip,rv1126-pinctrl",
4186                 .data = &rv1126_pin_ctrl },
4187         { .compatible = "rockchip,rk2928-pinctrl",
4188                 .data = &rk2928_pin_ctrl },
4189         { .compatible = "rockchip,rk3036-pinctrl",
4190                 .data = &rk3036_pin_ctrl },
4191         { .compatible = "rockchip,rk3066a-pinctrl",
4192                 .data = &rk3066a_pin_ctrl },
4193         { .compatible = "rockchip,rk3066b-pinctrl",
4194                 .data = &rk3066b_pin_ctrl },
4195         { .compatible = "rockchip,rk3128-pinctrl",
4196                 .data = (void *)&rk3128_pin_ctrl },
4197         { .compatible = "rockchip,rk3188-pinctrl",
4198                 .data = &rk3188_pin_ctrl },
4199         { .compatible = "rockchip,rk3228-pinctrl",
4200                 .data = &rk3228_pin_ctrl },
4201         { .compatible = "rockchip,rk3288-pinctrl",
4202                 .data = &rk3288_pin_ctrl },
4203         { .compatible = "rockchip,rk3308-pinctrl",
4204                 .data = &rk3308_pin_ctrl },
4205         { .compatible = "rockchip,rk3328-pinctrl",
4206                 .data = &rk3328_pin_ctrl },
4207         { .compatible = "rockchip,rk3368-pinctrl",
4208                 .data = &rk3368_pin_ctrl },
4209         { .compatible = "rockchip,rk3399-pinctrl",
4210                 .data = &rk3399_pin_ctrl },
4211         { .compatible = "rockchip,rk3568-pinctrl",
4212                 .data = &rk3568_pin_ctrl },
4213         { .compatible = "rockchip,rk3576-pinctrl",
4214                 .data = &rk3576_pin_ctrl },
4215         { .compatible = "rockchip,rk3588-pinctrl",
4216                 .data = &rk3588_pin_ctrl },
4217         {},
4218 };
4219
4220 static struct platform_driver rockchip_pinctrl_driver = {
4221         .probe          = rockchip_pinctrl_probe,
4222         .remove_new     = rockchip_pinctrl_remove,
4223         .driver = {
4224                 .name   = "rockchip-pinctrl",
4225                 .pm = &rockchip_pinctrl_dev_pm_ops,
4226                 .of_match_table = rockchip_pinctrl_dt_match,
4227         },
4228 };
4229
4230 static int __init rockchip_pinctrl_drv_register(void)
4231 {
4232         return platform_driver_register(&rockchip_pinctrl_driver);
4233 }
4234 postcore_initcall(rockchip_pinctrl_drv_register);
4235
4236 static void __exit rockchip_pinctrl_drv_unregister(void)
4237 {
4238         platform_driver_unregister(&rockchip_pinctrl_driver);
4239 }
4240 module_exit(rockchip_pinctrl_drv_unregister);
4241
4242 MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
4243 MODULE_LICENSE("GPL");
4244 MODULE_ALIAS("platform:pinctrl-rockchip");
4245 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);