drivers/net/phy/realtek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* drivers/net/phy/realtek.c
   3  *
   4  * Driver for Realtek PHYs
   5  *
   6  * Author: Johnson Leung <[email protected]>
   7  *
   8  * Copyright (c) 2004 Freescale Semiconductor, Inc.
   9  */
  10 #include <linux/bitops.h>
  11 #include <linux/of.h>
  12 #include <linux/phy.h>
  13 #include <linux/module.h>
  14 #include <linux/delay.h>
  15 #include <linux/clk.h>
  16
  17 #define RTL821x_PHYSR                           0x11
  18 #define RTL821x_PHYSR_DUPLEX                    BIT(13)
  19 #define RTL821x_PHYSR_SPEED                     GENMASK(15, 14)
  20
  21 #define RTL821x_INER                            0x12
  22 #define RTL8211B_INER_INIT                      0x6400
  23 #define RTL8211E_INER_LINK_STATUS               BIT(10)
  24 #define RTL8211F_INER_LINK_STATUS               BIT(4)
  25
  26 #define RTL821x_INSR                            0x13
  27
  28 #define RTL821x_EXT_PAGE_SELECT                 0x1e
  29 #define RTL821x_PAGE_SELECT                     0x1f
  30
  31 #define RTL8211F_PHYCR1                         0x18
  32 #define RTL8211F_PHYCR2                         0x19
  33 #define RTL8211F_INSR                           0x1d
  34
  35 #define RTL8211F_LEDCR                          0x10
  36 #define RTL8211F_LEDCR_MODE                     BIT(15)
  37 #define RTL8211F_LEDCR_ACT_TXRX                 BIT(4)
  38 #define RTL8211F_LEDCR_LINK_1000                BIT(3)
  39 #define RTL8211F_LEDCR_LINK_100                 BIT(1)
  40 #define RTL8211F_LEDCR_LINK_10                  BIT(0)
  41 #define RTL8211F_LEDCR_MASK                     GENMASK(4, 0)
  42 #define RTL8211F_LEDCR_SHIFT                    5
  43
  44 #define RTL8211F_TX_DELAY                       BIT(8)
  45 #define RTL8211F_RX_DELAY                       BIT(3)
  46
  47 #define RTL8211F_ALDPS_PLL_OFF                  BIT(1)
  48 #define RTL8211F_ALDPS_ENABLE                   BIT(2)
  49 #define RTL8211F_ALDPS_XTAL_OFF                 BIT(12)
  50
  51 #define RTL8211E_CTRL_DELAY                     BIT(13)
  52 #define RTL8211E_TX_DELAY                       BIT(12)
  53 #define RTL8211E_RX_DELAY                       BIT(11)
  54
  55 #define RTL8211F_CLKOUT_EN                      BIT(0)
  56
  57 #define RTL8201F_ISR                            0x1e
  58 #define RTL8201F_ISR_ANERR                      BIT(15)
  59 #define RTL8201F_ISR_DUPLEX                     BIT(13)
  60 #define RTL8201F_ISR_LINK                       BIT(11)
  61 #define RTL8201F_ISR_MASK                       (RTL8201F_ISR_ANERR | \
  62                                                  RTL8201F_ISR_DUPLEX | \
  63                                                  RTL8201F_ISR_LINK)
  64 #define RTL8201F_IER                            0x13
  65
  66 #define RTL822X_VND1_SERDES_OPTION                      0x697a
  67 #define RTL822X_VND1_SERDES_OPTION_MODE_MASK            GENMASK(5, 0)
  68 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII         0
  69 #define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX               2
  70
  71 #define RTL822X_VND1_SERDES_CTRL3                       0x7580
  72 #define RTL822X_VND1_SERDES_CTRL3_MODE_MASK             GENMASK(5, 0)
  73 #define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII                    0x02
  74 #define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX                0x16
  75
  76 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
  77  * is set, they cannot be accessed by C45-over-C22.
  78  */
  79 #define RTL822X_VND2_GBCR                               0xa412
  80
  81 #define RTL822X_VND2_GANLPAR                            0xa414
  82
  83 #define RTL822X_VND2_PHYSR                              0xa434
  84
  85 #define RTL8366RB_POWER_SAVE                    0x15
  86 #define RTL8366RB_POWER_SAVE_ON                 BIT(12)
  87
  88 #define RTL9000A_GINMR                          0x14
  89 #define RTL9000A_GINMR_LINK_STATUS              BIT(4)
  90
  91 #define RTLGEN_SPEED_MASK                       0x0630
  92
  93 #define RTL_GENERIC_PHYID                       0x001cc800
  94 #define RTL_8211FVD_PHYID                       0x001cc878
  95 #define RTL_8221B_VB_CG                         0x001cc849
  96 #define RTL_8221B_VN_CG                         0x001cc84a
  97 #define RTL_8251B                               0x001cc862
  98
  99 #define RTL8211F_LED_COUNT                      3
 100
 101 MODULE_DESCRIPTION("Realtek PHY driver");
 102 MODULE_AUTHOR("Johnson Leung");
 103 MODULE_LICENSE("GPL");
 104
 105 struct rtl821x_priv {
 106         u16 phycr1;
 107         u16 phycr2;
 108         bool has_phycr2;
 109         struct clk *clk;
 110 };
 111
 112 static int rtl821x_read_page(struct phy_device *phydev)
 113 {
 114         return __phy_read(phydev, RTL821x_PAGE_SELECT);
 115 }
 116
 117 static int rtl821x_write_page(struct phy_device *phydev, int page)
 118 {
 119         return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
 120 }
 121
 122 static int rtl821x_probe(struct phy_device *phydev)
 123 {
 124         struct device *dev = &phydev->mdio.dev;
 125         struct rtl821x_priv *priv;
 126         u32 phy_id = phydev->drv->phy_id;
 127         int ret;
 128
 129         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 130         if (!priv)
 131                 return -ENOMEM;
 132
 133         priv->clk = devm_clk_get_optional_enabled(dev, NULL);
 134         if (IS_ERR(priv->clk))
 135                 return dev_err_probe(dev, PTR_ERR(priv->clk),
 136                                      "failed to get phy clock\n");
 137
 138         ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
 139         if (ret < 0)
 140                 return ret;
 141
 142         priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
 143         if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
 144                 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
 145
 146         priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
 147         if (priv->has_phycr2) {
 148                 ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
 149                 if (ret < 0)
 150                         return ret;
 151
 152                 priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
 153                 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
 154                         priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
 155         }
 156
 157         phydev->priv = priv;
 158
 159         return 0;
 160 }
 161
 162 static int rtl8201_ack_interrupt(struct phy_device *phydev)
 163 {
 164         int err;
 165
 166         err = phy_read(phydev, RTL8201F_ISR);
 167
 168         return (err < 0) ? err : 0;
 169 }
 170
 171 static int rtl821x_ack_interrupt(struct phy_device *phydev)
 172 {
 173         int err;
 174
 175         err = phy_read(phydev, RTL821x_INSR);
 176
 177         return (err < 0) ? err : 0;
 178 }
 179
 180 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
 181 {
 182         int err;
 183
 184         err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
 185
 186         return (err < 0) ? err : 0;
 187 }
 188
 189 static int rtl8201_config_intr(struct phy_device *phydev)
 190 {
 191         u16 val;
 192         int err;
 193
 194         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 195                 err = rtl8201_ack_interrupt(phydev);
 196                 if (err)
 197                         return err;
 198
 199                 val = BIT(13) | BIT(12) | BIT(11);
 200                 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 201         } else {
 202                 val = 0;
 203                 err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
 204                 if (err)
 205                         return err;
 206
 207                 err = rtl8201_ack_interrupt(phydev);
 208         }
 209
 210         return err;
 211 }
 212
 213 static int rtl8211b_config_intr(struct phy_device *phydev)
 214 {
 215         int err;
 216
 217         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 218                 err = rtl821x_ack_interrupt(phydev);
 219                 if (err)
 220                         return err;
 221
 222                 err = phy_write(phydev, RTL821x_INER,
 223                                 RTL8211B_INER_INIT);
 224         } else {
 225                 err = phy_write(phydev, RTL821x_INER, 0);
 226                 if (err)
 227                         return err;
 228
 229                 err = rtl821x_ack_interrupt(phydev);
 230         }
 231
 232         return err;
 233 }
 234
 235 static int rtl8211e_config_intr(struct phy_device *phydev)
 236 {
 237         int err;
 238
 239         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 240                 err = rtl821x_ack_interrupt(phydev);
 241                 if (err)
 242                         return err;
 243
 244                 err = phy_write(phydev, RTL821x_INER,
 245                                 RTL8211E_INER_LINK_STATUS);
 246         } else {
 247                 err = phy_write(phydev, RTL821x_INER, 0);
 248                 if (err)
 249                         return err;
 250
 251                 err = rtl821x_ack_interrupt(phydev);
 252         }
 253
 254         return err;
 255 }
 256
 257 static int rtl8211f_config_intr(struct phy_device *phydev)
 258 {
 259         u16 val;
 260         int err;
 261
 262         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 263                 err = rtl8211f_ack_interrupt(phydev);
 264                 if (err)
 265                         return err;
 266
 267                 val = RTL8211F_INER_LINK_STATUS;
 268                 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 269         } else {
 270                 val = 0;
 271                 err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
 272                 if (err)
 273                         return err;
 274
 275                 err = rtl8211f_ack_interrupt(phydev);
 276         }
 277
 278         return err;
 279 }
 280
 281 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
 282 {
 283         int irq_status;
 284
 285         irq_status = phy_read(phydev, RTL8201F_ISR);
 286         if (irq_status < 0) {
 287                 phy_error(phydev);
 288                 return IRQ_NONE;
 289         }
 290
 291         if (!(irq_status & RTL8201F_ISR_MASK))
 292                 return IRQ_NONE;
 293
 294         phy_trigger_machine(phydev);
 295
 296         return IRQ_HANDLED;
 297 }
 298
 299 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
 300 {
 301         int irq_status, irq_enabled;
 302
 303         irq_status = phy_read(phydev, RTL821x_INSR);
 304         if (irq_status < 0) {
 305                 phy_error(phydev);
 306                 return IRQ_NONE;
 307         }
 308
 309         irq_enabled = phy_read(phydev, RTL821x_INER);
 310         if (irq_enabled < 0) {
 311                 phy_error(phydev);
 312                 return IRQ_NONE;
 313         }
 314
 315         if (!(irq_status & irq_enabled))
 316                 return IRQ_NONE;
 317
 318         phy_trigger_machine(phydev);
 319
 320         return IRQ_HANDLED;
 321 }
 322
 323 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
 324 {
 325         int irq_status;
 326
 327         irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
 328         if (irq_status < 0) {
 329                 phy_error(phydev);
 330                 return IRQ_NONE;
 331         }
 332
 333         if (!(irq_status & RTL8211F_INER_LINK_STATUS))
 334                 return IRQ_NONE;
 335
 336         phy_trigger_machine(phydev);
 337
 338         return IRQ_HANDLED;
 339 }
 340
 341 static int rtl8211_config_aneg(struct phy_device *phydev)
 342 {
 343         int ret;
 344
 345         ret = genphy_config_aneg(phydev);
 346         if (ret < 0)
 347                 return ret;
 348
 349         /* Quirk was copied from vendor driver. Unfortunately it includes no
 350          * description of the magic numbers.
 351          */
 352         if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
 353                 phy_write(phydev, 0x17, 0x2138);
 354                 phy_write(phydev, 0x0e, 0x0260);
 355         } else {
 356                 phy_write(phydev, 0x17, 0x2108);
 357                 phy_write(phydev, 0x0e, 0x0000);
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int rtl8211c_config_init(struct phy_device *phydev)
 364 {
 365         /* RTL8211C has an issue when operating in Gigabit slave mode */
 366         return phy_set_bits(phydev, MII_CTRL1000,
 367                             CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
 368 }
 369
 370 static int rtl8211f_config_init(struct phy_device *phydev)
 371 {
 372         struct rtl821x_priv *priv = phydev->priv;
 373         struct device *dev = &phydev->mdio.dev;
 374         u16 val_txdly, val_rxdly;
 375         int ret;
 376
 377         ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
 378                                        RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
 379                                        priv->phycr1);
 380         if (ret < 0) {
 381                 dev_err(dev, "aldps mode  configuration failed: %pe\n",
 382                         ERR_PTR(ret));
 383                 return ret;
 384         }
 385
 386         switch (phydev->interface) {
 387         case PHY_INTERFACE_MODE_RGMII:
 388                 val_txdly = 0;
 389                 val_rxdly = 0;
 390                 break;
 391
 392         case PHY_INTERFACE_MODE_RGMII_RXID:
 393                 val_txdly = 0;
 394                 val_rxdly = RTL8211F_RX_DELAY;
 395                 break;
 396
 397         case PHY_INTERFACE_MODE_RGMII_TXID:
 398                 val_txdly = RTL8211F_TX_DELAY;
 399                 val_rxdly = 0;
 400                 break;
 401
 402         case PHY_INTERFACE_MODE_RGMII_ID:
 403                 val_txdly = RTL8211F_TX_DELAY;
 404                 val_rxdly = RTL8211F_RX_DELAY;
 405                 break;
 406
 407         default: /* the rest of the modes imply leaving delay as is. */
 408                 return 0;
 409         }
 410
 411         ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
 412                                        val_txdly);
 413         if (ret < 0) {
 414                 dev_err(dev, "Failed to update the TX delay register\n");
 415                 return ret;
 416         } else if (ret) {
 417                 dev_dbg(dev,
 418                         "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
 419                         val_txdly ? "Enabling" : "Disabling");
 420         } else {
 421                 dev_dbg(dev,
 422                         "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
 423                         val_txdly ? "enabled" : "disabled");
 424         }
 425
 426         ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
 427                                        val_rxdly);
 428         if (ret < 0) {
 429                 dev_err(dev, "Failed to update the RX delay register\n");
 430                 return ret;
 431         } else if (ret) {
 432                 dev_dbg(dev,
 433                         "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
 434                         val_rxdly ? "Enabling" : "Disabling");
 435         } else {
 436                 dev_dbg(dev,
 437                         "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
 438                         val_rxdly ? "enabled" : "disabled");
 439         }
 440
 441         if (priv->has_phycr2) {
 442                 ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
 443                                        RTL8211F_CLKOUT_EN, priv->phycr2);
 444                 if (ret < 0) {
 445                         dev_err(dev, "clkout configuration failed: %pe\n",
 446                                 ERR_PTR(ret));
 447                         return ret;
 448                 }
 449
 450                 return genphy_soft_reset(phydev);
 451         }
 452
 453         return 0;
 454 }
 455
 456 static int rtl821x_suspend(struct phy_device *phydev)
 457 {
 458         struct rtl821x_priv *priv = phydev->priv;
 459         int ret = 0;
 460
 461         if (!phydev->wol_enabled) {
 462                 ret = genphy_suspend(phydev);
 463
 464                 if (ret)
 465                         return ret;
 466
 467                 clk_disable_unprepare(priv->clk);
 468         }
 469
 470         return ret;
 471 }
 472
 473 static int rtl821x_resume(struct phy_device *phydev)
 474 {
 475         struct rtl821x_priv *priv = phydev->priv;
 476         int ret;
 477
 478         if (!phydev->wol_enabled)
 479                 clk_prepare_enable(priv->clk);
 480
 481         ret = genphy_resume(phydev);
 482         if (ret < 0)
 483                 return ret;
 484
 485         msleep(20);
 486
 487         return 0;
 488 }
 489
 490 static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
 491                                         unsigned long rules)
 492 {
 493         const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
 494                                    BIT(TRIGGER_NETDEV_LINK_100) |
 495                                    BIT(TRIGGER_NETDEV_LINK_1000) |
 496                                    BIT(TRIGGER_NETDEV_RX) |
 497                                    BIT(TRIGGER_NETDEV_TX);
 498
 499         /* The RTL8211F PHY supports these LED settings on up to three LEDs:
 500          * - Link: Configurable subset of 10/100/1000 link rates
 501          * - Active: Blink on activity, RX or TX is not differentiated
 502          * The Active option has two modes, A and B:
 503          * - A: Link and Active indication at configurable, but matching,
 504          *      subset of 10/100/1000 link rates
 505          * - B: Link indication at configurable subset of 10/100/1000 link
 506          *      rates and Active indication always at all three 10+100+1000
 507          *      link rates.
 508          * This code currently uses mode B only.
 509          */
 510
 511         if (index >= RTL8211F_LED_COUNT)
 512                 return -EINVAL;
 513
 514         /* Filter out any other unsupported triggers. */
 515         if (rules & ~mask)
 516                 return -EOPNOTSUPP;
 517
 518         /* RX and TX are not differentiated, either both are set or not set. */
 519         if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
 520                 return -EOPNOTSUPP;
 521
 522         return 0;
 523 }
 524
 525 static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
 526                                        unsigned long *rules)
 527 {
 528         int val;
 529
 530         val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
 531         if (val < 0)
 532                 return val;
 533
 534         val >>= RTL8211F_LEDCR_SHIFT * index;
 535         val &= RTL8211F_LEDCR_MASK;
 536
 537         if (val & RTL8211F_LEDCR_LINK_10)
 538                 set_bit(TRIGGER_NETDEV_LINK_10, rules);
 539
 540         if (val & RTL8211F_LEDCR_LINK_100)
 541                 set_bit(TRIGGER_NETDEV_LINK_100, rules);
 542
 543         if (val & RTL8211F_LEDCR_LINK_1000)
 544                 set_bit(TRIGGER_NETDEV_LINK_1000, rules);
 545
 546         if (val & RTL8211F_LEDCR_ACT_TXRX) {
 547                 set_bit(TRIGGER_NETDEV_RX, rules);
 548                 set_bit(TRIGGER_NETDEV_TX, rules);
 549         }
 550
 551         return 0;
 552 }
 553
 554 static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
 555                                        unsigned long rules)
 556 {
 557         const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
 558         u16 reg = 0;
 559
 560         if (index >= RTL8211F_LED_COUNT)
 561                 return -EINVAL;
 562
 563         if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
 564                 reg |= RTL8211F_LEDCR_LINK_10;
 565
 566         if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
 567                 reg |= RTL8211F_LEDCR_LINK_100;
 568
 569         if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
 570                 reg |= RTL8211F_LEDCR_LINK_1000;
 571
 572         if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
 573             test_bit(TRIGGER_NETDEV_TX, &rules)) {
 574                 reg |= RTL8211F_LEDCR_ACT_TXRX;
 575         }
 576
 577         reg <<= RTL8211F_LEDCR_SHIFT * index;
 578         reg |= RTL8211F_LEDCR_MODE;      /* Mode B */
 579
 580         return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
 581 }
 582
 583 static int rtl8211e_config_init(struct phy_device *phydev)
 584 {
 585         int ret = 0, oldpage;
 586         u16 val;
 587
 588         /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
 589         switch (phydev->interface) {
 590         case PHY_INTERFACE_MODE_RGMII:
 591                 val = RTL8211E_CTRL_DELAY | 0;
 592                 break;
 593         case PHY_INTERFACE_MODE_RGMII_ID:
 594                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
 595                 break;
 596         case PHY_INTERFACE_MODE_RGMII_RXID:
 597                 val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
 598                 break;
 599         case PHY_INTERFACE_MODE_RGMII_TXID:
 600                 val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
 601                 break;
 602         default: /* the rest of the modes imply leaving delays as is. */
 603                 return 0;
 604         }
 605
 606         /* According to a sample driver there is a 0x1c config register on the
 607          * 0xa4 extension page (0x7) layout. It can be used to disable/enable
 608          * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
 609          * The configuration register definition:
 610          * 14 = reserved
 611          * 13 = Force Tx RX Delay controlled by bit12 bit11,
 612          * 12 = RX Delay, 11 = TX Delay
 613          * 10:0 = Test && debug settings reserved by realtek
 614          */
 615         oldpage = phy_select_page(phydev, 0x7);
 616         if (oldpage < 0)
 617                 goto err_restore_page;
 618
 619         ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
 620         if (ret)
 621                 goto err_restore_page;
 622
 623         ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
 624                            | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
 625                            val);
 626
 627 err_restore_page:
 628         return phy_restore_page(phydev, oldpage, ret);
 629 }
 630
 631 static int rtl8211b_suspend(struct phy_device *phydev)
 632 {
 633         phy_write(phydev, MII_MMD_DATA, BIT(9));
 634
 635         return genphy_suspend(phydev);
 636 }
 637
 638 static int rtl8211b_resume(struct phy_device *phydev)
 639 {
 640         phy_write(phydev, MII_MMD_DATA, 0);
 641
 642         return genphy_resume(phydev);
 643 }
 644
 645 static int rtl8366rb_config_init(struct phy_device *phydev)
 646 {
 647         int ret;
 648
 649         ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
 650                            RTL8366RB_POWER_SAVE_ON);
 651         if (ret) {
 652                 dev_err(&phydev->mdio.dev,
 653                         "error enabling power management\n");
 654         }
 655
 656         return ret;
 657 }
 658
 659 /* get actual speed to cover the downshift case */
 660 static void rtlgen_decode_speed(struct phy_device *phydev, int val)
 661 {
 662         switch (val & RTLGEN_SPEED_MASK) {
 663         case 0x0000:
 664                 phydev->speed = SPEED_10;
 665                 break;
 666         case 0x0010:
 667                 phydev->speed = SPEED_100;
 668                 break;
 669         case 0x0020:
 670                 phydev->speed = SPEED_1000;
 671                 break;
 672         case 0x0200:
 673                 phydev->speed = SPEED_10000;
 674                 break;
 675         case 0x0210:
 676                 phydev->speed = SPEED_2500;
 677                 break;
 678         case 0x0220:
 679                 phydev->speed = SPEED_5000;
 680                 break;
 681         default:
 682                 break;
 683         }
 684 }
 685
 686 static int rtlgen_read_status(struct phy_device *phydev)
 687 {
 688         int ret, val;
 689
 690         ret = genphy_read_status(phydev);
 691         if (ret < 0)
 692                 return ret;
 693
 694         if (!phydev->link)
 695                 return 0;
 696
 697         val = phy_read_paged(phydev, 0xa43, 0x12);
 698         if (val < 0)
 699                 return val;
 700
 701         rtlgen_decode_speed(phydev, val);
 702
 703         return 0;
 704 }
 705
 706 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 707 {
 708         int ret;
 709
 710         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
 711                 rtl821x_write_page(phydev, 0xa5c);
 712                 ret = __phy_read(phydev, 0x12);
 713                 rtl821x_write_page(phydev, 0);
 714         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 715                 rtl821x_write_page(phydev, 0xa5d);
 716                 ret = __phy_read(phydev, 0x10);
 717                 rtl821x_write_page(phydev, 0);
 718         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
 719                 rtl821x_write_page(phydev, 0xa5d);
 720                 ret = __phy_read(phydev, 0x11);
 721                 rtl821x_write_page(phydev, 0);
 722         } else {
 723                 ret = -EOPNOTSUPP;
 724         }
 725
 726         return ret;
 727 }
 728
 729 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 730                             u16 val)
 731 {
 732         int ret;
 733
 734         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
 735                 rtl821x_write_page(phydev, 0xa5d);
 736                 ret = __phy_write(phydev, 0x10, val);
 737                 rtl821x_write_page(phydev, 0);
 738         } else {
 739                 ret = -EOPNOTSUPP;
 740         }
 741
 742         return ret;
 743 }
 744
 745 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
 746 {
 747         int ret = rtlgen_read_mmd(phydev, devnum, regnum);
 748
 749         if (ret != -EOPNOTSUPP)
 750                 return ret;
 751
 752         if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
 753                 rtl821x_write_page(phydev, 0xa6e);
 754                 ret = __phy_read(phydev, 0x16);
 755                 rtl821x_write_page(phydev, 0);
 756         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 757                 rtl821x_write_page(phydev, 0xa6d);
 758                 ret = __phy_read(phydev, 0x12);
 759                 rtl821x_write_page(phydev, 0);
 760         } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
 761                 rtl821x_write_page(phydev, 0xa6d);
 762                 ret = __phy_read(phydev, 0x10);
 763                 rtl821x_write_page(phydev, 0);
 764         }
 765
 766         return ret;
 767 }
 768
 769 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
 770                              u16 val)
 771 {
 772         int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
 773
 774         if (ret != -EOPNOTSUPP)
 775                 return ret;
 776
 777         if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
 778                 rtl821x_write_page(phydev, 0xa6d);
 779                 ret = __phy_write(phydev, 0x12, val);
 780                 rtl821x_write_page(phydev, 0);
 781         }
 782
 783         return ret;
 784 }
 785
 786 static int rtl822xb_config_init(struct phy_device *phydev)
 787 {
 788         bool has_2500, has_sgmii;
 789         u16 mode;
 790         int ret;
 791
 792         has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
 793                             phydev->host_interfaces) ||
 794                    phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
 795
 796         has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
 797                              phydev->host_interfaces) ||
 798                     phydev->interface == PHY_INTERFACE_MODE_SGMII;
 799
 800         /* fill in possible interfaces */
 801         __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
 802                      has_2500);
 803         __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
 804                      has_sgmii);
 805
 806         if (!has_2500 && !has_sgmii)
 807                 return 0;
 808
 809         /* determine SerDes option mode */
 810         if (has_2500 && !has_sgmii) {
 811                 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
 812                 phydev->rate_matching = RATE_MATCH_PAUSE;
 813         } else {
 814                 mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
 815                 phydev->rate_matching = RATE_MATCH_NONE;
 816         }
 817
 818         /* the following sequence with magic numbers sets up the SerDes
 819          * option mode
 820          */
 821         ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
 822         if (ret < 0)
 823                 return ret;
 824
 825         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
 826                                      RTL822X_VND1_SERDES_OPTION,
 827                                      RTL822X_VND1_SERDES_OPTION_MODE_MASK,
 828                                      mode);
 829         if (ret < 0)
 830                 return ret;
 831
 832         ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
 833         if (ret < 0)
 834                 return ret;
 835
 836         ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
 837         if (ret < 0)
 838                 return ret;
 839
 840         return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
 841 }
 842
 843 static int rtl822xb_get_rate_matching(struct phy_device *phydev,
 844                                       phy_interface_t iface)
 845 {
 846         int val;
 847
 848         /* Only rate matching at 2500base-x */
 849         if (iface != PHY_INTERFACE_MODE_2500BASEX)
 850                 return RATE_MATCH_NONE;
 851
 852         val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
 853         if (val < 0)
 854                 return val;
 855
 856         if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
 857             RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
 858                 return RATE_MATCH_PAUSE;
 859
 860         /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
 861         return RATE_MATCH_NONE;
 862 }
 863
 864 static int rtl822x_get_features(struct phy_device *phydev)
 865 {
 866         int val;
 867
 868         val = phy_read_paged(phydev, 0xa61, 0x13);
 869         if (val < 0)
 870                 return val;
 871
 872         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
 873                          phydev->supported, val & MDIO_PMA_SPEED_2_5G);
 874         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
 875                          phydev->supported, val & MDIO_PMA_SPEED_5G);
 876         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
 877                          phydev->supported, val & MDIO_SPEED_10G);
 878
 879         return genphy_read_abilities(phydev);
 880 }
 881
 882 static int rtl822x_config_aneg(struct phy_device *phydev)
 883 {
 884         int ret = 0;
 885
 886         if (phydev->autoneg == AUTONEG_ENABLE) {
 887                 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
 888
 889                 ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
 890                                                MDIO_AN_10GBT_CTRL_ADV2_5G |
 891                                                MDIO_AN_10GBT_CTRL_ADV5G,
 892                                                adv);
 893                 if (ret < 0)
 894                         return ret;
 895         }
 896
 897         return __genphy_config_aneg(phydev, ret);
 898 }
 899
 900 static void rtl822xb_update_interface(struct phy_device *phydev)
 901 {
 902         int val;
 903
 904         if (!phydev->link)
 905                 return;
 906
 907         /* Change interface according to serdes mode */
 908         val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
 909         if (val < 0)
 910                 return;
 911
 912         switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
 913         case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
 914                 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 915                 break;
 916         case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
 917                 phydev->interface = PHY_INTERFACE_MODE_SGMII;
 918                 break;
 919         }
 920 }
 921
 922 static int rtl822x_read_status(struct phy_device *phydev)
 923 {
 924         if (phydev->autoneg == AUTONEG_ENABLE) {
 925                 int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
 926
 927                 if (lpadv < 0)
 928                         return lpadv;
 929
 930                 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising,
 931                                                   lpadv);
 932         }
 933
 934         return rtlgen_read_status(phydev);
 935 }
 936
 937 static int rtl822xb_read_status(struct phy_device *phydev)
 938 {
 939         int ret;
 940
 941         ret = rtl822x_read_status(phydev);
 942         if (ret < 0)
 943                 return ret;
 944
 945         rtl822xb_update_interface(phydev);
 946
 947         return 0;
 948 }
 949
 950 static int rtl822x_c45_get_features(struct phy_device *phydev)
 951 {
 952         linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
 953                          phydev->supported);
 954
 955         return genphy_c45_pma_read_abilities(phydev);
 956 }
 957
 958 static int rtl822x_c45_config_aneg(struct phy_device *phydev)
 959 {
 960         bool changed = false;
 961         int ret, val;
 962
 963         if (phydev->autoneg == AUTONEG_DISABLE)
 964                 return genphy_c45_pma_setup_forced(phydev);
 965
 966         ret = genphy_c45_an_config_aneg(phydev);
 967         if (ret < 0)
 968                 return ret;
 969         if (ret > 0)
 970                 changed = true;
 971
 972         val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
 973
 974         /* Vendor register as C45 has no standardized support for 1000BaseT */
 975         ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
 976                                      ADVERTISE_1000FULL, val);
 977         if (ret < 0)
 978                 return ret;
 979         if (ret > 0)
 980                 changed = true;
 981
 982         return genphy_c45_check_and_restart_aneg(phydev, changed);
 983 }
 984
 985 static int rtl822x_c45_read_status(struct phy_device *phydev)
 986 {
 987         int ret, val;
 988
 989         ret = genphy_c45_read_status(phydev);
 990         if (ret < 0)
 991                 return ret;
 992
 993         /* Vendor register as C45 has no standardized support for 1000BaseT */
 994         if (phydev->autoneg == AUTONEG_ENABLE) {
 995                 val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
 996                                    RTL822X_VND2_GANLPAR);
 997                 if (val < 0)
 998                         return val;
 999
1000                 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1001         }
1002
1003         if (!phydev->link)
1004                 return 0;
1005
1006         /* Read actual speed from vendor register. */
1007         val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL822X_VND2_PHYSR);
1008         if (val < 0)
1009                 return val;
1010
1011         rtlgen_decode_speed(phydev, val);
1012
1013         return 0;
1014 }
1015
1016 static int rtl822xb_c45_read_status(struct phy_device *phydev)
1017 {
1018         int ret;
1019
1020         ret = rtl822x_c45_read_status(phydev);
1021         if (ret < 0)
1022                 return ret;
1023
1024         rtl822xb_update_interface(phydev);
1025
1026         return 0;
1027 }
1028
1029 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1030 {
1031         int val;
1032
1033         phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1034         val = phy_read(phydev, 0x13);
1035         phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1036
1037         return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1038 }
1039
1040 static int rtlgen_match_phy_device(struct phy_device *phydev)
1041 {
1042         return phydev->phy_id == RTL_GENERIC_PHYID &&
1043                !rtlgen_supports_2_5gbps(phydev);
1044 }
1045
1046 static int rtl8226_match_phy_device(struct phy_device *phydev)
1047 {
1048         return phydev->phy_id == RTL_GENERIC_PHYID &&
1049                rtlgen_supports_2_5gbps(phydev);
1050 }
1051
1052 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1053                                bool is_c45)
1054 {
1055         if (phydev->is_c45)
1056                 return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1057         else
1058                 return !is_c45 && (id == phydev->phy_id);
1059 }
1060
1061 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
1062 {
1063         return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1064 }
1065
1066 static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
1067 {
1068         return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1069 }
1070
1071 static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
1072 {
1073         return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
1074 }
1075
1076 static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
1077 {
1078         return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
1079 }
1080
1081 static int rtlgen_resume(struct phy_device *phydev)
1082 {
1083         int ret = genphy_resume(phydev);
1084
1085         /* Internal PHY's from RTL8168h up may not be instantly ready */
1086         msleep(20);
1087
1088         return ret;
1089 }
1090
1091 static int rtlgen_c45_resume(struct phy_device *phydev)
1092 {
1093         int ret = genphy_c45_pma_resume(phydev);
1094
1095         msleep(20);
1096
1097         return ret;
1098 }
1099
1100 static int rtl9000a_config_init(struct phy_device *phydev)
1101 {
1102         phydev->autoneg = AUTONEG_DISABLE;
1103         phydev->speed = SPEED_100;
1104         phydev->duplex = DUPLEX_FULL;
1105
1106         return 0;
1107 }
1108
1109 static int rtl9000a_config_aneg(struct phy_device *phydev)
1110 {
1111         int ret;
1112         u16 ctl = 0;
1113
1114         switch (phydev->master_slave_set) {
1115         case MASTER_SLAVE_CFG_MASTER_FORCE:
1116                 ctl |= CTL1000_AS_MASTER;
1117                 break;
1118         case MASTER_SLAVE_CFG_SLAVE_FORCE:
1119                 break;
1120         case MASTER_SLAVE_CFG_UNKNOWN:
1121         case MASTER_SLAVE_CFG_UNSUPPORTED:
1122                 return 0;
1123         default:
1124                 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1125                 return -EOPNOTSUPP;
1126         }
1127
1128         ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1129         if (ret == 1)
1130                 ret = genphy_soft_reset(phydev);
1131
1132         return ret;
1133 }
1134
1135 static int rtl9000a_read_status(struct phy_device *phydev)
1136 {
1137         int ret;
1138
1139         phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1140         phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1141
1142         ret = genphy_update_link(phydev);
1143         if (ret)
1144                 return ret;
1145
1146         ret = phy_read(phydev, MII_CTRL1000);
1147         if (ret < 0)
1148                 return ret;
1149         if (ret & CTL1000_AS_MASTER)
1150                 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1151         else
1152                 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1153
1154         ret = phy_read(phydev, MII_STAT1000);
1155         if (ret < 0)
1156                 return ret;
1157         if (ret & LPA_1000MSRES)
1158                 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1159         else
1160                 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1161
1162         return 0;
1163 }
1164
1165 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1166 {
1167         int err;
1168
1169         err = phy_read(phydev, RTL8211F_INSR);
1170
1171         return (err < 0) ? err : 0;
1172 }
1173
1174 static int rtl9000a_config_intr(struct phy_device *phydev)
1175 {
1176         u16 val;
1177         int err;
1178
1179         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1180                 err = rtl9000a_ack_interrupt(phydev);
1181                 if (err)
1182                         return err;
1183
1184                 val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1185                 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1186         } else {
1187                 val = ~0;
1188                 err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1189                 if (err)
1190                         return err;
1191
1192                 err = rtl9000a_ack_interrupt(phydev);
1193         }
1194
1195         return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1196 }
1197
1198 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1199 {
1200         int irq_status;
1201
1202         irq_status = phy_read(phydev, RTL8211F_INSR);
1203         if (irq_status < 0) {
1204                 phy_error(phydev);
1205                 return IRQ_NONE;
1206         }
1207
1208         if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1209                 return IRQ_NONE;
1210
1211         phy_trigger_machine(phydev);
1212
1213         return IRQ_HANDLED;
1214 }
1215
1216 static struct phy_driver realtek_drvs[] = {
1217         {
1218                 PHY_ID_MATCH_EXACT(0x00008201),
1219                 .name           = "RTL8201CP Ethernet",
1220                 .read_page      = rtl821x_read_page,
1221                 .write_page     = rtl821x_write_page,
1222         }, {
1223                 PHY_ID_MATCH_EXACT(0x001cc816),
1224                 .name           = "RTL8201F Fast Ethernet",
1225                 .config_intr    = &rtl8201_config_intr,
1226                 .handle_interrupt = rtl8201_handle_interrupt,
1227                 .suspend        = genphy_suspend,
1228                 .resume         = genphy_resume,
1229                 .read_page      = rtl821x_read_page,
1230                 .write_page     = rtl821x_write_page,
1231         }, {
1232                 PHY_ID_MATCH_MODEL(0x001cc880),
1233                 .name           = "RTL8208 Fast Ethernet",
1234                 .read_mmd       = genphy_read_mmd_unsupported,
1235                 .write_mmd      = genphy_write_mmd_unsupported,
1236                 .suspend        = genphy_suspend,
1237                 .resume         = genphy_resume,
1238                 .read_page      = rtl821x_read_page,
1239                 .write_page     = rtl821x_write_page,
1240         }, {
1241                 PHY_ID_MATCH_EXACT(0x001cc910),
1242                 .name           = "RTL8211 Gigabit Ethernet",
1243                 .config_aneg    = rtl8211_config_aneg,
1244                 .read_mmd       = &genphy_read_mmd_unsupported,
1245                 .write_mmd      = &genphy_write_mmd_unsupported,
1246                 .read_page      = rtl821x_read_page,
1247                 .write_page     = rtl821x_write_page,
1248         }, {
1249                 PHY_ID_MATCH_EXACT(0x001cc912),
1250                 .name           = "RTL8211B Gigabit Ethernet",
1251                 .config_intr    = &rtl8211b_config_intr,
1252                 .handle_interrupt = rtl821x_handle_interrupt,
1253                 .read_mmd       = &genphy_read_mmd_unsupported,
1254                 .write_mmd      = &genphy_write_mmd_unsupported,
1255                 .suspend        = rtl8211b_suspend,
1256                 .resume         = rtl8211b_resume,
1257                 .read_page      = rtl821x_read_page,
1258                 .write_page     = rtl821x_write_page,
1259         }, {
1260                 PHY_ID_MATCH_EXACT(0x001cc913),
1261                 .name           = "RTL8211C Gigabit Ethernet",
1262                 .config_init    = rtl8211c_config_init,
1263                 .read_mmd       = &genphy_read_mmd_unsupported,
1264                 .write_mmd      = &genphy_write_mmd_unsupported,
1265                 .read_page      = rtl821x_read_page,
1266                 .write_page     = rtl821x_write_page,
1267         }, {
1268                 PHY_ID_MATCH_EXACT(0x001cc914),
1269                 .name           = "RTL8211DN Gigabit Ethernet",
1270                 .config_intr    = rtl8211e_config_intr,
1271                 .handle_interrupt = rtl821x_handle_interrupt,
1272                 .suspend        = genphy_suspend,
1273                 .resume         = genphy_resume,
1274                 .read_page      = rtl821x_read_page,
1275                 .write_page     = rtl821x_write_page,
1276         }, {
1277                 PHY_ID_MATCH_EXACT(0x001cc915),
1278                 .name           = "RTL8211E Gigabit Ethernet",
1279                 .config_init    = &rtl8211e_config_init,
1280                 .config_intr    = &rtl8211e_config_intr,
1281                 .handle_interrupt = rtl821x_handle_interrupt,
1282                 .suspend        = genphy_suspend,
1283                 .resume         = genphy_resume,
1284                 .read_page      = rtl821x_read_page,
1285                 .write_page     = rtl821x_write_page,
1286         }, {
1287                 PHY_ID_MATCH_EXACT(0x001cc916),
1288                 .name           = "RTL8211F Gigabit Ethernet",
1289                 .probe          = rtl821x_probe,
1290                 .config_init    = &rtl8211f_config_init,
1291                 .read_status    = rtlgen_read_status,
1292                 .config_intr    = &rtl8211f_config_intr,
1293                 .handle_interrupt = rtl8211f_handle_interrupt,
1294                 .suspend        = rtl821x_suspend,
1295                 .resume         = rtl821x_resume,
1296                 .read_page      = rtl821x_read_page,
1297                 .write_page     = rtl821x_write_page,
1298                 .flags          = PHY_ALWAYS_CALL_SUSPEND,
1299                 .led_hw_is_supported = rtl8211f_led_hw_is_supported,
1300                 .led_hw_control_get = rtl8211f_led_hw_control_get,
1301                 .led_hw_control_set = rtl8211f_led_hw_control_set,
1302         }, {
1303                 PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1304                 .name           = "RTL8211F-VD Gigabit Ethernet",
1305                 .probe          = rtl821x_probe,
1306                 .config_init    = &rtl8211f_config_init,
1307                 .read_status    = rtlgen_read_status,
1308                 .config_intr    = &rtl8211f_config_intr,
1309                 .handle_interrupt = rtl8211f_handle_interrupt,
1310                 .suspend        = rtl821x_suspend,
1311                 .resume         = rtl821x_resume,
1312                 .read_page      = rtl821x_read_page,
1313                 .write_page     = rtl821x_write_page,
1314                 .flags          = PHY_ALWAYS_CALL_SUSPEND,
1315         }, {
1316                 .name           = "Generic FE-GE Realtek PHY",
1317                 .match_phy_device = rtlgen_match_phy_device,
1318                 .read_status    = rtlgen_read_status,
1319                 .suspend        = genphy_suspend,
1320                 .resume         = rtlgen_resume,
1321                 .read_page      = rtl821x_read_page,
1322                 .write_page     = rtl821x_write_page,
1323                 .read_mmd       = rtlgen_read_mmd,
1324                 .write_mmd      = rtlgen_write_mmd,
1325         }, {
1326                 .name           = "RTL8226 2.5Gbps PHY",
1327                 .match_phy_device = rtl8226_match_phy_device,
1328                 .get_features   = rtl822x_get_features,
1329                 .config_aneg    = rtl822x_config_aneg,
1330                 .read_status    = rtl822x_read_status,
1331                 .suspend        = genphy_suspend,
1332                 .resume         = rtlgen_resume,
1333                 .read_page      = rtl821x_read_page,
1334                 .write_page     = rtl821x_write_page,
1335                 .read_mmd       = rtl822x_read_mmd,
1336                 .write_mmd      = rtl822x_write_mmd,
1337         }, {
1338                 PHY_ID_MATCH_EXACT(0x001cc840),
1339                 .name           = "RTL8226B_RTL8221B 2.5Gbps PHY",
1340                 .get_features   = rtl822x_get_features,
1341                 .config_aneg    = rtl822x_config_aneg,
1342                 .config_init    = rtl822xb_config_init,
1343                 .get_rate_matching = rtl822xb_get_rate_matching,
1344                 .read_status    = rtl822xb_read_status,
1345                 .suspend        = genphy_suspend,
1346                 .resume         = rtlgen_resume,
1347                 .read_page      = rtl821x_read_page,
1348                 .write_page     = rtl821x_write_page,
1349                 .read_mmd       = rtl822x_read_mmd,
1350                 .write_mmd      = rtl822x_write_mmd,
1351         }, {
1352                 PHY_ID_MATCH_EXACT(0x001cc838),
1353                 .name           = "RTL8226-CG 2.5Gbps PHY",
1354                 .get_features   = rtl822x_get_features,
1355                 .config_aneg    = rtl822x_config_aneg,
1356                 .read_status    = rtl822x_read_status,
1357                 .suspend        = genphy_suspend,
1358                 .resume         = rtlgen_resume,
1359                 .read_page      = rtl821x_read_page,
1360                 .write_page     = rtl821x_write_page,
1361         }, {
1362                 PHY_ID_MATCH_EXACT(0x001cc848),
1363                 .name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1364                 .get_features   = rtl822x_get_features,
1365                 .config_aneg    = rtl822x_config_aneg,
1366                 .config_init    = rtl822xb_config_init,
1367                 .get_rate_matching = rtl822xb_get_rate_matching,
1368                 .read_status    = rtl822xb_read_status,
1369                 .suspend        = genphy_suspend,
1370                 .resume         = rtlgen_resume,
1371                 .read_page      = rtl821x_read_page,
1372                 .write_page     = rtl821x_write_page,
1373         }, {
1374                 .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1375                 .name           = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1376                 .get_features   = rtl822x_get_features,
1377                 .config_aneg    = rtl822x_config_aneg,
1378                 .config_init    = rtl822xb_config_init,
1379                 .get_rate_matching = rtl822xb_get_rate_matching,
1380                 .read_status    = rtl822xb_read_status,
1381                 .suspend        = genphy_suspend,
1382                 .resume         = rtlgen_resume,
1383                 .read_page      = rtl821x_read_page,
1384                 .write_page     = rtl821x_write_page,
1385         }, {
1386                 .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1387                 .name           = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1388                 .config_init    = rtl822xb_config_init,
1389                 .get_rate_matching = rtl822xb_get_rate_matching,
1390                 .get_features   = rtl822x_c45_get_features,
1391                 .config_aneg    = rtl822x_c45_config_aneg,
1392                 .read_status    = rtl822xb_c45_read_status,
1393                 .suspend        = genphy_c45_pma_suspend,
1394                 .resume         = rtlgen_c45_resume,
1395         }, {
1396                 .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1397                 .name           = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1398                 .get_features   = rtl822x_get_features,
1399                 .config_aneg    = rtl822x_config_aneg,
1400                 .config_init    = rtl822xb_config_init,
1401                 .get_rate_matching = rtl822xb_get_rate_matching,
1402                 .read_status    = rtl822xb_read_status,
1403                 .suspend        = genphy_suspend,
1404                 .resume         = rtlgen_resume,
1405                 .read_page      = rtl821x_read_page,
1406                 .write_page     = rtl821x_write_page,
1407         }, {
1408                 .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1409                 .name           = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1410                 .config_init    = rtl822xb_config_init,
1411                 .get_rate_matching = rtl822xb_get_rate_matching,
1412                 .get_features   = rtl822x_c45_get_features,
1413                 .config_aneg    = rtl822x_c45_config_aneg,
1414                 .read_status    = rtl822xb_c45_read_status,
1415                 .suspend        = genphy_c45_pma_suspend,
1416                 .resume         = rtlgen_c45_resume,
1417         }, {
1418                 PHY_ID_MATCH_EXACT(0x001cc862),
1419                 .name           = "RTL8251B 5Gbps PHY",
1420                 .get_features   = rtl822x_get_features,
1421                 .config_aneg    = rtl822x_config_aneg,
1422                 .read_status    = rtl822x_read_status,
1423                 .suspend        = genphy_suspend,
1424                 .resume         = rtlgen_resume,
1425                 .read_page      = rtl821x_read_page,
1426                 .write_page     = rtl821x_write_page,
1427         }, {
1428                 PHY_ID_MATCH_EXACT(0x001ccad0),
1429                 .name           = "RTL8224 2.5Gbps PHY",
1430                 .get_features   = rtl822x_c45_get_features,
1431                 .config_aneg    = rtl822x_c45_config_aneg,
1432                 .read_status    = rtl822x_c45_read_status,
1433                 .suspend        = genphy_c45_pma_suspend,
1434                 .resume         = rtlgen_c45_resume,
1435         }, {
1436                 PHY_ID_MATCH_EXACT(0x001cc961),
1437                 .name           = "RTL8366RB Gigabit Ethernet",
1438                 .config_init    = &rtl8366rb_config_init,
1439                 /* These interrupts are handled by the irq controller
1440                  * embedded inside the RTL8366RB, they get unmasked when the
1441                  * irq is requested and ACKed by reading the status register,
1442                  * which is done by the irqchip code.
1443                  */
1444                 .config_intr    = genphy_no_config_intr,
1445                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1446                 .suspend        = genphy_suspend,
1447                 .resume         = genphy_resume,
1448         }, {
1449                 PHY_ID_MATCH_EXACT(0x001ccb00),
1450                 .name           = "RTL9000AA_RTL9000AN Ethernet",
1451                 .features       = PHY_BASIC_T1_FEATURES,
1452                 .config_init    = rtl9000a_config_init,
1453                 .config_aneg    = rtl9000a_config_aneg,
1454                 .read_status    = rtl9000a_read_status,
1455                 .config_intr    = rtl9000a_config_intr,
1456                 .handle_interrupt = rtl9000a_handle_interrupt,
1457                 .suspend        = genphy_suspend,
1458                 .resume         = genphy_resume,
1459                 .read_page      = rtl821x_read_page,
1460                 .write_page     = rtl821x_write_page,
1461         }, {
1462                 PHY_ID_MATCH_EXACT(0x001cc942),
1463                 .name           = "RTL8365MB-VC Gigabit Ethernet",
1464                 /* Interrupt handling analogous to RTL8366RB */
1465                 .config_intr    = genphy_no_config_intr,
1466                 .handle_interrupt = genphy_handle_interrupt_no_ack,
1467                 .suspend        = genphy_suspend,
1468                 .resume         = genphy_resume,
1469         }, {
1470                 PHY_ID_MATCH_EXACT(0x001cc960),
1471                 .name           = "RTL8366S Gigabit Ethernet",
1472                 .suspend        = genphy_suspend,
1473                 .resume         = genphy_resume,
1474                 .read_mmd       = genphy_read_mmd_unsupported,
1475                 .write_mmd      = genphy_write_mmd_unsupported,
1476         },
1477 };
1478
1479 module_phy_driver(realtek_drvs);
1480
1481 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1482         { PHY_ID_MATCH_VENDOR(0x001cc800) },
1483         { }
1484 };
1485
1486 MODULE_DEVICE_TABLE(mdio, realtek_tbl);