1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
4 * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
7 #include <net/pkt_cls.h>
9 #include "sparx5_main.h"
10 #include "sparx5_qos.h"
12 /* Calculate new base_time based on cycle_time.
14 * The hardware requires a base_time that is always in the future.
15 * We define threshold_time as current_time + (2 * cycle_time).
16 * If base_time is below threshold_time this function recalculates it to be in
18 * threshold_time <= base_time < (threshold_time + cycle_time)
20 * A very simple algorithm could be like this:
21 * new_base_time = org_base_time + N * cycle_time
22 * using the lowest N so (new_base_time >= threshold_time
24 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time,
25 const ktime_t org_base_time, ktime_t *new_base_time)
27 ktime_t current_time, threshold_time, new_time;
33 new_time = org_base_time;
35 sparx5_ptp_gettime64(&sparx5->phc[SPARX5_PHC_PORT].info, &ts);
36 current_time = timespec64_to_ktime(ts);
37 threshold_time = current_time + (2 * cycle_time);
38 diff_time = threshold_time - new_time;
39 nr_of_cycles = div_u64(diff_time, cycle_time);
40 nr_of_cycles_p2 = 1; /* Use 2^0 as start value */
42 if (new_time >= threshold_time) {
43 *new_base_time = new_time;
47 /* Calculate the smallest power of 2 (nr_of_cycles_p2)
48 * that is larger than nr_of_cycles.
50 while (nr_of_cycles_p2 < nr_of_cycles)
51 nr_of_cycles_p2 <<= 1; /* Next (higher) power of 2 */
53 /* Add as big chunks (power of 2 * cycle_time)
54 * as possible for each power of 2
56 while (nr_of_cycles_p2) {
57 if (new_time < threshold_time) {
58 new_time += cycle_time * nr_of_cycles_p2;
59 while (new_time < threshold_time)
60 new_time += cycle_time * nr_of_cycles_p2;
61 new_time -= cycle_time * nr_of_cycles_p2;
63 nr_of_cycles_p2 >>= 1; /* Next (lower) power of 2 */
65 new_time += cycle_time;
66 *new_base_time = new_time;
69 /* Max rates for leak groups */
70 static const u32 spx5_hsch_max_group_rate[SPX5_HSCH_LEAK_GRP_CNT] = {
71 1048568, /* 1.049 Gbps */
72 2621420, /* 2.621 Gbps */
73 10485680, /* 10.486 Gbps */
74 26214200 /* 26.214 Gbps */
77 static struct sparx5_layer layers[SPX5_HSCH_LAYER_CNT];
79 static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group)
83 value = spx5_rd(sparx5, HSCH_HSCH_TIMER_CFG(layer, group));
84 return HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(value);
87 static void sparx5_lg_set_leak_time(struct sparx5 *sparx5, u32 layer, u32 group,
90 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5,
91 HSCH_HSCH_TIMER_CFG(layer, group));
94 static u32 sparx5_lg_get_first(struct sparx5 *sparx5, u32 layer, u32 group)
98 value = spx5_rd(sparx5, HSCH_HSCH_LEAK_CFG(layer, group));
99 return HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(value);
102 static u32 sparx5_lg_get_next(struct sparx5 *sparx5, u32 layer, u32 group,
108 value = spx5_rd(sparx5, HSCH_SE_CONNECT(idx));
109 return HSCH_SE_CONNECT_SE_LEAK_LINK_GET(value);
112 static u32 sparx5_lg_get_last(struct sparx5 *sparx5, u32 layer, u32 group)
116 itr = sparx5_lg_get_first(sparx5, layer, group);
119 next = sparx5_lg_get_next(sparx5, layer, group, itr);
127 static bool sparx5_lg_is_last(struct sparx5 *sparx5, u32 layer, u32 group,
130 return idx == sparx5_lg_get_next(sparx5, layer, group, idx);
133 static bool sparx5_lg_is_first(struct sparx5 *sparx5, u32 layer, u32 group,
136 return idx == sparx5_lg_get_first(sparx5, layer, group);
139 static bool sparx5_lg_is_empty(struct sparx5 *sparx5, u32 layer, u32 group)
141 return sparx5_lg_get_leak_time(sparx5, layer, group) == 0;
144 static bool sparx5_lg_is_singular(struct sparx5 *sparx5, u32 layer, u32 group)
146 if (sparx5_lg_is_empty(sparx5, layer, group))
149 return sparx5_lg_get_first(sparx5, layer, group) ==
150 sparx5_lg_get_last(sparx5, layer, group);
153 static void sparx5_lg_enable(struct sparx5 *sparx5, u32 layer, u32 group,
156 sparx5_lg_set_leak_time(sparx5, layer, group, leak_time);
159 static void sparx5_lg_disable(struct sparx5 *sparx5, u32 layer, u32 group)
161 sparx5_lg_set_leak_time(sparx5, layer, group, 0);
164 static int sparx5_lg_get_group_by_index(struct sparx5 *sparx5, u32 layer,
170 for (i = 0; i < SPX5_HSCH_LEAK_GRP_CNT; i++) {
171 if (sparx5_lg_is_empty(sparx5, layer, i))
174 itr = sparx5_lg_get_first(sparx5, layer, i);
177 next = sparx5_lg_get_next(sparx5, layer, i, itr);
181 return 0; /* Found it */
184 break; /* Was not found */
193 static int sparx5_lg_get_group_by_rate(u32 layer, u32 rate, u32 *group)
195 struct sparx5_layer *l = &layers[layer];
196 struct sparx5_lg *lg;
199 for (i = 0; i < SPX5_HSCH_LEAK_GRP_CNT; i++) {
200 lg = &l->leak_groups[i];
201 if (rate <= lg->max_rate) {
210 static int sparx5_lg_get_adjacent(struct sparx5 *sparx5, u32 layer, u32 group,
211 u32 idx, u32 *prev, u32 *next, u32 *first)
215 *first = sparx5_lg_get_first(sparx5, layer, group);
221 *next = sparx5_lg_get_next(sparx5, layer, group, itr);
224 return 0; /* Found it */
227 return -1; /* Was not found */
236 static int sparx5_lg_conf_set(struct sparx5 *sparx5, u32 layer, u32 group,
237 u32 se_first, u32 idx, u32 idx_next, bool empty)
239 u32 leak_time = layers[layer].leak_groups[group].leak_time;
242 sparx5_lg_disable(sparx5, layer, group);
248 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer),
249 HSCH_HSCH_CFG_CFG_HSCH_LAYER, sparx5, HSCH_HSCH_CFG_CFG);
252 spx5_wr(HSCH_SE_CONNECT_SE_LEAK_LINK_SET(idx_next), sparx5,
253 HSCH_SE_CONNECT(idx));
255 /* Set the first element. */
256 spx5_rmw(HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(se_first),
257 HSCH_HSCH_LEAK_CFG_LEAK_FIRST, sparx5,
258 HSCH_HSCH_LEAK_CFG(layer, group));
261 sparx5_lg_enable(sparx5, layer, group, leak_time);
266 static int sparx5_lg_del(struct sparx5 *sparx5, u32 layer, u32 group, u32 idx)
268 u32 first, next, prev;
271 /* idx *must* be present in the leak group */
272 WARN_ON(sparx5_lg_get_adjacent(sparx5, layer, group, idx, &prev, &next,
275 if (sparx5_lg_is_singular(sparx5, layer, group)) {
277 } else if (sparx5_lg_is_last(sparx5, layer, group, idx)) {
278 /* idx is removed, prev is now last */
281 } else if (sparx5_lg_is_first(sparx5, layer, group, idx)) {
282 /* idx is removed and points to itself, first is next */
286 /* Next is not touched */
290 return sparx5_lg_conf_set(sparx5, layer, group, first, idx, next,
294 static int sparx5_lg_add(struct sparx5 *sparx5, u32 layer, u32 new_group,
297 u32 first, next, old_group;
299 pr_debug("ADD: layer: %d, new_group: %d, idx: %d", layer, new_group,
302 /* Is this SE already shaping ? */
303 if (sparx5_lg_get_group_by_index(sparx5, layer, idx, &old_group) >= 0) {
304 if (old_group != new_group) {
305 /* Delete from old group */
306 sparx5_lg_del(sparx5, layer, old_group, idx);
308 /* Nothing to do here */
313 /* We always add to head of the list */
316 if (sparx5_lg_is_empty(sparx5, layer, new_group))
319 next = sparx5_lg_get_first(sparx5, layer, new_group);
321 return sparx5_lg_conf_set(sparx5, layer, new_group, first, idx, next,
325 static int sparx5_shaper_conf_set(struct sparx5_port *port,
326 const struct sparx5_shaper *sh, u32 layer,
329 int (*sparx5_lg_action)(struct sparx5 *, u32, u32, u32);
330 struct sparx5 *sparx5 = port->sparx5;
332 if (!sh->rate && !sh->burst)
333 sparx5_lg_action = &sparx5_lg_del;
335 sparx5_lg_action = &sparx5_lg_add;
338 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer),
339 HSCH_HSCH_CFG_CFG_HSCH_LAYER, sparx5, HSCH_HSCH_CFG_CFG);
342 spx5_rmw(HSCH_SE_CFG_SE_FRM_MODE_SET(sh->mode), HSCH_SE_CFG_SE_FRM_MODE,
343 sparx5, HSCH_SE_CFG(idx));
345 /* Set committed rate and burst */
346 spx5_wr(HSCH_CIR_CFG_CIR_RATE_SET(sh->rate) |
347 HSCH_CIR_CFG_CIR_BURST_SET(sh->burst),
348 sparx5, HSCH_CIR_CFG(idx));
350 /* This has to be done after the shaper configuration has been set */
351 sparx5_lg_action(sparx5, layer, group, idx);
356 static u32 sparx5_weight_to_hw_cost(u32 weight_min, u32 weight)
358 return ((((SPX5_DWRR_COST_MAX << 4) * weight_min / weight) + 8) >> 4) -
362 static int sparx5_dwrr_conf_set(struct sparx5_port *port,
363 struct sparx5_dwrr *dwrr)
367 spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(2) |
368 HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(port->portno),
369 HSCH_HSCH_CFG_CFG_HSCH_LAYER | HSCH_HSCH_CFG_CFG_CFG_SE_IDX,
370 port->sparx5, HSCH_HSCH_CFG_CFG);
372 /* Number of *lower* indexes that are arbitrated dwrr */
373 spx5_rmw(HSCH_SE_CFG_SE_DWRR_CNT_SET(dwrr->count),
374 HSCH_SE_CFG_SE_DWRR_CNT, port->sparx5,
375 HSCH_SE_CFG(port->portno));
377 for (i = 0; i < dwrr->count; i++) {
378 spx5_rmw(HSCH_DWRR_ENTRY_DWRR_COST_SET(dwrr->cost[i]),
379 HSCH_DWRR_ENTRY_DWRR_COST, port->sparx5,
386 static int sparx5_leak_groups_init(struct sparx5 *sparx5)
388 struct sparx5_layer *layer;
389 u32 sys_clk_per_100ps;
390 struct sparx5_lg *lg;
394 sys_clk_per_100ps = spx5_rd(sparx5, HSCH_SYS_CLK_PER);
396 for (i = 0; i < SPX5_HSCH_LAYER_CNT; i++) {
398 for (ii = 0; ii < SPX5_HSCH_LEAK_GRP_CNT; ii++) {
399 lg = &layer->leak_groups[ii];
400 lg->max_rate = spx5_hsch_max_group_rate[ii];
402 /* Calculate the leak time in us, to serve a maximum
403 * rate of 'max_rate' for this group
405 leak_time_us = (SPX5_SE_RATE_MAX * 1000) / lg->max_rate;
407 /* Hardware wants leak time in ns */
408 lg->leak_time = 1000 * leak_time_us;
410 /* Calculate resolution */
411 lg->resolution = 1000 / leak_time_us;
413 /* Maximum number of shapers that can be served by
416 lg->max_ses = (1000 * leak_time_us) / sys_clk_per_100ps;
419 * Wanted bandwidth is 100Mbit:
421 * 100 mbps can be served by leak group zero.
423 * leak_time is 125000 ns.
426 * cir = 100000 / 8 = 12500
427 * leaks_pr_sec = 125000 / 10^9 = 8000
428 * bw = 12500 * 8000 = 10^8 (100 Mbit)
431 /* Disable by default - this also indicates an empty
434 sparx5_lg_disable(sparx5, i, ii);
441 int sparx5_qos_init(struct sparx5 *sparx5)
445 ret = sparx5_leak_groups_init(sparx5);
449 ret = sparx5_dcb_init(sparx5);
453 sparx5_psfp_init(sparx5);
458 int sparx5_tc_mqprio_add(struct net_device *ndev, u8 num_tc)
462 if (num_tc != SPX5_PRIOS) {
463 netdev_err(ndev, "Only %d traffic classes supported\n",
468 netdev_set_num_tc(ndev, num_tc);
470 for (i = 0; i < num_tc; i++)
471 netdev_set_tc_queue(ndev, i, 1, i);
473 netdev_dbg(ndev, "dev->num_tc %u dev->real_num_tx_queues %u\n",
474 ndev->num_tc, ndev->real_num_tx_queues);
479 int sparx5_tc_mqprio_del(struct net_device *ndev)
481 netdev_reset_tc(ndev);
483 netdev_dbg(ndev, "dev->num_tc %u dev->real_num_tx_queues %u\n",
484 ndev->num_tc, ndev->real_num_tx_queues);
489 int sparx5_tc_tbf_add(struct sparx5_port *port,
490 struct tc_tbf_qopt_offload_replace_params *params,
493 struct sparx5_shaper sh = {
494 .mode = SPX5_SE_MODE_DATARATE,
495 .rate = div_u64(params->rate.rate_bytes_ps, 1000) * 8,
496 .burst = params->max_size,
498 struct sparx5_lg *lg;
501 /* Find suitable group for this se */
502 if (sparx5_lg_get_group_by_rate(layer, sh.rate, &group) < 0) {
503 pr_debug("Could not find leak group for se with rate: %d",
508 lg = &layers[layer].leak_groups[group];
510 pr_debug("Found matching group (speed: %d)\n", lg->max_rate);
512 if (sh.rate < SPX5_SE_RATE_MIN || sh.burst < SPX5_SE_BURST_MIN)
515 /* Calculate committed rate and burst */
516 sh.rate = DIV_ROUND_UP(sh.rate, lg->resolution);
517 sh.burst = DIV_ROUND_UP(sh.burst, SPX5_SE_BURST_UNIT);
519 if (sh.rate > SPX5_SE_RATE_MAX || sh.burst > SPX5_SE_BURST_MAX)
522 return sparx5_shaper_conf_set(port, &sh, layer, idx, group);
525 int sparx5_tc_tbf_del(struct sparx5_port *port, u32 layer, u32 idx)
527 struct sparx5_shaper sh = {0};
530 sparx5_lg_get_group_by_index(port->sparx5, layer, idx, &group);
532 return sparx5_shaper_conf_set(port, &sh, layer, idx, group);
535 int sparx5_tc_ets_add(struct sparx5_port *port,
536 struct tc_ets_qopt_offload_replace_params *params)
538 struct sparx5_dwrr dwrr = {0};
539 /* Minimum weight for each iteration */
540 unsigned int w_min = 100;
543 /* Find minimum weight for all dwrr bands */
544 for (i = 0; i < SPX5_PRIOS; i++) {
545 if (params->quanta[i] == 0)
547 w_min = min(w_min, params->weights[i]);
550 for (i = 0; i < SPX5_PRIOS; i++) {
551 /* Strict band; skip */
552 if (params->quanta[i] == 0)
557 /* On the sparx5, bands with higher indexes are preferred and
558 * arbitrated strict. Strict bands are put in the lower indexes,
559 * by tc, so we reverse the bands here.
561 * Also convert the weight to something the hardware
564 dwrr.cost[SPX5_PRIOS - i - 1] =
565 sparx5_weight_to_hw_cost(w_min, params->weights[i]);
568 return sparx5_dwrr_conf_set(port, &dwrr);
571 int sparx5_tc_ets_del(struct sparx5_port *port)
573 struct sparx5_dwrr dwrr = {0};
575 return sparx5_dwrr_conf_set(port, &dwrr);