1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2023 Intel Corporation */
4 #ifndef _ICE_ETHTOOL_H_
5 #define _ICE_ETHTOOL_H_
7 struct ice_phy_type_to_ethtool {
12 struct ice_serdes_equalization_to_ethtool {
13 int rx_equalization_pre2;
14 int rx_equalization_pre1;
15 int rx_equalization_post1;
16 int rx_equalization_bflf;
17 int rx_equalization_bfhf;
18 int rx_equalization_drate;
19 int tx_equalization_pre1;
20 int tx_equalization_pre3;
21 int tx_equalization_atten;
22 int tx_equalization_post1;
23 int tx_equalization_pre2;
26 struct ice_regdump_to_ethtool {
27 /* A multilane port can have max 4 serdes */
28 struct ice_serdes_equalization_to_ethtool equalization[4];
31 /* Port topology from lport i.e.
32 * serdes mapping, pcsquad, macport, cage etc...
34 struct ice_port_topology {
36 u16 primary_serdes_lane;
37 u16 serdes_lane_count;
41 /* Macro to make PHY type to Ethtool link mode table entry.
42 * The index is the PHY type.
44 #define ICE_PHY_TYPE(LINK_SPEED, ETHTOOL_LINK_MODE) {\
45 .aq_link_speed = ICE_AQ_LINK_SPEED_##LINK_SPEED, \
46 .link_mode = ETHTOOL_LINK_MODE_##ETHTOOL_LINK_MODE##_BIT, \
49 /* Lookup table mapping PHY type low to link speed and Ethtool link modes.
50 * Array index corresponds to HW PHY type bit, see
51 * ice_adminq_cmd.h:ICE_PHY_TYPE_LOW_*.
53 static const struct ice_phy_type_to_ethtool
54 phy_type_low_lkup[] = {
55 [0] = ICE_PHY_TYPE(100MB, 100baseT_Full),
56 [1] = ICE_PHY_TYPE(100MB, 100baseT_Full),
57 [2] = ICE_PHY_TYPE(1000MB, 1000baseT_Full),
58 [3] = ICE_PHY_TYPE(1000MB, 1000baseX_Full),
59 [4] = ICE_PHY_TYPE(1000MB, 1000baseX_Full),
60 [5] = ICE_PHY_TYPE(1000MB, 1000baseKX_Full),
61 [6] = ICE_PHY_TYPE(1000MB, 1000baseT_Full),
62 [7] = ICE_PHY_TYPE(2500MB, 2500baseT_Full),
63 [8] = ICE_PHY_TYPE(2500MB, 2500baseX_Full),
64 [9] = ICE_PHY_TYPE(2500MB, 2500baseX_Full),
65 [10] = ICE_PHY_TYPE(5GB, 5000baseT_Full),
66 [11] = ICE_PHY_TYPE(5GB, 5000baseT_Full),
67 [12] = ICE_PHY_TYPE(10GB, 10000baseT_Full),
68 [13] = ICE_PHY_TYPE(10GB, 10000baseCR_Full),
69 [14] = ICE_PHY_TYPE(10GB, 10000baseSR_Full),
70 [15] = ICE_PHY_TYPE(10GB, 10000baseLR_Full),
71 [16] = ICE_PHY_TYPE(10GB, 10000baseKR_Full),
72 [17] = ICE_PHY_TYPE(10GB, 10000baseCR_Full),
73 [18] = ICE_PHY_TYPE(10GB, 10000baseKR_Full),
74 [19] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
75 [20] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
76 [21] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
77 [22] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
78 [23] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
79 [24] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
80 [25] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
81 [26] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
82 [27] = ICE_PHY_TYPE(25GB, 25000baseKR_Full),
83 [28] = ICE_PHY_TYPE(25GB, 25000baseSR_Full),
84 [29] = ICE_PHY_TYPE(25GB, 25000baseCR_Full),
85 [30] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
86 [31] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
87 [32] = ICE_PHY_TYPE(40GB, 40000baseLR4_Full),
88 [33] = ICE_PHY_TYPE(40GB, 40000baseKR4_Full),
89 [34] = ICE_PHY_TYPE(40GB, 40000baseSR4_Full),
90 [35] = ICE_PHY_TYPE(40GB, 40000baseCR4_Full),
91 [36] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
92 [37] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
93 [38] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
94 [39] = ICE_PHY_TYPE(50GB, 50000baseKR2_Full),
95 [40] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
96 [41] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
97 [42] = ICE_PHY_TYPE(50GB, 50000baseSR2_Full),
98 [43] = ICE_PHY_TYPE(50GB, 50000baseCR2_Full),
99 [44] = ICE_PHY_TYPE(50GB, 50000baseCR_Full),
100 [45] = ICE_PHY_TYPE(50GB, 50000baseSR_Full),
101 [46] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full),
102 [47] = ICE_PHY_TYPE(50GB, 50000baseLR_ER_FR_Full),
103 [48] = ICE_PHY_TYPE(50GB, 50000baseKR_Full),
104 [49] = ICE_PHY_TYPE(50GB, 50000baseSR_Full),
105 [50] = ICE_PHY_TYPE(50GB, 50000baseCR_Full),
106 [51] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
107 [52] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full),
108 [53] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full),
109 [54] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full),
110 [55] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
111 [56] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
112 [57] = ICE_PHY_TYPE(100GB, 100000baseSR4_Full),
113 [58] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
114 [59] = ICE_PHY_TYPE(100GB, 100000baseCR4_Full),
115 [60] = ICE_PHY_TYPE(100GB, 100000baseKR4_Full),
116 [61] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
117 [62] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
118 [63] = ICE_PHY_TYPE(100GB, 100000baseLR4_ER4_Full),
121 /* Lookup table mapping PHY type high to link speed and Ethtool link modes.
122 * Array index corresponds to HW PHY type bit, see
123 * ice_adminq_cmd.h:ICE_PHY_TYPE_HIGH_*
125 static const struct ice_phy_type_to_ethtool
126 phy_type_high_lkup[] = {
127 [0] = ICE_PHY_TYPE(100GB, 100000baseKR2_Full),
128 [1] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
129 [2] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
130 [3] = ICE_PHY_TYPE(100GB, 100000baseSR2_Full),
131 [4] = ICE_PHY_TYPE(100GB, 100000baseCR2_Full),
132 [5] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
133 [6] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
134 [7] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
135 [8] = ICE_PHY_TYPE(200GB, 200000baseLR4_ER4_FR4_Full),
136 [9] = ICE_PHY_TYPE(200GB, 200000baseDR4_Full),
137 [10] = ICE_PHY_TYPE(200GB, 200000baseKR4_Full),
138 [11] = ICE_PHY_TYPE(200GB, 200000baseSR4_Full),
139 [12] = ICE_PHY_TYPE(200GB, 200000baseCR4_Full),
142 #endif /* !_ICE_ETHTOOL_H_ */