drivers/iio/adc/stm32-dfsdm-adc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file is the ADC part of the STM32 DFSDM driver
   4  *
   5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6  * Author: Arnaud Pouliquen <[email protected]>.
   7  */
   8
   9 #include <linux/dmaengine.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
  12 #include <linux/iio/backend.h>
  13 #include <linux/iio/buffer.h>
  14 #include <linux/iio/hw-consumer.h>
  15 #include <linux/iio/sysfs.h>
  16 #include <linux/iio/timer/stm32-lptim-trigger.h>
  17 #include <linux/iio/timer/stm32-timer-trigger.h>
  18 #include <linux/iio/trigger.h>
  19 #include <linux/iio/trigger_consumer.h>
  20 #include <linux/iio/triggered_buffer.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regmap.h>
  27 #include <linux/slab.h>
  28
  29 #include "stm32-dfsdm.h"
  30
  31 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
  32
  33 /* Conversion timeout */
  34 #define DFSDM_TIMEOUT_US 100000
  35 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
  36
  37 /* Oversampling attribute default */
  38 #define DFSDM_DEFAULT_OVERSAMPLING  100
  39
  40 /* Oversampling max values */
  41 #define DFSDM_MAX_INT_OVERSAMPLING 256
  42 #define DFSDM_MAX_FL_OVERSAMPLING 1024
  43
  44 /* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
  45 #define DFSDM_DATA_MAX BIT(30)
  46 /*
  47  * Data are output as two's complement data in a 24 bit field.
  48  * Data from filters are in the range +/-2^(n-1)
  49  * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
  50  * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
  51  * So, the resolution of samples from filter is actually limited to 23 bits
  52  */
  53 #define DFSDM_DATA_RES 24
  54
  55 /* Filter configuration */
  56 #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
  57                             DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
  58                             DFSDM_CR1_JSCAN_MASK)
  59
  60 enum sd_converter_type {
  61         DFSDM_AUDIO,
  62         DFSDM_IIO,
  63 };
  64
  65 struct stm32_dfsdm_dev_data {
  66         int type;
  67         int (*init)(struct device *dev, struct iio_dev *indio_dev);
  68         unsigned int num_channels;
  69         const struct regmap_config *regmap_cfg;
  70 };
  71
  72 struct stm32_dfsdm_adc {
  73         struct stm32_dfsdm *dfsdm;
  74         const struct stm32_dfsdm_dev_data *dev_data;
  75         unsigned int fl_id;
  76         unsigned int nconv;
  77         unsigned long smask;
  78
  79         /* ADC specific */
  80         unsigned int oversamp;
  81         struct iio_hw_consumer *hwc;
  82         struct iio_backend **backend;
  83         struct completion completion;
  84         u32 *buffer;
  85
  86         /* Audio specific */
  87         unsigned int spi_freq;  /* SPI bus clock frequency */
  88         unsigned int sample_freq; /* Sample frequency after filter decimation */
  89         int (*cb)(const void *data, size_t size, void *cb_priv);
  90         void *cb_priv;
  91
  92         /* DMA */
  93         u8 *rx_buf;
  94         unsigned int bufi; /* Buffer current position */
  95         unsigned int buf_sz; /* Buffer size */
  96         struct dma_chan *dma_chan;
  97         dma_addr_t dma_buf;
  98 };
  99
 100 struct stm32_dfsdm_str2field {
 101         const char      *name;
 102         unsigned int    val;
 103 };
 104
 105 /* DFSDM channel serial interface type */
 106 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
 107         { "SPI_R", 0 }, /* SPI with data on rising edge */
 108         { "SPI_F", 1 }, /* SPI with data on falling edge */
 109         { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
 110         { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
 111         {},
 112 };
 113
 114 /* DFSDM channel clock source */
 115 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
 116         /* External SPI clock (CLKIN x) */
 117         { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
 118         /* Internal SPI clock (CLKOUT) */
 119         { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
 120         /* Internal SPI clock divided by 2 (falling edge) */
 121         { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
 122         /* Internal SPI clock divided by 2 (falling edge) */
 123         { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
 124         {},
 125 };
 126
 127 static int stm32_dfsdm_str2val(const char *str,
 128                                const struct stm32_dfsdm_str2field *list)
 129 {
 130         const struct stm32_dfsdm_str2field *p = list;
 131
 132         for (p = list; p && p->name; p++)
 133                 if (!strcmp(p->name, str))
 134                         return p->val;
 135
 136         return -EINVAL;
 137 }
 138
 139 /**
 140  * struct stm32_dfsdm_trig_info - DFSDM trigger info
 141  * @name:               name of the trigger, corresponding to its source
 142  * @jextsel:            trigger signal selection
 143  */
 144 struct stm32_dfsdm_trig_info {
 145         const char *name;
 146         unsigned int jextsel;
 147 };
 148
 149 /* hardware injected trigger enable, edge selection */
 150 enum stm32_dfsdm_jexten {
 151         STM32_DFSDM_JEXTEN_DISABLED,
 152         STM32_DFSDM_JEXTEN_RISING_EDGE,
 153         STM32_DFSDM_JEXTEN_FALLING_EDGE,
 154         STM32_DFSDM_EXTEN_BOTH_EDGES,
 155 };
 156
 157 static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
 158         { TIM1_TRGO, 0 },
 159         { TIM1_TRGO2, 1 },
 160         { TIM8_TRGO, 2 },
 161         { TIM8_TRGO2, 3 },
 162         { TIM3_TRGO, 4 },
 163         { TIM4_TRGO, 5 },
 164         { TIM16_OC1, 6 },
 165         { TIM6_TRGO, 7 },
 166         { TIM7_TRGO, 8 },
 167         { LPTIM1_OUT, 26 },
 168         { LPTIM2_OUT, 27 },
 169         { LPTIM3_OUT, 28 },
 170         {},
 171 };
 172
 173 static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
 174                                    struct iio_trigger *trig)
 175 {
 176         int i;
 177
 178         /* lookup triggers registered by stm32 timer trigger driver */
 179         for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
 180                 /**
 181                  * Checking both stm32 timer trigger type and trig name
 182                  * should be safe against arbitrary trigger names.
 183                  */
 184                 if ((is_stm32_timer_trigger(trig) ||
 185                      is_stm32_lptim_trigger(trig)) &&
 186                     !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
 187                         return stm32_dfsdm_trigs[i].jextsel;
 188                 }
 189         }
 190
 191         return -EINVAL;
 192 }
 193
 194 static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
 195                                     unsigned int fast, unsigned int oversamp)
 196 {
 197         unsigned int i, d, fosr, iosr;
 198         u64 res, max;
 199         int bits, shift;
 200         unsigned int m = 1;     /* multiplication factor */
 201         unsigned int p = fl->ford;      /* filter order (ford) */
 202         struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
 203
 204         pr_debug("Requested oversampling: %d\n", oversamp);
 205         /*
 206          * This function tries to compute filter oversampling and integrator
 207          * oversampling, base on oversampling ratio requested by user.
 208          *
 209          * Decimation d depends on the filter order and the oversampling ratios.
 210          * ford: filter order
 211          * fosr: filter over sampling ratio
 212          * iosr: integrator over sampling ratio
 213          */
 214         if (fl->ford == DFSDM_FASTSINC_ORDER) {
 215                 m = 2;
 216                 p = 2;
 217         }
 218
 219         /*
 220          * Look for filter and integrator oversampling ratios which allows
 221          * to maximize data output resolution.
 222          */
 223         for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
 224                 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
 225                         if (fast)
 226                                 d = fosr * iosr;
 227                         else if (fl->ford == DFSDM_FASTSINC_ORDER)
 228                                 d = fosr * (iosr + 3) + 2;
 229                         else
 230                                 d = fosr * (iosr - 1 + p) + p;
 231
 232                         if (d > oversamp)
 233                                 break;
 234                         else if (d != oversamp)
 235                                 continue;
 236                         /*
 237                          * Check resolution (limited to signed 32 bits)
 238                          *   res <= 2^31
 239                          * Sincx filters:
 240                          *   res = m * fosr^p x iosr (with m=1, p=ford)
 241                          * FastSinc filter
 242                          *   res = m * fosr^p x iosr (with m=2, p=2)
 243                          */
 244                         res = fosr;
 245                         for (i = p - 1; i > 0; i--) {
 246                                 res = res * (u64)fosr;
 247                                 if (res > DFSDM_DATA_MAX)
 248                                         break;
 249                         }
 250                         if (res > DFSDM_DATA_MAX)
 251                                 continue;
 252
 253                         res = res * (u64)m * (u64)iosr;
 254                         if (res > DFSDM_DATA_MAX)
 255                                 continue;
 256
 257                         if (res >= flo->res) {
 258                                 flo->res = res;
 259                                 flo->fosr = fosr;
 260                                 flo->iosr = iosr;
 261
 262                                 bits = fls(flo->res);
 263                                 /* 8 LBSs in data register contain chan info */
 264                                 max = flo->res << 8;
 265
 266                                 /* if resolution is not a power of two */
 267                                 if (flo->res > BIT(bits - 1))
 268                                         bits++;
 269                                 else
 270                                         max--;
 271
 272                                 shift = DFSDM_DATA_RES - bits;
 273                                 /*
 274                                  * Compute right/left shift
 275                                  * Right shift is performed by hardware
 276                                  * when transferring samples to data register.
 277                                  * Left shift is done by software on buffer
 278                                  */
 279                                 if (shift > 0) {
 280                                         /* Resolution is lower than 24 bits */
 281                                         flo->rshift = 0;
 282                                         flo->lshift = shift;
 283                                 } else {
 284                                         /*
 285                                          * If resolution is 24 bits or more,
 286                                          * max positive value may be ambiguous
 287                                          * (equal to max negative value as sign
 288                                          * bit is dropped).
 289                                          * Reduce resolution to 23 bits (rshift)
 290                                          * to keep the sign on bit 23 and treat
 291                                          * saturation before rescaling on 24
 292                                          * bits (lshift).
 293                                          */
 294                                         flo->rshift = 1 - shift;
 295                                         flo->lshift = 1;
 296                                         max >>= flo->rshift;
 297                                 }
 298                                 flo->max = (s32)max;
 299                                 flo->bits = bits;
 300
 301                                 pr_debug("fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
 302                                          fast, flo->fosr, flo->iosr,
 303                                          flo->res, bits, flo->rshift,
 304                                          flo->lshift);
 305                         }
 306                 }
 307         }
 308
 309         if (!flo->res)
 310                 return -EINVAL;
 311
 312         return 0;
 313 }
 314
 315 static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
 316                                         unsigned int oversamp)
 317 {
 318         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 319         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
 320         int ret0, ret1;
 321
 322         memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
 323         memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
 324
 325         ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
 326         ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
 327         if (ret0 < 0 && ret1 < 0) {
 328                 dev_err(&indio_dev->dev,
 329                         "Filter parameters not found: errors %d/%d\n",
 330                         ret0, ret1);
 331                 return -EINVAL;
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int stm32_dfsdm_start_channel(struct iio_dev *indio_dev)
 338 {
 339         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 340         struct regmap *regmap = adc->dfsdm->regmap;
 341         const struct iio_chan_spec *chan;
 342         unsigned int bit;
 343         int ret;
 344
 345         for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
 346                 chan = indio_dev->channels + bit;
 347                 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
 348                                          DFSDM_CHCFGR1_CHEN_MASK,
 349                                          DFSDM_CHCFGR1_CHEN(1));
 350                 if (ret < 0)
 351                         return ret;
 352         }
 353
 354         return 0;
 355 }
 356
 357 static void stm32_dfsdm_stop_channel(struct iio_dev *indio_dev)
 358 {
 359         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 360         struct regmap *regmap = adc->dfsdm->regmap;
 361         const struct iio_chan_spec *chan;
 362         unsigned int bit;
 363
 364         for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
 365                 chan = indio_dev->channels + bit;
 366                 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
 367                                    DFSDM_CHCFGR1_CHEN_MASK,
 368                                    DFSDM_CHCFGR1_CHEN(0));
 369         }
 370 }
 371
 372 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
 373                                       struct stm32_dfsdm_channel *ch)
 374 {
 375         unsigned int id = ch->id;
 376         struct regmap *regmap = dfsdm->regmap;
 377         int ret;
 378
 379         ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 380                                  DFSDM_CHCFGR1_SITP_MASK,
 381                                  DFSDM_CHCFGR1_SITP(ch->type));
 382         if (ret < 0)
 383                 return ret;
 384         ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 385                                  DFSDM_CHCFGR1_SPICKSEL_MASK,
 386                                  DFSDM_CHCFGR1_SPICKSEL(ch->src));
 387         if (ret < 0)
 388                 return ret;
 389         return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 390                                   DFSDM_CHCFGR1_CHINSEL_MASK,
 391                                   DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
 392 }
 393
 394 static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
 395                                     unsigned int fl_id,
 396                                     struct iio_trigger *trig)
 397 {
 398         struct stm32_dfsdm *dfsdm = adc->dfsdm;
 399         int ret;
 400
 401         /* Enable filter */
 402         ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 403                                  DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
 404         if (ret < 0)
 405                 return ret;
 406
 407         /* Nothing more to do for injected (scan mode/triggered) conversions */
 408         if (adc->nconv > 1 || trig)
 409                 return 0;
 410
 411         /* Software start (single or continuous) regular conversion */
 412         return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 413                                   DFSDM_CR1_RSWSTART_MASK,
 414                                   DFSDM_CR1_RSWSTART(1));
 415 }
 416
 417 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
 418                                     unsigned int fl_id)
 419 {
 420         /* Disable conversion */
 421         regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 422                            DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
 423 }
 424
 425 static int stm32_dfsdm_filter_set_trig(struct iio_dev *indio_dev,
 426                                        unsigned int fl_id,
 427                                        struct iio_trigger *trig)
 428 {
 429         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 430         struct regmap *regmap = adc->dfsdm->regmap;
 431         u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
 432         int ret;
 433
 434         if (trig) {
 435                 ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
 436                 if (ret < 0)
 437                         return ret;
 438
 439                 /* set trigger source and polarity (default to rising edge) */
 440                 jextsel = ret;
 441                 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
 442         }
 443
 444         ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
 445                                  DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
 446                                  DFSDM_CR1_JEXTSEL(jextsel) |
 447                                  DFSDM_CR1_JEXTEN(jexten));
 448         if (ret < 0)
 449                 return ret;
 450
 451         return 0;
 452 }
 453
 454 static int stm32_dfsdm_channels_configure(struct iio_dev *indio_dev,
 455                                           unsigned int fl_id,
 456                                           struct iio_trigger *trig)
 457 {
 458         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 459         struct regmap *regmap = adc->dfsdm->regmap;
 460         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
 461         struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
 462         const struct iio_chan_spec *chan;
 463         unsigned int bit;
 464         int ret;
 465
 466         fl->fast = 0;
 467
 468         /*
 469          * In continuous mode, use fast mode configuration,
 470          * if it provides a better resolution.
 471          */
 472         if (adc->nconv == 1 && !trig && iio_buffer_enabled(indio_dev)) {
 473                 if (fl->flo[1].res >= fl->flo[0].res) {
 474                         fl->fast = 1;
 475                         flo = &fl->flo[1];
 476                 }
 477         }
 478
 479         if (!flo->res)
 480                 return -EINVAL;
 481
 482         dev_dbg(&indio_dev->dev, "Samples actual resolution: %d bits",
 483                 min(flo->bits, (u32)DFSDM_DATA_RES - 1));
 484
 485         for_each_set_bit(bit, &adc->smask,
 486                          sizeof(adc->smask) * BITS_PER_BYTE) {
 487                 chan = indio_dev->channels + bit;
 488
 489                 ret = regmap_update_bits(regmap,
 490                                          DFSDM_CHCFGR2(chan->channel),
 491                                          DFSDM_CHCFGR2_DTRBS_MASK,
 492                                          DFSDM_CHCFGR2_DTRBS(flo->rshift));
 493                 if (ret)
 494                         return ret;
 495         }
 496
 497         return 0;
 498 }
 499
 500 static int stm32_dfsdm_filter_configure(struct iio_dev *indio_dev,
 501                                         unsigned int fl_id,
 502                                         struct iio_trigger *trig)
 503 {
 504         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 505         struct regmap *regmap = adc->dfsdm->regmap;
 506         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
 507         struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
 508         u32 cr1;
 509         const struct iio_chan_spec *chan;
 510         unsigned int bit, jchg = 0;
 511         int ret;
 512
 513         /* Average integrator oversampling */
 514         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
 515                                  DFSDM_FCR_IOSR(flo->iosr - 1));
 516         if (ret)
 517                 return ret;
 518
 519         /* Filter order and Oversampling */
 520         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
 521                                  DFSDM_FCR_FOSR(flo->fosr - 1));
 522         if (ret)
 523                 return ret;
 524
 525         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
 526                                  DFSDM_FCR_FORD(fl->ford));
 527         if (ret)
 528                 return ret;
 529
 530         ret = stm32_dfsdm_filter_set_trig(indio_dev, fl_id, trig);
 531         if (ret)
 532                 return ret;
 533
 534         ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
 535                                  DFSDM_CR1_FAST_MASK,
 536                                  DFSDM_CR1_FAST(fl->fast));
 537         if (ret)
 538                 return ret;
 539
 540         /*
 541          * DFSDM modes configuration W.R.T audio/iio type modes
 542          * ----------------------------------------------------------------
 543          * Modes         | regular |  regular     | injected | injected   |
 544          *               |         |  continuous  |          | + scan     |
 545          * --------------|---------|--------------|----------|------------|
 546          * single conv   |    x    |              |          |            |
 547          * (1 chan)      |         |              |          |            |
 548          * --------------|---------|--------------|----------|------------|
 549          * 1 Audio chan  |         | sample freq  |          |            |
 550          *               |         | or sync_mode |          |            |
 551          * --------------|---------|--------------|----------|------------|
 552          * 1 IIO chan    |         | sample freq  | trigger  |            |
 553          *               |         | or sync_mode |          |            |
 554          * --------------|---------|--------------|----------|------------|
 555          * 2+ IIO chans  |         |              |          | trigger or |
 556          *               |         |              |          | sync_mode  |
 557          * ----------------------------------------------------------------
 558          */
 559         if (adc->nconv == 1 && !trig) {
 560                 bit = __ffs(adc->smask);
 561                 chan = indio_dev->channels + bit;
 562
 563                 /* Use regular conversion for single channel without trigger */
 564                 cr1 = DFSDM_CR1_RCH(chan->channel);
 565
 566                 /* Continuous conversions triggered by SPI clk in buffer mode */
 567                 if (iio_buffer_enabled(indio_dev))
 568                         cr1 |= DFSDM_CR1_RCONT(1);
 569
 570                 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
 571         } else {
 572                 /* Use injected conversion for multiple channels */
 573                 for_each_set_bit(bit, &adc->smask,
 574                                  sizeof(adc->smask) * BITS_PER_BYTE) {
 575                         chan = indio_dev->channels + bit;
 576                         jchg |= BIT(chan->channel);
 577                 }
 578                 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
 579                 if (ret < 0)
 580                         return ret;
 581
 582                 /* Use scan mode for multiple channels */
 583                 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
 584
 585                 /*
 586                  * Continuous conversions not supported in injected mode,
 587                  * either use:
 588                  * - conversions in sync with filter 0
 589                  * - triggered conversions
 590                  */
 591                 if (!fl->sync_mode && !trig)
 592                         return -EINVAL;
 593                 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
 594         }
 595
 596         return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
 597                                   cr1);
 598 }
 599
 600 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
 601                                         struct iio_dev *indio_dev,
 602                                         struct iio_chan_spec *ch)
 603 {
 604         struct stm32_dfsdm_channel *df_ch;
 605         const char *of_str;
 606         int chan_idx = ch->scan_index;
 607         int ret, val;
 608
 609         ret = of_property_read_u32_index(indio_dev->dev.of_node,
 610                                          "st,adc-channels", chan_idx,
 611                                          &ch->channel);
 612         if (ret < 0) {
 613                 dev_err(&indio_dev->dev,
 614                         " Error parsing 'st,adc-channels' for idx %d\n",
 615                         chan_idx);
 616                 return ret;
 617         }
 618         if (ch->channel >= dfsdm->num_chs) {
 619                 dev_err(&indio_dev->dev,
 620                         " Error bad channel number %d (max = %d)\n",
 621                         ch->channel, dfsdm->num_chs);
 622                 return -EINVAL;
 623         }
 624
 625         ret = of_property_read_string_index(indio_dev->dev.of_node,
 626                                             "st,adc-channel-names", chan_idx,
 627                                             &ch->datasheet_name);
 628         if (ret < 0) {
 629                 dev_err(&indio_dev->dev,
 630                         " Error parsing 'st,adc-channel-names' for idx %d\n",
 631                         chan_idx);
 632                 return ret;
 633         }
 634
 635         df_ch =  &dfsdm->ch_list[ch->channel];
 636         df_ch->id = ch->channel;
 637
 638         ret = of_property_read_string_index(indio_dev->dev.of_node,
 639                                             "st,adc-channel-types", chan_idx,
 640                                             &of_str);
 641         if (!ret) {
 642                 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
 643                 if (val < 0)
 644                         return val;
 645         } else {
 646                 val = 0;
 647         }
 648         df_ch->type = val;
 649
 650         ret = of_property_read_string_index(indio_dev->dev.of_node,
 651                                             "st,adc-channel-clk-src", chan_idx,
 652                                             &of_str);
 653         if (!ret) {
 654                 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
 655                 if (val < 0)
 656                         return val;
 657         } else {
 658                 val = 0;
 659         }
 660         df_ch->src = val;
 661
 662         ret = of_property_read_u32_index(indio_dev->dev.of_node,
 663                                          "st,adc-alt-channel", chan_idx,
 664                                          &df_ch->alt_si);
 665         if (ret < 0)
 666                 df_ch->alt_si = 0;
 667
 668         return 0;
 669 }
 670
 671 static int stm32_dfsdm_generic_channel_parse_of(struct stm32_dfsdm *dfsdm,
 672                                                 struct iio_dev *indio_dev,
 673                                                 struct iio_chan_spec *ch,
 674                                                 struct fwnode_handle *node)
 675 {
 676         struct stm32_dfsdm_channel *df_ch;
 677         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 678         struct iio_backend *backend;
 679         const char *of_str;
 680         int ret, val;
 681
 682         ret = fwnode_property_read_u32(node, "reg", &ch->channel);
 683         if (ret < 0) {
 684                 dev_err(&indio_dev->dev, "Missing channel index %d\n", ret);
 685                 return ret;
 686         }
 687
 688         if (ch->channel >= dfsdm->num_chs) {
 689                 dev_err(&indio_dev->dev, " Error bad channel number %d (max = %d)\n",
 690                         ch->channel, dfsdm->num_chs);
 691                 return -EINVAL;
 692         }
 693
 694         ret = fwnode_property_read_string(node, "label", &ch->datasheet_name);
 695         if (ret < 0) {
 696                 dev_err(&indio_dev->dev,
 697                         " Error parsing 'label' for idx %d\n", ch->channel);
 698                 return ret;
 699         }
 700
 701         df_ch =  &dfsdm->ch_list[ch->channel];
 702         df_ch->id = ch->channel;
 703
 704         ret = fwnode_property_read_string(node, "st,adc-channel-type", &of_str);
 705         if (!ret) {
 706                 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
 707                 if (val < 0)
 708                         return val;
 709         } else {
 710                 val = 0;
 711         }
 712         df_ch->type = val;
 713
 714         ret = fwnode_property_read_string(node, "st,adc-channel-clk-src", &of_str);
 715         if (!ret) {
 716                 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
 717                 if (val < 0)
 718                         return val;
 719         } else {
 720                 val = 0;
 721         }
 722         df_ch->src = val;
 723
 724         ret = fwnode_property_read_u32(node, "st,adc-alt-channel", &df_ch->alt_si);
 725         if (ret != -EINVAL)
 726                 df_ch->alt_si = 0;
 727
 728         if (adc->dev_data->type == DFSDM_IIO) {
 729                 backend = devm_iio_backend_fwnode_get(&indio_dev->dev, NULL, node);
 730                 if (IS_ERR(backend))
 731                         return dev_err_probe(&indio_dev->dev, PTR_ERR(backend),
 732                                              "Failed to get backend\n");
 733                 adc->backend[ch->scan_index] = backend;
 734         }
 735
 736         return 0;
 737 }
 738
 739 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
 740                                           uintptr_t priv,
 741                                           const struct iio_chan_spec *chan,
 742                                           char *buf)
 743 {
 744         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 745
 746         return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
 747 }
 748
 749 static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
 750                                    unsigned int sample_freq,
 751                                    unsigned int spi_freq)
 752 {
 753         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 754         unsigned int oversamp;
 755         int ret;
 756
 757         oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
 758         if (spi_freq % sample_freq)
 759                 dev_dbg(&indio_dev->dev,
 760                         "Rate not accurate. requested (%u), actual (%u)\n",
 761                         sample_freq, spi_freq / oversamp);
 762
 763         ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
 764         if (ret < 0)
 765                 return ret;
 766
 767         adc->sample_freq = spi_freq / oversamp;
 768         adc->oversamp = oversamp;
 769
 770         return 0;
 771 }
 772
 773 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
 774                                           uintptr_t priv,
 775                                           const struct iio_chan_spec *chan,
 776                                           const char *buf, size_t len)
 777 {
 778         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 779         struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
 780         unsigned int sample_freq = adc->sample_freq;
 781         unsigned int spi_freq;
 782         int ret;
 783
 784         dev_err(&indio_dev->dev, "enter %s\n", __func__);
 785         /* If DFSDM is master on SPI, SPI freq can not be updated */
 786         if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
 787                 return -EPERM;
 788
 789         ret = kstrtoint(buf, 0, &spi_freq);
 790         if (ret)
 791                 return ret;
 792
 793         if (!spi_freq)
 794                 return -EINVAL;
 795
 796         if (sample_freq) {
 797                 ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
 798                 if (ret < 0)
 799                         return ret;
 800         }
 801         adc->spi_freq = spi_freq;
 802
 803         return len;
 804 }
 805
 806 static int stm32_dfsdm_start_conv(struct iio_dev *indio_dev,
 807                                   struct iio_trigger *trig)
 808 {
 809         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 810         struct regmap *regmap = adc->dfsdm->regmap;
 811         int ret;
 812
 813         ret = stm32_dfsdm_channels_configure(indio_dev, adc->fl_id, trig);
 814         if (ret < 0)
 815                 return ret;
 816
 817         ret = stm32_dfsdm_start_channel(indio_dev);
 818         if (ret < 0)
 819                 return ret;
 820
 821         ret = stm32_dfsdm_filter_configure(indio_dev, adc->fl_id, trig);
 822         if (ret < 0)
 823                 goto stop_channels;
 824
 825         ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
 826         if (ret < 0)
 827                 goto filter_unconfigure;
 828
 829         return 0;
 830
 831 filter_unconfigure:
 832         regmap_clear_bits(regmap, DFSDM_CR1(adc->fl_id), DFSDM_CR1_CFG_MASK);
 833 stop_channels:
 834         stm32_dfsdm_stop_channel(indio_dev);
 835
 836         return ret;
 837 }
 838
 839 static void stm32_dfsdm_stop_conv(struct iio_dev *indio_dev)
 840 {
 841         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 842         struct regmap *regmap = adc->dfsdm->regmap;
 843
 844         stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
 845
 846         regmap_clear_bits(regmap, DFSDM_CR1(adc->fl_id), DFSDM_CR1_CFG_MASK);
 847
 848         stm32_dfsdm_stop_channel(indio_dev);
 849 }
 850
 851 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
 852                                      unsigned int val)
 853 {
 854         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 855         unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
 856         unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
 857
 858         /*
 859          * DMA cyclic transfers are used, buffer is split into two periods.
 860          * There should be :
 861          * - always one buffer (period) DMA is working on
 862          * - one buffer (period) driver pushed to ASoC side.
 863          */
 864         watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
 865         adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
 866
 867         return 0;
 868 }
 869
 870 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
 871 {
 872         struct dma_tx_state state;
 873         enum dma_status status;
 874
 875         status = dmaengine_tx_status(adc->dma_chan,
 876                                      adc->dma_chan->cookie,
 877                                      &state);
 878         if (status == DMA_IN_PROGRESS) {
 879                 /* Residue is size in bytes from end of buffer */
 880                 unsigned int i = adc->buf_sz - state.residue;
 881                 unsigned int size;
 882
 883                 /* Return available bytes */
 884                 if (i >= adc->bufi)
 885                         size = i - adc->bufi;
 886                 else
 887                         size = adc->buf_sz + i - adc->bufi;
 888
 889                 return size;
 890         }
 891
 892         return 0;
 893 }
 894
 895 static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
 896                                             s32 *buffer)
 897 {
 898         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
 899         struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
 900         unsigned int i = adc->nconv;
 901         s32 *ptr = buffer;
 902
 903         while (i--) {
 904                 /* Mask 8 LSB that contains the channel ID */
 905                 *ptr &= 0xFFFFFF00;
 906                 /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
 907                 if (*ptr > flo->max)
 908                         *ptr -= 1;
 909                 /*
 910                  * Samples from filter are retrieved with 23 bits resolution
 911                  * or less. Shift left to align MSB on 24 bits.
 912                  */
 913                 *ptr <<= flo->lshift;
 914
 915                 ptr++;
 916         }
 917 }
 918
 919 static void stm32_dfsdm_dma_buffer_done(void *data)
 920 {
 921         struct iio_dev *indio_dev = data;
 922         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 923         int available = stm32_dfsdm_adc_dma_residue(adc);
 924         size_t old_pos;
 925
 926         /*
 927          * FIXME: In Kernel interface does not support cyclic DMA buffer,and
 928          * offers only an interface to push data samples per samples.
 929          * For this reason IIO buffer interface is not used and interface is
 930          * bypassed using a private callback registered by ASoC.
 931          * This should be a temporary solution waiting a cyclic DMA engine
 932          * support in IIO.
 933          */
 934
 935         dev_dbg(&indio_dev->dev, "pos = %d, available = %d\n",
 936                 adc->bufi, available);
 937         old_pos = adc->bufi;
 938
 939         while (available >= indio_dev->scan_bytes) {
 940                 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
 941
 942                 stm32_dfsdm_process_data(adc, buffer);
 943
 944                 available -= indio_dev->scan_bytes;
 945                 adc->bufi += indio_dev->scan_bytes;
 946                 if (adc->bufi >= adc->buf_sz) {
 947                         if (adc->cb)
 948                                 adc->cb(&adc->rx_buf[old_pos],
 949                                          adc->buf_sz - old_pos, adc->cb_priv);
 950                         adc->bufi = 0;
 951                         old_pos = 0;
 952                 }
 953                 /*
 954                  * In DMA mode the trigger services of IIO are not used
 955                  * (e.g. no call to iio_trigger_poll).
 956                  * Calling irq handler associated to the hardware trigger is not
 957                  * relevant as the conversions have already been done. Data
 958                  * transfers are performed directly in DMA callback instead.
 959                  * This implementation avoids to call trigger irq handler that
 960                  * may sleep, in an atomic context (DMA irq handler context).
 961                  */
 962                 if (adc->dev_data->type == DFSDM_IIO)
 963                         iio_push_to_buffers(indio_dev, buffer);
 964         }
 965         if (adc->cb)
 966                 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
 967                         adc->cb_priv);
 968 }
 969
 970 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
 971 {
 972         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 973         /*
 974          * The DFSDM supports half-word transfers. However, for 16 bits record,
 975          * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
 976          * shift is required.
 977          */
 978         struct dma_slave_config config = {
 979                 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
 980                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 981         };
 982         struct dma_async_tx_descriptor *desc;
 983         dma_cookie_t cookie;
 984         int ret;
 985
 986         if (!adc->dma_chan)
 987                 return -EINVAL;
 988
 989         dev_dbg(&indio_dev->dev, "size=%d watermark=%d\n",
 990                 adc->buf_sz, adc->buf_sz / 2);
 991
 992         if (adc->nconv == 1 && !indio_dev->trig)
 993                 config.src_addr += DFSDM_RDATAR(adc->fl_id);
 994         else
 995                 config.src_addr += DFSDM_JDATAR(adc->fl_id);
 996         ret = dmaengine_slave_config(adc->dma_chan, &config);
 997         if (ret)
 998                 return ret;
 999
1000         /* Prepare a DMA cyclic transaction */
1001         desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1002                                          adc->dma_buf,
1003                                          adc->buf_sz, adc->buf_sz / 2,
1004                                          DMA_DEV_TO_MEM,
1005                                          DMA_PREP_INTERRUPT);
1006         if (!desc)
1007                 return -EBUSY;
1008
1009         desc->callback = stm32_dfsdm_dma_buffer_done;
1010         desc->callback_param = indio_dev;
1011
1012         cookie = dmaengine_submit(desc);
1013         ret = dma_submit_error(cookie);
1014         if (ret)
1015                 goto err_stop_dma;
1016
1017         /* Issue pending DMA requests */
1018         dma_async_issue_pending(adc->dma_chan);
1019
1020         if (adc->nconv == 1 && !indio_dev->trig) {
1021                 /* Enable regular DMA transfer*/
1022                 ret = regmap_set_bits(adc->dfsdm->regmap,
1023                                       DFSDM_CR1(adc->fl_id),
1024                                       DFSDM_CR1_RDMAEN_MASK);
1025         } else {
1026                 /* Enable injected DMA transfer*/
1027                 ret = regmap_set_bits(adc->dfsdm->regmap,
1028                                       DFSDM_CR1(adc->fl_id),
1029                                       DFSDM_CR1_JDMAEN_MASK);
1030         }
1031
1032         if (ret < 0)
1033                 goto err_stop_dma;
1034
1035         return 0;
1036
1037 err_stop_dma:
1038         dmaengine_terminate_all(adc->dma_chan);
1039
1040         return ret;
1041 }
1042
1043 static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
1044 {
1045         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1046
1047         if (!adc->dma_chan)
1048                 return;
1049
1050         regmap_clear_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
1051                           DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK);
1052         dmaengine_terminate_all(adc->dma_chan);
1053 }
1054
1055 static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
1056                                         const unsigned long *scan_mask)
1057 {
1058         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1059
1060         adc->nconv = bitmap_weight(scan_mask, iio_get_masklength(indio_dev));
1061         adc->smask = *scan_mask;
1062
1063         dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
1064
1065         return 0;
1066 }
1067
1068 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1069 {
1070         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1071         int i = 0;
1072         int ret;
1073
1074         /* Reset adc buffer index */
1075         adc->bufi = 0;
1076
1077         if (adc->hwc) {
1078                 ret = iio_hw_consumer_enable(adc->hwc);
1079                 if (ret < 0)
1080                         return ret;
1081         }
1082
1083         if (adc->backend) {
1084                 while (adc->backend[i]) {
1085                         ret = iio_backend_enable(adc->backend[i]);
1086                         if (ret < 0)
1087                                 return ret;
1088                         i++;
1089                 }
1090         }
1091
1092         ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1093         if (ret < 0)
1094                 goto err_stop_hwc;
1095
1096         ret = stm32_dfsdm_adc_dma_start(indio_dev);
1097         if (ret) {
1098                 dev_err(&indio_dev->dev, "Can't start DMA\n");
1099                 goto stop_dfsdm;
1100         }
1101
1102         ret = stm32_dfsdm_start_conv(indio_dev, indio_dev->trig);
1103         if (ret) {
1104                 dev_err(&indio_dev->dev, "Can't start conversion\n");
1105                 goto err_stop_dma;
1106         }
1107
1108         return 0;
1109
1110 err_stop_dma:
1111         stm32_dfsdm_adc_dma_stop(indio_dev);
1112 stop_dfsdm:
1113         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1114 err_stop_hwc:
1115         if (adc->hwc)
1116                 iio_hw_consumer_disable(adc->hwc);
1117
1118         return ret;
1119 }
1120
1121 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1122 {
1123         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1124         int i = 0;
1125
1126         stm32_dfsdm_stop_conv(indio_dev);
1127
1128         stm32_dfsdm_adc_dma_stop(indio_dev);
1129
1130         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1131
1132         if (adc->backend) {
1133                 while (adc->backend[i]) {
1134                         iio_backend_disable(adc->backend[i]);
1135                         i++;
1136                 }
1137         }
1138
1139         if (adc->hwc)
1140                 iio_hw_consumer_disable(adc->hwc);
1141
1142         return 0;
1143 }
1144
1145 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
1146         .postenable = &stm32_dfsdm_postenable,
1147         .predisable = &stm32_dfsdm_predisable,
1148 };
1149
1150 /**
1151  * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
1152  *                             DMA transfer period is achieved.
1153  *
1154  * @iio_dev: Handle to IIO device.
1155  * @cb: Pointer to callback function:
1156  *      - data: pointer to data buffer
1157  *      - size: size in byte of the data buffer
1158  *      - private: pointer to consumer private structure.
1159  * @private: Pointer to consumer private structure.
1160  */
1161 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
1162                             int (*cb)(const void *data, size_t size,
1163                                       void *private),
1164                             void *private)
1165 {
1166         struct stm32_dfsdm_adc *adc;
1167
1168         if (!iio_dev)
1169                 return -EINVAL;
1170         adc = iio_priv(iio_dev);
1171
1172         adc->cb = cb;
1173         adc->cb_priv = private;
1174
1175         return 0;
1176 }
1177 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
1178
1179 /**
1180  * stm32_dfsdm_release_buff_cb - unregister buffer callback
1181  *
1182  * @iio_dev: Handle to IIO device.
1183  */
1184 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1185 {
1186         struct stm32_dfsdm_adc *adc;
1187
1188         if (!iio_dev)
1189                 return -EINVAL;
1190         adc = iio_priv(iio_dev);
1191
1192         adc->cb = NULL;
1193         adc->cb_priv = NULL;
1194
1195         return 0;
1196 }
1197 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1198
1199 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1200                                    const struct iio_chan_spec *chan, int *res)
1201 {
1202         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1203         long time_left;
1204         int ret;
1205
1206         reinit_completion(&adc->completion);
1207
1208         adc->buffer = res;
1209
1210         ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1211         if (ret < 0)
1212                 return ret;
1213
1214         ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1215                                  DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1216         if (ret < 0)
1217                 goto stop_dfsdm;
1218
1219         adc->nconv = 1;
1220         adc->smask = BIT(chan->scan_index);
1221         ret = stm32_dfsdm_start_conv(indio_dev, NULL);
1222         if (ret < 0) {
1223                 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1224                                    DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1225                 goto stop_dfsdm;
1226         }
1227
1228         time_left = wait_for_completion_interruptible_timeout(&adc->completion,
1229                                                               DFSDM_TIMEOUT);
1230
1231         /* Mask IRQ for regular conversion achievement*/
1232         regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1233                            DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1234
1235         if (time_left == 0)
1236                 ret = -ETIMEDOUT;
1237         else if (time_left < 0)
1238                 ret = time_left;
1239         else
1240                 ret = IIO_VAL_INT;
1241
1242         stm32_dfsdm_stop_conv(indio_dev);
1243
1244         stm32_dfsdm_process_data(adc, res);
1245
1246 stop_dfsdm:
1247         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1248
1249         return ret;
1250 }
1251
1252 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1253                                  struct iio_chan_spec const *chan,
1254                                  int val, int val2, long mask)
1255 {
1256         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1257         struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1258         unsigned int spi_freq;
1259         int ret = -EINVAL;
1260
1261         switch (ch->src) {
1262         case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1263                 spi_freq = adc->dfsdm->spi_master_freq;
1264                 break;
1265         case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1266         case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1267                 spi_freq = adc->dfsdm->spi_master_freq / 2;
1268                 break;
1269         default:
1270                 spi_freq = adc->spi_freq;
1271         }
1272
1273         switch (mask) {
1274         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1275                 ret = iio_device_claim_direct_mode(indio_dev);
1276                 if (ret)
1277                         return ret;
1278
1279                 ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
1280                 if (!ret) {
1281                         dev_dbg(&indio_dev->dev,
1282                                 "Sampling rate changed from (%u) to (%u)\n",
1283                                 adc->sample_freq, spi_freq / val);
1284                         adc->oversamp = val;
1285                         adc->sample_freq = spi_freq / val;
1286                 }
1287                 iio_device_release_direct_mode(indio_dev);
1288                 return ret;
1289
1290         case IIO_CHAN_INFO_SAMP_FREQ:
1291                 if (!val)
1292                         return -EINVAL;
1293
1294                 ret = iio_device_claim_direct_mode(indio_dev);
1295                 if (ret)
1296                         return ret;
1297
1298                 ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1299                 iio_device_release_direct_mode(indio_dev);
1300                 return ret;
1301         }
1302
1303         return -EINVAL;
1304 }
1305
1306 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1307                                 struct iio_chan_spec const *chan, int *val,
1308                                 int *val2, long mask)
1309 {
1310         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1311
1312         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
1313         struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
1314         u32 max = flo->max << (flo->lshift - chan->scan_type.shift);
1315         int idx = chan->scan_index;
1316         int ret;
1317
1318         if (flo->lshift < chan->scan_type.shift)
1319                 max = flo->max >> (chan->scan_type.shift - flo->lshift);
1320
1321         switch (mask) {
1322         case IIO_CHAN_INFO_RAW:
1323                 ret = iio_device_claim_direct_mode(indio_dev);
1324                 if (ret)
1325                         return ret;
1326                 if (adc->hwc)
1327                         ret = iio_hw_consumer_enable(adc->hwc);
1328                 if (adc->backend)
1329                         ret = iio_backend_enable(adc->backend[idx]);
1330                 if (ret < 0) {
1331                         dev_err(&indio_dev->dev,
1332                                 "%s: IIO enable failed (channel %d)\n",
1333                                 __func__, chan->channel);
1334                         iio_device_release_direct_mode(indio_dev);
1335                         return ret;
1336                 }
1337                 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1338                 if (adc->hwc)
1339                         iio_hw_consumer_disable(adc->hwc);
1340                 if (adc->backend)
1341                         iio_backend_disable(adc->backend[idx]);
1342                 if (ret < 0) {
1343                         dev_err(&indio_dev->dev,
1344                                 "%s: Conversion failed (channel %d)\n",
1345                                 __func__, chan->channel);
1346                         iio_device_release_direct_mode(indio_dev);
1347                         return ret;
1348                 }
1349                 iio_device_release_direct_mode(indio_dev);
1350                 return IIO_VAL_INT;
1351
1352         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1353                 *val = adc->oversamp;
1354
1355                 return IIO_VAL_INT;
1356
1357         case IIO_CHAN_INFO_SAMP_FREQ:
1358                 *val = adc->sample_freq;
1359
1360                 return IIO_VAL_INT;
1361
1362         case IIO_CHAN_INFO_SCALE:
1363                 /*
1364                  * Scale is expressed in mV.
1365                  * When fast mode is disabled, actual resolution may be lower
1366                  * than 2^n, where n = realbits - 1.
1367                  * This leads to underestimating the input voltage.
1368                  * To compensate this deviation, the voltage reference can be
1369                  * corrected with a factor = realbits resolution / actual max
1370                  */
1371                 if (adc->backend) {
1372                         ret = iio_backend_read_scale(adc->backend[idx], chan, val, NULL);
1373                         if (ret < 0)
1374                                 return ret;
1375
1376                         *val = div_u64((u64)*val * (u64)BIT(DFSDM_DATA_RES - 1), max);
1377                         *val2 = chan->scan_type.realbits;
1378                         if (chan->differential)
1379                                 *val *= 2;
1380                 }
1381                 return IIO_VAL_FRACTIONAL_LOG2;
1382
1383         case IIO_CHAN_INFO_OFFSET:
1384                 /*
1385                  * DFSDM output data are in the range [-2^n, 2^n],
1386                  * with n = realbits - 1.
1387                  * - Differential modulator:
1388                  * Offset correspond to SD modulator offset.
1389                  * - Single ended modulator:
1390                  * Input is in [0V, Vref] range,
1391                  * where 0V corresponds to -2^n, and Vref to 2^n.
1392                  * Add 2^n to offset. (i.e. middle of input range)
1393                  * offset = offset(sd) * vref / res(sd) * max / vref.
1394                  */
1395                 if (adc->backend) {
1396                         ret = iio_backend_read_offset(adc->backend[idx], chan, val, NULL);
1397                         if (ret < 0)
1398                                 return ret;
1399
1400                         *val = div_u64((u64)max * *val, BIT(*val2 - 1));
1401                         if (!chan->differential)
1402                                 *val += max;
1403                 }
1404                 return IIO_VAL_INT;
1405         }
1406
1407         return -EINVAL;
1408 }
1409
1410 static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1411                                         struct iio_trigger *trig)
1412 {
1413         return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1414 }
1415
1416 static const struct iio_info stm32_dfsdm_info_audio = {
1417         .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1418         .read_raw = stm32_dfsdm_read_raw,
1419         .write_raw = stm32_dfsdm_write_raw,
1420         .update_scan_mode = stm32_dfsdm_update_scan_mode,
1421 };
1422
1423 static const struct iio_info stm32_dfsdm_info_adc = {
1424         .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1425         .read_raw = stm32_dfsdm_read_raw,
1426         .write_raw = stm32_dfsdm_write_raw,
1427         .update_scan_mode = stm32_dfsdm_update_scan_mode,
1428         .validate_trigger = stm32_dfsdm_validate_trigger,
1429 };
1430
1431 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1432 {
1433         struct iio_dev *indio_dev = arg;
1434         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1435         struct regmap *regmap = adc->dfsdm->regmap;
1436         unsigned int status, int_en;
1437
1438         regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1439         regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1440
1441         if (status & DFSDM_ISR_REOCF_MASK) {
1442                 /* Read the data register clean the IRQ status */
1443                 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1444                 complete(&adc->completion);
1445         }
1446
1447         if (status & DFSDM_ISR_ROVRF_MASK) {
1448                 if (int_en & DFSDM_CR2_ROVRIE_MASK)
1449                         dev_warn(&indio_dev->dev, "Overrun detected\n");
1450                 regmap_set_bits(regmap, DFSDM_ICR(adc->fl_id),
1451                                 DFSDM_ICR_CLRROVRF_MASK);
1452         }
1453
1454         return IRQ_HANDLED;
1455 }
1456
1457 /*
1458  * Define external info for SPI Frequency and audio sampling rate that can be
1459  * configured by ASoC driver through consumer.h API
1460  */
1461 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1462         /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1463         {
1464                 .name = "spi_clk_freq",
1465                 .shared = IIO_SHARED_BY_TYPE,
1466                 .read = dfsdm_adc_audio_get_spiclk,
1467                 .write = dfsdm_adc_audio_set_spiclk,
1468         },
1469         { }
1470 };
1471
1472 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1473 {
1474         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1475
1476         if (adc->dma_chan) {
1477                 dma_free_coherent(adc->dma_chan->device->dev,
1478                                   DFSDM_DMA_BUFFER_SIZE,
1479                                   adc->rx_buf, adc->dma_buf);
1480                 dma_release_channel(adc->dma_chan);
1481         }
1482 }
1483
1484 static int stm32_dfsdm_dma_request(struct device *dev,
1485                                    struct iio_dev *indio_dev)
1486 {
1487         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1488
1489         adc->dma_chan = dma_request_chan(dev, "rx");
1490         if (IS_ERR(adc->dma_chan)) {
1491                 int ret = PTR_ERR(adc->dma_chan);
1492
1493                 adc->dma_chan = NULL;
1494                 return ret;
1495         }
1496
1497         adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1498                                          DFSDM_DMA_BUFFER_SIZE,
1499                                          &adc->dma_buf, GFP_KERNEL);
1500         if (!adc->rx_buf) {
1501                 dma_release_channel(adc->dma_chan);
1502                 return -ENOMEM;
1503         }
1504
1505         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1506         indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1507
1508         return 0;
1509 }
1510
1511 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, struct iio_chan_spec *ch,
1512                                          struct fwnode_handle *child)
1513 {
1514         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1515         int ret;
1516
1517         if (child)
1518                 ret = stm32_dfsdm_generic_channel_parse_of(adc->dfsdm, indio_dev, ch, child);
1519         else /* Legacy binding */
1520                 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1521         if (ret < 0)
1522                 return dev_err_probe(&indio_dev->dev, ret, "Failed to parse channel\n");
1523
1524         ch->type = IIO_VOLTAGE;
1525         ch->indexed = 1;
1526
1527         /*
1528          * IIO_CHAN_INFO_RAW: used to compute regular conversion
1529          * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1530          */
1531         if (child) {
1532                 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1533                                          BIT(IIO_CHAN_INFO_SCALE) |
1534                                          BIT(IIO_CHAN_INFO_OFFSET);
1535         } else {
1536                 /* Legacy. Scaling not supported */
1537                 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1538         }
1539
1540         ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1541                                         BIT(IIO_CHAN_INFO_SAMP_FREQ);
1542
1543         if (adc->dev_data->type == DFSDM_AUDIO) {
1544                 ch->ext_info = dfsdm_adc_audio_ext_info;
1545                 ch->scan_index = 0;
1546         } else {
1547                 ch->scan_type.shift = 8;
1548         }
1549         ch->scan_type.sign = 's';
1550         ch->scan_type.realbits = 24;
1551         ch->scan_type.storagebits = 32;
1552
1553         return stm32_dfsdm_chan_configure(adc->dfsdm,
1554                                           &adc->dfsdm->ch_list[ch->channel]);
1555 }
1556
1557 static int stm32_dfsdm_chan_init(struct iio_dev *indio_dev, struct iio_chan_spec *channels)
1558 {
1559         int num_ch = indio_dev->num_channels;
1560         int chan_idx = 0;
1561         int ret;
1562
1563         for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1564                 channels[chan_idx].scan_index = chan_idx;
1565                 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &channels[chan_idx], NULL);
1566                 if (ret < 0)
1567                         return dev_err_probe(&indio_dev->dev, ret, "Channels init failed\n");
1568         }
1569
1570         return 0;
1571 }
1572
1573 static int stm32_dfsdm_generic_chan_init(struct iio_dev *indio_dev, struct iio_chan_spec *channels)
1574 {
1575         int chan_idx = 0, ret;
1576
1577         device_for_each_child_node_scoped(&indio_dev->dev, child) {
1578                 /* Skip DAI node in DFSDM audio nodes */
1579                 if (fwnode_property_present(child, "compatible"))
1580                         continue;
1581
1582                 channels[chan_idx].scan_index = chan_idx;
1583                 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &channels[chan_idx], child);
1584                 if (ret < 0)
1585                         return dev_err_probe(&indio_dev->dev, ret, "Channels init failed\n");
1586
1587                 chan_idx++;
1588         }
1589
1590         return chan_idx;
1591 }
1592
1593 static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev)
1594 {
1595         struct iio_chan_spec *ch;
1596         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1597         struct stm32_dfsdm_channel *d_ch;
1598         bool legacy = false;
1599         int num_ch, ret;
1600
1601         /* If st,adc-channels is defined legacy binding is used. Else assume generic binding. */
1602         num_ch = of_property_count_u32_elems(indio_dev->dev.of_node, "st,adc-channels");
1603         if (num_ch == 1)
1604                 legacy = true;
1605
1606         ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1607         if (!ch)
1608                 return -ENOMEM;
1609
1610         indio_dev->num_channels = 1;
1611         indio_dev->channels = ch;
1612
1613         if (legacy)
1614                 ret = stm32_dfsdm_chan_init(indio_dev, ch);
1615         else
1616                 ret = stm32_dfsdm_generic_chan_init(indio_dev, ch);
1617
1618         if (ret < 0) {
1619                 dev_err(&indio_dev->dev, "Channels init failed\n");
1620                 return ret;
1621         }
1622         ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1623
1624         d_ch = &adc->dfsdm->ch_list[ch->channel];
1625         if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1626                 adc->spi_freq = adc->dfsdm->spi_master_freq;
1627
1628         return stm32_dfsdm_dma_request(dev, indio_dev);
1629 }
1630
1631 static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev)
1632 {
1633         struct iio_chan_spec *ch;
1634         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1635         int num_ch, ret;
1636         bool legacy = false;
1637
1638         adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1639         ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1640         if (ret < 0)
1641                 return ret;
1642
1643         num_ch = device_get_child_node_count(&indio_dev->dev);
1644         if (!num_ch) {
1645                 /* No channels nodes found. Assume legacy binding */
1646                 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node, "st,adc-channels");
1647                 if (num_ch < 0) {
1648                         dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1649                         return num_ch;
1650                 }
1651
1652                 legacy = true;
1653         }
1654
1655         if (num_ch > adc->dfsdm->num_chs) {
1656                 dev_err(&indio_dev->dev, "Number of channel [%d] exceeds [%d]\n",
1657                         num_ch, adc->dfsdm->num_chs);
1658                 return -EINVAL;
1659         }
1660         indio_dev->num_channels = num_ch;
1661
1662         if (legacy) {
1663                 /* Bind to SD modulator IIO device. */
1664                 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1665                 if (IS_ERR(adc->hwc))
1666                         return dev_err_probe(&indio_dev->dev, -EPROBE_DEFER,
1667                                              "waiting for SD modulator\n");
1668         } else {
1669                 /* Generic binding. SD modulator IIO device not used. Use SD modulator backend. */
1670                 adc->hwc = NULL;
1671
1672                 adc->backend = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*adc->backend),
1673                                             GFP_KERNEL);
1674                 if (!adc->backend)
1675                         return -ENOMEM;
1676         }
1677
1678         ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch), GFP_KERNEL);
1679         if (!ch)
1680                 return -ENOMEM;
1681         indio_dev->channels = ch;
1682
1683         if (legacy)
1684                 ret = stm32_dfsdm_chan_init(indio_dev, ch);
1685         else
1686                 ret = stm32_dfsdm_generic_chan_init(indio_dev, ch);
1687         if (ret < 0)
1688                 return ret;
1689
1690         init_completion(&adc->completion);
1691
1692         /* Optionally request DMA */
1693         ret = stm32_dfsdm_dma_request(dev, indio_dev);
1694         if (ret) {
1695                 if (ret != -ENODEV)
1696                         return dev_err_probe(dev, ret,
1697                                              "DMA channel request failed with\n");
1698
1699                 dev_dbg(dev, "No DMA support\n");
1700                 return 0;
1701         }
1702
1703         ret = iio_triggered_buffer_setup(indio_dev,
1704                                          &iio_pollfunc_store_time, NULL,
1705                                          &stm32_dfsdm_buffer_setup_ops);
1706         if (ret) {
1707                 stm32_dfsdm_dma_release(indio_dev);
1708                 dev_err(&indio_dev->dev, "buffer setup failed\n");
1709                 return ret;
1710         }
1711
1712         /* lptimer/timer hardware triggers */
1713         indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1714
1715         return 0;
1716 }
1717
1718 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1719         .type = DFSDM_IIO,
1720         .init = stm32_dfsdm_adc_init,
1721 };
1722
1723 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1724         .type = DFSDM_AUDIO,
1725         .init = stm32_dfsdm_audio_init,
1726 };
1727
1728 static const struct of_device_id stm32_dfsdm_adc_match[] = {
1729         {
1730                 .compatible = "st,stm32-dfsdm-adc",
1731                 .data = &stm32h7_dfsdm_adc_data,
1732         },
1733         {
1734                 .compatible = "st,stm32-dfsdm-dmic",
1735                 .data = &stm32h7_dfsdm_audio_data,
1736         },
1737         {}
1738 };
1739 MODULE_DEVICE_TABLE(of, stm32_dfsdm_adc_match);
1740
1741 static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1742 {
1743         struct device *dev = &pdev->dev;
1744         struct stm32_dfsdm_adc *adc;
1745         struct device_node *np = dev->of_node;
1746         const struct stm32_dfsdm_dev_data *dev_data;
1747         struct iio_dev *iio;
1748         char *name;
1749         int ret, irq, val;
1750
1751         dev_data = of_device_get_match_data(dev);
1752         iio = devm_iio_device_alloc(dev, sizeof(*adc));
1753         if (!iio) {
1754                 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1755                 return -ENOMEM;
1756         }
1757
1758         adc = iio_priv(iio);
1759         adc->dfsdm = dev_get_drvdata(dev->parent);
1760
1761         iio->dev.of_node = np;
1762         iio->modes = INDIO_DIRECT_MODE;
1763
1764         platform_set_drvdata(pdev, iio);
1765
1766         ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1767         if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1768                 dev_err(dev, "Missing or bad reg property\n");
1769                 return -EINVAL;
1770         }
1771
1772         name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1773         if (!name)
1774                 return -ENOMEM;
1775         if (dev_data->type == DFSDM_AUDIO) {
1776                 iio->info = &stm32_dfsdm_info_audio;
1777                 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1778         } else {
1779                 iio->info = &stm32_dfsdm_info_adc;
1780                 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1781         }
1782         iio->name = name;
1783
1784         /*
1785          * In a first step IRQs generated for channels are not treated.
1786          * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1787          */
1788         irq = platform_get_irq(pdev, 0);
1789         if (irq < 0)
1790                 return irq;
1791
1792         ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1793                                0, pdev->name, iio);
1794         if (ret < 0) {
1795                 dev_err(dev, "Failed to request IRQ\n");
1796                 return ret;
1797         }
1798
1799         ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1800         if (ret < 0) {
1801                 dev_err(dev, "Failed to set filter order\n");
1802                 return ret;
1803         }
1804
1805         adc->dfsdm->fl_list[adc->fl_id].ford = val;
1806
1807         ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1808         if (!ret)
1809                 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1810
1811         adc->dev_data = dev_data;
1812         ret = dev_data->init(dev, iio);
1813         if (ret < 0)
1814                 return ret;
1815
1816         ret = iio_device_register(iio);
1817         if (ret < 0)
1818                 goto err_cleanup;
1819
1820         if (dev_data->type == DFSDM_AUDIO) {
1821                 ret = of_platform_populate(np, NULL, NULL, dev);
1822                 if (ret < 0) {
1823                         dev_err(dev, "Failed to find an audio DAI\n");
1824                         goto err_unregister;
1825                 }
1826         }
1827
1828         return 0;
1829
1830 err_unregister:
1831         iio_device_unregister(iio);
1832 err_cleanup:
1833         stm32_dfsdm_dma_release(iio);
1834
1835         return ret;
1836 }
1837
1838 static void stm32_dfsdm_adc_remove(struct platform_device *pdev)
1839 {
1840         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1841         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1842
1843         if (adc->dev_data->type == DFSDM_AUDIO)
1844                 of_platform_depopulate(&pdev->dev);
1845         iio_device_unregister(indio_dev);
1846         stm32_dfsdm_dma_release(indio_dev);
1847 }
1848
1849 static int stm32_dfsdm_adc_suspend(struct device *dev)
1850 {
1851         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1852
1853         if (iio_buffer_enabled(indio_dev))
1854                 stm32_dfsdm_predisable(indio_dev);
1855
1856         return 0;
1857 }
1858
1859 static int stm32_dfsdm_adc_resume(struct device *dev)
1860 {
1861         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1862         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1863         const struct iio_chan_spec *chan;
1864         struct stm32_dfsdm_channel *ch;
1865         int i, ret;
1866
1867         /* restore channels configuration */
1868         for (i = 0; i < indio_dev->num_channels; i++) {
1869                 chan = indio_dev->channels + i;
1870                 ch = &adc->dfsdm->ch_list[chan->channel];
1871                 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1872                 if (ret)
1873                         return ret;
1874         }
1875
1876         if (iio_buffer_enabled(indio_dev))
1877                 stm32_dfsdm_postenable(indio_dev);
1878
1879         return 0;
1880 }
1881
1882 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1883                                 stm32_dfsdm_adc_suspend,
1884                                 stm32_dfsdm_adc_resume);
1885
1886 static struct platform_driver stm32_dfsdm_adc_driver = {
1887         .driver = {
1888                 .name = "stm32-dfsdm-adc",
1889                 .of_match_table = stm32_dfsdm_adc_match,
1890                 .pm = pm_sleep_ptr(&stm32_dfsdm_adc_pm_ops),
1891         },
1892         .probe = stm32_dfsdm_adc_probe,
1893         .remove_new = stm32_dfsdm_adc_remove,
1894 };
1895 module_platform_driver(stm32_dfsdm_adc_driver);
1896
1897 MODULE_DESCRIPTION("STM32 sigma delta ADC");
1898 MODULE_AUTHOR("Arnaud Pouliquen <[email protected]>");
1899 MODULE_LICENSE("GPL v2");
1900 MODULE_IMPORT_NS(IIO_BACKEND);