drivers/i2c/busses/i2c-piix4.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3     Copyright (c) 1998 - 2002 Frodo Looijaard <[email protected]> and
   4     Philip Edelbrock <[email protected]>
   5
   6 */
   7
   8 /*
   9    Supports:
  10         Intel PIIX4, 440MX
  11         Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
  12         ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
  13         AMD Hudson-2, ML, CZ
  14         Hygon CZ
  15         SMSC Victory66
  16
  17    Note: we assume there can only be one device, with one or more
  18    SMBus interfaces.
  19    The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
  20    For devices supporting multiple ports the i2c_adapter should provide
  21    an i2c_algorithm to access them.
  22 */
  23
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/pci.h>
  27 #include <linux/kernel.h>
  28 #include <linux/delay.h>
  29 #include <linux/stddef.h>
  30 #include <linux/ioport.h>
  31 #include <linux/i2c.h>
  32 #include <linux/i2c-smbus.h>
  33 #include <linux/slab.h>
  34 #include <linux/dmi.h>
  35 #include <linux/acpi.h>
  36 #include <linux/io.h>
  37
  38
  39 /* PIIX4 SMBus address offsets */
  40 #define SMBHSTSTS       (0 + piix4_smba)
  41 #define SMBHSLVSTS      (1 + piix4_smba)
  42 #define SMBHSTCNT       (2 + piix4_smba)
  43 #define SMBHSTCMD       (3 + piix4_smba)
  44 #define SMBHSTADD       (4 + piix4_smba)
  45 #define SMBHSTDAT0      (5 + piix4_smba)
  46 #define SMBHSTDAT1      (6 + piix4_smba)
  47 #define SMBBLKDAT       (7 + piix4_smba)
  48 #define SMBSLVCNT       (8 + piix4_smba)
  49 #define SMBSHDWCMD      (9 + piix4_smba)
  50 #define SMBSLVEVT       (0xA + piix4_smba)
  51 #define SMBSLVDAT       (0xC + piix4_smba)
  52
  53 /* count for request_region */
  54 #define SMBIOSIZE       9
  55
  56 /* PCI Address Constants */
  57 #define SMBBA           0x090
  58 #define SMBHSTCFG       0x0D2
  59 #define SMBSLVC         0x0D3
  60 #define SMBSHDW1        0x0D4
  61 #define SMBSHDW2        0x0D5
  62 #define SMBREV          0x0D6
  63
  64 /* Other settings */
  65 #define MAX_TIMEOUT     500
  66 #define  ENABLE_INT9    0
  67
  68 /* PIIX4 constants */
  69 #define PIIX4_QUICK             0x00
  70 #define PIIX4_BYTE              0x04
  71 #define PIIX4_BYTE_DATA         0x08
  72 #define PIIX4_WORD_DATA         0x0C
  73 #define PIIX4_BLOCK_DATA        0x14
  74
  75 /* Multi-port constants */
  76 #define PIIX4_MAX_ADAPTERS      4
  77 #define HUDSON2_MAIN_PORTS      2 /* HUDSON2, KERNCZ reserves ports 3, 4 */
  78
  79 /* SB800 constants */
  80 #define SB800_PIIX4_SMB_IDX             0xcd6
  81 #define SB800_PIIX4_SMB_MAP_SIZE        2
  82
  83 #define KERNCZ_IMC_IDX                  0x3e
  84 #define KERNCZ_IMC_DATA                 0x3f
  85
  86 /*
  87  * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
  88  * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
  89  * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
  90  */
  91 #define SB800_PIIX4_PORT_IDX            0x2c
  92 #define SB800_PIIX4_PORT_IDX_ALT        0x2e
  93 #define SB800_PIIX4_PORT_IDX_SEL        0x2f
  94 #define SB800_PIIX4_PORT_IDX_MASK       0x06
  95 #define SB800_PIIX4_PORT_IDX_SHIFT      1
  96
  97 /* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
  98 #define SB800_PIIX4_PORT_IDX_KERNCZ             0x02
  99 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ        0x18
 100 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ       3
 101
 102 #define SB800_PIIX4_FCH_PM_ADDR                 0xFED80300
 103 #define SB800_PIIX4_FCH_PM_SIZE                 8
 104
 105 /* insmod parameters */
 106
 107 /* If force is set to anything different from 0, we forcibly enable the
 108    PIIX4. DANGEROUS! */
 109 static int force;
 110 module_param (force, int, 0);
 111 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
 112
 113 /* If force_addr is set to anything different from 0, we forcibly enable
 114    the PIIX4 at the given address. VERY DANGEROUS! */
 115 static int force_addr;
 116 module_param_hw(force_addr, int, ioport, 0);
 117 MODULE_PARM_DESC(force_addr,
 118                  "Forcibly enable the PIIX4 at the given address. "
 119                  "EXTREMELY DANGEROUS!");
 120
 121 static int srvrworks_csb5_delay;
 122 static struct pci_driver piix4_driver;
 123
 124 static const struct dmi_system_id piix4_dmi_blacklist[] = {
 125         {
 126                 .ident = "Sapphire AM2RD790",
 127                 .matches = {
 128                         DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
 129                         DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
 130                 },
 131         },
 132         {
 133                 .ident = "DFI Lanparty UT 790FX",
 134                 .matches = {
 135                         DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
 136                         DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
 137                 },
 138         },
 139         { }
 140 };
 141
 142 /* The IBM entry is in a separate table because we only check it
 143    on Intel-based systems */
 144 static const struct dmi_system_id piix4_dmi_ibm[] = {
 145         {
 146                 .ident = "IBM",
 147                 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
 148         },
 149         { }
 150 };
 151
 152 /*
 153  * SB800 globals
 154  */
 155 static u8 piix4_port_sel_sb800;
 156 static u8 piix4_port_mask_sb800;
 157 static u8 piix4_port_shift_sb800;
 158 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
 159         " port 0", " port 2", " port 3", " port 4"
 160 };
 161 static const char *piix4_aux_port_name_sb800 = " port 1";
 162
 163 struct sb800_mmio_cfg {
 164         void __iomem *addr;
 165         bool use_mmio;
 166 };
 167
 168 struct i2c_piix4_adapdata {
 169         unsigned short smba;
 170
 171         /* SB800 */
 172         bool sb800_main;
 173         bool notify_imc;
 174         u8 port;                /* Port number, shifted */
 175         struct sb800_mmio_cfg mmio_cfg;
 176 };
 177
 178 static int piix4_sb800_region_request(struct device *dev,
 179                                       struct sb800_mmio_cfg *mmio_cfg)
 180 {
 181         if (mmio_cfg->use_mmio) {
 182                 void __iomem *addr;
 183
 184                 if (!request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
 185                                               SB800_PIIX4_FCH_PM_SIZE,
 186                                               "sb800_piix4_smb")) {
 187                         dev_err(dev,
 188                                 "SMBus base address memory region 0x%x already in use.\n",
 189                                 SB800_PIIX4_FCH_PM_ADDR);
 190                         return -EBUSY;
 191                 }
 192
 193                 addr = ioremap(SB800_PIIX4_FCH_PM_ADDR,
 194                                SB800_PIIX4_FCH_PM_SIZE);
 195                 if (!addr) {
 196                         release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
 197                                            SB800_PIIX4_FCH_PM_SIZE);
 198                         dev_err(dev, "SMBus base address mapping failed.\n");
 199                         return -ENOMEM;
 200                 }
 201
 202                 mmio_cfg->addr = addr;
 203
 204                 return 0;
 205         }
 206
 207         if (!request_muxed_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE,
 208                                   "sb800_piix4_smb")) {
 209                 dev_err(dev,
 210                         "SMBus base address index region 0x%x already in use.\n",
 211                         SB800_PIIX4_SMB_IDX);
 212                 return -EBUSY;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static void piix4_sb800_region_release(struct device *dev,
 219                                        struct sb800_mmio_cfg *mmio_cfg)
 220 {
 221         if (mmio_cfg->use_mmio) {
 222                 iounmap(mmio_cfg->addr);
 223                 release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
 224                                    SB800_PIIX4_FCH_PM_SIZE);
 225                 return;
 226         }
 227
 228         release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE);
 229 }
 230
 231 static bool piix4_sb800_use_mmio(struct pci_dev *PIIX4_dev)
 232 {
 233         /*
 234          * cd6h/cd7h port I/O accesses can be disabled on AMD processors
 235          * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on
 236          * the same processors and is the recommended access method.
 237          */
 238         return (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
 239                 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
 240                 PIIX4_dev->revision >= 0x51);
 241 }
 242
 243 static int piix4_setup(struct pci_dev *PIIX4_dev,
 244                        const struct pci_device_id *id)
 245 {
 246         unsigned char temp;
 247         unsigned short piix4_smba;
 248
 249         if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
 250             (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
 251                 srvrworks_csb5_delay = 1;
 252
 253         /* On some motherboards, it was reported that accessing the SMBus
 254            caused severe hardware problems */
 255         if (dmi_check_system(piix4_dmi_blacklist)) {
 256                 dev_err(&PIIX4_dev->dev,
 257                         "Accessing the SMBus on this system is unsafe!\n");
 258                 return -EPERM;
 259         }
 260
 261         /* Don't access SMBus on IBM systems which get corrupted eeproms */
 262         if (dmi_check_system(piix4_dmi_ibm) &&
 263                         PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
 264                 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
 265                         "may corrupt your serial eeprom! Refusing to load "
 266                         "module!\n");
 267                 return -EPERM;
 268         }
 269
 270         /* Determine the address of the SMBus areas */
 271         if (force_addr) {
 272                 piix4_smba = force_addr & 0xfff0;
 273                 force = 0;
 274         } else {
 275                 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
 276                 piix4_smba &= 0xfff0;
 277                 if(piix4_smba == 0) {
 278                         dev_err(&PIIX4_dev->dev, "SMBus base address "
 279                                 "uninitialized - upgrade BIOS or use "
 280                                 "force_addr=0xaddr\n");
 281                         return -ENODEV;
 282                 }
 283         }
 284
 285         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 286                 return -ENODEV;
 287
 288         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 289                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 290                         piix4_smba);
 291                 return -EBUSY;
 292         }
 293
 294         pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
 295
 296         /* If force_addr is set, we program the new address here. Just to make
 297            sure, we disable the PIIX4 first. */
 298         if (force_addr) {
 299                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
 300                 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
 301                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
 302                 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
 303                         "new address %04x!\n", piix4_smba);
 304         } else if ((temp & 1) == 0) {
 305                 if (force) {
 306                         /* This should never need to be done, but has been
 307                          * noted that many Dell machines have the SMBus
 308                          * interface on the PIIX4 disabled!? NOTE: This assumes
 309                          * I/O space and other allocations WERE done by the
 310                          * Bios!  Don't complain if your hardware does weird
 311                          * things after enabling this. :') Check for Bios
 312                          * updates before resorting to this.
 313                          */
 314                         pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
 315                                               temp | 1);
 316                         dev_notice(&PIIX4_dev->dev,
 317                                    "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
 318                 } else {
 319                         dev_err(&PIIX4_dev->dev,
 320                                 "SMBus Host Controller not enabled!\n");
 321                         release_region(piix4_smba, SMBIOSIZE);
 322                         return -ENODEV;
 323                 }
 324         }
 325
 326         if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
 327                 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
 328         else if ((temp & 0x0E) == 0)
 329                 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
 330         else
 331                 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
 332                         "(or code out of date)!\n");
 333
 334         pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
 335         dev_info(&PIIX4_dev->dev,
 336                  "SMBus Host Controller at 0x%x, revision %d\n",
 337                  piix4_smba, temp);
 338
 339         return piix4_smba;
 340 }
 341
 342 static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev,
 343                                   u8 smb_en,
 344                                   u8 aux,
 345                                   u8 *smb_en_status,
 346                                   unsigned short *piix4_smba)
 347 {
 348         struct sb800_mmio_cfg mmio_cfg;
 349         u8 smba_en_lo;
 350         u8 smba_en_hi;
 351         int retval;
 352
 353         mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
 354         retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
 355         if (retval)
 356                 return retval;
 357
 358         if (mmio_cfg.use_mmio) {
 359                 smba_en_lo = ioread8(mmio_cfg.addr);
 360                 smba_en_hi = ioread8(mmio_cfg.addr + 1);
 361         } else {
 362                 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
 363                 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
 364                 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
 365                 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
 366         }
 367
 368         piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg);
 369
 370         if (!smb_en) {
 371                 *smb_en_status = smba_en_lo & 0x10;
 372                 *piix4_smba = smba_en_hi << 8;
 373                 if (aux)
 374                         *piix4_smba |= 0x20;
 375         } else {
 376                 *smb_en_status = smba_en_lo & 0x01;
 377                 *piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
 378         }
 379
 380         if (!*smb_en_status) {
 381                 dev_err(&PIIX4_dev->dev,
 382                         "SMBus Host Controller not enabled!\n");
 383                 return -ENODEV;
 384         }
 385
 386         return 0;
 387 }
 388
 389 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
 390                              const struct pci_device_id *id, u8 aux)
 391 {
 392         unsigned short piix4_smba;
 393         u8 smb_en, smb_en_status, port_sel;
 394         u8 i2ccfg, i2ccfg_offset = 0x10;
 395         struct sb800_mmio_cfg mmio_cfg;
 396         int retval;
 397
 398         /* SB800 and later SMBus does not support forcing address */
 399         if (force || force_addr) {
 400                 dev_err(&PIIX4_dev->dev, "SMBus does not support "
 401                         "forcing address!\n");
 402                 return -EINVAL;
 403         }
 404
 405         /* Determine the address of the SMBus areas */
 406         if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
 407              PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
 408              PIIX4_dev->revision >= 0x41) ||
 409             (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
 410              PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
 411              PIIX4_dev->revision >= 0x49) ||
 412             (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
 413              PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
 414                 smb_en = 0x00;
 415         else
 416                 smb_en = (aux) ? 0x28 : 0x2c;
 417
 418         retval = piix4_setup_sb800_smba(PIIX4_dev, smb_en, aux, &smb_en_status,
 419                                         &piix4_smba);
 420
 421         if (retval)
 422                 return retval;
 423
 424         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 425                 return -ENODEV;
 426
 427         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 428                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 429                         piix4_smba);
 430                 return -EBUSY;
 431         }
 432
 433         /* Aux SMBus does not support IRQ information */
 434         if (aux) {
 435                 dev_info(&PIIX4_dev->dev,
 436                          "Auxiliary SMBus Host Controller at 0x%x\n",
 437                          piix4_smba);
 438                 return piix4_smba;
 439         }
 440
 441         /* Request the SMBus I2C bus config region */
 442         if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
 443                 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
 444                         "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
 445                 release_region(piix4_smba, SMBIOSIZE);
 446                 return -EBUSY;
 447         }
 448         i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
 449         release_region(piix4_smba + i2ccfg_offset, 1);
 450
 451         if (i2ccfg & 1)
 452                 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
 453         else
 454                 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
 455
 456         dev_info(&PIIX4_dev->dev,
 457                  "SMBus Host Controller at 0x%x, revision %d\n",
 458                  piix4_smba, i2ccfg >> 4);
 459
 460         /* Find which register is used for port selection */
 461         if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
 462             PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
 463                 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
 464                     (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
 465                      PIIX4_dev->revision >= 0x1F)) {
 466                         piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
 467                         piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
 468                         piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
 469                 } else {
 470                         piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
 471                         piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
 472                         piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
 473                 }
 474         } else {
 475                 mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
 476                 retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
 477                 if (retval) {
 478                         release_region(piix4_smba, SMBIOSIZE);
 479                         return retval;
 480                 }
 481
 482                 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
 483                 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
 484                 piix4_port_sel_sb800 = (port_sel & 0x01) ?
 485                                        SB800_PIIX4_PORT_IDX_ALT :
 486                                        SB800_PIIX4_PORT_IDX;
 487                 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
 488                 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
 489                 piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg);
 490         }
 491
 492         dev_info(&PIIX4_dev->dev,
 493                  "Using register 0x%02x for SMBus port selection\n",
 494                  (unsigned int)piix4_port_sel_sb800);
 495
 496         return piix4_smba;
 497 }
 498
 499 static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
 500                            const struct pci_device_id *id,
 501                            unsigned short base_reg_addr)
 502 {
 503         /* Set up auxiliary SMBus controllers found on some
 504          * AMD chipsets e.g. SP5100 (SB700 derivative) */
 505
 506         unsigned short piix4_smba;
 507
 508         /* Read address of auxiliary SMBus controller */
 509         pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
 510         if ((piix4_smba & 1) == 0) {
 511                 dev_dbg(&PIIX4_dev->dev,
 512                         "Auxiliary SMBus controller not enabled\n");
 513                 return -ENODEV;
 514         }
 515
 516         piix4_smba &= 0xfff0;
 517         if (piix4_smba == 0) {
 518                 dev_dbg(&PIIX4_dev->dev,
 519                         "Auxiliary SMBus base address uninitialized\n");
 520                 return -ENODEV;
 521         }
 522
 523         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 524                 return -ENODEV;
 525
 526         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 527                 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
 528                         "already in use!\n", piix4_smba);
 529                 return -EBUSY;
 530         }
 531
 532         dev_info(&PIIX4_dev->dev,
 533                  "Auxiliary SMBus Host Controller at 0x%x\n",
 534                  piix4_smba);
 535
 536         return piix4_smba;
 537 }
 538
 539 static int piix4_transaction(struct i2c_adapter *piix4_adapter)
 540 {
 541         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
 542         unsigned short piix4_smba = adapdata->smba;
 543         int temp;
 544         int result = 0;
 545         int timeout = 0;
 546
 547         dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 548                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 549                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 550                 inb_p(SMBHSTDAT1));
 551
 552         /* Make sure the SMBus host is ready to start transmitting */
 553         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 554                 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
 555                         "Resetting...\n", temp);
 556                 outb_p(temp, SMBHSTSTS);
 557                 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 558                         dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
 559                         return -EBUSY;
 560                 } else {
 561                         dev_dbg(&piix4_adapter->dev, "Successful!\n");
 562                 }
 563         }
 564
 565         /* start the transaction by setting bit 6 */
 566         outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
 567
 568         /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
 569         if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
 570                 usleep_range(2000, 2100);
 571         else
 572                 usleep_range(250, 500);
 573
 574         while ((++timeout < MAX_TIMEOUT) &&
 575                ((temp = inb_p(SMBHSTSTS)) & 0x01))
 576                 usleep_range(250, 500);
 577
 578         /* If the SMBus is still busy, we give up */
 579         if (timeout == MAX_TIMEOUT) {
 580                 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
 581                 result = -ETIMEDOUT;
 582         }
 583
 584         if (temp & 0x10) {
 585                 result = -EIO;
 586                 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
 587         }
 588
 589         if (temp & 0x08) {
 590                 result = -EIO;
 591                 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
 592                         "locked until next hard reset. (sorry!)\n");
 593                 /* Clock stops and target is stuck in mid-transmission */
 594         }
 595
 596         if (temp & 0x04) {
 597                 result = -ENXIO;
 598                 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
 599         }
 600
 601         if (inb_p(SMBHSTSTS) != 0x00)
 602                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 603
 604         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 605                 dev_err(&piix4_adapter->dev, "Failed reset at end of "
 606                         "transaction (%02x)\n", temp);
 607         }
 608         dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 609                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 610                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 611                 inb_p(SMBHSTDAT1));
 612         return result;
 613 }
 614
 615 /* Return negative errno on error. */
 616 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
 617                  unsigned short flags, char read_write,
 618                  u8 command, int size, union i2c_smbus_data * data)
 619 {
 620         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
 621         unsigned short piix4_smba = adapdata->smba;
 622         int i, len;
 623         int status;
 624
 625         switch (size) {
 626         case I2C_SMBUS_QUICK:
 627                 outb_p((addr << 1) | read_write,
 628                        SMBHSTADD);
 629                 size = PIIX4_QUICK;
 630                 break;
 631         case I2C_SMBUS_BYTE:
 632                 outb_p((addr << 1) | read_write,
 633                        SMBHSTADD);
 634                 if (read_write == I2C_SMBUS_WRITE)
 635                         outb_p(command, SMBHSTCMD);
 636                 size = PIIX4_BYTE;
 637                 break;
 638         case I2C_SMBUS_BYTE_DATA:
 639                 outb_p((addr << 1) | read_write,
 640                        SMBHSTADD);
 641                 outb_p(command, SMBHSTCMD);
 642                 if (read_write == I2C_SMBUS_WRITE)
 643                         outb_p(data->byte, SMBHSTDAT0);
 644                 size = PIIX4_BYTE_DATA;
 645                 break;
 646         case I2C_SMBUS_WORD_DATA:
 647                 outb_p((addr << 1) | read_write,
 648                        SMBHSTADD);
 649                 outb_p(command, SMBHSTCMD);
 650                 if (read_write == I2C_SMBUS_WRITE) {
 651                         outb_p(data->word & 0xff, SMBHSTDAT0);
 652                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 653                 }
 654                 size = PIIX4_WORD_DATA;
 655                 break;
 656         case I2C_SMBUS_BLOCK_DATA:
 657                 outb_p((addr << 1) | read_write,
 658                        SMBHSTADD);
 659                 outb_p(command, SMBHSTCMD);
 660                 if (read_write == I2C_SMBUS_WRITE) {
 661                         len = data->block[0];
 662                         if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
 663                                 return -EINVAL;
 664                         outb_p(len, SMBHSTDAT0);
 665                         inb_p(SMBHSTCNT);       /* Reset SMBBLKDAT */
 666                         for (i = 1; i <= len; i++)
 667                                 outb_p(data->block[i], SMBBLKDAT);
 668                 }
 669                 size = PIIX4_BLOCK_DATA;
 670                 break;
 671         default:
 672                 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
 673                 return -EOPNOTSUPP;
 674         }
 675
 676         outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
 677
 678         status = piix4_transaction(adap);
 679         if (status)
 680                 return status;
 681
 682         if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
 683                 return 0;
 684
 685
 686         switch (size) {
 687         case PIIX4_BYTE:
 688         case PIIX4_BYTE_DATA:
 689                 data->byte = inb_p(SMBHSTDAT0);
 690                 break;
 691         case PIIX4_WORD_DATA:
 692                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 693                 break;
 694         case PIIX4_BLOCK_DATA:
 695                 data->block[0] = inb_p(SMBHSTDAT0);
 696                 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 697                         return -EPROTO;
 698                 inb_p(SMBHSTCNT);       /* Reset SMBBLKDAT */
 699                 for (i = 1; i <= data->block[0]; i++)
 700                         data->block[i] = inb_p(SMBBLKDAT);
 701                 break;
 702         }
 703         return 0;
 704 }
 705
 706 static uint8_t piix4_imc_read(uint8_t idx)
 707 {
 708         outb_p(idx, KERNCZ_IMC_IDX);
 709         return inb_p(KERNCZ_IMC_DATA);
 710 }
 711
 712 static void piix4_imc_write(uint8_t idx, uint8_t value)
 713 {
 714         outb_p(idx, KERNCZ_IMC_IDX);
 715         outb_p(value, KERNCZ_IMC_DATA);
 716 }
 717
 718 static int piix4_imc_sleep(void)
 719 {
 720         int timeout = MAX_TIMEOUT;
 721
 722         if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
 723                 return -EBUSY;
 724
 725         /* clear response register */
 726         piix4_imc_write(0x82, 0x00);
 727         /* request ownership flag */
 728         piix4_imc_write(0x83, 0xB4);
 729         /* kick off IMC Mailbox command 96 */
 730         piix4_imc_write(0x80, 0x96);
 731
 732         while (timeout--) {
 733                 if (piix4_imc_read(0x82) == 0xfa) {
 734                         release_region(KERNCZ_IMC_IDX, 2);
 735                         return 0;
 736                 }
 737                 usleep_range(1000, 2000);
 738         }
 739
 740         release_region(KERNCZ_IMC_IDX, 2);
 741         return -ETIMEDOUT;
 742 }
 743
 744 static void piix4_imc_wakeup(void)
 745 {
 746         int timeout = MAX_TIMEOUT;
 747
 748         if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
 749                 return;
 750
 751         /* clear response register */
 752         piix4_imc_write(0x82, 0x00);
 753         /* release ownership flag */
 754         piix4_imc_write(0x83, 0xB5);
 755         /* kick off IMC Mailbox command 96 */
 756         piix4_imc_write(0x80, 0x96);
 757
 758         while (timeout--) {
 759                 if (piix4_imc_read(0x82) == 0xfa)
 760                         break;
 761                 usleep_range(1000, 2000);
 762         }
 763
 764         release_region(KERNCZ_IMC_IDX, 2);
 765 }
 766
 767 static int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg)
 768 {
 769         u8 smba_en_lo, val;
 770
 771         if (mmio_cfg->use_mmio) {
 772                 smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800);
 773                 val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
 774                 if (smba_en_lo != val)
 775                         iowrite8(val, mmio_cfg->addr + piix4_port_sel_sb800);
 776
 777                 return (smba_en_lo & piix4_port_mask_sb800);
 778         }
 779
 780         outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
 781         smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
 782
 783         val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
 784         if (smba_en_lo != val)
 785                 outb_p(val, SB800_PIIX4_SMB_IDX + 1);
 786
 787         return (smba_en_lo & piix4_port_mask_sb800);
 788 }
 789
 790 /*
 791  * Handles access to multiple SMBus ports on the SB800.
 792  * The port is selected by bits 2:1 of the smb_en register (0x2c).
 793  * Returns negative errno on error.
 794  *
 795  * Note: The selected port must be returned to the initial selection to avoid
 796  * problems on certain systems.
 797  */
 798 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
 799                  unsigned short flags, char read_write,
 800                  u8 command, int size, union i2c_smbus_data *data)
 801 {
 802         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
 803         unsigned short piix4_smba = adapdata->smba;
 804         int retries = MAX_TIMEOUT;
 805         int smbslvcnt;
 806         u8 prev_port;
 807         int retval;
 808
 809         retval = piix4_sb800_region_request(&adap->dev, &adapdata->mmio_cfg);
 810         if (retval)
 811                 return retval;
 812
 813         /* Request the SMBUS semaphore, avoid conflicts with the IMC */
 814         smbslvcnt  = inb_p(SMBSLVCNT);
 815         do {
 816                 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
 817
 818                 /* Check the semaphore status */
 819                 smbslvcnt  = inb_p(SMBSLVCNT);
 820                 if (smbslvcnt & 0x10)
 821                         break;
 822
 823                 usleep_range(1000, 2000);
 824         } while (--retries);
 825         /* SMBus is still owned by the IMC, we give up */
 826         if (!retries) {
 827                 retval = -EBUSY;
 828                 goto release;
 829         }
 830
 831         /*
 832          * Notify the IMC (Integrated Micro Controller) if required.
 833          * Among other responsibilities, the IMC is in charge of monitoring
 834          * the System fans and temperature sensors, and act accordingly.
 835          * All this is done through SMBus and can/will collide
 836          * with our transactions if they are long (BLOCK_DATA).
 837          * Therefore we need to request the ownership flag during those
 838          * transactions.
 839          */
 840         if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
 841                 int ret;
 842
 843                 ret = piix4_imc_sleep();
 844                 switch (ret) {
 845                 case -EBUSY:
 846                         dev_warn(&adap->dev,
 847                                  "IMC base address index region 0x%x already in use.\n",
 848                                  KERNCZ_IMC_IDX);
 849                         break;
 850                 case -ETIMEDOUT:
 851                         dev_warn(&adap->dev,
 852                                  "Failed to communicate with the IMC.\n");
 853                         break;
 854                 default:
 855                         break;
 856                 }
 857
 858                 /* If IMC communication fails do not retry */
 859                 if (ret) {
 860                         dev_warn(&adap->dev,
 861                                  "Continuing without IMC notification.\n");
 862                         adapdata->notify_imc = false;
 863                 }
 864         }
 865
 866         prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg);
 867
 868         retval = piix4_access(adap, addr, flags, read_write,
 869                               command, size, data);
 870
 871         piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg);
 872
 873         /* Release the semaphore */
 874         outb_p(smbslvcnt | 0x20, SMBSLVCNT);
 875
 876         if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
 877                 piix4_imc_wakeup();
 878
 879 release:
 880         piix4_sb800_region_release(&adap->dev, &adapdata->mmio_cfg);
 881         return retval;
 882 }
 883
 884 static u32 piix4_func(struct i2c_adapter *adapter)
 885 {
 886         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 887             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 888             I2C_FUNC_SMBUS_BLOCK_DATA;
 889 }
 890
 891 static const struct i2c_algorithm smbus_algorithm = {
 892         .smbus_xfer     = piix4_access,
 893         .functionality  = piix4_func,
 894 };
 895
 896 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
 897         .smbus_xfer     = piix4_access_sb800,
 898         .functionality  = piix4_func,
 899 };
 900
 901 static const struct pci_device_id piix4_ids[] = {
 902         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
 903         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
 904         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
 905         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
 906         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
 907         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
 908         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
 909         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
 910         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
 911         { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
 912         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 913                      PCI_DEVICE_ID_SERVERWORKS_OSB4) },
 914         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 915                      PCI_DEVICE_ID_SERVERWORKS_CSB5) },
 916         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 917                      PCI_DEVICE_ID_SERVERWORKS_CSB6) },
 918         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 919                      PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
 920         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 921                      PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
 922         { 0, }
 923 };
 924
 925 MODULE_DEVICE_TABLE (pci, piix4_ids);
 926
 927 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
 928 static struct i2c_adapter *piix4_aux_adapter;
 929 static int piix4_adapter_count;
 930
 931 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
 932                              bool sb800_main, u8 port, bool notify_imc,
 933                              u8 hw_port_nr, const char *name,
 934                              struct i2c_adapter **padap)
 935 {
 936         struct i2c_adapter *adap;
 937         struct i2c_piix4_adapdata *adapdata;
 938         int retval;
 939
 940         adap = kzalloc(sizeof(*adap), GFP_KERNEL);
 941         if (adap == NULL) {
 942                 release_region(smba, SMBIOSIZE);
 943                 return -ENOMEM;
 944         }
 945
 946         adap->owner = THIS_MODULE;
 947         adap->class = I2C_CLASS_HWMON;
 948         adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
 949                                 : &smbus_algorithm;
 950
 951         adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
 952         if (adapdata == NULL) {
 953                 kfree(adap);
 954                 release_region(smba, SMBIOSIZE);
 955                 return -ENOMEM;
 956         }
 957
 958         adapdata->mmio_cfg.use_mmio = piix4_sb800_use_mmio(dev);
 959         adapdata->smba = smba;
 960         adapdata->sb800_main = sb800_main;
 961         adapdata->port = port << piix4_port_shift_sb800;
 962         adapdata->notify_imc = notify_imc;
 963
 964         /* set up the sysfs linkage to our parent device */
 965         adap->dev.parent = &dev->dev;
 966
 967         if (has_acpi_companion(&dev->dev)) {
 968                 acpi_preset_companion(&adap->dev,
 969                                       ACPI_COMPANION(&dev->dev),
 970                                       hw_port_nr);
 971         }
 972
 973         snprintf(adap->name, sizeof(adap->name),
 974                 "SMBus PIIX4 adapter%s at %04x", name, smba);
 975
 976         i2c_set_adapdata(adap, adapdata);
 977
 978         retval = i2c_add_adapter(adap);
 979         if (retval) {
 980                 kfree(adapdata);
 981                 kfree(adap);
 982                 release_region(smba, SMBIOSIZE);
 983                 return retval;
 984         }
 985
 986         /*
 987          * The AUX bus can not be probed as on some platforms it reports all
 988          * devices present and all reads return "0".
 989          * This would allow the ee1004 to be probed incorrectly.
 990          */
 991         if (port == 0)
 992                 i2c_register_spd(adap);
 993
 994         *padap = adap;
 995         return 0;
 996 }
 997
 998 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
 999                                     bool notify_imc)
1000 {
1001         struct i2c_piix4_adapdata *adapdata;
1002         int port;
1003         int retval;
1004
1005         if (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
1006             (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
1007              dev->revision >= 0x1F)) {
1008                 piix4_adapter_count = HUDSON2_MAIN_PORTS;
1009         } else {
1010                 piix4_adapter_count = PIIX4_MAX_ADAPTERS;
1011         }
1012
1013         for (port = 0; port < piix4_adapter_count; port++) {
1014                 u8 hw_port_nr = port == 0 ? 0 : port + 1;
1015
1016                 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
1017                                            hw_port_nr,
1018                                            piix4_main_port_names_sb800[port],
1019                                            &piix4_main_adapters[port]);
1020                 if (retval < 0)
1021                         goto error;
1022         }
1023
1024         return retval;
1025
1026 error:
1027         dev_err(&dev->dev,
1028                 "Error setting up SB800 adapters. Unregistering!\n");
1029         while (--port >= 0) {
1030                 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
1031                 if (adapdata->smba) {
1032                         i2c_del_adapter(piix4_main_adapters[port]);
1033                         kfree(adapdata);
1034                         kfree(piix4_main_adapters[port]);
1035                         piix4_main_adapters[port] = NULL;
1036                 }
1037         }
1038
1039         return retval;
1040 }
1041
1042 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
1043 {
1044         int retval;
1045         bool is_sb800 = false;
1046
1047         if ((dev->vendor == PCI_VENDOR_ID_ATI &&
1048              dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
1049              dev->revision >= 0x40) ||
1050             dev->vendor == PCI_VENDOR_ID_AMD ||
1051             dev->vendor == PCI_VENDOR_ID_HYGON) {
1052                 bool notify_imc = false;
1053                 is_sb800 = true;
1054
1055                 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
1056                      dev->vendor == PCI_VENDOR_ID_HYGON) &&
1057                     dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
1058                         u8 imc;
1059
1060                         /*
1061                          * Detect if IMC is active or not, this method is
1062                          * described on coreboot's AMD IMC notes
1063                          */
1064                         pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
1065                                                  0x40, &imc);
1066                         if (imc & 0x80)
1067                                 notify_imc = true;
1068                 }
1069
1070                 /* base address location etc changed in SB800 */
1071                 retval = piix4_setup_sb800(dev, id, 0);
1072                 if (retval < 0)
1073                         return retval;
1074
1075                 /*
1076                  * Try to register multiplexed main SMBus adapter,
1077                  * give up if we can't
1078                  */
1079                 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
1080                 if (retval < 0)
1081                         return retval;
1082         } else {
1083                 retval = piix4_setup(dev, id);
1084                 if (retval < 0)
1085                         return retval;
1086
1087                 /* Try to register main SMBus adapter, give up if we can't */
1088                 retval = piix4_add_adapter(dev, retval, false, 0, false, 0,
1089                                            "", &piix4_main_adapters[0]);
1090                 if (retval < 0)
1091                         return retval;
1092                 piix4_adapter_count = 1;
1093         }
1094
1095         /* Check for auxiliary SMBus on some AMD chipsets */
1096         retval = -ENODEV;
1097
1098         if (dev->vendor == PCI_VENDOR_ID_ATI &&
1099             dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
1100                 if (dev->revision < 0x40) {
1101                         retval = piix4_setup_aux(dev, id, 0x58);
1102                 } else {
1103                         /* SB800 added aux bus too */
1104                         retval = piix4_setup_sb800(dev, id, 1);
1105                 }
1106         }
1107
1108         if (dev->vendor == PCI_VENDOR_ID_AMD &&
1109             (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS ||
1110              dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) {
1111                 retval = piix4_setup_sb800(dev, id, 1);
1112         }
1113
1114         if (retval > 0) {
1115                 /* Try to add the aux adapter if it exists,
1116                  * piix4_add_adapter will clean up if this fails */
1117                 piix4_add_adapter(dev, retval, false, 0, false, 1,
1118                                   is_sb800 ? piix4_aux_port_name_sb800 : "",
1119                                   &piix4_aux_adapter);
1120         }
1121
1122         return 0;
1123 }
1124
1125 static void piix4_adap_remove(struct i2c_adapter *adap)
1126 {
1127         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
1128
1129         if (adapdata->smba) {
1130                 i2c_del_adapter(adap);
1131                 if (adapdata->port == (0 << piix4_port_shift_sb800))
1132                         release_region(adapdata->smba, SMBIOSIZE);
1133                 kfree(adapdata);
1134                 kfree(adap);
1135         }
1136 }
1137
1138 static void piix4_remove(struct pci_dev *dev)
1139 {
1140         int port = piix4_adapter_count;
1141
1142         while (--port >= 0) {
1143                 if (piix4_main_adapters[port]) {
1144                         piix4_adap_remove(piix4_main_adapters[port]);
1145                         piix4_main_adapters[port] = NULL;
1146                 }
1147         }
1148
1149         if (piix4_aux_adapter) {
1150                 piix4_adap_remove(piix4_aux_adapter);
1151                 piix4_aux_adapter = NULL;
1152         }
1153 }
1154
1155 static struct pci_driver piix4_driver = {
1156         .name           = "piix4_smbus",
1157         .id_table       = piix4_ids,
1158         .probe          = piix4_probe,
1159         .remove         = piix4_remove,
1160 };
1161
1162 module_pci_driver(piix4_driver);
1163
1164 MODULE_AUTHOR("Frodo Looijaard <[email protected]>");
1165 MODULE_AUTHOR("Philip Edelbrock <[email protected]>");
1166 MODULE_DESCRIPTION("PIIX4 SMBus driver");
1167 MODULE_LICENSE("GPL");