drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn31_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38
  39 #include "dml/dcn30/dcn30_fpu.h"
  40
  41 #include "dcn10/dcn10_ipp.h"
  42 #include "dcn30/dcn30_hubbub.h"
  43 #include "dcn31/dcn31_hubbub.h"
  44 #include "dcn30/dcn30_mpc.h"
  45 #include "dcn31/dcn31_hubp.h"
  46 #include "irq/dcn31/irq_service_dcn31.h"
  47 #include "dcn30/dcn30_dpp.h"
  48 #include "dcn31/dcn31_optc.h"
  49 #include "dcn20/dcn20_hwseq.h"
  50 #include "dcn30/dcn30_hwseq.h"
  51 #include "dce110/dce110_hwseq.h"
  52 #include "dcn30/dcn30_opp.h"
  53 #include "dcn20/dcn20_dsc.h"
  54 #include "dcn30/dcn30_vpg.h"
  55 #include "dcn30/dcn30_afmt.h"
  56 #include "dcn30/dcn30_dio_stream_encoder.h"
  57 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  58 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  59 #include "dcn31/dcn31_apg.h"
  60 #include "dcn31/dcn31_dio_link_encoder.h"
  61 #include "dcn31/dcn31_vpg.h"
  62 #include "dcn31/dcn31_afmt.h"
  63 #include "dce/dce_clock_source.h"
  64 #include "dce/dce_audio.h"
  65 #include "dce/dce_hwseq.h"
  66 #include "clk_mgr.h"
  67 #include "virtual/virtual_stream_encoder.h"
  68 #include "dce110/dce110_resource.h"
  69 #include "dml/display_mode_vba.h"
  70 #include "dml/dcn31/dcn31_fpu.h"
  71 #include "dcn31/dcn31_dccg.h"
  72 #include "dcn10/dcn10_resource.h"
  73 #include "dcn31/dcn31_panel_cntl.h"
  74
  75 #include "dcn30/dcn30_dwb.h"
  76 #include "dcn30/dcn30_mmhubbub.h"
  77
  78 #include "yellow_carp_offset.h"
  79 #include "dcn/dcn_3_1_2_offset.h"
  80 #include "dcn/dcn_3_1_2_sh_mask.h"
  81 #include "nbio/nbio_7_2_0_offset.h"
  82 #include "dpcs/dpcs_4_2_0_offset.h"
  83 #include "dpcs/dpcs_4_2_0_sh_mask.h"
  84 #include "mmhub/mmhub_2_3_0_offset.h"
  85 #include "mmhub/mmhub_2_3_0_sh_mask.h"
  86
  87
  88 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
  89 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
  90 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
  91 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
  92
  93 #include "reg_helper.h"
  94 #include "dce/dmub_abm.h"
  95 #include "dce/dmub_psr.h"
  96 #include "dce/dce_aux.h"
  97 #include "dce/dce_i2c.h"
  98 #include "dce/dmub_replay.h"
  99
 100 #include "dml/dcn30/display_mode_vba_30.h"
 101 #include "vm_helper.h"
 102 #include "dcn20/dcn20_vmid.h"
 103
 104 #include "link_enc_cfg.h"
 105
 106 #define DC_LOGGER \
 107         dc->ctx->logger
 108 #define DC_LOGGER_INIT(logger)
 109
 110 enum dcn31_clk_src_array_id {
 111         DCN31_CLK_SRC_PLL0,
 112         DCN31_CLK_SRC_PLL1,
 113         DCN31_CLK_SRC_PLL2,
 114         DCN31_CLK_SRC_PLL3,
 115         DCN31_CLK_SRC_PLL4,
 116         DCN30_CLK_SRC_TOTAL
 117 };
 118
 119 /* begin *********************
 120  * macros to expend register list macro defined in HW object header file
 121  */
 122
 123 /* DCN */
 124 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 125
 126 #define BASE(seg) BASE_INNER(seg)
 127
 128 #define SR(reg_name)\
 129                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 130                                         reg ## reg_name
 131
 132 #define SRI(reg_name, block, id)\
 133         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 134                                         reg ## block ## id ## _ ## reg_name
 135
 136 #define SRI2(reg_name, block, id)\
 137         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 138                                         reg ## reg_name
 139
 140 #define SRIR(var_name, reg_name, block, id)\
 141         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 142                                         reg ## block ## id ## _ ## reg_name
 143
 144 #define SRII(reg_name, block, id)\
 145         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 146                                         reg ## block ## id ## _ ## reg_name
 147
 148 #define SRII_MPC_RMU(reg_name, block, id)\
 149         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 150                                         reg ## block ## id ## _ ## reg_name
 151
 152 #define SRII_DWB(reg_name, temp_name, block, id)\
 153         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 154                                         reg ## block ## id ## _ ## temp_name
 155
 156 #define SF_DWB2(reg_name, block, id, field_name, post_fix)      \
 157         .field_name = reg_name ## __ ## field_name ## post_fix
 158
 159 #define DCCG_SRII(reg_name, block, id)\
 160         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 161                                         reg ## block ## id ## _ ## reg_name
 162
 163 #define VUPDATE_SRII(reg_name, block, id)\
 164         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 165                                         reg ## reg_name ## _ ## block ## id
 166
 167 /* NBIO */
 168 #define NBIO_BASE_INNER(seg) \
 169         NBIO_BASE__INST0_SEG ## seg
 170
 171 #define NBIO_BASE(seg) \
 172         NBIO_BASE_INNER(seg)
 173
 174 #define NBIO_SR(reg_name)\
 175                 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 176                                         regBIF_BX1_ ## reg_name
 177
 178 /* MMHUB */
 179 #define MMHUB_BASE_INNER(seg) \
 180         MMHUB_BASE__INST0_SEG ## seg
 181
 182 #define MMHUB_BASE(seg) \
 183         MMHUB_BASE_INNER(seg)
 184
 185 #define MMHUB_SR(reg_name)\
 186                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
 187                                         mm ## reg_name
 188
 189 /* CLOCK */
 190 #define CLK_BASE_INNER(seg) \
 191         CLK_BASE__INST0_SEG ## seg
 192
 193 #define CLK_BASE(seg) \
 194         CLK_BASE_INNER(seg)
 195
 196 #define CLK_SRI(reg_name, block, inst)\
 197         .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 198                                         reg ## block ## _ ## inst ## _ ## reg_name
 199
 200
 201 static const struct bios_registers bios_regs = {
 202                 NBIO_SR(BIOS_SCRATCH_3),
 203                 NBIO_SR(BIOS_SCRATCH_6)
 204 };
 205
 206 #define clk_src_regs(index, pllid)\
 207 [index] = {\
 208         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 209 }
 210
 211 static const struct dce110_clk_src_regs clk_src_regs[] = {
 212         clk_src_regs(0, A),
 213         clk_src_regs(1, B),
 214         clk_src_regs(2, C),
 215         clk_src_regs(3, D),
 216         clk_src_regs(4, E)
 217 };
 218 /*pll_id being rempped in dmub, in driver it is logical instance*/
 219 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
 220         clk_src_regs(0, A),
 221         clk_src_regs(1, B),
 222         clk_src_regs(2, F),
 223         clk_src_regs(3, G),
 224         clk_src_regs(4, E)
 225 };
 226
 227 static const struct dce110_clk_src_shift cs_shift = {
 228                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 229 };
 230
 231 static const struct dce110_clk_src_mask cs_mask = {
 232                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 233 };
 234
 235 #define abm_regs(id)\
 236 [id] = {\
 237                 ABM_DCN302_REG_LIST(id)\
 238 }
 239
 240 static const struct dce_abm_registers abm_regs[] = {
 241                 abm_regs(0),
 242                 abm_regs(1),
 243                 abm_regs(2),
 244                 abm_regs(3),
 245 };
 246
 247 static const struct dce_abm_shift abm_shift = {
 248                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 249 };
 250
 251 static const struct dce_abm_mask abm_mask = {
 252                 ABM_MASK_SH_LIST_DCN30(_MASK)
 253 };
 254
 255 #define audio_regs(id)\
 256 [id] = {\
 257                 AUD_COMMON_REG_LIST(id)\
 258 }
 259
 260 static const struct dce_audio_registers audio_regs[] = {
 261         audio_regs(0),
 262         audio_regs(1),
 263         audio_regs(2),
 264         audio_regs(3),
 265         audio_regs(4),
 266         audio_regs(5),
 267         audio_regs(6)
 268 };
 269
 270 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 271                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 272                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 273                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 274
 275 static const struct dce_audio_shift audio_shift = {
 276                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 277 };
 278
 279 static const struct dce_audio_mask audio_mask = {
 280                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 281 };
 282
 283 #define vpg_regs(id)\
 284 [id] = {\
 285         VPG_DCN31_REG_LIST(id)\
 286 }
 287
 288 static const struct dcn31_vpg_registers vpg_regs[] = {
 289         vpg_regs(0),
 290         vpg_regs(1),
 291         vpg_regs(2),
 292         vpg_regs(3),
 293         vpg_regs(4),
 294         vpg_regs(5),
 295         vpg_regs(6),
 296         vpg_regs(7),
 297         vpg_regs(8),
 298         vpg_regs(9),
 299 };
 300
 301 static const struct dcn31_vpg_shift vpg_shift = {
 302         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 303 };
 304
 305 static const struct dcn31_vpg_mask vpg_mask = {
 306         DCN31_VPG_MASK_SH_LIST(_MASK)
 307 };
 308
 309 #define afmt_regs(id)\
 310 [id] = {\
 311         AFMT_DCN31_REG_LIST(id)\
 312 }
 313
 314 static const struct dcn31_afmt_registers afmt_regs[] = {
 315         afmt_regs(0),
 316         afmt_regs(1),
 317         afmt_regs(2),
 318         afmt_regs(3),
 319         afmt_regs(4),
 320         afmt_regs(5)
 321 };
 322
 323 static const struct dcn31_afmt_shift afmt_shift = {
 324         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 325 };
 326
 327 static const struct dcn31_afmt_mask afmt_mask = {
 328         DCN31_AFMT_MASK_SH_LIST(_MASK)
 329 };
 330
 331 #define apg_regs(id)\
 332 [id] = {\
 333         APG_DCN31_REG_LIST(id)\
 334 }
 335
 336 static const struct dcn31_apg_registers apg_regs[] = {
 337         apg_regs(0),
 338         apg_regs(1),
 339         apg_regs(2),
 340         apg_regs(3)
 341 };
 342
 343 static const struct dcn31_apg_shift apg_shift = {
 344         DCN31_APG_MASK_SH_LIST(__SHIFT)
 345 };
 346
 347 static const struct dcn31_apg_mask apg_mask = {
 348                 DCN31_APG_MASK_SH_LIST(_MASK)
 349 };
 350
 351 #define stream_enc_regs(id)\
 352 [id] = {\
 353         SE_DCN3_REG_LIST(id)\
 354 }
 355
 356 /* Some encoders won't be initialized here - but they're logical, not physical. */
 357 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
 358         stream_enc_regs(0),
 359         stream_enc_regs(1),
 360         stream_enc_regs(2),
 361         stream_enc_regs(3),
 362         stream_enc_regs(4)
 363 };
 364
 365 static const struct dcn10_stream_encoder_shift se_shift = {
 366                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 367 };
 368
 369 static const struct dcn10_stream_encoder_mask se_mask = {
 370                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 371 };
 372
 373
 374 #define aux_regs(id)\
 375 [id] = {\
 376         DCN2_AUX_REG_LIST(id)\
 377 }
 378
 379 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 380                 aux_regs(0),
 381                 aux_regs(1),
 382                 aux_regs(2),
 383                 aux_regs(3),
 384                 aux_regs(4)
 385 };
 386
 387 #define hpd_regs(id)\
 388 [id] = {\
 389         HPD_REG_LIST(id)\
 390 }
 391
 392 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 393                 hpd_regs(0),
 394                 hpd_regs(1),
 395                 hpd_regs(2),
 396                 hpd_regs(3),
 397                 hpd_regs(4)
 398 };
 399
 400 #define link_regs(id, phyid)\
 401 [id] = {\
 402         LE_DCN31_REG_LIST(id), \
 403         UNIPHY_DCN2_REG_LIST(phyid), \
 404         DPCS_DCN31_REG_LIST(id), \
 405 }
 406
 407 static const struct dce110_aux_registers_shift aux_shift = {
 408         DCN_AUX_MASK_SH_LIST(__SHIFT)
 409 };
 410
 411 static const struct dce110_aux_registers_mask aux_mask = {
 412         DCN_AUX_MASK_SH_LIST(_MASK)
 413 };
 414
 415 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 416         link_regs(0, A),
 417         link_regs(1, B),
 418         link_regs(2, C),
 419         link_regs(3, D),
 420         link_regs(4, E)
 421 };
 422
 423 static const struct dcn10_link_enc_shift le_shift = {
 424         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 425         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 426 };
 427
 428 static const struct dcn10_link_enc_mask le_mask = {
 429         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 430         DPCS_DCN31_MASK_SH_LIST(_MASK)
 431 };
 432
 433 #define hpo_dp_stream_encoder_reg_list(id)\
 434 [id] = {\
 435         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 436 }
 437
 438 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 439         hpo_dp_stream_encoder_reg_list(0),
 440         hpo_dp_stream_encoder_reg_list(1),
 441         hpo_dp_stream_encoder_reg_list(2),
 442         hpo_dp_stream_encoder_reg_list(3),
 443 };
 444
 445 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 446         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 447 };
 448
 449 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 450         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 451 };
 452
 453 #define hpo_dp_link_encoder_reg_list(id)\
 454 [id] = {\
 455         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 456         DCN3_1_RDPCSTX_REG_LIST(0),\
 457         DCN3_1_RDPCSTX_REG_LIST(1),\
 458         DCN3_1_RDPCSTX_REG_LIST(2),\
 459         DCN3_1_RDPCSTX_REG_LIST(3),\
 460         DCN3_1_RDPCSTX_REG_LIST(4)\
 461 }
 462
 463 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 464         hpo_dp_link_encoder_reg_list(0),
 465         hpo_dp_link_encoder_reg_list(1),
 466 };
 467
 468 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 469         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 470 };
 471
 472 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 473         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 474 };
 475
 476 #define dpp_regs(id)\
 477 [id] = {\
 478         DPP_REG_LIST_DCN30(id),\
 479 }
 480
 481 static const struct dcn3_dpp_registers dpp_regs[] = {
 482         dpp_regs(0),
 483         dpp_regs(1),
 484         dpp_regs(2),
 485         dpp_regs(3)
 486 };
 487
 488 static const struct dcn3_dpp_shift tf_shift = {
 489                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 490 };
 491
 492 static const struct dcn3_dpp_mask tf_mask = {
 493                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 494 };
 495
 496 #define opp_regs(id)\
 497 [id] = {\
 498         OPP_REG_LIST_DCN30(id),\
 499 }
 500
 501 static const struct dcn20_opp_registers opp_regs[] = {
 502         opp_regs(0),
 503         opp_regs(1),
 504         opp_regs(2),
 505         opp_regs(3)
 506 };
 507
 508 static const struct dcn20_opp_shift opp_shift = {
 509         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 510 };
 511
 512 static const struct dcn20_opp_mask opp_mask = {
 513         OPP_MASK_SH_LIST_DCN20(_MASK)
 514 };
 515
 516 #define aux_engine_regs(id)\
 517 [id] = {\
 518         AUX_COMMON_REG_LIST0(id), \
 519         .AUXN_IMPCAL = 0, \
 520         .AUXP_IMPCAL = 0, \
 521         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 522 }
 523
 524 static const struct dce110_aux_registers aux_engine_regs[] = {
 525                 aux_engine_regs(0),
 526                 aux_engine_regs(1),
 527                 aux_engine_regs(2),
 528                 aux_engine_regs(3),
 529                 aux_engine_regs(4)
 530 };
 531
 532 #define dwbc_regs_dcn3(id)\
 533 [id] = {\
 534         DWBC_COMMON_REG_LIST_DCN30(id),\
 535 }
 536
 537 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 538         dwbc_regs_dcn3(0),
 539 };
 540
 541 static const struct dcn30_dwbc_shift dwbc30_shift = {
 542         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 543 };
 544
 545 static const struct dcn30_dwbc_mask dwbc30_mask = {
 546         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 547 };
 548
 549 #define mcif_wb_regs_dcn3(id)\
 550 [id] = {\
 551         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 552 }
 553
 554 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 555         mcif_wb_regs_dcn3(0)
 556 };
 557
 558 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 559         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 560 };
 561
 562 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 563         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 564 };
 565
 566 #define dsc_regsDCN20(id)\
 567 [id] = {\
 568         DSC_REG_LIST_DCN20(id)\
 569 }
 570
 571 static const struct dcn20_dsc_registers dsc_regs[] = {
 572         dsc_regsDCN20(0),
 573         dsc_regsDCN20(1),
 574         dsc_regsDCN20(2)
 575 };
 576
 577 static const struct dcn20_dsc_shift dsc_shift = {
 578         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 579 };
 580
 581 static const struct dcn20_dsc_mask dsc_mask = {
 582         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 583 };
 584
 585 static const struct dcn30_mpc_registers mpc_regs = {
 586                 MPC_REG_LIST_DCN3_0(0),
 587                 MPC_REG_LIST_DCN3_0(1),
 588                 MPC_REG_LIST_DCN3_0(2),
 589                 MPC_REG_LIST_DCN3_0(3),
 590                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 591                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 592                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 593                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 594                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 595                 MPC_RMU_REG_LIST_DCN3AG(0),
 596                 MPC_RMU_REG_LIST_DCN3AG(1),
 597                 //MPC_RMU_REG_LIST_DCN3AG(2),
 598                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 599 };
 600
 601 static const struct dcn30_mpc_shift mpc_shift = {
 602         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 603 };
 604
 605 static const struct dcn30_mpc_mask mpc_mask = {
 606         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 607 };
 608
 609 #define optc_regs(id)\
 610 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 611
 612 static const struct dcn_optc_registers optc_regs[] = {
 613         optc_regs(0),
 614         optc_regs(1),
 615         optc_regs(2),
 616         optc_regs(3)
 617 };
 618
 619 static const struct dcn_optc_shift optc_shift = {
 620         OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 621 };
 622
 623 static const struct dcn_optc_mask optc_mask = {
 624         OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 625 };
 626
 627 #define hubp_regs(id)\
 628 [id] = {\
 629         HUBP_REG_LIST_DCN30(id)\
 630 }
 631
 632 static const struct dcn_hubp2_registers hubp_regs[] = {
 633                 hubp_regs(0),
 634                 hubp_regs(1),
 635                 hubp_regs(2),
 636                 hubp_regs(3)
 637 };
 638
 639
 640 static const struct dcn_hubp2_shift hubp_shift = {
 641                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 642 };
 643
 644 static const struct dcn_hubp2_mask hubp_mask = {
 645                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 646 };
 647 static const struct dcn_hubbub_registers hubbub_reg = {
 648                 HUBBUB_REG_LIST_DCN31(0)
 649 };
 650
 651 static const struct dcn_hubbub_shift hubbub_shift = {
 652                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 653 };
 654
 655 static const struct dcn_hubbub_mask hubbub_mask = {
 656                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 657 };
 658
 659 static const struct dccg_registers dccg_regs = {
 660                 DCCG_REG_LIST_DCN31()
 661 };
 662
 663 static const struct dccg_shift dccg_shift = {
 664                 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 665 };
 666
 667 static const struct dccg_mask dccg_mask = {
 668                 DCCG_MASK_SH_LIST_DCN31(_MASK)
 669 };
 670
 671
 672 #define SRII2(reg_name_pre, reg_name_post, id)\
 673         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 674                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 675                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 676
 677
 678 #define HWSEQ_DCN31_REG_LIST()\
 679         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 680         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 681         SR(DIO_MEM_PWR_CTRL), \
 682         SR(ODM_MEM_PWR_CTRL3), \
 683         SR(DMU_MEM_PWR_CNTL), \
 684         SR(MMHUBBUB_MEM_PWR_CNTL), \
 685         SR(DCCG_GATE_DISABLE_CNTL), \
 686         SR(DCCG_GATE_DISABLE_CNTL2), \
 687         SR(DCFCLK_CNTL),\
 688         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 689         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 690         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 691         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 692         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 693         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 694         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 695         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 696         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 697         SR(MICROSECOND_TIME_BASE_DIV), \
 698         SR(MILLISECOND_TIME_BASE_DIV), \
 699         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 700         SR(RBBMIF_TIMEOUT_DIS), \
 701         SR(RBBMIF_TIMEOUT_DIS_2), \
 702         SR(DCHUBBUB_CRC_CTRL), \
 703         SR(DPP_TOP0_DPP_CRC_CTRL), \
 704         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 705         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 706         SR(MPC_CRC_CTRL), \
 707         SR(MPC_CRC_RESULT_GB), \
 708         SR(MPC_CRC_RESULT_C), \
 709         SR(MPC_CRC_RESULT_AR), \
 710         SR(DOMAIN0_PG_CONFIG), \
 711         SR(DOMAIN1_PG_CONFIG), \
 712         SR(DOMAIN2_PG_CONFIG), \
 713         SR(DOMAIN3_PG_CONFIG), \
 714         SR(DOMAIN16_PG_CONFIG), \
 715         SR(DOMAIN17_PG_CONFIG), \
 716         SR(DOMAIN18_PG_CONFIG), \
 717         SR(DOMAIN0_PG_STATUS), \
 718         SR(DOMAIN1_PG_STATUS), \
 719         SR(DOMAIN2_PG_STATUS), \
 720         SR(DOMAIN3_PG_STATUS), \
 721         SR(DOMAIN16_PG_STATUS), \
 722         SR(DOMAIN17_PG_STATUS), \
 723         SR(DOMAIN18_PG_STATUS), \
 724         SR(D1VGA_CONTROL), \
 725         SR(D2VGA_CONTROL), \
 726         SR(D3VGA_CONTROL), \
 727         SR(D4VGA_CONTROL), \
 728         SR(D5VGA_CONTROL), \
 729         SR(D6VGA_CONTROL), \
 730         SR(DC_IP_REQUEST_CNTL), \
 731         SR(AZALIA_AUDIO_DTO), \
 732         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 733         SR(HPO_TOP_HW_CONTROL)
 734
 735 static const struct dce_hwseq_registers hwseq_reg = {
 736                 HWSEQ_DCN31_REG_LIST()
 737 };
 738
 739 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 740         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 741         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 742         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 743         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 744         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 745         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 746         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 747         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 748         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 749         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 750         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 751         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 752         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 753         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 754         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 755         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 756         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 757         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 758         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 759         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 760         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 761         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 762         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 763         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 764         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 765         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 766         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 767         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 768         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 769         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 770         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 771         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 772         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 773
 774 static const struct dce_hwseq_shift hwseq_shift = {
 775                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 776 };
 777
 778 static const struct dce_hwseq_mask hwseq_mask = {
 779                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 780 };
 781 #define vmid_regs(id)\
 782 [id] = {\
 783                 DCN20_VMID_REG_LIST(id)\
 784 }
 785
 786 static const struct dcn_vmid_registers vmid_regs[] = {
 787         vmid_regs(0),
 788         vmid_regs(1),
 789         vmid_regs(2),
 790         vmid_regs(3),
 791         vmid_regs(4),
 792         vmid_regs(5),
 793         vmid_regs(6),
 794         vmid_regs(7),
 795         vmid_regs(8),
 796         vmid_regs(9),
 797         vmid_regs(10),
 798         vmid_regs(11),
 799         vmid_regs(12),
 800         vmid_regs(13),
 801         vmid_regs(14),
 802         vmid_regs(15)
 803 };
 804
 805 static const struct dcn20_vmid_shift vmid_shifts = {
 806                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 807 };
 808
 809 static const struct dcn20_vmid_mask vmid_masks = {
 810                 DCN20_VMID_MASK_SH_LIST(_MASK)
 811 };
 812
 813 static const struct resource_caps res_cap_dcn31 = {
 814         .num_timing_generator = 4,
 815         .num_opp = 4,
 816         .num_video_plane = 4,
 817         .num_audio = 5,
 818         .num_stream_encoder = 5,
 819         .num_dig_link_enc = 5,
 820         .num_hpo_dp_stream_encoder = 4,
 821         .num_hpo_dp_link_encoder = 2,
 822         .num_pll = 5,
 823         .num_dwb = 1,
 824         .num_ddc = 5,
 825         .num_vmid = 16,
 826         .num_mpc_3dlut = 2,
 827         .num_dsc = 3,
 828 };
 829
 830 static const struct dc_plane_cap plane_cap = {
 831         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 832         .per_pixel_alpha = true,
 833
 834         .pixel_format_support = {
 835                         .argb8888 = true,
 836                         .nv12 = true,
 837                         .fp16 = true,
 838                         .p010 = true,
 839                         .ayuv = false,
 840         },
 841
 842         .max_upscale_factor = {
 843                         .argb8888 = 16000,
 844                         .nv12 = 16000,
 845                         .fp16 = 16000
 846         },
 847
 848         // 6:1 downscaling ratio: 1000/6 = 166.666
 849         .max_downscale_factor = {
 850                         .argb8888 = 167,
 851                         .nv12 = 167,
 852                         .fp16 = 167
 853         },
 854         64,
 855         64
 856 };
 857
 858 static const struct dc_debug_options debug_defaults_drv = {
 859         .disable_dmcu = true,
 860         .force_abm_enable = false,
 861         .timing_trace = false,
 862         .clock_trace = true,
 863         .disable_pplib_clock_request = false,
 864         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 865         .force_single_disp_pipe_split = false,
 866         .disable_dcc = DCC_ENABLE,
 867         .vsr_support = true,
 868         .performance_trace = false,
 869         .max_downscale_src_width = 4096,/*upto true 4K*/
 870         .disable_pplib_wm_range = false,
 871         .scl_reset_length10 = true,
 872         .sanity_checks = true,
 873         .underflow_assert_delay_us = 0xFFFFFFFF,
 874         .dwb_fi_phase = -1, // -1 = disable,
 875         .dmub_command_table = true,
 876         .pstate_enabled = true,
 877         .use_max_lb = true,
 878         .enable_mem_low_power = {
 879                 .bits = {
 880                         .vga = true,
 881                         .i2c = true,
 882                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
 883                         .dscl = true,
 884                         .cm = true,
 885                         .mpc = true,
 886                         .optc = true,
 887                         .vpg = true,
 888                         .afmt = true,
 889                 }
 890         },
 891         .disable_z10 = true,
 892         .enable_legacy_fast_update = true,
 893         .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
 894         .dml_hostvm_override = DML_HOSTVM_NO_OVERRIDE,
 895         .using_dml2 = false,
 896 };
 897
 898 static const struct dc_panel_config panel_config_defaults = {
 899         .psr = {
 900                 .disable_psr = false,
 901                 .disallow_psrsu = false,
 902                 .disallow_replay = false,
 903         },
 904         .ilr = {
 905                 .optimize_edp_link_rate = true,
 906         },
 907 };
 908
 909 static void dcn31_dpp_destroy(struct dpp **dpp)
 910 {
 911         kfree(TO_DCN20_DPP(*dpp));
 912         *dpp = NULL;
 913 }
 914
 915 static struct dpp *dcn31_dpp_create(
 916         struct dc_context *ctx,
 917         uint32_t inst)
 918 {
 919         struct dcn3_dpp *dpp =
 920                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 921
 922         if (!dpp)
 923                 return NULL;
 924
 925         if (dpp3_construct(dpp, ctx, inst,
 926                         &dpp_regs[inst], &tf_shift, &tf_mask))
 927                 return &dpp->base;
 928
 929         BREAK_TO_DEBUGGER();
 930         kfree(dpp);
 931         return NULL;
 932 }
 933
 934 static struct output_pixel_processor *dcn31_opp_create(
 935         struct dc_context *ctx, uint32_t inst)
 936 {
 937         struct dcn20_opp *opp =
 938                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 939
 940         if (!opp) {
 941                 BREAK_TO_DEBUGGER();
 942                 return NULL;
 943         }
 944
 945         dcn20_opp_construct(opp, ctx, inst,
 946                         &opp_regs[inst], &opp_shift, &opp_mask);
 947         return &opp->base;
 948 }
 949
 950 static struct dce_aux *dcn31_aux_engine_create(
 951         struct dc_context *ctx,
 952         uint32_t inst)
 953 {
 954         struct aux_engine_dce110 *aux_engine =
 955                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 956
 957         if (!aux_engine)
 958                 return NULL;
 959
 960         dce110_aux_engine_construct(aux_engine, ctx, inst,
 961                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 962                                     &aux_engine_regs[inst],
 963                                         &aux_mask,
 964                                         &aux_shift,
 965                                         ctx->dc->caps.extended_aux_timeout_support);
 966
 967         return &aux_engine->base;
 968 }
 969 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 970
 971 static const struct dce_i2c_registers i2c_hw_regs[] = {
 972                 i2c_inst_regs(1),
 973                 i2c_inst_regs(2),
 974                 i2c_inst_regs(3),
 975                 i2c_inst_regs(4),
 976                 i2c_inst_regs(5),
 977 };
 978
 979 static const struct dce_i2c_shift i2c_shifts = {
 980                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 981 };
 982
 983 static const struct dce_i2c_mask i2c_masks = {
 984                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 985 };
 986
 987 static struct dce_i2c_hw *dcn31_i2c_hw_create(
 988         struct dc_context *ctx,
 989         uint32_t inst)
 990 {
 991         struct dce_i2c_hw *dce_i2c_hw =
 992                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 993
 994         if (!dce_i2c_hw)
 995                 return NULL;
 996
 997         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 998                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 999
1000         return dce_i2c_hw;
1001 }
1002 static struct mpc *dcn31_mpc_create(
1003                 struct dc_context *ctx,
1004                 int num_mpcc,
1005                 int num_rmu)
1006 {
1007         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1008                                           GFP_KERNEL);
1009
1010         if (!mpc30)
1011                 return NULL;
1012
1013         dcn30_mpc_construct(mpc30, ctx,
1014                         &mpc_regs,
1015                         &mpc_shift,
1016                         &mpc_mask,
1017                         num_mpcc,
1018                         num_rmu);
1019
1020         return &mpc30->base;
1021 }
1022
1023 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1024 {
1025         int i;
1026
1027         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1028                                           GFP_KERNEL);
1029
1030         if (!hubbub3)
1031                 return NULL;
1032
1033         hubbub31_construct(hubbub3, ctx,
1034                         &hubbub_reg,
1035                         &hubbub_shift,
1036                         &hubbub_mask,
1037                         dcn3_1_ip.det_buffer_size_kbytes,
1038                         dcn3_1_ip.pixel_chunk_size_kbytes,
1039                         dcn3_1_ip.config_return_buffer_size_in_kbytes);
1040
1041
1042         for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1043                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1044
1045                 vmid->ctx = ctx;
1046
1047                 vmid->regs = &vmid_regs[i];
1048                 vmid->shifts = &vmid_shifts;
1049                 vmid->masks = &vmid_masks;
1050         }
1051
1052         return &hubbub3->base;
1053 }
1054
1055 static struct timing_generator *dcn31_timing_generator_create(
1056                 struct dc_context *ctx,
1057                 uint32_t instance)
1058 {
1059         struct optc *tgn10 =
1060                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1061
1062         if (!tgn10)
1063                 return NULL;
1064
1065         tgn10->base.inst = instance;
1066         tgn10->base.ctx = ctx;
1067
1068         tgn10->tg_regs = &optc_regs[instance];
1069         tgn10->tg_shift = &optc_shift;
1070         tgn10->tg_mask = &optc_mask;
1071
1072         dcn31_timing_generator_init(tgn10);
1073
1074         return &tgn10->base;
1075 }
1076
1077 static const struct encoder_feature_support link_enc_feature = {
1078                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1079                 .max_hdmi_pixel_clock = 600000,
1080                 .hdmi_ycbcr420_supported = true,
1081                 .dp_ycbcr420_supported = true,
1082                 .fec_supported = true,
1083                 .flags.bits.IS_HBR2_CAPABLE = true,
1084                 .flags.bits.IS_HBR3_CAPABLE = true,
1085                 .flags.bits.IS_TPS3_CAPABLE = true,
1086                 .flags.bits.IS_TPS4_CAPABLE = true
1087 };
1088
1089 static struct link_encoder *dcn31_link_encoder_create(
1090         struct dc_context *ctx,
1091         const struct encoder_init_data *enc_init_data)
1092 {
1093         struct dcn20_link_encoder *enc20 =
1094                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1095
1096         if (!enc20)
1097                 return NULL;
1098
1099         dcn31_link_encoder_construct(enc20,
1100                         enc_init_data,
1101                         &link_enc_feature,
1102                         &link_enc_regs[enc_init_data->transmitter],
1103                         &link_enc_aux_regs[enc_init_data->channel - 1],
1104                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1105                         &le_shift,
1106                         &le_mask);
1107
1108         return &enc20->enc10.base;
1109 }
1110
1111 /* Create a minimal link encoder object not associated with a particular
1112  * physical connector.
1113  * resource_funcs.link_enc_create_minimal
1114  */
1115 static struct link_encoder *dcn31_link_enc_create_minimal(
1116                 struct dc_context *ctx, enum engine_id eng_id)
1117 {
1118         struct dcn20_link_encoder *enc20;
1119
1120         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1121                 return NULL;
1122
1123         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1124         if (!enc20)
1125                 return NULL;
1126
1127         dcn31_link_encoder_construct_minimal(
1128                         enc20,
1129                         ctx,
1130                         &link_enc_feature,
1131                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1132                         eng_id);
1133
1134         return &enc20->enc10.base;
1135 }
1136
1137 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1138 {
1139         struct dcn31_panel_cntl *panel_cntl =
1140                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1141
1142         if (!panel_cntl)
1143                 return NULL;
1144
1145         dcn31_panel_cntl_construct(panel_cntl, init_data);
1146
1147         return &panel_cntl->base;
1148 }
1149
1150 static void read_dce_straps(
1151         struct dc_context *ctx,
1152         struct resource_straps *straps)
1153 {
1154         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1155                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1156
1157 }
1158
1159 static struct audio *dcn31_create_audio(
1160                 struct dc_context *ctx, unsigned int inst)
1161 {
1162         return dce_audio_create(ctx, inst,
1163                         &audio_regs[inst], &audio_shift, &audio_mask);
1164 }
1165
1166 static struct vpg *dcn31_vpg_create(
1167         struct dc_context *ctx,
1168         uint32_t inst)
1169 {
1170         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1171
1172         if (!vpg31)
1173                 return NULL;
1174
1175         vpg31_construct(vpg31, ctx, inst,
1176                         &vpg_regs[inst],
1177                         &vpg_shift,
1178                         &vpg_mask);
1179
1180         return &vpg31->base;
1181 }
1182
1183 static struct afmt *dcn31_afmt_create(
1184         struct dc_context *ctx,
1185         uint32_t inst)
1186 {
1187         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1188
1189         if (!afmt31)
1190                 return NULL;
1191
1192         afmt31_construct(afmt31, ctx, inst,
1193                         &afmt_regs[inst],
1194                         &afmt_shift,
1195                         &afmt_mask);
1196
1197         // Light sleep by default, no need to power down here
1198
1199         return &afmt31->base;
1200 }
1201
1202 static struct apg *dcn31_apg_create(
1203         struct dc_context *ctx,
1204         uint32_t inst)
1205 {
1206         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1207
1208         if (!apg31)
1209                 return NULL;
1210
1211         apg31_construct(apg31, ctx, inst,
1212                         &apg_regs[inst],
1213                         &apg_shift,
1214                         &apg_mask);
1215
1216         return &apg31->base;
1217 }
1218
1219 static struct stream_encoder *dcn31_stream_encoder_create(
1220         enum engine_id eng_id,
1221         struct dc_context *ctx)
1222 {
1223         struct dcn10_stream_encoder *enc1;
1224         struct vpg *vpg;
1225         struct afmt *afmt;
1226         int vpg_inst;
1227         int afmt_inst;
1228
1229         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1230         if (eng_id <= ENGINE_ID_DIGF) {
1231                 vpg_inst = eng_id;
1232                 afmt_inst = eng_id;
1233         } else
1234                 return NULL;
1235
1236         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1237         vpg = dcn31_vpg_create(ctx, vpg_inst);
1238         afmt = dcn31_afmt_create(ctx, afmt_inst);
1239
1240         if (!enc1 || !vpg || !afmt) {
1241                 kfree(enc1);
1242                 kfree(vpg);
1243                 kfree(afmt);
1244                 return NULL;
1245         }
1246
1247         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1248                                         eng_id, vpg, afmt,
1249                                         &stream_enc_regs[eng_id],
1250                                         &se_shift, &se_mask);
1251
1252         return &enc1->base;
1253 }
1254
1255 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1256         enum engine_id eng_id,
1257         struct dc_context *ctx)
1258 {
1259         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1260         struct vpg *vpg;
1261         struct apg *apg;
1262         uint32_t hpo_dp_inst;
1263         uint32_t vpg_inst;
1264         uint32_t apg_inst;
1265
1266         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1267         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1268
1269         /* Mapping of VPG register blocks to HPO DP block instance:
1270          * VPG[6] -> HPO_DP[0]
1271          * VPG[7] -> HPO_DP[1]
1272          * VPG[8] -> HPO_DP[2]
1273          * VPG[9] -> HPO_DP[3]
1274          */
1275         vpg_inst = hpo_dp_inst + 6;
1276
1277         /* Mapping of APG register blocks to HPO DP block instance:
1278          * APG[0] -> HPO_DP[0]
1279          * APG[1] -> HPO_DP[1]
1280          * APG[2] -> HPO_DP[2]
1281          * APG[3] -> HPO_DP[3]
1282          */
1283         apg_inst = hpo_dp_inst;
1284
1285         /* allocate HPO stream encoder and create VPG sub-block */
1286         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1287         vpg = dcn31_vpg_create(ctx, vpg_inst);
1288         apg = dcn31_apg_create(ctx, apg_inst);
1289
1290         if (!hpo_dp_enc31 || !vpg || !apg) {
1291                 kfree(hpo_dp_enc31);
1292                 kfree(vpg);
1293                 kfree(apg);
1294                 return NULL;
1295         }
1296
1297         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1298                                         hpo_dp_inst, eng_id, vpg, apg,
1299                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1300                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1301
1302         return &hpo_dp_enc31->base;
1303 }
1304
1305 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1306         uint8_t inst,
1307         struct dc_context *ctx)
1308 {
1309         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1310
1311         /* allocate HPO link encoder */
1312         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1313         if (!hpo_dp_enc31)
1314                 return NULL; /* out of memory */
1315
1316         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1317                                         &hpo_dp_link_enc_regs[inst],
1318                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1319
1320         return &hpo_dp_enc31->base;
1321 }
1322
1323 static struct dce_hwseq *dcn31_hwseq_create(
1324         struct dc_context *ctx)
1325 {
1326         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1327
1328         if (hws) {
1329                 hws->ctx = ctx;
1330                 hws->regs = &hwseq_reg;
1331                 hws->shifts = &hwseq_shift;
1332                 hws->masks = &hwseq_mask;
1333         }
1334         return hws;
1335 }
1336 static const struct resource_create_funcs res_create_funcs = {
1337         .read_dce_straps = read_dce_straps,
1338         .create_audio = dcn31_create_audio,
1339         .create_stream_encoder = dcn31_stream_encoder_create,
1340         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1341         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1342         .create_hwseq = dcn31_hwseq_create,
1343 };
1344
1345 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1346 {
1347         unsigned int i;
1348
1349         for (i = 0; i < pool->base.stream_enc_count; i++) {
1350                 if (pool->base.stream_enc[i] != NULL) {
1351                         if (pool->base.stream_enc[i]->vpg != NULL) {
1352                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1353                                 pool->base.stream_enc[i]->vpg = NULL;
1354                         }
1355                         if (pool->base.stream_enc[i]->afmt != NULL) {
1356                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1357                                 pool->base.stream_enc[i]->afmt = NULL;
1358                         }
1359                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1360                         pool->base.stream_enc[i] = NULL;
1361                 }
1362         }
1363
1364         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1365                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1366                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1367                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1368                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1369                         }
1370                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1371                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1372                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1373                         }
1374                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1375                         pool->base.hpo_dp_stream_enc[i] = NULL;
1376                 }
1377         }
1378
1379         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1380                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1381                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1382                         pool->base.hpo_dp_link_enc[i] = NULL;
1383                 }
1384         }
1385
1386         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1387                 if (pool->base.dscs[i] != NULL)
1388                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1389         }
1390
1391         if (pool->base.mpc != NULL) {
1392                 kfree(TO_DCN20_MPC(pool->base.mpc));
1393                 pool->base.mpc = NULL;
1394         }
1395         if (pool->base.hubbub != NULL) {
1396                 kfree(pool->base.hubbub);
1397                 pool->base.hubbub = NULL;
1398         }
1399         for (i = 0; i < pool->base.pipe_count; i++) {
1400                 if (pool->base.dpps[i] != NULL)
1401                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1402
1403                 if (pool->base.ipps[i] != NULL)
1404                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1405
1406                 if (pool->base.hubps[i] != NULL) {
1407                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1408                         pool->base.hubps[i] = NULL;
1409                 }
1410
1411                 if (pool->base.irqs != NULL) {
1412                         dal_irq_service_destroy(&pool->base.irqs);
1413                 }
1414         }
1415
1416         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1417                 if (pool->base.engines[i] != NULL)
1418                         dce110_engine_destroy(&pool->base.engines[i]);
1419                 if (pool->base.hw_i2cs[i] != NULL) {
1420                         kfree(pool->base.hw_i2cs[i]);
1421                         pool->base.hw_i2cs[i] = NULL;
1422                 }
1423                 if (pool->base.sw_i2cs[i] != NULL) {
1424                         kfree(pool->base.sw_i2cs[i]);
1425                         pool->base.sw_i2cs[i] = NULL;
1426                 }
1427         }
1428
1429         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1430                 if (pool->base.opps[i] != NULL)
1431                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1432         }
1433
1434         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1435                 if (pool->base.timing_generators[i] != NULL)    {
1436                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1437                         pool->base.timing_generators[i] = NULL;
1438                 }
1439         }
1440
1441         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1442                 if (pool->base.dwbc[i] != NULL) {
1443                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1444                         pool->base.dwbc[i] = NULL;
1445                 }
1446                 if (pool->base.mcif_wb[i] != NULL) {
1447                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1448                         pool->base.mcif_wb[i] = NULL;
1449                 }
1450         }
1451
1452         for (i = 0; i < pool->base.audio_count; i++) {
1453                 if (pool->base.audios[i])
1454                         dce_aud_destroy(&pool->base.audios[i]);
1455         }
1456
1457         for (i = 0; i < pool->base.clk_src_count; i++) {
1458                 if (pool->base.clock_sources[i] != NULL) {
1459                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1460                         pool->base.clock_sources[i] = NULL;
1461                 }
1462         }
1463
1464         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1465                 if (pool->base.mpc_lut[i] != NULL) {
1466                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1467                         pool->base.mpc_lut[i] = NULL;
1468                 }
1469                 if (pool->base.mpc_shaper[i] != NULL) {
1470                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1471                         pool->base.mpc_shaper[i] = NULL;
1472                 }
1473         }
1474
1475         if (pool->base.dp_clock_source != NULL) {
1476                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1477                 pool->base.dp_clock_source = NULL;
1478         }
1479
1480         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1481                 if (pool->base.multiple_abms[i] != NULL)
1482                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1483         }
1484
1485         if (pool->base.psr != NULL)
1486                 dmub_psr_destroy(&pool->base.psr);
1487
1488         if (pool->base.replay != NULL)
1489                 dmub_replay_destroy(&pool->base.replay);
1490
1491         if (pool->base.dccg != NULL)
1492                 dcn_dccg_destroy(&pool->base.dccg);
1493 }
1494
1495 static struct hubp *dcn31_hubp_create(
1496         struct dc_context *ctx,
1497         uint32_t inst)
1498 {
1499         struct dcn20_hubp *hubp2 =
1500                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1501
1502         if (!hubp2)
1503                 return NULL;
1504
1505         if (hubp31_construct(hubp2, ctx, inst,
1506                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1507                 return &hubp2->base;
1508
1509         BREAK_TO_DEBUGGER();
1510         kfree(hubp2);
1511         return NULL;
1512 }
1513
1514 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1515 {
1516         int i;
1517         uint32_t pipe_count = pool->res_cap->num_dwb;
1518
1519         for (i = 0; i < pipe_count; i++) {
1520                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1521                                                     GFP_KERNEL);
1522
1523                 if (!dwbc30) {
1524                         dm_error("DC: failed to create dwbc30!\n");
1525                         return false;
1526                 }
1527
1528                 dcn30_dwbc_construct(dwbc30, ctx,
1529                                 &dwbc30_regs[i],
1530                                 &dwbc30_shift,
1531                                 &dwbc30_mask,
1532                                 i);
1533
1534                 pool->dwbc[i] = &dwbc30->base;
1535         }
1536         return true;
1537 }
1538
1539 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1540 {
1541         int i;
1542         uint32_t pipe_count = pool->res_cap->num_dwb;
1543
1544         for (i = 0; i < pipe_count; i++) {
1545                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1546                                                     GFP_KERNEL);
1547
1548                 if (!mcif_wb30) {
1549                         dm_error("DC: failed to create mcif_wb30!\n");
1550                         return false;
1551                 }
1552
1553                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1554                                 &mcif_wb30_regs[i],
1555                                 &mcif_wb30_shift,
1556                                 &mcif_wb30_mask,
1557                                 i);
1558
1559                 pool->mcif_wb[i] = &mcif_wb30->base;
1560         }
1561         return true;
1562 }
1563
1564 static struct display_stream_compressor *dcn31_dsc_create(
1565         struct dc_context *ctx, uint32_t inst)
1566 {
1567         struct dcn20_dsc *dsc =
1568                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1569
1570         if (!dsc) {
1571                 BREAK_TO_DEBUGGER();
1572                 return NULL;
1573         }
1574
1575         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1576         return &dsc->base;
1577 }
1578
1579 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1580 {
1581         struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1582
1583         dcn31_resource_destruct(dcn31_pool);
1584         kfree(dcn31_pool);
1585         *pool = NULL;
1586 }
1587
1588 static struct clock_source *dcn31_clock_source_create(
1589                 struct dc_context *ctx,
1590                 struct dc_bios *bios,
1591                 enum clock_source_id id,
1592                 const struct dce110_clk_src_regs *regs,
1593                 bool dp_clk_src)
1594 {
1595         struct dce110_clk_src *clk_src =
1596                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1597
1598         if (!clk_src)
1599                 return NULL;
1600
1601         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1602                         regs, &cs_shift, &cs_mask)) {
1603                 clk_src->base.dp_clk_src = dp_clk_src;
1604                 return &clk_src->base;
1605         }
1606
1607         kfree(clk_src);
1608         BREAK_TO_DEBUGGER();
1609         return NULL;
1610 }
1611
1612 static bool is_dual_plane(enum surface_pixel_format format)
1613 {
1614         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1615 }
1616
1617 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
1618                                           struct dc_state *context,
1619                                           display_e2e_pipe_params_st *pipes,
1620                                           bool fast_validate)
1621 {
1622         uint32_t pipe_cnt;
1623         int i;
1624
1625         dc_assert_fp_enabled();
1626
1627         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1628
1629         for (i = 0; i < pipe_cnt; i++) {
1630                 pipes[i].pipe.src.gpuvm = 1;
1631                 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {
1632                         //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1633                         pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled;
1634                 } else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_FALSE)
1635                         pipes[i].pipe.src.hostvm = false;
1636                 else if (dc->debug.dml_hostvm_override == DML_HOSTVM_OVERRIDE_TRUE)
1637                         pipes[i].pipe.src.hostvm = true;
1638         }
1639         return pipe_cnt;
1640 }
1641
1642 int dcn31_populate_dml_pipes_from_context(
1643         struct dc *dc, struct dc_state *context,
1644         display_e2e_pipe_params_st *pipes,
1645         bool fast_validate)
1646 {
1647         int i, pipe_cnt;
1648         struct resource_context *res_ctx = &context->res_ctx;
1649         struct pipe_ctx *pipe = 0;
1650         bool upscaled = false;
1651
1652         DC_FP_START();
1653         dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1654         DC_FP_END();
1655
1656         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1657                 struct dc_crtc_timing *timing;
1658
1659                 if (!res_ctx->pipe_ctx[i].stream)
1660                         continue;
1661                 pipe = &res_ctx->pipe_ctx[i];
1662                 timing = &pipe->stream->timing;
1663                 if (pipe->plane_state &&
1664                                 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1665                                 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1666                         upscaled = true;
1667
1668                 /*
1669                  * Immediate flip can be set dynamically after enabling the plane.
1670                  * We need to require support for immediate flip or underflow can be
1671                  * intermittently experienced depending on peak b/w requirements.
1672                  */
1673                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1674                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1675                 pipes[pipe_cnt].pipe.src.gpuvm = true;
1676                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1677                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1678                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1679                 DC_FP_START();
1680                 dcn31_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1681                 DC_FP_END();
1682
1683
1684                 if (pipes[pipe_cnt].dout.dsc_enable) {
1685                         switch (timing->display_color_depth) {
1686                         case COLOR_DEPTH_888:
1687                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1688                                 break;
1689                         case COLOR_DEPTH_101010:
1690                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1691                                 break;
1692                         case COLOR_DEPTH_121212:
1693                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1694                                 break;
1695                         default:
1696                                 ASSERT(0);
1697                                 break;
1698                         }
1699                 }
1700
1701                 pipe_cnt++;
1702         }
1703         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1704         dc->config.enable_4to1MPC = false;
1705         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1706                 if (is_dual_plane(pipe->plane_state->format)
1707                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1708                         dc->config.enable_4to1MPC = true;
1709                 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1710                         /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1711                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1712                         pipes[0].pipe.src.unbounded_req_mode = true;
1713                 }
1714         } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1715                         && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1716                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1717         } else if (context->stream_count >= 3 && upscaled) {
1718                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1719         }
1720
1721         return pipe_cnt;
1722 }
1723
1724 void dcn31_calculate_wm_and_dlg(
1725                 struct dc *dc, struct dc_state *context,
1726                 display_e2e_pipe_params_st *pipes,
1727                 int pipe_cnt,
1728                 int vlevel)
1729 {
1730         DC_FP_START();
1731         dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
1732         DC_FP_END();
1733 }
1734
1735 void
1736 dcn31_populate_dml_writeback_from_context(struct dc *dc,
1737                                           struct resource_context *res_ctx,
1738                                           display_e2e_pipe_params_st *pipes)
1739 {
1740         DC_FP_START();
1741         dcn30_populate_dml_writeback_from_context(dc, res_ctx, pipes);
1742         DC_FP_END();
1743 }
1744
1745 void
1746 dcn31_set_mcif_arb_params(struct dc *dc,
1747                           struct dc_state *context,
1748                           display_e2e_pipe_params_st *pipes,
1749                           int pipe_cnt)
1750 {
1751         DC_FP_START();
1752         dcn30_set_mcif_arb_params(dc, context, pipes, pipe_cnt);
1753         DC_FP_END();
1754 }
1755
1756 bool dcn31_validate_bandwidth(struct dc *dc,
1757                 struct dc_state *context,
1758                 bool fast_validate)
1759 {
1760         bool out = false;
1761
1762         BW_VAL_TRACE_SETUP();
1763
1764         int vlevel = 0;
1765         int pipe_cnt = 0;
1766         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1767         DC_LOGGER_INIT(dc->ctx->logger);
1768
1769         BW_VAL_TRACE_COUNT();
1770
1771         if (!pipes)
1772                 goto validate_fail;
1773
1774         DC_FP_START();
1775         out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
1776         DC_FP_END();
1777
1778         // Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
1779         if (pipe_cnt == 0)
1780                 fast_validate = false;
1781
1782         if (!out)
1783                 goto validate_fail;
1784
1785         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1786
1787         if (fast_validate) {
1788                 BW_VAL_TRACE_SKIP(fast);
1789                 goto validate_out;
1790         }
1791         if (dc->res_pool->funcs->calculate_wm_and_dlg)
1792                 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1793
1794         BW_VAL_TRACE_END_WATERMARKS();
1795
1796         goto validate_out;
1797
1798 validate_fail:
1799         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1800                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1801
1802         BW_VAL_TRACE_SKIP(fail);
1803         out = false;
1804
1805 validate_out:
1806         kfree(pipes);
1807
1808         BW_VAL_TRACE_FINISH();
1809
1810         return out;
1811 }
1812
1813 static void dcn31_get_panel_config_defaults(struct dc_panel_config *panel_config)
1814 {
1815         *panel_config = panel_config_defaults;
1816 }
1817
1818 static struct dc_cap_funcs cap_funcs = {
1819         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1820 };
1821
1822 static struct resource_funcs dcn31_res_pool_funcs = {
1823         .destroy = dcn31_destroy_resource_pool,
1824         .link_enc_create = dcn31_link_encoder_create,
1825         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1826         .link_encs_assign = link_enc_cfg_link_encs_assign,
1827         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1828         .panel_cntl_create = dcn31_panel_cntl_create,
1829         .validate_bandwidth = dcn31_validate_bandwidth,
1830         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1831         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1832         .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
1833         .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1834         .release_pipe = dcn20_release_pipe,
1835         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1836         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1837         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1838         .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context,
1839         .set_mcif_arb_params = dcn31_set_mcif_arb_params,
1840         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1841         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1842         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1843         .update_bw_bounding_box = dcn31_update_bw_bounding_box,
1844         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1845         .get_panel_config_defaults = dcn31_get_panel_config_defaults,
1846 };
1847
1848 static struct clock_source *dcn30_clock_source_create(
1849                 struct dc_context *ctx,
1850                 struct dc_bios *bios,
1851                 enum clock_source_id id,
1852                 const struct dce110_clk_src_regs *regs,
1853                 bool dp_clk_src)
1854 {
1855         struct dce110_clk_src *clk_src =
1856                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1857
1858         if (!clk_src)
1859                 return NULL;
1860
1861         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1862                         regs, &cs_shift, &cs_mask)) {
1863                 clk_src->base.dp_clk_src = dp_clk_src;
1864                 return &clk_src->base;
1865         }
1866
1867         kfree(clk_src);
1868         BREAK_TO_DEBUGGER();
1869         return NULL;
1870 }
1871
1872 static bool dcn31_resource_construct(
1873         uint8_t num_virtual_links,
1874         struct dc *dc,
1875         struct dcn31_resource_pool *pool)
1876 {
1877         int i;
1878         struct dc_context *ctx = dc->ctx;
1879         struct irq_service_init_data init_data;
1880
1881         ctx->dc_bios->regs = &bios_regs;
1882
1883         pool->base.res_cap = &res_cap_dcn31;
1884
1885         pool->base.funcs = &dcn31_res_pool_funcs;
1886
1887         /*************************************************
1888          *  Resource + asic cap harcoding                *
1889          *************************************************/
1890         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1891         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1892         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1893         dc->caps.max_downscale_ratio = 600;
1894         dc->caps.i2c_speed_in_khz = 100;
1895         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1896         dc->caps.max_cursor_size = 256;
1897         dc->caps.min_horizontal_blanking_period = 80;
1898         dc->caps.dmdata_alloc_size = 2048;
1899
1900         dc->caps.max_slave_planes = 2;
1901         dc->caps.max_slave_yuv_planes = 2;
1902         dc->caps.max_slave_rgb_planes = 2;
1903         dc->caps.post_blend_color_processing = true;
1904         dc->caps.force_dp_tps4_for_cp2520 = true;
1905         if (dc->config.forceHBR2CP2520)
1906                 dc->caps.force_dp_tps4_for_cp2520 = false;
1907         dc->caps.dp_hpo = true;
1908         dc->caps.dp_hdmi21_pcon_support = true;
1909         dc->caps.edp_dsc_support = true;
1910         dc->caps.extended_aux_timeout_support = true;
1911         dc->caps.dmcub_support = true;
1912         dc->caps.is_apu = true;
1913         dc->caps.zstate_support = true;
1914
1915         /* Color pipeline capabilities */
1916         dc->caps.color.dpp.dcn_arch = 1;
1917         dc->caps.color.dpp.input_lut_shared = 0;
1918         dc->caps.color.dpp.icsc = 1;
1919         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1920         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1921         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1922         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1923         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1924         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1925         dc->caps.color.dpp.post_csc = 1;
1926         dc->caps.color.dpp.gamma_corr = 1;
1927         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1928
1929         dc->caps.color.dpp.hw_3d_lut = 1;
1930         dc->caps.color.dpp.ogam_ram = 1;
1931         // no OGAM ROM on DCN301
1932         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1933         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1934         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1935         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1936         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1937         dc->caps.color.dpp.ocsc = 0;
1938
1939         dc->caps.color.mpc.gamut_remap = 1;
1940         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1941         dc->caps.color.mpc.ogam_ram = 1;
1942         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1943         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1944         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1945         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1946         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1947         dc->caps.color.mpc.ocsc = 1;
1948
1949         /* Use pipe context based otg sync logic */
1950         dc->config.use_pipe_ctx_sync_logic = true;
1951         dc->config.disable_hbr_audio_dp2 = true;
1952
1953         /* read VBIOS LTTPR caps */
1954         {
1955                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1956                         enum bp_result bp_query_result;
1957                         uint8_t is_vbios_lttpr_enable = 0;
1958
1959                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1960                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1961                 }
1962
1963                 /* interop bit is implicit */
1964                 {
1965                         dc->caps.vbios_lttpr_aware = true;
1966                 }
1967         }
1968
1969         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1970                 dc->debug = debug_defaults_drv;
1971
1972         // Init the vm_helper
1973         if (dc->vm_helper)
1974                 vm_helper_init(dc->vm_helper, 16);
1975
1976         /*************************************************
1977          *  Create resources                             *
1978          *************************************************/
1979
1980         /* Clock Sources for Pixel Clock*/
1981         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1982                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1983                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1984                                 &clk_src_regs[0], false);
1985         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1986                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1987                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1988                                 &clk_src_regs[1], false);
1989         /*move phypllx_pixclk_resync to dmub next*/
1990         if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1991                 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1992                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1993                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1994                                 &clk_src_regs_b0[2], false);
1995                 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1996                         dcn30_clock_source_create(ctx, ctx->dc_bios,
1997                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1998                                 &clk_src_regs_b0[3], false);
1999         } else {
2000                 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2001                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2002                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2003                                 &clk_src_regs[2], false);
2004                 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2005                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2006                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2007                                 &clk_src_regs[3], false);
2008         }
2009
2010         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2011                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2012                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2013                                 &clk_src_regs[4], false);
2014
2015         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2016
2017         /* todo: not reuse phy_pll registers */
2018         pool->base.dp_clock_source =
2019                         dcn31_clock_source_create(ctx, ctx->dc_bios,
2020                                 CLOCK_SOURCE_ID_DP_DTO,
2021                                 &clk_src_regs[0], true);
2022
2023         for (i = 0; i < pool->base.clk_src_count; i++) {
2024                 if (pool->base.clock_sources[i] == NULL) {
2025                         dm_error("DC: failed to create clock sources!\n");
2026                         BREAK_TO_DEBUGGER();
2027                         goto create_fail;
2028                 }
2029         }
2030
2031         /* TODO: DCCG */
2032         pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2033         if (pool->base.dccg == NULL) {
2034                 dm_error("DC: failed to create dccg!\n");
2035                 BREAK_TO_DEBUGGER();
2036                 goto create_fail;
2037         }
2038
2039         /* TODO: IRQ */
2040         init_data.ctx = dc->ctx;
2041         pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2042         if (!pool->base.irqs)
2043                 goto create_fail;
2044
2045         /* HUBBUB */
2046         pool->base.hubbub = dcn31_hubbub_create(ctx);
2047         if (pool->base.hubbub == NULL) {
2048                 BREAK_TO_DEBUGGER();
2049                 dm_error("DC: failed to create hubbub!\n");
2050                 goto create_fail;
2051         }
2052
2053         /* HUBPs, DPPs, OPPs and TGs */
2054         for (i = 0; i < pool->base.pipe_count; i++) {
2055                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2056                 if (pool->base.hubps[i] == NULL) {
2057                         BREAK_TO_DEBUGGER();
2058                         dm_error(
2059                                 "DC: failed to create hubps!\n");
2060                         goto create_fail;
2061                 }
2062
2063                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2064                 if (pool->base.dpps[i] == NULL) {
2065                         BREAK_TO_DEBUGGER();
2066                         dm_error(
2067                                 "DC: failed to create dpps!\n");
2068                         goto create_fail;
2069                 }
2070         }
2071
2072         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2073                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2074                 if (pool->base.opps[i] == NULL) {
2075                         BREAK_TO_DEBUGGER();
2076                         dm_error(
2077                                 "DC: failed to create output pixel processor!\n");
2078                         goto create_fail;
2079                 }
2080         }
2081
2082         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2083                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2084                                 ctx, i);
2085                 if (pool->base.timing_generators[i] == NULL) {
2086                         BREAK_TO_DEBUGGER();
2087                         dm_error("DC: failed to create tg!\n");
2088                         goto create_fail;
2089                 }
2090         }
2091         pool->base.timing_generator_count = i;
2092
2093         /* PSR */
2094         pool->base.psr = dmub_psr_create(ctx);
2095         if (pool->base.psr == NULL) {
2096                 dm_error("DC: failed to create psr obj!\n");
2097                 BREAK_TO_DEBUGGER();
2098                 goto create_fail;
2099         }
2100
2101         /* Replay */
2102         pool->base.replay = dmub_replay_create(ctx);
2103         if (pool->base.replay == NULL) {
2104                 dm_error("DC: failed to create replay obj!\n");
2105                 BREAK_TO_DEBUGGER();
2106                 goto create_fail;
2107         }
2108
2109         /* ABM */
2110         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2111                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2112                                 &abm_regs[i],
2113                                 &abm_shift,
2114                                 &abm_mask);
2115                 if (pool->base.multiple_abms[i] == NULL) {
2116                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2117                         BREAK_TO_DEBUGGER();
2118                         goto create_fail;
2119                 }
2120         }
2121
2122         /* MPC and DSC */
2123         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2124         if (pool->base.mpc == NULL) {
2125                 BREAK_TO_DEBUGGER();
2126                 dm_error("DC: failed to create mpc!\n");
2127                 goto create_fail;
2128         }
2129
2130         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2131                 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2132                 if (pool->base.dscs[i] == NULL) {
2133                         BREAK_TO_DEBUGGER();
2134                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2135                         goto create_fail;
2136                 }
2137         }
2138
2139         /* DWB and MMHUBBUB */
2140         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2141                 BREAK_TO_DEBUGGER();
2142                 dm_error("DC: failed to create dwbc!\n");
2143                 goto create_fail;
2144         }
2145
2146         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2147                 BREAK_TO_DEBUGGER();
2148                 dm_error("DC: failed to create mcif_wb!\n");
2149                 goto create_fail;
2150         }
2151
2152         /* AUX and I2C */
2153         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2154                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2155                 if (pool->base.engines[i] == NULL) {
2156                         BREAK_TO_DEBUGGER();
2157                         dm_error(
2158                                 "DC:failed to create aux engine!!\n");
2159                         goto create_fail;
2160                 }
2161                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2162                 if (pool->base.hw_i2cs[i] == NULL) {
2163                         BREAK_TO_DEBUGGER();
2164                         dm_error(
2165                                 "DC:failed to create hw i2c!!\n");
2166                         goto create_fail;
2167                 }
2168                 pool->base.sw_i2cs[i] = NULL;
2169         }
2170
2171         if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2172             dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2173             !dc->debug.dpia_debug.bits.disable_dpia) {
2174                 /* YELLOW CARP B0 has 4 DPIA's */
2175                 pool->base.usb4_dpia_count = 4;
2176         }
2177
2178         if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1)
2179                 pool->base.usb4_dpia_count = 4;
2180
2181         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2182         if (!resource_construct(num_virtual_links, dc, &pool->base,
2183                         &res_create_funcs))
2184                 goto create_fail;
2185
2186         /* HW Sequencer and Plane caps */
2187         dcn31_hw_sequencer_construct(dc);
2188
2189         dc->caps.max_planes =  pool->base.pipe_count;
2190
2191         for (i = 0; i < dc->caps.max_planes; ++i)
2192                 dc->caps.planes[i] = plane_cap;
2193
2194         dc->cap_funcs = cap_funcs;
2195
2196         dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2197
2198         return true;
2199
2200 create_fail:
2201         dcn31_resource_destruct(pool);
2202
2203         return false;
2204 }
2205
2206 struct resource_pool *dcn31_create_resource_pool(
2207                 const struct dc_init_data *init_data,
2208                 struct dc *dc)
2209 {
2210         struct dcn31_resource_pool *pool =
2211                 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2212
2213         if (!pool)
2214                 return NULL;
2215
2216         if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2217                 return &pool->base;
2218
2219         BREAK_TO_DEBUGGER();
2220         kfree(pool);
2221         return NULL;
2222 }