]> Git Repo - linux.git/blob - drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
crypto: akcipher - Drop sign/verify operations
[linux.git] / drivers / gpu / drm / amd / display / dc / link / protocols / link_dp_training.c
1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25
26 /* FILE POLICY AND INTENDED USAGE:
27  * This file implements all generic dp link training helper functions and top
28  * level generic training sequence. All variations of dp link training sequence
29  * should be called inside the top level training functions in this file to
30  * ensure the integrity of our overall training procedure across different types
31  * of link encoding and back end hardware.
32  */
33 #include "link_dp_training.h"
34 #include "link_dp_training_8b_10b.h"
35 #include "link_dp_training_128b_132b.h"
36 #include "link_dp_training_auxless.h"
37 #include "link_dp_training_dpia.h"
38 #include "link_dp_training_fixed_vs_pe_retimer.h"
39 #include "link_dpcd.h"
40 #include "link/accessories/link_dp_trace.h"
41 #include "link_dp_phy.h"
42 #include "link_dp_capability.h"
43 #include "link_edp_panel_control.h"
44 #include "link/link_detection.h"
45 #include "link/link_validation.h"
46 #include "atomfirmware.h"
47 #include "link_enc_cfg.h"
48 #include "resource.h"
49 #include "dm_helpers.h"
50
51 #define DC_LOGGER \
52         link->ctx->logger
53
54 #define POST_LT_ADJ_REQ_LIMIT 6
55 #define POST_LT_ADJ_REQ_TIMEOUT 200
56 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
57
58 void dp_log_training_result(
59         struct dc_link *link,
60         const struct link_training_settings *lt_settings,
61         enum link_training_result status)
62 {
63         char *link_rate = "Unknown";
64         char *lt_result = "Unknown";
65         char *lt_spread = "Disabled";
66
67         switch (lt_settings->link_settings.link_rate) {
68         case LINK_RATE_LOW:
69                 link_rate = "RBR";
70                 break;
71         case LINK_RATE_RATE_2:
72                 link_rate = "R2";
73                 break;
74         case LINK_RATE_RATE_3:
75                 link_rate = "R3";
76                 break;
77         case LINK_RATE_HIGH:
78                 link_rate = "HBR";
79                 break;
80         case LINK_RATE_RBR2:
81                 link_rate = "RBR2";
82                 break;
83         case LINK_RATE_RATE_6:
84                 link_rate = "R6";
85                 break;
86         case LINK_RATE_HIGH2:
87                 link_rate = "HBR2";
88                 break;
89         case LINK_RATE_RATE_8:
90                 link_rate = "R8";
91                 break;
92         case LINK_RATE_HIGH3:
93                 link_rate = "HBR3";
94                 break;
95         case LINK_RATE_UHBR10:
96                 link_rate = "UHBR10";
97                 break;
98         case LINK_RATE_UHBR13_5:
99                 link_rate = "UHBR13.5";
100                 break;
101         case LINK_RATE_UHBR20:
102                 link_rate = "UHBR20";
103                 break;
104         default:
105                 break;
106         }
107
108         switch (status) {
109         case LINK_TRAINING_SUCCESS:
110                 lt_result = "pass";
111                 break;
112         case LINK_TRAINING_CR_FAIL_LANE0:
113                 lt_result = "CR failed lane0";
114                 break;
115         case LINK_TRAINING_CR_FAIL_LANE1:
116                 lt_result = "CR failed lane1";
117                 break;
118         case LINK_TRAINING_CR_FAIL_LANE23:
119                 lt_result = "CR failed lane23";
120                 break;
121         case LINK_TRAINING_EQ_FAIL_CR:
122                 lt_result = "CR failed in EQ";
123                 break;
124         case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
125                 lt_result = "CR failed in EQ partially";
126                 break;
127         case LINK_TRAINING_EQ_FAIL_EQ:
128                 lt_result = "EQ failed";
129                 break;
130         case LINK_TRAINING_LQA_FAIL:
131                 lt_result = "LQA failed";
132                 break;
133         case LINK_TRAINING_LINK_LOSS:
134                 lt_result = "Link loss";
135                 break;
136         case DP_128b_132b_LT_FAILED:
137                 lt_result = "LT_FAILED received";
138                 break;
139         case DP_128b_132b_MAX_LOOP_COUNT_REACHED:
140                 lt_result = "max loop count reached";
141                 break;
142         case DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT:
143                 lt_result = "channel EQ timeout";
144                 break;
145         case DP_128b_132b_CDS_DONE_TIMEOUT:
146                 lt_result = "CDS timeout";
147                 break;
148         default:
149                 break;
150         }
151
152         switch (lt_settings->link_settings.link_spread) {
153         case LINK_SPREAD_DISABLED:
154                 lt_spread = "Disabled";
155                 break;
156         case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
157                 lt_spread = "0.5% 30KHz";
158                 break;
159         case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
160                 lt_spread = "0.5% 33KHz";
161                 break;
162         default:
163                 break;
164         }
165
166         /* Connectivity log: link training */
167
168         /* TODO - DP2.0 Log: add connectivity log for FFE PRESET */
169
170         CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
171                                 link_rate,
172                                 lt_settings->link_settings.lane_count,
173                                 lt_result,
174                                 lt_settings->hw_lane_settings[0].VOLTAGE_SWING,
175                                 lt_settings->hw_lane_settings[0].PRE_EMPHASIS,
176                                 lt_spread);
177 }
178
179 uint8_t dp_initialize_scrambling_data_symbols(
180         struct dc_link *link,
181         enum dc_dp_training_pattern pattern)
182 {
183         uint8_t disable_scrabled_data_symbols = 0;
184
185         switch (pattern) {
186         case DP_TRAINING_PATTERN_SEQUENCE_1:
187         case DP_TRAINING_PATTERN_SEQUENCE_2:
188         case DP_TRAINING_PATTERN_SEQUENCE_3:
189                 disable_scrabled_data_symbols = 1;
190                 break;
191         case DP_TRAINING_PATTERN_SEQUENCE_4:
192         case DP_128b_132b_TPS1:
193         case DP_128b_132b_TPS2:
194                 disable_scrabled_data_symbols = 0;
195                 break;
196         default:
197                 ASSERT(0);
198                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
199                         __func__, pattern);
200                 break;
201         }
202         return disable_scrabled_data_symbols;
203 }
204
205 enum dpcd_training_patterns
206         dp_training_pattern_to_dpcd_training_pattern(
207         struct dc_link *link,
208         enum dc_dp_training_pattern pattern)
209 {
210         enum dpcd_training_patterns dpcd_tr_pattern =
211         DPCD_TRAINING_PATTERN_VIDEOIDLE;
212
213         switch (pattern) {
214         case DP_TRAINING_PATTERN_SEQUENCE_1:
215                 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS1\n", __func__);
216                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
217                 break;
218         case DP_TRAINING_PATTERN_SEQUENCE_2:
219                 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS2\n", __func__);
220                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
221                 break;
222         case DP_TRAINING_PATTERN_SEQUENCE_3:
223                 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS3\n", __func__);
224                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
225                 break;
226         case DP_TRAINING_PATTERN_SEQUENCE_4:
227                 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern TPS4\n", __func__);
228                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
229                 break;
230         case DP_128b_132b_TPS1:
231                 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS1\n", __func__);
232                 dpcd_tr_pattern = DPCD_128b_132b_TPS1;
233                 break;
234         case DP_128b_132b_TPS2:
235                 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS2\n", __func__);
236                 dpcd_tr_pattern = DPCD_128b_132b_TPS2;
237                 break;
238         case DP_128b_132b_TPS2_CDS:
239                 DC_LOG_HW_LINK_TRAINING("%s: Using DP 128b/132b training pattern TPS2 CDS\n",
240                                         __func__);
241                 dpcd_tr_pattern = DPCD_128b_132b_TPS2_CDS;
242                 break;
243         case DP_TRAINING_PATTERN_VIDEOIDLE:
244                 DC_LOG_HW_LINK_TRAINING("%s: Using DP training pattern videoidle\n", __func__);
245                 dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
246                 break;
247         default:
248                 ASSERT(0);
249                 DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
250                         __func__, pattern);
251                 break;
252         }
253
254         return dpcd_tr_pattern;
255 }
256
257 uint8_t dp_get_nibble_at_index(const uint8_t *buf,
258         uint32_t index)
259 {
260         uint8_t nibble;
261         nibble = buf[index / 2];
262
263         if (index % 2)
264                 nibble >>= 4;
265         else
266                 nibble &= 0x0F;
267
268         return nibble;
269 }
270
271 void dp_wait_for_training_aux_rd_interval(
272         struct dc_link *link,
273         uint32_t wait_in_micro_secs)
274 {
275         fsleep(wait_in_micro_secs);
276
277         DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
278                 __func__,
279                 wait_in_micro_secs);
280 }
281
282 /* maximum pre emphasis level allowed for each voltage swing level*/
283 static const enum dc_pre_emphasis voltage_swing_to_pre_emphasis[] = {
284                 PRE_EMPHASIS_LEVEL3,
285                 PRE_EMPHASIS_LEVEL2,
286                 PRE_EMPHASIS_LEVEL1,
287                 PRE_EMPHASIS_DISABLED };
288
289 static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
290         enum dc_voltage_swing voltage)
291 {
292         enum dc_pre_emphasis pre_emphasis;
293         pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;
294
295         if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
296                 pre_emphasis = voltage_swing_to_pre_emphasis[voltage];
297
298         return pre_emphasis;
299
300 }
301
302 static void maximize_lane_settings(const struct link_training_settings *lt_settings,
303                 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
304 {
305         uint32_t lane;
306         struct dc_lane_settings max_requested;
307
308         max_requested.VOLTAGE_SWING = lane_settings[0].VOLTAGE_SWING;
309         max_requested.PRE_EMPHASIS = lane_settings[0].PRE_EMPHASIS;
310         max_requested.FFE_PRESET = lane_settings[0].FFE_PRESET;
311
312         /* Determine what the maximum of the requested settings are*/
313         for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) {
314                 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING)
315                         max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING;
316
317                 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS)
318                         max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS;
319                 if (lane_settings[lane].FFE_PRESET.settings.level >
320                                 max_requested.FFE_PRESET.settings.level)
321                         max_requested.FFE_PRESET.settings.level =
322                                         lane_settings[lane].FFE_PRESET.settings.level;
323         }
324
325         /* make sure the requested settings are
326          * not higher than maximum settings*/
327         if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
328                 max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;
329
330         if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
331                 max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
332
333         /* Note, we are not checking
334          * if max_requested.FFE_PRESET.settings.level >  DP_FFE_PRESET_MAX_LEVEL,
335          * since FFE_PRESET.settings.level is 4 bits and DP_FFE_PRESET_MAX_LEVEL equals 15,
336          * so FFE_PRESET.settings.level will never be greater than 15.
337          */
338
339         /* make sure the pre-emphasis matches the voltage swing*/
340         if (max_requested.PRE_EMPHASIS >
341                 get_max_pre_emphasis_for_voltage_swing(
342                         max_requested.VOLTAGE_SWING))
343                 max_requested.PRE_EMPHASIS =
344                 get_max_pre_emphasis_for_voltage_swing(
345                         max_requested.VOLTAGE_SWING);
346
347         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
348                 lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING;
349                 lane_settings[lane].PRE_EMPHASIS = max_requested.PRE_EMPHASIS;
350                 lane_settings[lane].FFE_PRESET = max_requested.FFE_PRESET;
351         }
352 }
353
354 void dp_hw_to_dpcd_lane_settings(
355                 const struct link_training_settings *lt_settings,
356                 const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
357                 union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
358 {
359         uint8_t lane = 0;
360
361         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
362                 if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
363                                 DP_8b_10b_ENCODING) {
364                         dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET =
365                                         (uint8_t)(hw_lane_settings[lane].VOLTAGE_SWING);
366                         dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET =
367                                         (uint8_t)(hw_lane_settings[lane].PRE_EMPHASIS);
368                         dpcd_lane_settings[lane].bits.MAX_SWING_REACHED =
369                                         (hw_lane_settings[lane].VOLTAGE_SWING ==
370                                                         VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
371                         dpcd_lane_settings[lane].bits.MAX_PRE_EMPHASIS_REACHED =
372                                         (hw_lane_settings[lane].PRE_EMPHASIS ==
373                                                         PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
374                 } else if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
375                                 DP_128b_132b_ENCODING) {
376                         dpcd_lane_settings[lane].tx_ffe.PRESET_VALUE =
377                                         hw_lane_settings[lane].FFE_PRESET.settings.level;
378                 }
379         }
380 }
381
382 uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings)
383 {
384         uint8_t link_rate = 0;
385         enum dp_link_encoding encoding = link_dp_get_encoding_format(link_settings);
386
387         if (encoding == DP_128b_132b_ENCODING)
388                 switch (link_settings->link_rate) {
389                 case LINK_RATE_UHBR10:
390                         link_rate = 0x1;
391                         break;
392                 case LINK_RATE_UHBR20:
393                         link_rate = 0x2;
394                         break;
395                 case LINK_RATE_UHBR13_5:
396                         link_rate = 0x4;
397                         break;
398                 default:
399                         link_rate = 0;
400                         break;
401                 }
402         else if (encoding == DP_8b_10b_ENCODING)
403                 link_rate = (uint8_t) link_settings->link_rate;
404         else
405                 link_rate = 0;
406
407         return link_rate;
408 }
409
410 /* Only used for channel equalization */
411 uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
412 {
413         unsigned int aux_rd_interval_us = 400;
414
415         switch (dpcd_aux_read_interval) {
416         case 0x01:
417                 aux_rd_interval_us = 4000;
418                 break;
419         case 0x02:
420                 aux_rd_interval_us = 8000;
421                 break;
422         case 0x03:
423                 aux_rd_interval_us = 12000;
424                 break;
425         case 0x04:
426                 aux_rd_interval_us = 16000;
427                 break;
428         case 0x05:
429                 aux_rd_interval_us = 32000;
430                 break;
431         case 0x06:
432                 aux_rd_interval_us = 64000;
433                 break;
434         default:
435                 break;
436         }
437
438         return aux_rd_interval_us;
439 }
440
441 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
442                                         union lane_status *dpcd_lane_status)
443 {
444         enum link_training_result result = LINK_TRAINING_SUCCESS;
445
446         if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
447                 result = LINK_TRAINING_CR_FAIL_LANE0;
448         else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
449                 result = LINK_TRAINING_CR_FAIL_LANE1;
450         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
451                 result = LINK_TRAINING_CR_FAIL_LANE23;
452         else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
453                 result = LINK_TRAINING_CR_FAIL_LANE23;
454         return result;
455 }
456
457 bool is_repeater(const struct link_training_settings *lt_settings, uint32_t offset)
458 {
459         return (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
460 }
461
462 bool dp_is_max_vs_reached(
463         const struct link_training_settings *lt_settings)
464 {
465         uint32_t lane;
466         for (lane = 0; lane <
467                 (uint32_t)(lt_settings->link_settings.lane_count);
468                 lane++) {
469                 if (lt_settings->dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET
470                         == VOLTAGE_SWING_MAX_LEVEL)
471                         return true;
472         }
473         return false;
474
475 }
476
477 bool dp_is_cr_done(enum dc_lane_count ln_count,
478         union lane_status *dpcd_lane_status)
479 {
480         bool done = true;
481         uint32_t lane;
482         /*LANEx_CR_DONE bits All 1's?*/
483         for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
484                 if (!dpcd_lane_status[lane].bits.CR_DONE_0)
485                         done = false;
486         }
487         return done;
488
489 }
490
491 bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
492                 union lane_status *dpcd_lane_status)
493 {
494         bool done = true;
495         uint32_t lane;
496         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
497                 if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
498                         done = false;
499         return done;
500 }
501
502 bool dp_is_symbol_locked(enum dc_lane_count ln_count,
503                 union lane_status *dpcd_lane_status)
504 {
505         bool locked = true;
506         uint32_t lane;
507         for (lane = 0; lane < (uint32_t)(ln_count); lane++)
508                 if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
509                         locked = false;
510         return locked;
511 }
512
513 bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
514 {
515         return align_status.bits.INTERLANE_ALIGN_DONE == 1;
516 }
517
518 bool dp_check_interlane_aligned(union lane_align_status_updated align_status,
519                 struct dc_link *link,
520                 uint8_t retries)
521 {
522         /* Take into consideration corner case for DP 1.4a LL Compliance CTS as USB4
523          * has to share encoders unlike DP and USBC
524          */
525         return (dp_is_interlane_aligned(align_status) ||
526                         (link->skip_fallback_on_link_loss && retries));
527 }
528
529 uint32_t dp_get_eq_aux_rd_interval(
530                 const struct dc_link *link,
531                 const struct link_training_settings *lt_settings,
532                 uint32_t offset,
533                 uint8_t retries)
534 {
535         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
536                 if (offset == 0 && retries == 1 && lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
537                         return max(lt_settings->eq_pattern_time, (uint32_t) DPIA_CLK_SYNC_DELAY);
538                 else
539                         return dpia_get_eq_aux_rd_interval(link, lt_settings, offset);
540         } else if (is_repeater(lt_settings, offset))
541                 return dp_translate_training_aux_read_interval(
542                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);
543         else
544                 return lt_settings->eq_pattern_time;
545 }
546
547 bool dp_check_dpcd_reqeust_status(const struct dc_link *link,
548                 enum dc_status status)
549 {
550         return (status != DC_OK && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA);
551 }
552
553 enum link_training_result dp_check_link_loss_status(
554         struct dc_link *link,
555         const struct link_training_settings *link_training_setting)
556 {
557         enum link_training_result status = LINK_TRAINING_SUCCESS;
558         union lane_status lane_status;
559         union lane_align_status_updated dpcd_lane_status_updated;
560         uint8_t dpcd_buf[6] = {0};
561         uint32_t lane;
562
563         core_link_read_dpcd(
564                         link,
565                         DP_SINK_COUNT,
566                         (uint8_t *)(dpcd_buf),
567                         sizeof(dpcd_buf));
568
569         /*parse lane status*/
570         for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
571                 /*
572                  * check lanes status
573                  */
574                 lane_status.raw = dp_get_nibble_at_index(&dpcd_buf[2], lane);
575                 dpcd_lane_status_updated.raw = dpcd_buf[4];
576
577                 if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
578                         !lane_status.bits.CR_DONE_0 ||
579                         !lane_status.bits.SYMBOL_LOCKED_0 ||
580                         !dp_is_interlane_aligned(dpcd_lane_status_updated)) {
581                         /* if one of the channel equalization, clock
582                          * recovery or symbol lock is dropped
583                          * consider it as (link has been
584                          * dropped) dp sink status has changed
585                          */
586                         status = LINK_TRAINING_LINK_LOSS;
587                         break;
588                 }
589         }
590
591         return status;
592 }
593
594 enum dc_status dp_get_lane_status_and_lane_adjust(
595         struct dc_link *link,
596         const struct link_training_settings *link_training_setting,
597         union lane_status ln_status[LANE_COUNT_DP_MAX],
598         union lane_align_status_updated *ln_align,
599         union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
600         uint32_t offset)
601 {
602         unsigned int lane01_status_address = DP_LANE0_1_STATUS;
603         uint8_t lane_adjust_offset = 4;
604         unsigned int lane01_adjust_address;
605         uint8_t dpcd_buf[6] = {0};
606         uint32_t lane;
607         enum dc_status status;
608
609         if (is_repeater(link_training_setting, offset)) {
610                 lane01_status_address =
611                                 DP_LANE0_1_STATUS_PHY_REPEATER1 +
612                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
613                 lane_adjust_offset = 3;
614         }
615
616         status = core_link_read_dpcd(
617                 link,
618                 lane01_status_address,
619                 (uint8_t *)(dpcd_buf),
620                 sizeof(dpcd_buf));
621
622         if (status != DC_OK) {
623                 DC_LOG_HW_LINK_TRAINING("%s:\n Failed to read from address 0x%X,"
624                         " keep current lane status and lane adjust unchanged",
625                         __func__,
626                         lane01_status_address);
627                 return status;
628         }
629
630         for (lane = 0; lane <
631                 (uint32_t)(link_training_setting->link_settings.lane_count);
632                 lane++) {
633
634                 ln_status[lane].raw =
635                         dp_get_nibble_at_index(&dpcd_buf[0], lane);
636                 ln_adjust[lane].raw =
637                         dp_get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
638         }
639
640         ln_align->raw = dpcd_buf[2];
641
642         if (is_repeater(link_training_setting, offset)) {
643                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
644                                 " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
645                         __func__,
646                         offset,
647                         lane01_status_address, dpcd_buf[0],
648                         lane01_status_address + 1, dpcd_buf[1]);
649
650                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
651                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
652
653                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
654                                 " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
655                                         __func__,
656                                         offset,
657                                         lane01_adjust_address,
658                                         dpcd_buf[lane_adjust_offset],
659                                         lane01_adjust_address + 1,
660                                         dpcd_buf[lane_adjust_offset + 1]);
661         } else {
662                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
663                         __func__,
664                         lane01_status_address, dpcd_buf[0],
665                         lane01_status_address + 1, dpcd_buf[1]);
666
667                 lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;
668
669                 DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
670                         __func__,
671                         lane01_adjust_address,
672                         dpcd_buf[lane_adjust_offset],
673                         lane01_adjust_address + 1,
674                         dpcd_buf[lane_adjust_offset + 1]);
675         }
676
677         return status;
678 }
679
680 static void override_lane_settings(const struct link_training_settings *lt_settings,
681                 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
682 {
683         uint32_t lane;
684
685         if (lt_settings->voltage_swing == NULL &&
686                         lt_settings->pre_emphasis == NULL &&
687                         lt_settings->ffe_preset == NULL &&
688                         lt_settings->post_cursor2 == NULL)
689
690                 return;
691
692         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
693                 if (lt_settings->voltage_swing)
694                         lane_settings[lane].VOLTAGE_SWING = *lt_settings->voltage_swing;
695                 if (lt_settings->pre_emphasis)
696                         lane_settings[lane].PRE_EMPHASIS = *lt_settings->pre_emphasis;
697                 if (lt_settings->post_cursor2)
698                         lane_settings[lane].POST_CURSOR2 = *lt_settings->post_cursor2;
699                 if (lt_settings->ffe_preset)
700                         lane_settings[lane].FFE_PRESET = *lt_settings->ffe_preset;
701         }
702 }
703
704 void dp_get_lttpr_mode_override(struct dc_link *link, enum lttpr_mode *override)
705 {
706         if (!dp_is_lttpr_present(link))
707                 return;
708
709         if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_TRANSPARENT) {
710                 *override = LTTPR_MODE_TRANSPARENT;
711         } else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_TRANSPARENT) {
712                 *override = LTTPR_MODE_NON_TRANSPARENT;
713         } else if (link->dc->debug.lttpr_mode_override == LTTPR_MODE_NON_LTTPR) {
714                 *override = LTTPR_MODE_NON_LTTPR;
715         }
716         DC_LOG_DC("lttpr_mode_override chose LTTPR_MODE = %d\n", (uint8_t)(*override));
717 }
718
719 void override_training_settings(
720                 struct dc_link *link,
721                 const struct dc_link_training_overrides *overrides,
722                 struct link_training_settings *lt_settings)
723 {
724         uint32_t lane;
725
726         /* Override link spread */
727         if (!link->dp_ss_off && overrides->downspread != NULL)
728                 lt_settings->link_settings.link_spread = *overrides->downspread ?
729                                 LINK_SPREAD_05_DOWNSPREAD_30KHZ
730                                 : LINK_SPREAD_DISABLED;
731
732         /* Override lane settings */
733         if (overrides->voltage_swing != NULL)
734                 lt_settings->voltage_swing = overrides->voltage_swing;
735         if (overrides->pre_emphasis != NULL)
736                 lt_settings->pre_emphasis = overrides->pre_emphasis;
737         if (overrides->post_cursor2 != NULL)
738                 lt_settings->post_cursor2 = overrides->post_cursor2;
739         if (overrides->ffe_preset != NULL)
740                 lt_settings->ffe_preset = overrides->ffe_preset;
741         /* Override HW lane settings with BIOS forced values if present */
742         if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
743                         lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT) {
744                 lt_settings->voltage_swing = &link->bios_forced_drive_settings.VOLTAGE_SWING;
745                 lt_settings->pre_emphasis = &link->bios_forced_drive_settings.PRE_EMPHASIS;
746                 lt_settings->always_match_dpcd_with_hw_lane_settings = false;
747         }
748         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
749                 lt_settings->hw_lane_settings[lane].VOLTAGE_SWING =
750                         lt_settings->voltage_swing != NULL ?
751                         *lt_settings->voltage_swing :
752                         VOLTAGE_SWING_LEVEL0;
753                 lt_settings->hw_lane_settings[lane].PRE_EMPHASIS =
754                         lt_settings->pre_emphasis != NULL ?
755                         *lt_settings->pre_emphasis
756                         : PRE_EMPHASIS_DISABLED;
757                 lt_settings->hw_lane_settings[lane].POST_CURSOR2 =
758                         lt_settings->post_cursor2 != NULL ?
759                         *lt_settings->post_cursor2
760                         : POST_CURSOR2_DISABLED;
761         }
762
763         if (lt_settings->always_match_dpcd_with_hw_lane_settings)
764                 dp_hw_to_dpcd_lane_settings(lt_settings,
765                                 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
766
767         /* Override training timings */
768         if (overrides->cr_pattern_time != NULL)
769                 lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
770         if (overrides->eq_pattern_time != NULL)
771                 lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
772         if (overrides->pattern_for_cr != NULL)
773                 lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
774         if (overrides->pattern_for_eq != NULL)
775                 lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
776         if (overrides->enhanced_framing != NULL)
777                 lt_settings->enhanced_framing = *overrides->enhanced_framing;
778         if (link->preferred_training_settings.fec_enable != NULL)
779                 lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
780
781         /* Check DP tunnel LTTPR mode debug option. */
782         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr)
783                 lt_settings->lttpr_mode = LTTPR_MODE_NON_LTTPR;
784
785         dp_get_lttpr_mode_override(link, &lt_settings->lttpr_mode);
786
787 }
788
789 enum dc_dp_training_pattern decide_cr_training_pattern(
790                 const struct dc_link_settings *link_settings)
791 {
792         switch (link_dp_get_encoding_format(link_settings)) {
793         case DP_8b_10b_ENCODING:
794         default:
795                 return DP_TRAINING_PATTERN_SEQUENCE_1;
796         case DP_128b_132b_ENCODING:
797                 return DP_128b_132b_TPS1;
798         }
799 }
800
801 enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
802                 const struct dc_link_settings *link_settings)
803 {
804         struct link_encoder *link_enc;
805         struct encoder_feature_support *enc_caps;
806         struct dpcd_caps *rx_caps = &link->dpcd_caps;
807         enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
808
809         link_enc = link_enc_cfg_get_link_enc(link);
810         ASSERT(link_enc);
811         enc_caps = &link_enc->features;
812
813         switch (link_dp_get_encoding_format(link_settings)) {
814         case DP_8b_10b_ENCODING:
815                 if (enc_caps->flags.bits.IS_TPS4_CAPABLE &&
816                                 rx_caps->max_down_spread.bits.TPS4_SUPPORTED)
817                         pattern = DP_TRAINING_PATTERN_SEQUENCE_4;
818                 else if (enc_caps->flags.bits.IS_TPS3_CAPABLE &&
819                                 rx_caps->max_ln_count.bits.TPS3_SUPPORTED)
820                         pattern = DP_TRAINING_PATTERN_SEQUENCE_3;
821                 else
822                         pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
823                 break;
824         case DP_128b_132b_ENCODING:
825                 pattern = DP_128b_132b_TPS2;
826                 break;
827         default:
828                 pattern = DP_TRAINING_PATTERN_SEQUENCE_2;
829                 break;
830         }
831         return pattern;
832 }
833
834 enum lttpr_mode dp_decide_lttpr_mode(struct dc_link *link,
835                 struct dc_link_settings *link_setting)
836 {
837         enum dp_link_encoding encoding = link_dp_get_encoding_format(link_setting);
838
839         if (encoding == DP_8b_10b_ENCODING)
840                 return dp_decide_8b_10b_lttpr_mode(link);
841         else if (encoding == DP_128b_132b_ENCODING)
842                 return dp_decide_128b_132b_lttpr_mode(link);
843
844         ASSERT(0);
845         return LTTPR_MODE_NON_LTTPR;
846 }
847
848 void dp_decide_lane_settings(
849                 const struct link_training_settings *lt_settings,
850                 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
851                 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
852                 union dpcd_training_lane *dpcd_lane_settings)
853 {
854         uint32_t lane;
855
856         for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
857                 if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
858                                 DP_8b_10b_ENCODING) {
859                         hw_lane_settings[lane].VOLTAGE_SWING =
860                                         (enum dc_voltage_swing)(ln_adjust[lane].bits.
861                                                         VOLTAGE_SWING_LANE);
862                         hw_lane_settings[lane].PRE_EMPHASIS =
863                                         (enum dc_pre_emphasis)(ln_adjust[lane].bits.
864                                                         PRE_EMPHASIS_LANE);
865                 } else if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
866                                 DP_128b_132b_ENCODING) {
867                         hw_lane_settings[lane].FFE_PRESET.raw =
868                                         ln_adjust[lane].tx_ffe.PRESET_VALUE;
869                 }
870         }
871         dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
872
873         if (lt_settings->disallow_per_lane_settings) {
874                 /* we find the maximum of the requested settings across all lanes*/
875                 /* and set this maximum for all lanes*/
876                 maximize_lane_settings(lt_settings, hw_lane_settings);
877                 override_lane_settings(lt_settings, hw_lane_settings);
878
879                 if (lt_settings->always_match_dpcd_with_hw_lane_settings)
880                         dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
881         }
882
883 }
884
885 void dp_decide_training_settings(
886                 struct dc_link *link,
887                 const struct dc_link_settings *link_settings,
888                 struct link_training_settings *lt_settings)
889 {
890         if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING)
891                 decide_8b_10b_training_settings(link, link_settings, lt_settings);
892         else if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING)
893                 decide_128b_132b_training_settings(link, link_settings, lt_settings);
894 }
895
896
897 enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
898 {
899         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
900
901         DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
902         return core_link_write_dpcd(link,
903                         DP_PHY_REPEATER_MODE,
904                         (uint8_t *)&repeater_mode,
905                         sizeof(repeater_mode));
906 }
907
908 static enum dc_status configure_lttpr_mode_non_transparent(
909                 struct dc_link *link,
910                 const struct link_training_settings *lt_settings)
911 {
912         /* aux timeout is already set to extended */
913         /* RESET/SET lttpr mode to enable non transparent mode */
914         uint8_t repeater_cnt;
915         uint32_t aux_interval_address;
916         uint8_t repeater_id;
917         enum dc_status result = DC_ERROR_UNEXPECTED;
918         uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;
919         const struct dc *dc = link->dc;
920
921         enum dp_link_encoding encoding = dc->link_srv->dp_get_encoding_format(&lt_settings->link_settings);
922
923         if (encoding == DP_8b_10b_ENCODING) {
924                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
925                 result = core_link_write_dpcd(link,
926                                 DP_PHY_REPEATER_MODE,
927                                 (uint8_t *)&repeater_mode,
928                                 sizeof(repeater_mode));
929
930         }
931
932         if (result == DC_OK) {
933                 link->dpcd_caps.lttpr_caps.mode = repeater_mode;
934         }
935
936         if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {
937
938                 DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);
939
940                 repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
941                 result = core_link_write_dpcd(link,
942                                 DP_PHY_REPEATER_MODE,
943                                 (uint8_t *)&repeater_mode,
944                                 sizeof(repeater_mode));
945
946                 if (result == DC_OK) {
947                         link->dpcd_caps.lttpr_caps.mode = repeater_mode;
948                 }
949
950                 if (encoding == DP_8b_10b_ENCODING) {
951                         repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
952
953                         /* Driver does not need to train the first hop. Skip DPCD read and clear
954                          * AUX_RD_INTERVAL for DPTX-to-DPIA hop.
955                          */
956                         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && repeater_cnt > 0 && repeater_cnt < MAX_REPEATER_CNT)
957                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[--repeater_cnt] = 0;
958
959                         for (repeater_id = repeater_cnt; repeater_id > 0 && repeater_id < MAX_REPEATER_CNT; repeater_id--) {
960                                 aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
961                                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
962                                 core_link_read_dpcd(
963                                                 link,
964                                                 aux_interval_address,
965                                                 (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
966                                                 sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
967                                 link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
968                         }
969                 }
970         }
971
972         return result;
973 }
974
975 enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
976 {
977         enum dc_status status = DC_OK;
978
979         if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
980                 status = configure_lttpr_mode_transparent(link);
981
982         else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
983                 status = configure_lttpr_mode_non_transparent(link, lt_settings);
984
985         return status;
986 }
987
988 void repeater_training_done(struct dc_link *link, uint32_t offset)
989 {
990         union dpcd_training_pattern dpcd_pattern = {0};
991
992         const uint32_t dpcd_base_lt_offset =
993                         DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
994                                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
995         /* Set training not in progress*/
996         dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;
997
998         core_link_write_dpcd(
999                 link,
1000                 dpcd_base_lt_offset,
1001                 &dpcd_pattern.raw,
1002                 1);
1003
1004         DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
1005                 __func__,
1006                 offset,
1007                 dpcd_base_lt_offset,
1008                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1009 }
1010
1011 static enum link_training_result dpcd_exit_training_mode(struct dc_link *link, enum dp_link_encoding encoding)
1012 {
1013         enum dc_status status;
1014         uint8_t sink_status = 0;
1015         uint8_t i;
1016
1017         /* clear training pattern set */
1018         status = dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
1019
1020         if (dp_check_dpcd_reqeust_status(link, status))
1021                 return LINK_TRAINING_ABORT;
1022
1023         if (encoding == DP_128b_132b_ENCODING) {
1024                 /* poll for intra-hop disable */
1025                 for (i = 0; i < 10; i++) {
1026                         if ((core_link_read_dpcd(link, DP_SINK_STATUS, &sink_status, 1) == DC_OK) &&
1027                                         (sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION) == 0)
1028                                 break;
1029                         fsleep(1000);
1030                 }
1031         }
1032
1033         return LINK_TRAINING_SUCCESS;
1034 }
1035
1036 enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
1037                 struct link_training_settings *lt_settings)
1038 {
1039         enum dp_link_encoding encoding =
1040                         link_dp_get_encoding_format(
1041                                         &lt_settings->link_settings);
1042         enum dc_status status;
1043
1044         status = core_link_write_dpcd(
1045                         link,
1046                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1047                         (uint8_t *) &encoding,
1048                         1);
1049         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
1050                                         __func__,
1051                                         DP_MAIN_LINK_CHANNEL_CODING_SET,
1052                                         encoding);
1053
1054         return status;
1055 }
1056
1057 enum dc_status dpcd_set_training_pattern(
1058         struct dc_link *link,
1059         enum dc_dp_training_pattern training_pattern)
1060 {
1061         enum dc_status status;
1062         union dpcd_training_pattern dpcd_pattern = {0};
1063
1064         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
1065                         dp_training_pattern_to_dpcd_training_pattern(
1066                                         link, training_pattern);
1067
1068         status = core_link_write_dpcd(
1069                 link,
1070                 DP_TRAINING_PATTERN_SET,
1071                 &dpcd_pattern.raw,
1072                 1);
1073
1074         DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
1075                 __func__,
1076                 DP_TRAINING_PATTERN_SET,
1077                 dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1078
1079         return status;
1080 }
1081
1082 enum dc_status dpcd_set_link_settings(
1083         struct dc_link *link,
1084         const struct link_training_settings *lt_settings)
1085 {
1086         uint8_t rate;
1087         enum dc_status status;
1088
1089         union down_spread_ctrl downspread = {0};
1090         union lane_count_set lane_count_set = {0};
1091
1092         downspread.raw = (uint8_t)
1093         (lt_settings->link_settings.link_spread);
1094
1095         lane_count_set.bits.LANE_COUNT_SET =
1096         lt_settings->link_settings.lane_count;
1097
1098         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1099         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1100
1101
1102         if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
1103                         lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
1104                 lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
1105                                 link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
1106         }
1107
1108         status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1109                 &downspread.raw, sizeof(downspread));
1110
1111         status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
1112                 &lane_count_set.raw, 1);
1113
1114         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13 &&
1115                         lt_settings->link_settings.use_link_rate_set == true) {
1116                 rate = 0;
1117                 /* WA for some MUX chips that will power down with eDP and lose supported
1118                  * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
1119                  * MUX chip gets link rate set back before link training.
1120                  */
1121                 if (link->connector_signal == SIGNAL_TYPE_EDP) {
1122                         uint8_t supported_link_rates[16] = {0};
1123
1124                         core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
1125                                         supported_link_rates, sizeof(supported_link_rates));
1126                 }
1127                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
1128                 status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
1129                                 &lt_settings->link_settings.link_rate_set, 1);
1130         } else {
1131                 rate = get_dpcd_link_rate(&lt_settings->link_settings);
1132
1133                 status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
1134         }
1135
1136         if (rate) {
1137                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
1138                         __func__,
1139                         DP_LINK_BW_SET,
1140                         lt_settings->link_settings.link_rate,
1141                         DP_LANE_COUNT_SET,
1142                         lt_settings->link_settings.lane_count,
1143                         lt_settings->enhanced_framing,
1144                         DP_DOWNSPREAD_CTRL,
1145                         lt_settings->link_settings.link_spread);
1146         } else {
1147                 DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
1148                         __func__,
1149                         DP_LINK_RATE_SET,
1150                         lt_settings->link_settings.link_rate_set,
1151                         DP_LANE_COUNT_SET,
1152                         lt_settings->link_settings.lane_count,
1153                         lt_settings->enhanced_framing,
1154                         DP_DOWNSPREAD_CTRL,
1155                         lt_settings->link_settings.link_spread);
1156         }
1157
1158         return status;
1159 }
1160
1161 enum dc_status dpcd_set_lane_settings(
1162         struct dc_link *link,
1163         const struct link_training_settings *link_training_setting,
1164         uint32_t offset)
1165 {
1166         unsigned int lane0_set_address;
1167         enum dc_status status;
1168         lane0_set_address = DP_TRAINING_LANE0_SET;
1169
1170         if (is_repeater(link_training_setting, offset))
1171                 lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
1172                 ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1173
1174         status = core_link_write_dpcd(link,
1175                 lane0_set_address,
1176                 (uint8_t *)(link_training_setting->dpcd_lane_settings),
1177                 link_training_setting->link_settings.lane_count);
1178
1179         if (is_repeater(link_training_setting, offset)) {
1180                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
1181                                 " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
1182                         __func__,
1183                         offset,
1184                         lane0_set_address,
1185                         link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1186                         link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1187                         link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1188                         link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1189
1190         } else {
1191                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
1192                         __func__,
1193                         lane0_set_address,
1194                         link_training_setting->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1195                         link_training_setting->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1196                         link_training_setting->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1197                         link_training_setting->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1198         }
1199
1200         return status;
1201 }
1202
1203 void dpcd_set_lt_pattern_and_lane_settings(
1204         struct dc_link *link,
1205         const struct link_training_settings *lt_settings,
1206         enum dc_dp_training_pattern pattern,
1207         uint32_t offset)
1208 {
1209         uint32_t dpcd_base_lt_offset;
1210         uint8_t dpcd_lt_buffer[5] = {0};
1211         union dpcd_training_pattern dpcd_pattern = {0};
1212         uint32_t size_in_bytes;
1213         bool edp_workaround = false; /* TODO link_prop.INTERNAL */
1214         dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
1215
1216         if (is_repeater(lt_settings, offset))
1217                 dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
1218                         ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
1219
1220         /*****************************************************************
1221         * DpcdAddress_TrainingPatternSet
1222         *****************************************************************/
1223         dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
1224                 dp_training_pattern_to_dpcd_training_pattern(link, pattern);
1225
1226         dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
1227                 dp_initialize_scrambling_data_symbols(link, pattern);
1228
1229         dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
1230                 = dpcd_pattern.raw;
1231
1232         if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1233                 dpia_set_tps_notification(
1234                         link,
1235                         lt_settings,
1236                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET,
1237                         offset);
1238
1239         if (is_repeater(lt_settings, offset)) {
1240                 DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
1241                         __func__,
1242                         offset,
1243                         dpcd_base_lt_offset,
1244                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1245         } else {
1246                 DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
1247                         __func__,
1248                         dpcd_base_lt_offset,
1249                         dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
1250         }
1251
1252         /* concatenate everything into one buffer*/
1253         size_in_bytes = lt_settings->link_settings.lane_count *
1254                         sizeof(lt_settings->dpcd_lane_settings[0]);
1255
1256          // 0x00103 - 0x00102
1257         memmove(
1258                 &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
1259                 lt_settings->dpcd_lane_settings,
1260                 size_in_bytes);
1261
1262         if (is_repeater(lt_settings, offset)) {
1263                 if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
1264                                 DP_128b_132b_ENCODING)
1265                         DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1266                                         " 0x%X TX_FFE_PRESET_VALUE = %x\n",
1267                                         __func__,
1268                                         offset,
1269                                         dpcd_base_lt_offset,
1270                                         lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
1271                 else if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
1272                                 DP_8b_10b_ENCODING)
1273                 DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
1274                                 " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
1275                         __func__,
1276                         offset,
1277                         dpcd_base_lt_offset,
1278                         lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1279                         lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1280                         lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1281                         lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1282         } else {
1283                 if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
1284                                 DP_128b_132b_ENCODING)
1285                         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X TX_FFE_PRESET_VALUE = %x\n",
1286                                         __func__,
1287                                         dpcd_base_lt_offset,
1288                                         lt_settings->dpcd_lane_settings[0].tx_ffe.PRESET_VALUE);
1289                 else if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
1290                                 DP_8b_10b_ENCODING)
1291                         DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
1292                                         __func__,
1293                                         dpcd_base_lt_offset,
1294                                         lt_settings->dpcd_lane_settings[0].bits.VOLTAGE_SWING_SET,
1295                                         lt_settings->dpcd_lane_settings[0].bits.PRE_EMPHASIS_SET,
1296                                         lt_settings->dpcd_lane_settings[0].bits.MAX_SWING_REACHED,
1297                                         lt_settings->dpcd_lane_settings[0].bits.MAX_PRE_EMPHASIS_REACHED);
1298         }
1299         if (edp_workaround) {
1300                 /* for eDP write in 2 parts because the 5-byte burst is
1301                 * causing issues on some eDP panels (EPR#366724)
1302                 */
1303                 core_link_write_dpcd(
1304                         link,
1305                         DP_TRAINING_PATTERN_SET,
1306                         &dpcd_pattern.raw,
1307                         sizeof(dpcd_pattern.raw));
1308
1309                 core_link_write_dpcd(
1310                         link,
1311                         DP_TRAINING_LANE0_SET,
1312                         (uint8_t *)(lt_settings->dpcd_lane_settings),
1313                         size_in_bytes);
1314
1315         } else if (link_dp_get_encoding_format(&lt_settings->link_settings) ==
1316                         DP_128b_132b_ENCODING) {
1317                 core_link_write_dpcd(
1318                                 link,
1319                                 dpcd_base_lt_offset,
1320                                 dpcd_lt_buffer,
1321                                 sizeof(dpcd_lt_buffer));
1322         } else
1323                 /* write it all in (1 + number-of-lanes)-byte burst*/
1324                 core_link_write_dpcd(
1325                                 link,
1326                                 dpcd_base_lt_offset,
1327                                 dpcd_lt_buffer,
1328                                 size_in_bytes + sizeof(dpcd_pattern.raw));
1329 }
1330
1331 void start_clock_recovery_pattern_early(struct dc_link *link,
1332                 const struct link_resource *link_res,
1333                 struct link_training_settings *lt_settings,
1334                 uint32_t offset)
1335 {
1336         DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
1337                         __func__);
1338         dp_set_hw_training_pattern(link, link_res, lt_settings->pattern_for_cr, offset);
1339         dp_set_hw_lane_settings(link, link_res, lt_settings, offset);
1340         udelay(400);
1341 }
1342
1343 void dp_set_hw_test_pattern(
1344         struct dc_link *link,
1345         const struct link_resource *link_res,
1346         enum dp_test_pattern test_pattern,
1347         uint8_t *custom_pattern,
1348         uint32_t custom_pattern_size)
1349 {
1350         const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
1351         struct encoder_set_dp_phy_pattern_param pattern_param = {0};
1352
1353         pattern_param.dp_phy_pattern = test_pattern;
1354         pattern_param.custom_pattern = custom_pattern;
1355         pattern_param.custom_pattern_size = custom_pattern_size;
1356         pattern_param.dp_panel_mode = dp_get_panel_mode(link);
1357
1358         if (link_hwss->ext.set_dp_link_test_pattern)
1359                 link_hwss->ext.set_dp_link_test_pattern(link, link_res, &pattern_param);
1360 }
1361
1362 bool dp_set_hw_training_pattern(
1363         struct dc_link *link,
1364         const struct link_resource *link_res,
1365         enum dc_dp_training_pattern pattern,
1366         uint32_t offset)
1367 {
1368         enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
1369
1370         switch (pattern) {
1371         case DP_TRAINING_PATTERN_SEQUENCE_1:
1372                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN1;
1373                 break;
1374         case DP_TRAINING_PATTERN_SEQUENCE_2:
1375                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN2;
1376                 break;
1377         case DP_TRAINING_PATTERN_SEQUENCE_3:
1378                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN3;
1379                 break;
1380         case DP_TRAINING_PATTERN_SEQUENCE_4:
1381                 test_pattern = DP_TEST_PATTERN_TRAINING_PATTERN4;
1382                 break;
1383         case DP_128b_132b_TPS1:
1384                 test_pattern = DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE;
1385                 break;
1386         case DP_128b_132b_TPS2:
1387                 test_pattern = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE;
1388                 break;
1389         default:
1390                 break;
1391         }
1392
1393         dp_set_hw_test_pattern(link, link_res, test_pattern, NULL, 0);
1394
1395         return true;
1396 }
1397
1398 static bool perform_post_lt_adj_req_sequence(
1399                 struct dc_link *link,
1400                 const struct link_resource *link_res,
1401                 struct link_training_settings *lt_settings)
1402 {
1403         enum dc_lane_count lane_count =
1404         lt_settings->link_settings.lane_count;
1405
1406         uint32_t adj_req_count;
1407         uint32_t adj_req_timer;
1408         bool req_drv_setting_changed;
1409         uint32_t lane;
1410         union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
1411         union lane_align_status_updated dpcd_lane_status_updated = {0};
1412         union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = {0};
1413
1414         req_drv_setting_changed = false;
1415         for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
1416         adj_req_count++) {
1417
1418                 req_drv_setting_changed = false;
1419
1420                 for (adj_req_timer = 0;
1421                         adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
1422                         adj_req_timer++) {
1423
1424                         dp_get_lane_status_and_lane_adjust(
1425                                 link,
1426                                 lt_settings,
1427                                 dpcd_lane_status,
1428                                 &dpcd_lane_status_updated,
1429                                 dpcd_lane_adjust,
1430                                 DPRX);
1431
1432                         if (dpcd_lane_status_updated.bits.
1433                                         POST_LT_ADJ_REQ_IN_PROGRESS == 0)
1434                                 return true;
1435
1436                         if (!dp_is_cr_done(lane_count, dpcd_lane_status))
1437                                 return false;
1438
1439                         if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
1440                                         !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
1441                                         !dp_is_interlane_aligned(dpcd_lane_status_updated))
1442                                 return false;
1443
1444                         for (lane = 0; lane < (uint32_t)(lane_count); lane++) {
1445
1446                                 if (lt_settings->
1447                                 dpcd_lane_settings[lane].bits.VOLTAGE_SWING_SET !=
1448                                 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_LANE ||
1449                                 lt_settings->dpcd_lane_settings[lane].bits.PRE_EMPHASIS_SET !=
1450                                 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_LANE) {
1451
1452                                         req_drv_setting_changed = true;
1453                                         break;
1454                                 }
1455                         }
1456
1457                         if (req_drv_setting_changed) {
1458                                 dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
1459                                                 lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
1460
1461                                 dp_set_drive_settings(link,
1462                                                 link_res,
1463                                                 lt_settings);
1464                                 break;
1465                         }
1466
1467                         msleep(1);
1468                 }
1469
1470                 if (!req_drv_setting_changed) {
1471                         DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
1472                                 __func__);
1473
1474                         ASSERT(0);
1475                         return true;
1476                 }
1477         }
1478         DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
1479                 __func__);
1480
1481         ASSERT(0);
1482         return true;
1483
1484 }
1485
1486 static enum link_training_result dp_transition_to_video_idle(
1487         struct dc_link *link,
1488         const struct link_resource *link_res,
1489         struct link_training_settings *lt_settings,
1490         enum link_training_result status)
1491 {
1492         union lane_count_set lane_count_set = {0};
1493
1494         /* 4. mainlink output idle pattern*/
1495         dp_set_hw_test_pattern(link, link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1496
1497         /*
1498          * 5. post training adjust if required
1499          * If the upstream DPTX and downstream DPRX both support TPS4,
1500          * TPS4 must be used instead of POST_LT_ADJ_REQ.
1501          */
1502         if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
1503                         lt_settings->pattern_for_eq >= DP_TRAINING_PATTERN_SEQUENCE_4) {
1504                 /* delay 5ms after Main Link output idle pattern and then check
1505                  * DPCD 0202h.
1506                  */
1507                 if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
1508                         msleep(5);
1509                         if (!link->skip_fallback_on_link_loss)
1510                                 status = dp_check_link_loss_status(link, lt_settings);
1511                 }
1512                 return status;
1513         }
1514
1515         if (status == LINK_TRAINING_SUCCESS &&
1516                 perform_post_lt_adj_req_sequence(link, link_res, lt_settings) == false)
1517                 status = LINK_TRAINING_LQA_FAIL;
1518
1519         lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
1520         lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
1521         lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
1522
1523         core_link_write_dpcd(
1524                 link,
1525                 DP_LANE_COUNT_SET,
1526                 &lane_count_set.raw,
1527                 sizeof(lane_count_set));
1528
1529         return status;
1530 }
1531
1532 enum link_training_result dp_perform_link_training(
1533         struct dc_link *link,
1534         const struct link_resource *link_res,
1535         const struct dc_link_settings *link_settings,
1536         bool skip_video_pattern)
1537 {
1538         enum link_training_result status = LINK_TRAINING_SUCCESS;
1539         struct link_training_settings lt_settings = {0};
1540         enum dp_link_encoding encoding =
1541                         link_dp_get_encoding_format(link_settings);
1542
1543         /* decide training settings */
1544         dp_decide_training_settings(
1545                         link,
1546                         link_settings,
1547                         &lt_settings);
1548
1549         override_training_settings(
1550                         link,
1551                         &link->preferred_training_settings,
1552                         &lt_settings);
1553
1554         /* reset previous training states */
1555         dpcd_exit_training_mode(link, encoding);
1556
1557         /* configure link prior to entering training mode */
1558         dpcd_configure_lttpr_mode(link, &lt_settings);
1559         dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready);
1560         dpcd_configure_channel_coding(link, &lt_settings);
1561
1562         /* enter training mode:
1563          * Per DP specs starting from here, DPTX device shall not issue
1564          * Non-LT AUX transactions inside training mode.
1565          */
1566         if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) && encoding == DP_8b_10b_ENCODING)
1567                 status = dp_perform_fixed_vs_pe_training_sequence(link, link_res, &lt_settings);
1568         else if (encoding == DP_8b_10b_ENCODING)
1569                 status = dp_perform_8b_10b_link_training(link, link_res, &lt_settings);
1570         else if (encoding == DP_128b_132b_ENCODING)
1571                 status = dp_perform_128b_132b_link_training(link, link_res, &lt_settings);
1572         else
1573                 ASSERT(0);
1574
1575         /* exit training mode */
1576         if ((dpcd_exit_training_mode(link, encoding) != LINK_TRAINING_SUCCESS || status == LINK_TRAINING_ABORT) &&
1577                         link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
1578                 dpia_training_abort(link, &lt_settings, 0);
1579
1580         /* switch to video idle */
1581         if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
1582                 status = dp_transition_to_video_idle(link,
1583                                 link_res,
1584                                 &lt_settings,
1585                                 status);
1586
1587         /* dump debug data */
1588         dp_log_training_result(link, &lt_settings, status);
1589         if (status != LINK_TRAINING_SUCCESS)
1590                 link->ctx->dc->debug_data.ltFailCount++;
1591         return status;
1592 }
1593
1594 bool perform_link_training_with_retries(
1595         const struct dc_link_settings *link_setting,
1596         bool skip_video_pattern,
1597         int attempts,
1598         struct pipe_ctx *pipe_ctx,
1599         enum signal_type signal,
1600         bool do_fallback)
1601 {
1602         int j;
1603         uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
1604         struct dc_stream_state *stream = pipe_ctx->stream;
1605         struct dc_link *link = stream->link;
1606         enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
1607         enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
1608         struct dc_link_settings cur_link_settings = *link_setting;
1609         struct dc_link_settings max_link_settings = *link_setting;
1610         const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
1611         int fail_count = 0;
1612         bool is_link_bw_low = false; /* link bandwidth < stream bandwidth */
1613         bool is_link_bw_min = /* RBR x 1 */
1614                 (cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1615                 (cur_link_settings.lane_count <= LANE_COUNT_ONE);
1616
1617         dp_trace_commit_lt_init(link);
1618
1619
1620         if (link_dp_get_encoding_format(&cur_link_settings) == DP_8b_10b_ENCODING)
1621                 /* We need to do this before the link training to ensure the idle
1622                  * pattern in SST mode will be sent right after the link training
1623                  */
1624                 link_hwss->setup_stream_encoder(pipe_ctx);
1625
1626         dp_trace_set_lt_start_timestamp(link, false);
1627         j = 0;
1628         while (j < attempts && fail_count < (attempts * 10)) {
1629
1630                 DC_LOG_HW_LINK_TRAINING("%s: Beginning link(%d) training attempt %u of %d @ rate(%d) x lane(%d) @ spread = %x\n",
1631                                         __func__, link->link_index, (unsigned int)j + 1, attempts,
1632                                        cur_link_settings.link_rate, cur_link_settings.lane_count,
1633                                        cur_link_settings.link_spread);
1634
1635                 dp_enable_link_phy(
1636                         link,
1637                         &pipe_ctx->link_res,
1638                         signal,
1639                         pipe_ctx->clock_source->id,
1640                         &cur_link_settings);
1641
1642                 if (stream->sink_patches.dppowerup_delay > 0) {
1643                         int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
1644
1645                         msleep(delay_dp_power_up_in_ms);
1646                 }
1647
1648                 edp_set_panel_assr(link, pipe_ctx, &panel_mode, true);
1649
1650                 dp_set_panel_mode(link, panel_mode);
1651
1652                 if (link->aux_access_disabled) {
1653                         dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &cur_link_settings);
1654                         return true;
1655                 } else {
1656                         if (!link->dc->config.consolidated_dpia_dp_lt && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
1657                                 status = dpia_perform_link_training(
1658                                                 link,
1659                                                 &pipe_ctx->link_res,
1660                                                 &cur_link_settings,
1661                                                 skip_video_pattern);
1662
1663                                 /* Transmit idle pattern once training successful. */
1664                                 if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {
1665                                         dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
1666                                         // Update verified link settings to current one
1667                                         // Because DPIA LT might fallback to lower link setting.
1668                                         if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1669                                                 link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
1670                                                 link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
1671                                                 dm_helpers_dp_mst_update_branch_bandwidth(link->ctx, link);
1672                                         }
1673                                 }
1674                         } else {
1675                                 status = dp_perform_link_training(
1676                                                 link,
1677                                                 &pipe_ctx->link_res,
1678                                                 &cur_link_settings,
1679                                                 skip_video_pattern);
1680                         }
1681
1682                         dp_trace_lt_total_count_increment(link, false);
1683                         dp_trace_lt_result_update(link, status, false);
1684                         dp_trace_set_lt_end_timestamp(link, false);
1685                         if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {
1686                                 // Update verified link settings to current one
1687                                 // Because DPIA LT might fallback to lower link setting.
1688                                 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1689                                                 stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1690                                         link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
1691                                         link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
1692                                         dm_helpers_dp_mst_update_branch_bandwidth(link->ctx, link);
1693                                 }
1694                                 return true;
1695                         }
1696                 }
1697
1698                 fail_count++;
1699                 dp_trace_lt_fail_count_update(link, fail_count, false);
1700                 if (link->ep_type == DISPLAY_ENDPOINT_PHY) {
1701                         /* latest link training still fail or link training is aborted
1702                          * skip delay and keep PHY on
1703                          */
1704                         if (j == (attempts - 1) || (status == LINK_TRAINING_ABORT))
1705                                 break;
1706                 }
1707
1708                 if (j == (attempts - 1)) {
1709                         DC_LOG_WARNING(
1710                                 "%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) @ spread = %x : fail reason:(%d)\n",
1711                                 __func__, link->link_index, (unsigned int)j + 1, attempts,
1712                                 cur_link_settings.link_rate, cur_link_settings.lane_count,
1713                                 cur_link_settings.link_spread, status);
1714                 } else {
1715                         DC_LOG_HW_LINK_TRAINING(
1716                                 "%s: Link(%d) training attempt %u of %d failed @ rate(%d) x lane(%d) @ spread = %x : fail reason:(%d)\n",
1717                                 __func__, link->link_index, (unsigned int)j + 1, attempts,
1718                                 cur_link_settings.link_rate, cur_link_settings.lane_count,
1719                                 cur_link_settings.link_spread, status);
1720                 }
1721
1722                 dp_disable_link_phy(link, &pipe_ctx->link_res, signal);
1723
1724                 /* Abort link training if failure due to sink being unplugged. */
1725                 if (status == LINK_TRAINING_ABORT) {
1726                         enum dc_connection_type type = dc_connection_none;
1727
1728                         if (link_detect_connection_type(link, &type) && type == dc_connection_none) {
1729                                 DC_LOG_HW_LINK_TRAINING("%s: Aborting training because sink unplugged\n", __func__);
1730                                 break;
1731                         }
1732                 }
1733
1734                 /* Try to train again at original settings if:
1735                  * - not falling back between training attempts;
1736                  * - aborted previous attempt due to reasons other than sink unplug;
1737                  * - successfully trained but at a link rate lower than that required by stream;
1738                  * - reached minimum link bandwidth.
1739                  */
1740                 if (!do_fallback || (status == LINK_TRAINING_ABORT) ||
1741                                 (status == LINK_TRAINING_SUCCESS && is_link_bw_low) ||
1742                                 is_link_bw_min) {
1743                         j++;
1744                         cur_link_settings = *link_setting;
1745                         delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
1746                         is_link_bw_low = false;
1747                         is_link_bw_min = (cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1748                                 (cur_link_settings.lane_count <= LANE_COUNT_ONE);
1749
1750                 } else if (do_fallback) { /* Try training at lower link bandwidth if doing fallback. */
1751                         uint32_t req_bw;
1752                         uint32_t link_bw;
1753                         enum dc_link_encoding_format link_encoding = DC_LINK_ENCODING_UNSPECIFIED;
1754
1755                         decide_fallback_link_setting(link, &max_link_settings,
1756                                         &cur_link_settings, status);
1757
1758                         if (link_dp_get_encoding_format(&cur_link_settings) == DP_8b_10b_ENCODING)
1759                                 link_encoding = DC_LINK_ENCODING_DP_8b_10b;
1760                         else if (link_dp_get_encoding_format(&cur_link_settings) == DP_128b_132b_ENCODING)
1761                                 link_encoding = DC_LINK_ENCODING_DP_128b_132b;
1762
1763                         /* Flag if reduced link bandwidth no longer meets stream requirements or fallen back to
1764                          * minimum link bandwidth.
1765                          */
1766                         req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, link_encoding);
1767                         link_bw = dp_link_bandwidth_kbps(link, &cur_link_settings);
1768                         is_link_bw_low = (req_bw > link_bw);
1769                         is_link_bw_min = ((cur_link_settings.link_rate <= LINK_RATE_LOW) &&
1770                                 (cur_link_settings.lane_count <= LANE_COUNT_ONE));
1771
1772                         if (is_link_bw_low) {
1773                                 DC_LOG_WARNING(
1774                                         "%s: Link(%d) bandwidth too low after fallback req_bw(%d) > link_bw(%d)\n",
1775                                         __func__, link->link_index, req_bw, link_bw);
1776
1777                                 return false;
1778                         }
1779                 }
1780
1781                 msleep(delay_between_attempts);
1782         }
1783
1784         return false;
1785 }
1786
This page took 0.146216 seconds and 4 git commands to generate.