drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 /* FILE POLICY AND INTENDED USAGE:
  27  * This file implements dp specific link capability retrieval sequence. It is
  28  * responsible for retrieving, parsing, overriding, deciding capability obtained
  29  * from dp link. Link capability consists of encoders, DPRXs, cables, retimers,
  30  * usb and all other possible backend capabilities. Other components should
  31  * include this header file in order to access link capability. Accessing link
  32  * capability by dereferencing dc_link outside dp_link_capability is not a
  33  * recommended method as it makes the component dependent on the underlying data
  34  * structure used to represent link capability instead of function interfaces.
  35  */
  36
  37 #include "link_dp_capability.h"
  38 #include "link_ddc.h"
  39 #include "link_dpcd.h"
  40 #include "link_dp_dpia.h"
  41 #include "link_dp_phy.h"
  42 #include "link_edp_panel_control.h"
  43 #include "link_dp_irq_handler.h"
  44 #include "link/accessories/link_dp_trace.h"
  45 #include "link/link_detection.h"
  46 #include "link/link_validation.h"
  47 #include "link_dp_training.h"
  48 #include "atomfirmware.h"
  49 #include "resource.h"
  50 #include "link_enc_cfg.h"
  51 #include "dc_dmub_srv.h"
  52 #include "gpio_service_interface.h"
  53
  54 #define DC_LOGGER \
  55         link->ctx->logger
  56 #define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
  57
  58 #ifndef MAX
  59 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
  60 #endif
  61 #ifndef MIN
  62 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
  63 #endif
  64
  65 struct dp_lt_fallback_entry {
  66         enum dc_lane_count lane_count;
  67         enum dc_link_rate link_rate;
  68 };
  69
  70 static const struct dp_lt_fallback_entry dp_lt_fallbacks[] = {
  71                 /* This link training fallback array is ordered by
  72                  * link bandwidth from highest to lowest.
  73                  * DP specs makes it a normative policy to always
  74                  * choose the next highest link bandwidth during
  75                  * link training fallback.
  76                  */
  77                 {LANE_COUNT_FOUR, LINK_RATE_UHBR20},
  78                 {LANE_COUNT_FOUR, LINK_RATE_UHBR13_5},
  79                 {LANE_COUNT_TWO, LINK_RATE_UHBR20},
  80                 {LANE_COUNT_FOUR, LINK_RATE_UHBR10},
  81                 {LANE_COUNT_TWO, LINK_RATE_UHBR13_5},
  82                 {LANE_COUNT_FOUR, LINK_RATE_HIGH3},
  83                 {LANE_COUNT_ONE, LINK_RATE_UHBR20},
  84                 {LANE_COUNT_TWO, LINK_RATE_UHBR10},
  85                 {LANE_COUNT_FOUR, LINK_RATE_HIGH2},
  86                 {LANE_COUNT_ONE, LINK_RATE_UHBR13_5},
  87                 {LANE_COUNT_TWO, LINK_RATE_HIGH3},
  88                 {LANE_COUNT_ONE, LINK_RATE_UHBR10},
  89                 {LANE_COUNT_TWO, LINK_RATE_HIGH2},
  90                 {LANE_COUNT_FOUR, LINK_RATE_HIGH},
  91                 {LANE_COUNT_ONE, LINK_RATE_HIGH3},
  92                 {LANE_COUNT_FOUR, LINK_RATE_LOW},
  93                 {LANE_COUNT_ONE, LINK_RATE_HIGH2},
  94                 {LANE_COUNT_TWO, LINK_RATE_HIGH},
  95                 {LANE_COUNT_TWO, LINK_RATE_LOW},
  96                 {LANE_COUNT_ONE, LINK_RATE_HIGH},
  97                 {LANE_COUNT_ONE, LINK_RATE_LOW},
  98 };
  99
 100 static const struct dc_link_settings fail_safe_link_settings = {
 101                 .lane_count = LANE_COUNT_ONE,
 102                 .link_rate = LINK_RATE_LOW,
 103                 .link_spread = LINK_SPREAD_DISABLED,
 104 };
 105
 106 bool is_dp_active_dongle(const struct dc_link *link)
 107 {
 108         return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) &&
 109                                 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER);
 110 }
 111
 112 bool is_dp_branch_device(const struct dc_link *link)
 113 {
 114         return link->dpcd_caps.is_branch_dev;
 115 }
 116
 117 static int translate_dpcd_max_bpc(enum dpcd_downstream_port_max_bpc bpc)
 118 {
 119         switch (bpc) {
 120         case DOWN_STREAM_MAX_8BPC:
 121                 return 8;
 122         case DOWN_STREAM_MAX_10BPC:
 123                 return 10;
 124         case DOWN_STREAM_MAX_12BPC:
 125                 return 12;
 126         case DOWN_STREAM_MAX_16BPC:
 127                 return 16;
 128         default:
 129                 break;
 130         }
 131
 132         return -1;
 133 }
 134
 135 uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count)
 136 {
 137         switch (lttpr_repeater_count) {
 138         case 0x80: // 1 lttpr repeater
 139                 return 1;
 140         case 0x40: // 2 lttpr repeaters
 141                 return 2;
 142         case 0x20: // 3 lttpr repeaters
 143                 return 3;
 144         case 0x10: // 4 lttpr repeaters
 145                 return 4;
 146         case 0x08: // 5 lttpr repeaters
 147                 return 5;
 148         case 0x04: // 6 lttpr repeaters
 149                 return 6;
 150         case 0x02: // 7 lttpr repeaters
 151                 return 7;
 152         case 0x01: // 8 lttpr repeaters
 153                 return 8;
 154         default:
 155                 break;
 156         }
 157         return 0; // invalid value
 158 }
 159
 160 uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw)
 161 {
 162         switch (bw) {
 163         case 0b001:
 164                 return 9000000;
 165         case 0b010:
 166                 return 18000000;
 167         case 0b011:
 168                 return 24000000;
 169         case 0b100:
 170                 return 32000000;
 171         case 0b101:
 172                 return 40000000;
 173         case 0b110:
 174                 return 48000000;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz)
 181 {
 182         enum dc_link_rate link_rate;
 183         // LinkRate is normally stored as a multiplier of 0.27 Gbps per lane. Do the translation.
 184         switch (link_rate_in_khz) {
 185         case 1620000:
 186                 link_rate = LINK_RATE_LOW;      // Rate_1 (RBR) - 1.62 Gbps/Lane
 187                 break;
 188         case 2160000:
 189                 link_rate = LINK_RATE_RATE_2;   // Rate_2       - 2.16 Gbps/Lane
 190                 break;
 191         case 2430000:
 192                 link_rate = LINK_RATE_RATE_3;   // Rate_3       - 2.43 Gbps/Lane
 193                 break;
 194         case 2700000:
 195                 link_rate = LINK_RATE_HIGH;     // Rate_4 (HBR) - 2.70 Gbps/Lane
 196                 break;
 197         case 3240000:
 198                 link_rate = LINK_RATE_RBR2;     // Rate_5 (RBR2)- 3.24 Gbps/Lane
 199                 break;
 200         case 4320000:
 201                 link_rate = LINK_RATE_RATE_6;   // Rate_6       - 4.32 Gbps/Lane
 202                 break;
 203         case 5400000:
 204                 link_rate = LINK_RATE_HIGH2;    // Rate_7 (HBR2)- 5.40 Gbps/Lane
 205                 break;
 206         case 6750000:
 207                 link_rate = LINK_RATE_RATE_8;   // Rate_8       - 6.75 Gbps/Lane
 208                 break;
 209         case 8100000:
 210                 link_rate = LINK_RATE_HIGH3;    // Rate_9 (HBR3)- 8.10 Gbps/Lane
 211                 break;
 212         case 10000000:
 213                 link_rate = LINK_RATE_UHBR10;   // UHBR10 - 10.0 Gbps/Lane
 214                 break;
 215         case 13500000:
 216                 link_rate = LINK_RATE_UHBR13_5; // UHBR13.5 - 13.5 Gbps/Lane
 217                 break;
 218         case 20000000:
 219                 link_rate = LINK_RATE_UHBR20;   // UHBR20 - 20.0 Gbps/Lane
 220                 break;
 221
 222         default:
 223                 link_rate = LINK_RATE_UNKNOWN;
 224                 break;
 225         }
 226         return link_rate;
 227 }
 228
 229 static union dp_cable_id intersect_cable_id(
 230                 union dp_cable_id *a, union dp_cable_id *b)
 231 {
 232         union dp_cable_id out;
 233
 234         out.bits.UHBR10_20_CAPABILITY = MIN(a->bits.UHBR10_20_CAPABILITY,
 235                         b->bits.UHBR10_20_CAPABILITY);
 236         out.bits.UHBR13_5_CAPABILITY = MIN(a->bits.UHBR13_5_CAPABILITY,
 237                         b->bits.UHBR13_5_CAPABILITY);
 238         out.bits.CABLE_TYPE = MAX(a->bits.CABLE_TYPE, b->bits.CABLE_TYPE);
 239
 240         return out;
 241 }
 242
 243 /*
 244  * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw.
 245  */
 246 static uint32_t intersect_frl_link_bw_support(
 247         const uint32_t max_supported_frl_bw_in_kbps,
 248         const union hdmi_encoded_link_bw hdmi_encoded_link_bw)
 249 {
 250         uint32_t supported_bw_in_kbps = max_supported_frl_bw_in_kbps;
 251
 252         // HDMI_ENCODED_LINK_BW bits are only valid if HDMI Link Configuration bit is 1 (FRL mode)
 253         if (hdmi_encoded_link_bw.bits.FRL_MODE) {
 254                 if (hdmi_encoded_link_bw.bits.BW_48Gbps)
 255                         supported_bw_in_kbps = 48000000;
 256                 else if (hdmi_encoded_link_bw.bits.BW_40Gbps)
 257                         supported_bw_in_kbps = 40000000;
 258                 else if (hdmi_encoded_link_bw.bits.BW_32Gbps)
 259                         supported_bw_in_kbps = 32000000;
 260                 else if (hdmi_encoded_link_bw.bits.BW_24Gbps)
 261                         supported_bw_in_kbps = 24000000;
 262                 else if (hdmi_encoded_link_bw.bits.BW_18Gbps)
 263                         supported_bw_in_kbps = 18000000;
 264                 else if (hdmi_encoded_link_bw.bits.BW_9Gbps)
 265                         supported_bw_in_kbps = 9000000;
 266         }
 267
 268         return supported_bw_in_kbps;
 269 }
 270
 271 static enum clock_source_id get_clock_source_id(struct dc_link *link)
 272 {
 273         enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
 274         struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;
 275
 276         if (dp_cs != NULL) {
 277                 dp_cs_id = dp_cs->id;
 278         } else {
 279                 /*
 280                  * dp clock source is not initialized for some reason.
 281                  * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
 282                  */
 283                 ASSERT(dp_cs);
 284         }
 285
 286         return dp_cs_id;
 287 }
 288
 289 static void dp_wa_power_up_0010FA(struct dc_link *link, uint8_t *dpcd_data,
 290                 int length)
 291 {
 292         int retry = 0;
 293
 294         if (!link->dpcd_caps.dpcd_rev.raw) {
 295                 do {
 296                         dpcd_write_rx_power_ctrl(link, true);
 297                         core_link_read_dpcd(link, DP_DPCD_REV,
 298                                                         dpcd_data, length);
 299                         link->dpcd_caps.dpcd_rev.raw = dpcd_data[
 300                                 DP_DPCD_REV -
 301                                 DP_DPCD_REV];
 302                 } while (retry++ < 4 && !link->dpcd_caps.dpcd_rev.raw);
 303         }
 304
 305         if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER) {
 306                 switch (link->dpcd_caps.branch_dev_id) {
 307                 /* 0010FA active dongles (DP-VGA, DP-DLDVI converters) power down
 308                  * all internal circuits including AUX communication preventing
 309                  * reading DPCD table and EDID (spec violation).
 310                  * Encoder will skip DP RX power down on disable_output to
 311                  * keep receiver powered all the time.*/
 312                 case DP_BRANCH_DEVICE_ID_0010FA:
 313                 case DP_BRANCH_DEVICE_ID_0080E1:
 314                 case DP_BRANCH_DEVICE_ID_00E04C:
 315                         link->wa_flags.dp_keep_receiver_powered = true;
 316                         break;
 317
 318                 /* TODO: May need work around for other dongles. */
 319                 default:
 320                         link->wa_flags.dp_keep_receiver_powered = false;
 321                         break;
 322                 }
 323         } else
 324                 link->wa_flags.dp_keep_receiver_powered = false;
 325 }
 326
 327 bool dp_is_fec_supported(const struct dc_link *link)
 328 {
 329         /* TODO - use asic cap instead of link_enc->features
 330          * we no longer know which link enc to use for this link before commit
 331          */
 332         struct link_encoder *link_enc = NULL;
 333
 334         link_enc = link_enc_cfg_get_link_enc(link);
 335         ASSERT(link_enc);
 336
 337         return (dc_is_dp_signal(link->connector_signal) && link_enc &&
 338                         link_enc->features.fec_supported &&
 339                         link->dpcd_caps.fec_cap.bits.FEC_CAPABLE);
 340 }
 341
 342 bool dp_should_enable_fec(const struct dc_link *link)
 343 {
 344         bool force_disable = false;
 345
 346         if (link->fec_state == dc_link_fec_enabled)
 347                 force_disable = false;
 348         else if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
 349                         link->local_sink &&
 350                         link->local_sink->edid_caps.panel_patch.disable_fec)
 351                 force_disable = true;
 352         else if (link->connector_signal == SIGNAL_TYPE_EDP
 353                         && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.
 354                          dsc_support.DSC_SUPPORT == false
 355                                 || link->panel_config.dsc.disable_dsc_edp
 356                                 || !link->dc->caps.edp_dsc_support))
 357                 force_disable = true;
 358
 359         return !force_disable && dp_is_fec_supported(link);
 360 }
 361
 362 bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
 363 {
 364         /* If this assert is hit then we have a link encoder dynamic management issue */
 365         ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true);
 366         return (pipe_ctx->stream_res.hpo_dp_stream_enc &&
 367                         pipe_ctx->link_res.hpo_dp_link_enc &&
 368                         dc_is_dp_signal(pipe_ctx->stream->signal));
 369 }
 370
 371 bool dp_is_lttpr_present(struct dc_link *link)
 372 {
 373         /* Some sink devices report invalid LTTPR revision, so don't validate against that cap */
 374         return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
 375                         link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
 376                         link->dpcd_caps.lttpr_caps.max_lane_count <= 4);
 377 }
 378
 379 /* in DP compliance test, DPR-120 may have
 380  * a random value in its MAX_LINK_BW dpcd field.
 381  * We map it to the maximum supported link rate that
 382  * is smaller than MAX_LINK_BW in this case.
 383  */
 384 static enum dc_link_rate get_link_rate_from_max_link_bw(
 385                  uint8_t max_link_bw)
 386 {
 387         enum dc_link_rate link_rate;
 388
 389         if (max_link_bw >= LINK_RATE_HIGH3) {
 390                 link_rate = LINK_RATE_HIGH3;
 391         } else if (max_link_bw < LINK_RATE_HIGH3
 392                         && max_link_bw >= LINK_RATE_HIGH2) {
 393                 link_rate = LINK_RATE_HIGH2;
 394         } else if (max_link_bw < LINK_RATE_HIGH2
 395                         && max_link_bw >= LINK_RATE_HIGH) {
 396                 link_rate = LINK_RATE_HIGH;
 397         } else if (max_link_bw < LINK_RATE_HIGH
 398                         && max_link_bw >= LINK_RATE_LOW) {
 399                 link_rate = LINK_RATE_LOW;
 400         } else {
 401                 link_rate = LINK_RATE_UNKNOWN;
 402         }
 403
 404         return link_rate;
 405 }
 406
 407 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
 408 {
 409
 410         enum dc_link_rate lttpr_max_link_rate = LINK_RATE_UNKNOWN;
 411
 412         switch (link->dpcd_caps.lttpr_caps.max_link_rate) {
 413         case LINK_RATE_LOW:
 414         case LINK_RATE_HIGH:
 415         case LINK_RATE_HIGH2:
 416         case LINK_RATE_HIGH3:
 417                 lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
 418                 break;
 419         }
 420
 421         if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
 422                 lttpr_max_link_rate = LINK_RATE_UHBR20;
 423         else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
 424                 lttpr_max_link_rate = LINK_RATE_UHBR13_5;
 425         else if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR10)
 426                 lttpr_max_link_rate = LINK_RATE_UHBR10;
 427
 428         return lttpr_max_link_rate;
 429 }
 430
 431 static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link)
 432 {
 433         enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN;
 434
 435         if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR20) {
 436                 cable_max_link_rate = LINK_RATE_UHBR20;
 437         } else if (link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY) {
 438                 cable_max_link_rate = LINK_RATE_UHBR13_5;
 439         } else if (link->dpcd_caps.cable_id.bits.UHBR10_20_CAPABILITY & DP_UHBR10) {
 440                 // allow DP40 cables to do UHBR13.5 for passive or unknown cable type
 441                 if (link->dpcd_caps.cable_id.bits.CABLE_TYPE < 2) {
 442                         cable_max_link_rate = LINK_RATE_UHBR13_5;
 443                 } else {
 444                         cable_max_link_rate = LINK_RATE_UHBR10;
 445                 }
 446         }
 447
 448         return cable_max_link_rate;
 449 }
 450
 451 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count)
 452 {
 453         return lane_count <= LANE_COUNT_ONE;
 454 }
 455
 456 static inline bool reached_minimum_link_rate(enum dc_link_rate link_rate)
 457 {
 458         return link_rate <= LINK_RATE_LOW;
 459 }
 460
 461 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count)
 462 {
 463         switch (lane_count) {
 464         case LANE_COUNT_FOUR:
 465                 return LANE_COUNT_TWO;
 466         case LANE_COUNT_TWO:
 467                 return LANE_COUNT_ONE;
 468         case LANE_COUNT_ONE:
 469                 return LANE_COUNT_UNKNOWN;
 470         default:
 471                 return LANE_COUNT_UNKNOWN;
 472         }
 473 }
 474
 475 static enum dc_link_rate reduce_link_rate(const struct dc_link *link, enum dc_link_rate link_rate)
 476 {
 477         // NEEDSWORK: provide some details about why this function never returns some of the
 478         // obscure link rates such as 4.32 Gbps or 3.24 Gbps and if such behavior is intended.
 479         //
 480
 481         switch (link_rate) {
 482         case LINK_RATE_UHBR20:
 483                 return LINK_RATE_UHBR13_5;
 484         case LINK_RATE_UHBR13_5:
 485                 return LINK_RATE_UHBR10;
 486         case LINK_RATE_UHBR10:
 487                 return LINK_RATE_HIGH3;
 488         case LINK_RATE_HIGH3:
 489                 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->debug.support_eDP1_5)
 490                         return LINK_RATE_RATE_8;
 491                 return LINK_RATE_HIGH2;
 492         case LINK_RATE_RATE_8:
 493                 return LINK_RATE_HIGH2;
 494         case LINK_RATE_HIGH2:
 495                 return LINK_RATE_HIGH;
 496         case LINK_RATE_RATE_6:
 497         case LINK_RATE_RBR2:
 498                 return LINK_RATE_HIGH;
 499         case LINK_RATE_HIGH:
 500                 return LINK_RATE_LOW;
 501         case LINK_RATE_RATE_3:
 502         case LINK_RATE_RATE_2:
 503                 return LINK_RATE_LOW;
 504         case LINK_RATE_LOW:
 505         default:
 506                 return LINK_RATE_UNKNOWN;
 507         }
 508 }
 509
 510 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count)
 511 {
 512         switch (lane_count) {
 513         case LANE_COUNT_ONE:
 514                 return LANE_COUNT_TWO;
 515         case LANE_COUNT_TWO:
 516                 return LANE_COUNT_FOUR;
 517         default:
 518                 return LANE_COUNT_UNKNOWN;
 519         }
 520 }
 521
 522 static enum dc_link_rate increase_link_rate(struct dc_link *link,
 523                 enum dc_link_rate link_rate)
 524 {
 525         switch (link_rate) {
 526         case LINK_RATE_LOW:
 527                 return LINK_RATE_HIGH;
 528         case LINK_RATE_HIGH:
 529                 return LINK_RATE_HIGH2;
 530         case LINK_RATE_HIGH2:
 531                 return LINK_RATE_HIGH3;
 532         case LINK_RATE_HIGH3:
 533                 return LINK_RATE_UHBR10;
 534         case LINK_RATE_UHBR10:
 535                 /* upto DP2.x specs UHBR13.5 is the only link rate that could be
 536                  * not supported by DPRX when higher link rate is supported.
 537                  * so we treat it as a special case for code simplicity. When we
 538                  * have new specs with more link rates like this, we should
 539                  * consider a more generic solution to handle discrete link
 540                  * rate capabilities.
 541                  */
 542                 return link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 ?
 543                                 LINK_RATE_UHBR13_5 : LINK_RATE_UHBR20;
 544         case LINK_RATE_UHBR13_5:
 545                 return LINK_RATE_UHBR20;
 546         default:
 547                 return LINK_RATE_UNKNOWN;
 548         }
 549 }
 550
 551 static void increase_edp_link_rate(struct dc_link *link,
 552                 struct dc_link_settings *current_link_setting)
 553 {
 554         if (current_link_setting->use_link_rate_set) {
 555                 if (current_link_setting->link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 556                         current_link_setting->link_rate_set++;
 557                         current_link_setting->link_rate =
 558                                 link->dpcd_caps.edp_supported_link_rates[current_link_setting->link_rate_set];
 559                 } else {
 560                         current_link_setting->use_link_rate_set = false;
 561                         current_link_setting->link_rate = LINK_RATE_UHBR10;
 562                 }
 563         } else {
 564                 current_link_setting->link_rate = increase_link_rate(link, current_link_setting->link_rate);
 565         }
 566 }
 567
 568 static bool decide_fallback_link_setting_max_bw_policy(
 569                 struct dc_link *link,
 570                 const struct dc_link_settings *max,
 571                 struct dc_link_settings *cur,
 572                 enum link_training_result training_result)
 573 {
 574         uint32_t cur_idx = 0, next_idx;
 575         bool found = false;
 576
 577         if (training_result == LINK_TRAINING_ABORT)
 578                 return false;
 579
 580         while (cur_idx < ARRAY_SIZE(dp_lt_fallbacks))
 581                 /* find current index */
 582                 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count &&
 583                                 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate)
 584                         break;
 585                 else
 586                         cur_idx++;
 587
 588         next_idx = cur_idx + 1;
 589
 590         while (next_idx < ARRAY_SIZE(dp_lt_fallbacks))
 591                 /* find next index */
 592                 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count ||
 593                                 dp_lt_fallbacks[next_idx].link_rate > max->link_rate)
 594                         next_idx++;
 595                 else if (dp_lt_fallbacks[next_idx].link_rate == LINK_RATE_UHBR13_5 &&
 596                                 link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5 == 0)
 597                         /* upto DP2.x specs UHBR13.5 is the only link rate that
 598                          * could be not supported by DPRX when higher link rate
 599                          * is supported. so we treat it as a special case for
 600                          * code simplicity. When we have new specs with more
 601                          * link rates like this, we should consider a more
 602                          * generic solution to handle discrete link rate
 603                          * capabilities.
 604                          */
 605                         next_idx++;
 606                 else
 607                         break;
 608
 609         if (next_idx < ARRAY_SIZE(dp_lt_fallbacks)) {
 610                 cur->lane_count = dp_lt_fallbacks[next_idx].lane_count;
 611                 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate;
 612                 found = true;
 613         }
 614
 615         return found;
 616 }
 617
 618 /*
 619  * function: set link rate and lane count fallback based
 620  * on current link setting and last link training result
 621  * return value:
 622  *                      true - link setting could be set
 623  *                      false - has reached minimum setting
 624  *                                      and no further fallback could be done
 625  */
 626 bool decide_fallback_link_setting(
 627                 struct dc_link *link,
 628                 struct dc_link_settings *max,
 629                 struct dc_link_settings *cur,
 630                 enum link_training_result training_result)
 631 {
 632         if (link_dp_get_encoding_format(max) == DP_128b_132b_ENCODING ||
 633                         link->dc->debug.force_dp2_lt_fallback_method)
 634                 return decide_fallback_link_setting_max_bw_policy(link, max,
 635                                 cur, training_result);
 636
 637         switch (training_result) {
 638         case LINK_TRAINING_CR_FAIL_LANE0:
 639         case LINK_TRAINING_CR_FAIL_LANE1:
 640         case LINK_TRAINING_CR_FAIL_LANE23:
 641         case LINK_TRAINING_LQA_FAIL:
 642         {
 643                 if (!reached_minimum_link_rate(cur->link_rate)) {
 644                         cur->link_rate = reduce_link_rate(link, cur->link_rate);
 645                 } else if (!reached_minimum_lane_count(cur->lane_count)) {
 646                         cur->link_rate = max->link_rate;
 647                         if (training_result == LINK_TRAINING_CR_FAIL_LANE0)
 648                                 return false;
 649                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE1)
 650                                 cur->lane_count = LANE_COUNT_ONE;
 651                         else if (training_result == LINK_TRAINING_CR_FAIL_LANE23)
 652                                 cur->lane_count = LANE_COUNT_TWO;
 653                         else
 654                                 cur->lane_count = reduce_lane_count(cur->lane_count);
 655                 } else {
 656                         return false;
 657                 }
 658                 break;
 659         }
 660         case LINK_TRAINING_EQ_FAIL_EQ:
 661         case LINK_TRAINING_EQ_FAIL_CR_PARTIAL:
 662         {
 663                 if (!reached_minimum_lane_count(cur->lane_count)) {
 664                         cur->lane_count = reduce_lane_count(cur->lane_count);
 665                 } else if (!reached_minimum_link_rate(cur->link_rate)) {
 666                         cur->link_rate = reduce_link_rate(link, cur->link_rate);
 667                         /* Reduce max link rate to avoid potential infinite loop.
 668                          * Needed so that any subsequent CR_FAIL fallback can't
 669                          * re-set the link rate higher than the link rate from
 670                          * the latest EQ_FAIL fallback.
 671                          */
 672                         max->link_rate = cur->link_rate;
 673                         cur->lane_count = max->lane_count;
 674                 } else {
 675                         return false;
 676                 }
 677                 break;
 678         }
 679         case LINK_TRAINING_EQ_FAIL_CR:
 680         {
 681                 if (!reached_minimum_link_rate(cur->link_rate)) {
 682                         cur->link_rate = reduce_link_rate(link, cur->link_rate);
 683                         /* Reduce max link rate to avoid potential infinite loop.
 684                          * Needed so that any subsequent CR_FAIL fallback can't
 685                          * re-set the link rate higher than the link rate from
 686                          * the latest EQ_FAIL fallback.
 687                          */
 688                         max->link_rate = cur->link_rate;
 689                         cur->lane_count = max->lane_count;
 690                 } else {
 691                         return false;
 692                 }
 693                 break;
 694         }
 695         default:
 696                 return false;
 697         }
 698         return true;
 699 }
 700 static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw)
 701 {
 702         struct dc_link_settings initial_link_setting = {
 703                 LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0};
 704         struct dc_link_settings current_link_setting =
 705                         initial_link_setting;
 706         uint32_t link_bw;
 707
 708         if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
 709                 return false;
 710
 711         /* search for the minimum link setting that:
 712          * 1. is supported according to the link training result
 713          * 2. could support the b/w requested by the timing
 714          */
 715         while (current_link_setting.link_rate <=
 716                         link->verified_link_cap.link_rate) {
 717                 link_bw = dp_link_bandwidth_kbps(
 718                                 link,
 719                                 &current_link_setting);
 720                 if (req_bw <= link_bw) {
 721                         *link_setting = current_link_setting;
 722                         return true;
 723                 }
 724
 725                 if (current_link_setting.lane_count <
 726                                 link->verified_link_cap.lane_count) {
 727                         current_link_setting.lane_count =
 728                                         increase_lane_count(
 729                                                         current_link_setting.lane_count);
 730                 } else {
 731                         current_link_setting.link_rate =
 732                                         increase_link_rate(link,
 733                                                         current_link_setting.link_rate);
 734                         current_link_setting.lane_count =
 735                                         initial_link_setting.lane_count;
 736                 }
 737         }
 738
 739         return false;
 740 }
 741
 742 bool edp_decide_link_settings(struct dc_link *link,
 743                 struct dc_link_settings *link_setting, uint32_t req_bw)
 744 {
 745         struct dc_link_settings initial_link_setting;
 746         struct dc_link_settings current_link_setting;
 747         uint32_t link_bw;
 748
 749         /*
 750          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
 751          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
 752          */
 753         if (!edp_is_ilr_optimization_enabled(link)) {
 754                 *link_setting = link->verified_link_cap;
 755                 return true;
 756         }
 757
 758         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
 759         initial_link_setting.lane_count = LANE_COUNT_ONE;
 760         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
 761         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
 762         initial_link_setting.use_link_rate_set = true;
 763         initial_link_setting.link_rate_set = 0;
 764         current_link_setting = initial_link_setting;
 765
 766         /* search for the minimum link setting that:
 767          * 1. is supported according to the link training result
 768          * 2. could support the b/w requested by the timing
 769          */
 770         while (current_link_setting.link_rate <=
 771                         link->verified_link_cap.link_rate) {
 772                 link_bw = dp_link_bandwidth_kbps(
 773                                 link,
 774                                 &current_link_setting);
 775                 if (req_bw <= link_bw) {
 776                         *link_setting = current_link_setting;
 777                         return true;
 778                 }
 779
 780                 if (current_link_setting.lane_count <
 781                                 link->verified_link_cap.lane_count) {
 782                         current_link_setting.lane_count =
 783                                         increase_lane_count(
 784                                                         current_link_setting.lane_count);
 785                 } else {
 786                         increase_edp_link_rate(link, &current_link_setting);
 787                 }
 788         }
 789         return false;
 790 }
 791
 792 bool decide_edp_link_settings_with_dsc(struct dc_link *link,
 793                 struct dc_link_settings *link_setting,
 794                 uint32_t req_bw,
 795                 enum dc_link_rate max_link_rate)
 796 {
 797         struct dc_link_settings initial_link_setting;
 798         struct dc_link_settings current_link_setting;
 799         uint32_t link_bw;
 800
 801         unsigned int policy = 0;
 802
 803         policy = link->panel_config.dsc.force_dsc_edp_policy;
 804         if (max_link_rate == LINK_RATE_UNKNOWN)
 805                 max_link_rate = link->verified_link_cap.link_rate;
 806         /*
 807          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
 808          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
 809          */
 810         if (!edp_is_ilr_optimization_enabled(link)) {
 811                 /* for DSC enabled case, we search for minimum lane count */
 812                 memset(&initial_link_setting, 0, sizeof(initial_link_setting));
 813                 initial_link_setting.lane_count = LANE_COUNT_ONE;
 814                 initial_link_setting.link_rate = LINK_RATE_LOW;
 815                 initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
 816                 initial_link_setting.use_link_rate_set = false;
 817                 initial_link_setting.link_rate_set = 0;
 818                 current_link_setting = initial_link_setting;
 819                 if (req_bw > dp_link_bandwidth_kbps(link, &link->verified_link_cap))
 820                         return false;
 821
 822                 /* search for the minimum link setting that:
 823                  * 1. is supported according to the link training result
 824                  * 2. could support the b/w requested by the timing
 825                  */
 826                 while (current_link_setting.link_rate <=
 827                                 max_link_rate) {
 828                         link_bw = dp_link_bandwidth_kbps(
 829                                         link,
 830                                         &current_link_setting);
 831                         if (req_bw <= link_bw) {
 832                                 *link_setting = current_link_setting;
 833                                 return true;
 834                         }
 835                         if (policy) {
 836                                 /* minimize lane */
 837                                 if (current_link_setting.link_rate < max_link_rate) {
 838                                         increase_edp_link_rate(link, &current_link_setting);
 839                                 } else {
 840                                         if (current_link_setting.lane_count <
 841                                                                         link->verified_link_cap.lane_count) {
 842                                                 current_link_setting.lane_count =
 843                                                                 increase_lane_count(
 844                                                                                 current_link_setting.lane_count);
 845                                                 current_link_setting.link_rate = initial_link_setting.link_rate;
 846                                         } else
 847                                                 break;
 848                                 }
 849                         } else {
 850                                 /* minimize link rate */
 851                                 if (current_link_setting.lane_count <
 852                                                 link->verified_link_cap.lane_count) {
 853                                         current_link_setting.lane_count =
 854                                                         increase_lane_count(
 855                                                                         current_link_setting.lane_count);
 856                                 } else {
 857                                         increase_edp_link_rate(link, &current_link_setting);
 858                                         current_link_setting.lane_count =
 859                                                         initial_link_setting.lane_count;
 860                                 }
 861                         }
 862                 }
 863                 return false;
 864         }
 865
 866         /* if optimize edp link is supported */
 867         memset(&initial_link_setting, 0, sizeof(initial_link_setting));
 868         initial_link_setting.lane_count = LANE_COUNT_ONE;
 869         initial_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[0];
 870         initial_link_setting.link_spread = LINK_SPREAD_DISABLED;
 871         initial_link_setting.use_link_rate_set = true;
 872         initial_link_setting.link_rate_set = 0;
 873         current_link_setting = initial_link_setting;
 874
 875         /* search for the minimum link setting that:
 876          * 1. is supported according to the link training result
 877          * 2. could support the b/w requested by the timing
 878          */
 879         while (current_link_setting.link_rate <=
 880                         max_link_rate) {
 881                 link_bw = dp_link_bandwidth_kbps(
 882                                 link,
 883                                 &current_link_setting);
 884                 if (req_bw <= link_bw) {
 885                         *link_setting = current_link_setting;
 886                         return true;
 887                 }
 888                 if (policy) {
 889                         /* minimize lane */
 890                         if (current_link_setting.link_rate < max_link_rate) {
 891                                 increase_edp_link_rate(link, &current_link_setting);
 892                         } else {
 893                                 if (current_link_setting.lane_count < link->verified_link_cap.lane_count) {
 894                                         current_link_setting.lane_count =
 895                                                         increase_lane_count(
 896                                                                         current_link_setting.lane_count);
 897                                         current_link_setting.link_rate_set = initial_link_setting.link_rate_set;
 898                                         current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set;
 899                                         current_link_setting.link_rate =
 900                                                 link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set];
 901                                 } else
 902                                         break;
 903                         }
 904                 } else {
 905                         /* minimize link rate */
 906                         if (current_link_setting.lane_count <
 907                                         link->verified_link_cap.lane_count) {
 908                                 current_link_setting.lane_count =
 909                                                 increase_lane_count(
 910                                                                 current_link_setting.lane_count);
 911                         } else {
 912                                 increase_edp_link_rate(link, &current_link_setting);
 913                                 if (current_link_setting.link_rate == LINK_RATE_UNKNOWN)
 914                                         break;
 915                         }
 916                 }
 917         }
 918         return false;
 919 }
 920
 921 static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting)
 922 {
 923         *link_setting = link->verified_link_cap;
 924         return true;
 925 }
 926
 927 bool link_decide_link_settings(struct dc_stream_state *stream,
 928         struct dc_link_settings *link_setting)
 929 {
 930         struct dc_link *link = stream->link;
 931         uint32_t req_bw = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(link));
 932
 933         memset(link_setting, 0, sizeof(*link_setting));
 934
 935         if (dc_is_dp_signal(stream->signal)  &&
 936                         link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
 937                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) {
 938                 /* if preferred is specified through AMDDP, use it, if it's enough
 939                  * to drive the mode
 940                  */
 941                 *link_setting = link->preferred_link_setting;
 942         } else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 943                 /* MST doesn't perform link training for now
 944                  * TODO: add MST specific link training routine
 945                  */
 946                 decide_mst_link_settings(link, link_setting);
 947         } else if (link->connector_signal == SIGNAL_TYPE_EDP) {
 948                 /* enable edp link optimization for DSC eDP case */
 949                 if (stream->timing.flags.DSC) {
 950                         enum dc_link_rate max_link_rate = LINK_RATE_UNKNOWN;
 951
 952                         if (link->panel_config.dsc.force_dsc_edp_policy) {
 953                                 /* calculate link max link rate cap*/
 954                                 struct dc_link_settings tmp_link_setting;
 955                                 struct dc_crtc_timing tmp_timing = stream->timing;
 956                                 uint32_t orig_req_bw;
 957
 958                                 tmp_link_setting.link_rate = LINK_RATE_UNKNOWN;
 959                                 tmp_timing.flags.DSC = 0;
 960                                 orig_req_bw = dc_bandwidth_in_kbps_from_timing(&tmp_timing,
 961                                                 dc_link_get_highest_encoding_format(link));
 962                                 edp_decide_link_settings(link, &tmp_link_setting, orig_req_bw);
 963                                 max_link_rate = tmp_link_setting.link_rate;
 964                         }
 965                         decide_edp_link_settings_with_dsc(link, link_setting, req_bw, max_link_rate);
 966                 } else {
 967                         edp_decide_link_settings(link, link_setting, req_bw);
 968                 }
 969         } else if (stream->signal == SIGNAL_TYPE_VIRTUAL) {
 970                 link_setting->lane_count = LANE_COUNT_FOUR;
 971                 link_setting->link_rate = LINK_RATE_HIGH3;
 972         } else {
 973                 decide_dp_link_settings(link, link_setting, req_bw);
 974         }
 975
 976         return link_setting->lane_count != LANE_COUNT_UNKNOWN &&
 977                         link_setting->link_rate != LINK_RATE_UNKNOWN;
 978 }
 979
 980 enum dp_link_encoding link_dp_get_encoding_format(const struct dc_link_settings *link_settings)
 981 {
 982         if ((link_settings->link_rate >= LINK_RATE_LOW) &&
 983                         (link_settings->link_rate <= LINK_RATE_HIGH3))
 984                 return DP_8b_10b_ENCODING;
 985         else if ((link_settings->link_rate >= LINK_RATE_UHBR10) &&
 986                         (link_settings->link_rate <= LINK_RATE_UHBR20))
 987                 return DP_128b_132b_ENCODING;
 988         return DP_UNKNOWN_ENCODING;
 989 }
 990
 991 enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link)
 992 {
 993         struct dc_link_settings link_settings = {0};
 994
 995         if (!dc_is_dp_signal(link->connector_signal))
 996                 return DP_UNKNOWN_ENCODING;
 997
 998         if (link->preferred_link_setting.lane_count !=
 999                         LANE_COUNT_UNKNOWN &&
1000                         link->preferred_link_setting.link_rate !=
1001                                         LINK_RATE_UNKNOWN) {
1002                 link_settings = link->preferred_link_setting;
1003         } else {
1004                 decide_mst_link_settings(link, &link_settings);
1005         }
1006
1007         return link_dp_get_encoding_format(&link_settings);
1008 }
1009
1010 static void read_dp_device_vendor_id(struct dc_link *link)
1011 {
1012         struct dp_device_vendor_id dp_id = {0};
1013
1014         /* read IEEE branch device id */
1015         core_link_read_dpcd(
1016                 link,
1017                 DP_BRANCH_OUI,
1018                 (uint8_t *)&dp_id,
1019                 sizeof(dp_id));
1020
1021         link->dpcd_caps.branch_dev_id =
1022                 (dp_id.ieee_oui[0] << 16) +
1023                 (dp_id.ieee_oui[1] << 8) +
1024                 dp_id.ieee_oui[2];
1025
1026         memmove(
1027                 link->dpcd_caps.branch_dev_name,
1028                 dp_id.ieee_device_id,
1029                 sizeof(dp_id.ieee_device_id));
1030 }
1031
1032 static enum dc_status wake_up_aux_channel(struct dc_link *link)
1033 {
1034         enum dc_status status = DC_ERROR_UNEXPECTED;
1035         uint32_t aux_channel_retry_cnt = 0;
1036         uint8_t dpcd_power_state = '\0';
1037
1038         while (status != DC_OK && aux_channel_retry_cnt < 10) {
1039                 status = core_link_read_dpcd(link, DP_SET_POWER,
1040                                 &dpcd_power_state, sizeof(dpcd_power_state));
1041
1042                 /* Delay 1 ms if AUX CH is in power down state. Based on spec
1043                  * section 2.3.1.2, if AUX CH may be powered down due to
1044                  * write to DPCD 600h = 2. Sink AUX CH is monitoring differential
1045                  * signal and may need up to 1 ms before being able to reply.
1046                  */
1047                 if (status != DC_OK || dpcd_power_state == DP_SET_POWER_D3) {
1048                         fsleep(1000);
1049                         aux_channel_retry_cnt++;
1050                 }
1051         }
1052
1053         if (status != DC_OK) {
1054                 dpcd_power_state = DP_SET_POWER_D0;
1055                 status = core_link_write_dpcd(
1056                                 link,
1057                                 DP_SET_POWER,
1058                                 &dpcd_power_state,
1059                                 sizeof(dpcd_power_state));
1060
1061                 dpcd_power_state = DP_SET_POWER_D3;
1062                 status = core_link_write_dpcd(
1063                                 link,
1064                                 DP_SET_POWER,
1065                                 &dpcd_power_state,
1066                                 sizeof(dpcd_power_state));
1067                 DC_LOG_DC("%s: Failed to power up sink\n", __func__);
1068                 return DC_ERROR_UNEXPECTED;
1069         }
1070
1071         return DC_OK;
1072 }
1073
1074 static void get_active_converter_info(
1075         uint8_t data, struct dc_link *link)
1076 {
1077         union dp_downstream_port_present ds_port = { .byte = data };
1078         memset(&link->dpcd_caps.dongle_caps, 0, sizeof(link->dpcd_caps.dongle_caps));
1079
1080         /* decode converter info*/
1081         if (!ds_port.fields.PORT_PRESENT) {
1082                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1083                 set_dongle_type(link->ddc,
1084                                 link->dpcd_caps.dongle_type);
1085                 link->dpcd_caps.is_branch_dev = false;
1086                 return;
1087         }
1088
1089         /* DPCD 0x5 bit 0 = 1, it indicate it's branch device */
1090         link->dpcd_caps.is_branch_dev = ds_port.fields.PORT_PRESENT;
1091
1092         switch (ds_port.fields.PORT_TYPE) {
1093         case DOWNSTREAM_VGA:
1094                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_VGA_CONVERTER;
1095                 break;
1096         case DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS:
1097                 /* At this point we don't know is it DVI or HDMI or DP++,
1098                  * assume DVI.*/
1099                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_DP_DVI_CONVERTER;
1100                 break;
1101         default:
1102                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1103                 break;
1104         }
1105
1106         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_11) {
1107                 uint8_t det_caps[16] = {0}; /* CTS 4.2.2.7 expects source to read Detailed Capabilities Info : 00080h-0008F.*/
1108                 union dwnstream_port_caps_byte0 *port_caps =
1109                         (union dwnstream_port_caps_byte0 *)det_caps;
1110                 if (core_link_read_dpcd(link, DP_DOWNSTREAM_PORT_0,
1111                                 det_caps, sizeof(det_caps)) == DC_OK) {
1112
1113                         switch (port_caps->bits.DWN_STRM_PORTX_TYPE) {
1114                         /*Handle DP case as DONGLE_NONE*/
1115                         case DOWN_STREAM_DETAILED_DP:
1116                                 link->dpcd_caps.dongle_type = DISPLAY_DONGLE_NONE;
1117                                 break;
1118                         case DOWN_STREAM_DETAILED_VGA:
1119                                 link->dpcd_caps.dongle_type =
1120                                         DISPLAY_DONGLE_DP_VGA_CONVERTER;
1121                                 break;
1122                         case DOWN_STREAM_DETAILED_DVI:
1123                                 link->dpcd_caps.dongle_type =
1124                                         DISPLAY_DONGLE_DP_DVI_CONVERTER;
1125                                 break;
1126                         case DOWN_STREAM_DETAILED_HDMI:
1127                         case DOWN_STREAM_DETAILED_DP_PLUS_PLUS:
1128                                 /*Handle DP++ active converter case, process DP++ case as HDMI case according DP1.4 spec*/
1129                                 link->dpcd_caps.dongle_type =
1130                                         DISPLAY_DONGLE_DP_HDMI_CONVERTER;
1131
1132                                 link->dpcd_caps.dongle_caps.dongle_type = link->dpcd_caps.dongle_type;
1133                                 if (ds_port.fields.DETAILED_CAPS) {
1134
1135                                         union dwnstream_port_caps_byte3_hdmi
1136                                                 hdmi_caps = {.raw = det_caps[3] };
1137                                         union dwnstream_port_caps_byte2
1138                                                 hdmi_color_caps = {.raw = det_caps[2] };
1139                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz =
1140                                                 det_caps[1] * 2500;
1141
1142                                         link->dpcd_caps.dongle_caps.is_dp_hdmi_s3d_converter =
1143                                                 hdmi_caps.bits.FRAME_SEQ_TO_FRAME_PACK;
1144                                         /*YCBCR capability only for HDMI case*/
1145                                         if (port_caps->bits.DWN_STRM_PORTX_TYPE
1146                                                         == DOWN_STREAM_DETAILED_HDMI) {
1147                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_pass_through =
1148                                                                 hdmi_caps.bits.YCrCr422_PASS_THROUGH;
1149                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_pass_through =
1150                                                                 hdmi_caps.bits.YCrCr420_PASS_THROUGH;
1151                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr422_converter =
1152                                                                 hdmi_caps.bits.YCrCr422_CONVERSION;
1153                                                 link->dpcd_caps.dongle_caps.is_dp_hdmi_ycbcr420_converter =
1154                                                                 hdmi_caps.bits.YCrCr420_CONVERSION;
1155                                         }
1156
1157                                         link->dpcd_caps.dongle_caps.dp_hdmi_max_bpc =
1158                                                 translate_dpcd_max_bpc(
1159                                                         hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT);
1160
1161                                         if (link->dc->caps.dp_hdmi21_pcon_support) {
1162                                                 union hdmi_encoded_link_bw hdmi_encoded_link_bw;
1163
1164                                                 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps =
1165                                                                 link_bw_kbps_from_raw_frl_link_rate_data(
1166                                                                                 hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT);
1167
1168                                                 // Intersect reported max link bw support with the supported link rate post FRL link training
1169                                                 if (core_link_read_dpcd(link, DP_PCON_HDMI_POST_FRL_STATUS,
1170                                                                 &hdmi_encoded_link_bw.raw, sizeof(hdmi_encoded_link_bw)) == DC_OK) {
1171                                                         link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps = intersect_frl_link_bw_support(
1172                                                                         link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps,
1173                                                                         hdmi_encoded_link_bw);
1174                                                         DC_LOG_DC("%s: pcon frl link bw = %u\n", __func__,
1175                                                                 link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps);
1176                                                 }
1177
1178                                                 if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0)
1179                                                         link->dpcd_caps.dongle_caps.extendedCapValid = true;
1180                                         }
1181
1182                                         if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0)
1183                                                 link->dpcd_caps.dongle_caps.extendedCapValid = true;
1184                                 }
1185
1186                                 break;
1187                         }
1188                 }
1189         }
1190
1191         set_dongle_type(link->ddc, link->dpcd_caps.dongle_type);
1192
1193         {
1194                 struct dp_sink_hw_fw_revision dp_hw_fw_revision = {0};
1195
1196                 core_link_read_dpcd(
1197                         link,
1198                         DP_BRANCH_REVISION_START,
1199                         (uint8_t *)&dp_hw_fw_revision,
1200                         sizeof(dp_hw_fw_revision));
1201
1202                 link->dpcd_caps.branch_hw_revision =
1203                         dp_hw_fw_revision.ieee_hw_rev;
1204
1205                 memmove(
1206                         link->dpcd_caps.branch_fw_revision,
1207                         dp_hw_fw_revision.ieee_fw_rev,
1208                         sizeof(dp_hw_fw_revision.ieee_fw_rev));
1209         }
1210         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
1211                         link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1212                 union dp_dfp_cap_ext dfp_cap_ext;
1213                 memset(&dfp_cap_ext, '\0', sizeof (dfp_cap_ext));
1214                 core_link_read_dpcd(
1215                                 link,
1216                                 DP_DFP_CAPABILITY_EXTENSION_SUPPORT,
1217                                 dfp_cap_ext.raw,
1218                                 sizeof(dfp_cap_ext.raw));
1219                 link->dpcd_caps.dongle_caps.dfp_cap_ext.supported = dfp_cap_ext.fields.supported;
1220                 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps =
1221                                 dfp_cap_ext.fields.max_pixel_rate_in_mps[0] +
1222                                 (dfp_cap_ext.fields.max_pixel_rate_in_mps[1] << 8);
1223                 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width =
1224                                 dfp_cap_ext.fields.max_video_h_active_width[0] +
1225                                 (dfp_cap_ext.fields.max_video_h_active_width[1] << 8);
1226                 link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height =
1227                                 dfp_cap_ext.fields.max_video_v_active_height[0] +
1228                                 (dfp_cap_ext.fields.max_video_v_active_height[1] << 8);
1229                 link->dpcd_caps.dongle_caps.dfp_cap_ext.encoding_format_caps =
1230                                 dfp_cap_ext.fields.encoding_format_caps;
1231                 link->dpcd_caps.dongle_caps.dfp_cap_ext.rgb_color_depth_caps =
1232                                 dfp_cap_ext.fields.rgb_color_depth_caps;
1233                 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr444_color_depth_caps =
1234                                 dfp_cap_ext.fields.ycbcr444_color_depth_caps;
1235                 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr422_color_depth_caps =
1236                                 dfp_cap_ext.fields.ycbcr422_color_depth_caps;
1237                 link->dpcd_caps.dongle_caps.dfp_cap_ext.ycbcr420_color_depth_caps =
1238                                 dfp_cap_ext.fields.ycbcr420_color_depth_caps;
1239                 DC_LOG_DP2("DFP capability extension is read at link %d", link->link_index);
1240                 DC_LOG_DP2("\tdfp_cap_ext.supported = %s", link->dpcd_caps.dongle_caps.dfp_cap_ext.supported ? "true" : "false");
1241                 DC_LOG_DP2("\tdfp_cap_ext.max_pixel_rate_in_mps = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_pixel_rate_in_mps);
1242                 DC_LOG_DP2("\tdfp_cap_ext.max_video_h_active_width = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_h_active_width);
1243                 DC_LOG_DP2("\tdfp_cap_ext.max_video_v_active_height = %d", link->dpcd_caps.dongle_caps.dfp_cap_ext.max_video_v_active_height);
1244         }
1245 }
1246
1247 static void apply_usbc_combo_phy_reset_wa(struct dc_link *link,
1248                 struct dc_link_settings *link_settings)
1249 {
1250         /* Temporary Renoir-specific workaround PHY will sometimes be in bad
1251          * state on hotplugging display from certain USB-C dongle, so add extra
1252          * cycle of enabling and disabling the PHY before first link training.
1253          */
1254         struct link_resource link_res = {0};
1255         enum clock_source_id dp_cs_id = get_clock_source_id(link);
1256
1257         dp_enable_link_phy(link, &link_res, link->connector_signal,
1258                         dp_cs_id, link_settings);
1259         dp_disable_link_phy(link, &link_res, link->connector_signal);
1260 }
1261
1262 bool dp_overwrite_extended_receiver_cap(struct dc_link *link)
1263 {
1264         uint8_t dpcd_data[16] = {0};
1265         uint32_t read_dpcd_retry_cnt = 3;
1266         enum dc_status status = DC_ERROR_UNEXPECTED;
1267         union dp_downstream_port_present ds_port = { 0 };
1268         union down_stream_port_count down_strm_port_count;
1269         union edp_configuration_cap edp_config_cap;
1270
1271         int i;
1272
1273         for (i = 0; i < read_dpcd_retry_cnt; i++) {
1274                 status = core_link_read_dpcd(
1275                                 link,
1276                                 DP_DPCD_REV,
1277                                 dpcd_data,
1278                                 sizeof(dpcd_data));
1279                 if (status == DC_OK)
1280                         break;
1281         }
1282
1283         link->dpcd_caps.dpcd_rev.raw =
1284                 dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1285
1286         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1287                 return false;
1288
1289         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1290                         DP_DPCD_REV];
1291
1292         get_active_converter_info(ds_port.byte, link);
1293
1294         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1295                         DP_DPCD_REV];
1296
1297         link->dpcd_caps.allow_invalid_MSA_timing_param =
1298                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1299
1300         link->dpcd_caps.max_ln_count.raw = dpcd_data[
1301                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1302
1303         link->dpcd_caps.max_down_spread.raw = dpcd_data[
1304                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1305
1306         link->reported_link_cap.lane_count =
1307                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1308         link->reported_link_cap.link_rate = dpcd_data[
1309                 DP_MAX_LINK_RATE - DP_DPCD_REV];
1310         link->reported_link_cap.link_spread =
1311                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1312                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1313
1314         edp_config_cap.raw = dpcd_data[
1315                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1316         link->dpcd_caps.panel_mode_edp =
1317                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1318         link->dpcd_caps.dpcd_display_control_capable =
1319                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1320
1321         return true;
1322 }
1323
1324 void dpcd_set_source_specific_data(struct dc_link *link)
1325 {
1326         if (!link->dc->vendor_signature.is_valid) {
1327                 enum dc_status __maybe_unused result_write_min_hblank = DC_NOT_SUPPORTED;
1328                 struct dpcd_amd_signature amd_signature = {0};
1329                 struct dpcd_amd_device_id amd_device_id = {0};
1330
1331                 amd_device_id.device_id_byte1 =
1332                                 (uint8_t)(link->ctx->asic_id.chip_id);
1333                 amd_device_id.device_id_byte2 =
1334                                 (uint8_t)(link->ctx->asic_id.chip_id >> 8);
1335                 amd_device_id.dce_version =
1336                                 (uint8_t)(link->ctx->dce_version);
1337                 amd_device_id.dal_version_byte1 = 0x0; // needed? where to get?
1338                 amd_device_id.dal_version_byte2 = 0x0; // needed? where to get?
1339
1340                 core_link_read_dpcd(link, DP_SOURCE_OUI,
1341                                 (uint8_t *)(&amd_signature),
1342                                 sizeof(amd_signature));
1343
1344                 if (!((amd_signature.AMD_IEEE_TxSignature_byte1 == 0x0) &&
1345                         (amd_signature.AMD_IEEE_TxSignature_byte2 == 0x0) &&
1346                         (amd_signature.AMD_IEEE_TxSignature_byte3 == 0x1A))) {
1347
1348                         amd_signature.AMD_IEEE_TxSignature_byte1 = 0x0;
1349                         amd_signature.AMD_IEEE_TxSignature_byte2 = 0x0;
1350                         amd_signature.AMD_IEEE_TxSignature_byte3 = 0x1A;
1351
1352                         core_link_write_dpcd(link, DP_SOURCE_OUI,
1353                                 (uint8_t *)(&amd_signature),
1354                                 sizeof(amd_signature));
1355                 }
1356
1357                 core_link_write_dpcd(link, DP_SOURCE_OUI+0x03,
1358                                 (uint8_t *)(&amd_device_id),
1359                                 sizeof(amd_device_id));
1360
1361                 if (link->ctx->dce_version >= DCN_VERSION_2_0 &&
1362                         link->dc->caps.min_horizontal_blanking_period != 0) {
1363
1364                         uint8_t hblank_size = (uint8_t)link->dc->caps.min_horizontal_blanking_period;
1365
1366                         result_write_min_hblank = core_link_write_dpcd(link,
1367                                 DP_SOURCE_MINIMUM_HBLANK_SUPPORTED, (uint8_t *)(&hblank_size),
1368                                 sizeof(hblank_size));
1369                 }
1370                 DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
1371                                                         WPP_BIT_FLAG_DC_DETECTION_DP_CAPS,
1372                                                         "result=%u link_index=%u enum dce_version=%d DPCD=0x%04X min_hblank=%u branch_dev_id=0x%x branch_dev_name='%c%c%c%c%c%c'",
1373                                                         result_write_min_hblank,
1374                                                         link->link_index,
1375                                                         link->ctx->dce_version,
1376                                                         DP_SOURCE_MINIMUM_HBLANK_SUPPORTED,
1377                                                         link->dc->caps.min_horizontal_blanking_period,
1378                                                         link->dpcd_caps.branch_dev_id,
1379                                                         link->dpcd_caps.branch_dev_name[0],
1380                                                         link->dpcd_caps.branch_dev_name[1],
1381                                                         link->dpcd_caps.branch_dev_name[2],
1382                                                         link->dpcd_caps.branch_dev_name[3],
1383                                                         link->dpcd_caps.branch_dev_name[4],
1384                                                         link->dpcd_caps.branch_dev_name[5]);
1385         } else {
1386                 core_link_write_dpcd(link, DP_SOURCE_OUI,
1387                                 link->dc->vendor_signature.data.raw,
1388                                 sizeof(link->dc->vendor_signature.data.raw));
1389         }
1390 }
1391
1392 void dpcd_write_cable_id_to_dprx(struct dc_link *link)
1393 {
1394         if (!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED ||
1395                         link->dpcd_caps.cable_id.raw == 0 ||
1396                         link->dprx_states.cable_id_written)
1397                 return;
1398
1399         core_link_write_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX,
1400                         &link->dpcd_caps.cable_id.raw,
1401                         sizeof(link->dpcd_caps.cable_id.raw));
1402
1403         link->dprx_states.cable_id_written = 1;
1404 }
1405
1406 static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id)
1407 {
1408         union dmub_rb_cmd cmd;
1409
1410         if (!link->ctx->dmub_srv ||
1411                         link->ep_type != DISPLAY_ENDPOINT_PHY ||
1412                         link->link_enc->features.flags.bits.DP_IS_USB_C == 0)
1413                 return false;
1414
1415         memset(&cmd, 0, sizeof(cmd));
1416         cmd.cable_id.header.type = DMUB_CMD_GET_USBC_CABLE_ID;
1417         cmd.cable_id.header.payload_bytes = sizeof(cmd.cable_id.data);
1418         cmd.cable_id.data.input.phy_inst = resource_transmitter_to_phy_idx(
1419                         link->dc, link->link_enc->transmitter);
1420         if (dc_wake_and_execute_dmub_cmd(link->dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
1421                         cmd.cable_id.header.ret_status == 1) {
1422                 cable_id->raw = cmd.cable_id.data.output_raw;
1423                 DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw);
1424         }
1425         return cmd.cable_id.header.ret_status == 1;
1426 }
1427
1428 static void retrieve_cable_id(struct dc_link *link)
1429 {
1430         union dp_cable_id usbc_cable_id = {0};
1431
1432         link->dpcd_caps.cable_id.raw = 0;
1433         core_link_read_dpcd(link, DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX,
1434                         &link->dpcd_caps.cable_id.raw, sizeof(uint8_t));
1435
1436         if (get_usbc_cable_id(link, &usbc_cable_id))
1437                 link->dpcd_caps.cable_id = intersect_cable_id(
1438                                 &link->dpcd_caps.cable_id, &usbc_cable_id);
1439 }
1440
1441 bool read_is_mst_supported(struct dc_link *link)
1442 {
1443         bool mst          = false;
1444         enum dc_status st = DC_OK;
1445         union dpcd_rev rev;
1446         union mstm_cap cap;
1447
1448         if (link->preferred_training_settings.mst_enable &&
1449                 *link->preferred_training_settings.mst_enable == false) {
1450                 return false;
1451         }
1452
1453         rev.raw  = 0;
1454         cap.raw  = 0;
1455
1456         st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
1457                         sizeof(rev));
1458
1459         if (st == DC_OK && rev.raw >= DPCD_REV_12) {
1460
1461                 st = core_link_read_dpcd(link, DP_MSTM_CAP,
1462                                 &cap.raw, sizeof(cap));
1463                 if (st == DC_OK && cap.bits.MST_CAP == 1)
1464                         mst = true;
1465         }
1466         return mst;
1467
1468 }
1469
1470 /* Read additional sink caps defined in source specific DPCD area
1471  * This function currently only reads from SinkCapability address (DP_SOURCE_SINK_CAP)
1472  * TODO: Add FS caps and read from DP_SOURCE_SINK_FS_CAP as well
1473  */
1474 static bool dpcd_read_sink_ext_caps(struct dc_link *link)
1475 {
1476         uint8_t dpcd_data = 0;
1477         uint8_t edp_general_cap2 = 0;
1478
1479         if (!link)
1480                 return false;
1481
1482         if (core_link_read_dpcd(link, DP_SOURCE_SINK_CAP, &dpcd_data, 1) != DC_OK)
1483                 return false;
1484
1485         link->dpcd_sink_ext_caps.raw = dpcd_data;
1486
1487         if (core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_2, &edp_general_cap2, 1) != DC_OK)
1488                 return false;
1489
1490         link->dpcd_caps.panel_luminance_control = (edp_general_cap2 & DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) != 0;
1491
1492         return true;
1493 }
1494
1495 enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
1496 {
1497         uint8_t lttpr_dpcd_data[8] = {0};
1498         enum dc_status status;
1499         bool is_lttpr_present;
1500
1501         /* Logic to determine LTTPR support*/
1502         bool vbios_lttpr_interop = link->dc->caps.vbios_lttpr_aware;
1503
1504         if (!vbios_lttpr_interop || !link->dc->caps.extended_aux_timeout_support)
1505                 return DC_NOT_SUPPORTED;
1506
1507         /* By reading LTTPR capability, RX assumes that we will enable
1508          * LTTPR extended aux timeout if LTTPR is present.
1509          */
1510         status = core_link_read_dpcd(
1511                         link,
1512                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
1513                         lttpr_dpcd_data,
1514                         sizeof(lttpr_dpcd_data));
1515
1516         link->dpcd_caps.lttpr_caps.revision.raw =
1517                         lttpr_dpcd_data[DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV -
1518                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1519
1520         link->dpcd_caps.lttpr_caps.max_link_rate =
1521                         lttpr_dpcd_data[DP_MAX_LINK_RATE_PHY_REPEATER -
1522                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1523
1524         link->dpcd_caps.lttpr_caps.phy_repeater_cnt =
1525                         lttpr_dpcd_data[DP_PHY_REPEATER_CNT -
1526                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1527
1528         link->dpcd_caps.lttpr_caps.max_lane_count =
1529                         lttpr_dpcd_data[DP_MAX_LANE_COUNT_PHY_REPEATER -
1530                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1531
1532         link->dpcd_caps.lttpr_caps.mode =
1533                         lttpr_dpcd_data[DP_PHY_REPEATER_MODE -
1534                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1535
1536         link->dpcd_caps.lttpr_caps.max_ext_timeout =
1537                         lttpr_dpcd_data[DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT -
1538                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1539         link->dpcd_caps.lttpr_caps.main_link_channel_coding.raw =
1540                         lttpr_dpcd_data[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
1541                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1542
1543         link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.raw =
1544                         lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
1545                                                         DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
1546
1547         /* If this chip cap is set, at least one retimer must exist in the chain
1548          * Override count to 1 if we receive a known bad count (0 or an invalid value) */
1549         if ((link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN) &&
1550                         (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
1551                 /* If you see this message consistently, either the host platform has FIXED_VS flag
1552                  * incorrectly configured or the sink device is returning an invalid count.
1553                  */
1554                 DC_LOG_ERROR("lttpr_caps phy_repeater_cnt is 0x%x, forcing it to 0x80.",
1555                              link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1556                 link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
1557                 DC_LOG_DC("lttpr_caps forced phy_repeater_cnt = %d\n", link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
1558         }
1559
1560         /* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
1561         is_lttpr_present = dp_is_lttpr_present(link);
1562
1563         if (is_lttpr_present)
1564                 CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
1565
1566         DC_LOG_DC("is_lttpr_present = %d\n", is_lttpr_present);
1567         return status;
1568 }
1569
1570 static bool retrieve_link_cap(struct dc_link *link)
1571 {
1572         /* DP_ADAPTER_CAP - DP_DPCD_REV + 1 == 16 and also DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16,
1573          * which means size 16 will be good for both of those DPCD register block reads
1574          */
1575         uint8_t dpcd_data[16];
1576         /*Only need to read 1 byte starting from DP_DPRX_FEATURE_ENUMERATION_LIST.
1577          */
1578         uint8_t dpcd_dprx_data = '\0';
1579
1580         struct dp_device_vendor_id sink_id;
1581         union down_stream_port_count down_strm_port_count;
1582         union edp_configuration_cap edp_config_cap;
1583         union dp_downstream_port_present ds_port = { 0 };
1584         enum dc_status status = DC_ERROR_UNEXPECTED;
1585         uint32_t read_dpcd_retry_cnt = 3;
1586         int i;
1587         struct dp_sink_hw_fw_revision dp_hw_fw_revision;
1588         const uint32_t post_oui_delay = 30; // 30ms
1589         bool is_fec_supported = false;
1590         bool is_dsc_basic_supported = false;
1591         bool is_dsc_passthrough_supported = false;
1592
1593         memset(dpcd_data, '\0', sizeof(dpcd_data));
1594         memset(&down_strm_port_count,
1595                 '\0', sizeof(union down_stream_port_count));
1596         memset(&edp_config_cap, '\0',
1597                 sizeof(union edp_configuration_cap));
1598
1599         /* if extended timeout is supported in hardware,
1600          * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
1601          * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
1602          */
1603         try_to_configure_aux_timeout(link->ddc,
1604                         LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD);
1605
1606         status = dp_retrieve_lttpr_cap(link);
1607
1608         if (status != DC_OK) {
1609                 status = wake_up_aux_channel(link);
1610                 if (status == DC_OK)
1611                         dp_retrieve_lttpr_cap(link);
1612                 else
1613                         return false;
1614         }
1615
1616         if (dp_is_lttpr_present(link)) {
1617                 configure_lttpr_mode_transparent(link);
1618
1619                 // Echo TOTAL_LTTPR_CNT back downstream
1620                 core_link_write_dpcd(
1621                                 link,
1622                                 DP_TOTAL_LTTPR_CNT,
1623                                 &link->dpcd_caps.lttpr_caps.phy_repeater_cnt,
1624                                 sizeof(link->dpcd_caps.lttpr_caps.phy_repeater_cnt));
1625         }
1626
1627         /* Read DP tunneling information. */
1628         status = dpcd_get_tunneling_device_data(link);
1629
1630         dpcd_set_source_specific_data(link);
1631         /* Sink may need to configure internals based on vendor, so allow some
1632          * time before proceeding with possibly vendor specific transactions
1633          */
1634         msleep(post_oui_delay);
1635
1636         for (i = 0; i < read_dpcd_retry_cnt; i++) {
1637                 status = core_link_read_dpcd(
1638                                 link,
1639                                 DP_DPCD_REV,
1640                                 dpcd_data,
1641                                 sizeof(dpcd_data));
1642                 if (status == DC_OK)
1643                         break;
1644         }
1645
1646
1647         if (status != DC_OK) {
1648                 dm_error("%s: Read receiver caps dpcd data failed.\n", __func__);
1649                 return false;
1650         }
1651
1652         if (!dp_is_lttpr_present(link))
1653                 try_to_configure_aux_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
1654
1655
1656         {
1657                 union training_aux_rd_interval aux_rd_interval;
1658
1659                 aux_rd_interval.raw =
1660                         dpcd_data[DP_TRAINING_AUX_RD_INTERVAL];
1661
1662                 link->dpcd_caps.ext_receiver_cap_field_present =
1663                                 aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1;
1664
1665                 if (aux_rd_interval.bits.EXT_RECEIVER_CAP_FIELD_PRESENT == 1) {
1666                         uint8_t ext_cap_data[16];
1667
1668                         memset(ext_cap_data, '\0', sizeof(ext_cap_data));
1669                         for (i = 0; i < read_dpcd_retry_cnt; i++) {
1670                                 status = core_link_read_dpcd(
1671                                 link,
1672                                 DP_DP13_DPCD_REV,
1673                                 ext_cap_data,
1674                                 sizeof(ext_cap_data));
1675                                 if (status == DC_OK) {
1676                                         memcpy(dpcd_data, ext_cap_data, sizeof(dpcd_data));
1677                                         break;
1678                                 }
1679                         }
1680                         if (status != DC_OK)
1681                                 dm_error("%s: Read extend caps data failed, use cap from dpcd 0.\n", __func__);
1682                 }
1683         }
1684
1685         link->dpcd_caps.dpcd_rev.raw =
1686                         dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
1687
1688         if (link->dpcd_caps.ext_receiver_cap_field_present) {
1689                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1690                         status = core_link_read_dpcd(
1691                                         link,
1692                                         DP_DPRX_FEATURE_ENUMERATION_LIST,
1693                                         &dpcd_dprx_data,
1694                                         sizeof(dpcd_dprx_data));
1695                         if (status == DC_OK)
1696                                 break;
1697                 }
1698
1699                 link->dpcd_caps.dprx_feature.raw = dpcd_dprx_data;
1700
1701                 if (status != DC_OK)
1702                         dm_error("%s: Read DPRX caps data failed.\n", __func__);
1703
1704                 /* AdaptiveSyncCapability  */
1705                 dpcd_dprx_data = 0;
1706                 for (i = 0; i < read_dpcd_retry_cnt; i++) {
1707                         status = core_link_read_dpcd(
1708                                         link, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
1709                                         &dpcd_dprx_data, sizeof(dpcd_dprx_data));
1710                         if (status == DC_OK)
1711                                 break;
1712                 }
1713
1714                 link->dpcd_caps.adaptive_sync_caps.dp_adap_sync_caps.raw = dpcd_dprx_data;
1715
1716                 if (status != DC_OK)
1717                         dm_error("%s: Read DPRX caps data failed. Addr:%#x\n",
1718                                         __func__, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1);
1719         }
1720
1721         else {
1722                 link->dpcd_caps.dprx_feature.raw = 0;
1723         }
1724
1725
1726         /* Error condition checking...
1727          * It is impossible for Sink to report Max Lane Count = 0.
1728          * It is possible for Sink to report Max Link Rate = 0, if it is
1729          * an eDP device that is reporting specialized link rates in the
1730          * SUPPORTED_LINK_RATE table.
1731          */
1732         if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)
1733                 return false;
1734
1735         ds_port.byte = dpcd_data[DP_DOWNSTREAMPORT_PRESENT -
1736                                  DP_DPCD_REV];
1737
1738         read_dp_device_vendor_id(link);
1739
1740         /* TODO - decouple raw mst capability from policy decision */
1741         link->dpcd_caps.is_mst_capable = read_is_mst_supported(link);
1742         DC_LOG_DC("%s: MST_Support: %s\n", __func__, str_yes_no(link->dpcd_caps.is_mst_capable));
1743
1744         get_active_converter_info(ds_port.byte, link);
1745
1746         dp_wa_power_up_0010FA(link, dpcd_data, sizeof(dpcd_data));
1747
1748         down_strm_port_count.raw = dpcd_data[DP_DOWN_STREAM_PORT_COUNT -
1749                                  DP_DPCD_REV];
1750
1751         link->dpcd_caps.allow_invalid_MSA_timing_param =
1752                 down_strm_port_count.bits.IGNORE_MSA_TIMING_PARAM;
1753
1754         link->dpcd_caps.max_ln_count.raw = dpcd_data[
1755                 DP_MAX_LANE_COUNT - DP_DPCD_REV];
1756
1757         link->dpcd_caps.max_down_spread.raw = dpcd_data[
1758                 DP_MAX_DOWNSPREAD - DP_DPCD_REV];
1759
1760         link->reported_link_cap.lane_count =
1761                 link->dpcd_caps.max_ln_count.bits.MAX_LANE_COUNT;
1762         link->reported_link_cap.link_rate = get_link_rate_from_max_link_bw(
1763                         dpcd_data[DP_MAX_LINK_RATE - DP_DPCD_REV]);
1764         link->reported_link_cap.link_spread =
1765                 link->dpcd_caps.max_down_spread.bits.MAX_DOWN_SPREAD ?
1766                 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
1767
1768         edp_config_cap.raw = dpcd_data[
1769                 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
1770         link->dpcd_caps.panel_mode_edp =
1771                 edp_config_cap.bits.ALT_SCRAMBLER_RESET;
1772         link->dpcd_caps.dpcd_display_control_capable =
1773                 edp_config_cap.bits.DPCD_DISPLAY_CONTROL_CAPABLE;
1774         link->dpcd_caps.channel_coding_cap.raw =
1775                         dpcd_data[DP_MAIN_LINK_CHANNEL_CODING - DP_DPCD_REV];
1776         link->test_pattern_enabled = false;
1777         link->compliance_test_state.raw = 0;
1778
1779         /* read sink count */
1780         core_link_read_dpcd(link,
1781                         DP_SINK_COUNT,
1782                         &link->dpcd_caps.sink_count.raw,
1783                         sizeof(link->dpcd_caps.sink_count.raw));
1784
1785         /* read sink ieee oui */
1786         core_link_read_dpcd(link,
1787                         DP_SINK_OUI,
1788                         (uint8_t *)(&sink_id),
1789                         sizeof(sink_id));
1790
1791         link->dpcd_caps.sink_dev_id =
1792                         (sink_id.ieee_oui[0] << 16) +
1793                         (sink_id.ieee_oui[1] << 8) +
1794                         (sink_id.ieee_oui[2]);
1795
1796         memmove(
1797                 link->dpcd_caps.sink_dev_id_str,
1798                 sink_id.ieee_device_id,
1799                 sizeof(sink_id.ieee_device_id));
1800
1801         core_link_read_dpcd(
1802                 link,
1803                 DP_SINK_HW_REVISION_START,
1804                 (uint8_t *)&dp_hw_fw_revision,
1805                 sizeof(dp_hw_fw_revision));
1806
1807         link->dpcd_caps.sink_hw_revision =
1808                 dp_hw_fw_revision.ieee_hw_rev;
1809
1810         memmove(
1811                 link->dpcd_caps.sink_fw_revision,
1812                 dp_hw_fw_revision.ieee_fw_rev,
1813                 sizeof(dp_hw_fw_revision.ieee_fw_rev));
1814
1815         /* Quirk for Retina panels: wrong DP_MAX_LINK_RATE */
1816         {
1817                 uint8_t str_mbp_2018[] = { 101, 68, 21, 103, 98, 97 };
1818                 uint8_t fwrev_mbp_2018[] = { 7, 4 };
1819                 uint8_t fwrev_mbp_2018_vega[] = { 8, 4 };
1820
1821                 /* We also check for the firmware revision as 16,1 models have an
1822                  * identical device id and are incorrectly quirked otherwise.
1823                  */
1824                 if ((link->dpcd_caps.sink_dev_id == 0x0010fa) &&
1825                     !memcmp(link->dpcd_caps.sink_dev_id_str, str_mbp_2018,
1826                              sizeof(str_mbp_2018)) &&
1827                     (!memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018,
1828                              sizeof(fwrev_mbp_2018)) ||
1829                     !memcmp(link->dpcd_caps.sink_fw_revision, fwrev_mbp_2018_vega,
1830                              sizeof(fwrev_mbp_2018_vega)))) {
1831                         link->reported_link_cap.link_rate = LINK_RATE_RBR2;
1832                 }
1833         }
1834
1835         memset(&link->dpcd_caps.dsc_caps, '\0',
1836                         sizeof(link->dpcd_caps.dsc_caps));
1837         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1838         /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */
1839         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) {
1840                 status = core_link_read_dpcd(
1841                                 link,
1842                                 DP_FEC_CAPABILITY,
1843                                 &link->dpcd_caps.fec_cap.raw,
1844                                 sizeof(link->dpcd_caps.fec_cap.raw));
1845                 status = core_link_read_dpcd(
1846                                 link,
1847                                 DP_DSC_SUPPORT,
1848                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
1849                                 sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw));
1850                 if (status == DC_OK) {
1851                         is_fec_supported = link->dpcd_caps.fec_cap.bits.FEC_CAPABLE;
1852                         is_dsc_basic_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT;
1853                         is_dsc_passthrough_supported = link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT;
1854                         DC_LOG_DC("%s: FEC_Sink_Support: %s\n", __func__,
1855                                   str_yes_no(is_fec_supported));
1856                         DC_LOG_DC("%s: DSC_Basic_Sink_Support: %s\n", __func__,
1857                                   str_yes_no(is_dsc_basic_supported));
1858                         DC_LOG_DC("%s: DSC_Passthrough_Sink_Support: %s\n", __func__,
1859                                   str_yes_no(is_dsc_passthrough_supported));
1860                 }
1861                 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) {
1862                         status = core_link_read_dpcd(
1863                                         link,
1864                                         DP_DSC_BRANCH_OVERALL_THROUGHPUT_0,
1865                                         link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
1866                                         sizeof(link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw));
1867                         DC_LOG_DSC("DSC branch decoder capability is read at link %d", link->link_index);
1868                         DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_0 = 0x%02x",
1869                                         link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_0);
1870                         DC_LOG_DSC("\tBRANCH_OVERALL_THROUGHPUT_1 = 0x%02x",
1871                                         link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_OVERALL_THROUGHPUT_1);
1872                         DC_LOG_DSC("\tBRANCH_MAX_LINE_WIDTH 0x%02x",
1873                                         link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.fields.BRANCH_MAX_LINE_WIDTH);
1874                 }
1875
1876                 /* Apply work around to disable FEC and DSC for USB4 tunneling in TBT3 compatibility mode
1877                  * only if required.
1878                  */
1879                 if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA &&
1880                                 link->dc->debug.dpia_debug.bits.enable_force_tbt3_work_around &&
1881                                 link->dpcd_caps.is_branch_dev &&
1882                                 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 &&
1883                                 link->dpcd_caps.branch_hw_revision == DP_BRANCH_HW_REV_10 &&
1884                                 (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE ||
1885                                 link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT)) {
1886                         /* A TBT3 device is expected to report no support for FEC or DSC to a USB4 DPIA.
1887                          * Clear FEC and DSC capabilities as a work around if that is not the case.
1888                          */
1889                         link->wa_flags.dpia_forced_tbt3_mode = true;
1890                         memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps));
1891                         memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
1892                         DC_LOG_DSC("Clear DSC SUPPORT for USB4 link(%d) in TBT3 compatibility mode", link->link_index);
1893                 } else
1894                         link->wa_flags.dpia_forced_tbt3_mode = false;
1895         }
1896
1897         if (!dpcd_read_sink_ext_caps(link))
1898                 link->dpcd_sink_ext_caps.raw = 0;
1899
1900         if (link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
1901                 DC_LOG_DP2("128b/132b encoding is supported at link %d", link->link_index);
1902
1903                 core_link_read_dpcd(link,
1904                                 DP_128B132B_SUPPORTED_LINK_RATES,
1905                                 &link->dpcd_caps.dp_128b_132b_supported_link_rates.raw,
1906                                 sizeof(link->dpcd_caps.dp_128b_132b_supported_link_rates.raw));
1907                 if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR20)
1908                         link->reported_link_cap.link_rate = LINK_RATE_UHBR20;
1909                 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
1910                         link->reported_link_cap.link_rate = LINK_RATE_UHBR13_5;
1911                 else if (link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR10)
1912                         link->reported_link_cap.link_rate = LINK_RATE_UHBR10;
1913                 else
1914                         dm_error("%s: Invalid RX 128b_132b_supported_link_rates\n", __func__);
1915                 DC_LOG_DP2("128b/132b supported link rates is read at link %d", link->link_index);
1916                 DC_LOG_DP2("\tmax 128b/132b link rate support is %d.%d GHz",
1917                                 link->reported_link_cap.link_rate / 100,
1918                                 link->reported_link_cap.link_rate % 100);
1919
1920                 core_link_read_dpcd(link,
1921                                 DP_SINK_VIDEO_FALLBACK_FORMATS,
1922                                 &link->dpcd_caps.fallback_formats.raw,
1923                                 sizeof(link->dpcd_caps.fallback_formats.raw));
1924                 DC_LOG_DP2("sink video fallback format is read at link %d", link->link_index);
1925                 if (link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support)
1926                         DC_LOG_DP2("\t1920x1080@60Hz 24bpp fallback format supported");
1927                 if (link->dpcd_caps.fallback_formats.bits.dp_1280x720_60Hz_24bpp_support)
1928                         DC_LOG_DP2("\t1280x720@60Hz 24bpp fallback format supported");
1929                 if (link->dpcd_caps.fallback_formats.bits.dp_1024x768_60Hz_24bpp_support)
1930                         DC_LOG_DP2("\t1024x768@60Hz 24bpp fallback format supported");
1931                 if (link->dpcd_caps.fallback_formats.raw == 0) {
1932                         DC_LOG_DP2("\tno supported fallback formats, assume 1920x1080@60Hz 24bpp is supported");
1933                         link->dpcd_caps.fallback_formats.bits.dp_1920x1080_60Hz_24bpp_support = 1;
1934                 }
1935
1936                 core_link_read_dpcd(link,
1937                                 DP_FEC_CAPABILITY_1,
1938                                 &link->dpcd_caps.fec_cap1.raw,
1939                                 sizeof(link->dpcd_caps.fec_cap1.raw));
1940                 DC_LOG_DP2("FEC CAPABILITY 1 is read at link %d", link->link_index);
1941                 if (link->dpcd_caps.fec_cap1.bits.AGGREGATED_ERROR_COUNTERS_CAPABLE)
1942                         DC_LOG_DP2("\tFEC aggregated error counters are supported");
1943         }
1944
1945         core_link_read_dpcd(link,
1946                         DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP,
1947                         link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw,
1948                         sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw));
1949
1950         retrieve_cable_id(link);
1951         dpcd_write_cable_id_to_dprx(link);
1952
1953         /* Connectivity log: detection */
1954         CONN_DATA_DETECT(link, dpcd_data, sizeof(dpcd_data), "Rx Caps: ");
1955
1956         return true;
1957 }
1958
1959 bool detect_dp_sink_caps(struct dc_link *link)
1960 {
1961         return retrieve_link_cap(link);
1962 }
1963
1964 void detect_edp_sink_caps(struct dc_link *link)
1965 {
1966         uint8_t supported_link_rates[16];
1967         uint32_t entry;
1968         uint32_t link_rate_in_khz;
1969         enum dc_link_rate link_rate = LINK_RATE_UNKNOWN;
1970         uint8_t backlight_adj_cap = 0;
1971         uint8_t general_edp_cap = 0;
1972
1973         retrieve_link_cap(link);
1974         link->dpcd_caps.edp_supported_link_rates_count = 0;
1975         memset(supported_link_rates, 0, sizeof(supported_link_rates));
1976
1977         /*
1978          * edp_supported_link_rates_count is only valid for eDP v1.4 or higher.
1979          * Per VESA eDP spec, "The DPCD revision for eDP v1.4 is 13h"
1980          */
1981         if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_13) {
1982                 // Read DPCD 00010h - 0001Fh 16 bytes at one shot
1983                 core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
1984                                                         supported_link_rates, sizeof(supported_link_rates));
1985
1986                 for (entry = 0; entry < 16; entry += 2) {
1987                         // DPCD register reports per-lane link rate = 16-bit link rate capability
1988                         // value X 200 kHz. Need multiplier to find link rate in kHz.
1989                         link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
1990                                                                                 supported_link_rates[entry]) * 200;
1991
1992                         DC_LOG_DC("%s: eDP v1.4 supported sink rates: [%d] %d kHz\n", __func__,
1993                                   entry / 2, link_rate_in_khz);
1994
1995                         if (link_rate_in_khz != 0) {
1996                                 link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
1997                                 link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
1998                                 link->dpcd_caps.edp_supported_link_rates_count++;
1999                         }
2000                 }
2001         }
2002
2003         core_link_read_dpcd(link, DP_EDP_BACKLIGHT_ADJUSTMENT_CAP,
2004                                                 &backlight_adj_cap, sizeof(backlight_adj_cap));
2005
2006         link->dpcd_caps.dynamic_backlight_capable_edp =
2007                                 (backlight_adj_cap & DP_EDP_DYNAMIC_BACKLIGHT_CAP) ? true:false;
2008
2009         core_link_read_dpcd(link, DP_EDP_GENERAL_CAP_1,
2010                                                 &general_edp_cap, sizeof(general_edp_cap));
2011
2012         link->dpcd_caps.set_power_state_capable_edp =
2013                                 (general_edp_cap & DP_EDP_SET_POWER_CAP) ? true:false;
2014
2015         set_default_brightness_aux(link);
2016
2017         core_link_read_dpcd(link, DP_EDP_DPCD_REV,
2018                 &link->dpcd_caps.edp_rev,
2019                 sizeof(link->dpcd_caps.edp_rev));
2020         /*
2021          * PSR is only valid for eDP v1.3 or higher.
2022          */
2023         if (link->dpcd_caps.edp_rev >= DP_EDP_13) {
2024                 core_link_read_dpcd(link, DP_PSR_SUPPORT,
2025                         &link->dpcd_caps.psr_info.psr_version,
2026                         sizeof(link->dpcd_caps.psr_info.psr_version));
2027                 if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)
2028                         core_link_read_dpcd(link, DP_FORCE_PSRSU_CAPABILITY,
2029                                                 &link->dpcd_caps.psr_info.force_psrsu_cap,
2030                                                 sizeof(link->dpcd_caps.psr_info.force_psrsu_cap));
2031                 core_link_read_dpcd(link, DP_PSR_CAPS,
2032                         &link->dpcd_caps.psr_info.psr_dpcd_caps.raw,
2033                         sizeof(link->dpcd_caps.psr_info.psr_dpcd_caps.raw));
2034                 if (link->dpcd_caps.psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED) {
2035                         core_link_read_dpcd(link, DP_PSR2_SU_Y_GRANULARITY,
2036                                 &link->dpcd_caps.psr_info.psr2_su_y_granularity_cap,
2037                                 sizeof(link->dpcd_caps.psr_info.psr2_su_y_granularity_cap));
2038                 }
2039         }
2040
2041         /*
2042          * ALPM is only valid for eDP v1.4 or higher.
2043          */
2044         if (link->dpcd_caps.dpcd_rev.raw >= DP_EDP_14)
2045                 core_link_read_dpcd(link, DP_RECEIVER_ALPM_CAP,
2046                         &link->dpcd_caps.alpm_caps.raw,
2047                         sizeof(link->dpcd_caps.alpm_caps.raw));
2048
2049         /*
2050          * Read REPLAY info
2051          */
2052         core_link_read_dpcd(link, DP_SINK_PR_PIXEL_DEVIATION_PER_LINE,
2053                         &link->dpcd_caps.pr_info.pixel_deviation_per_line,
2054                         sizeof(link->dpcd_caps.pr_info.pixel_deviation_per_line));
2055         core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE,
2056                         &link->dpcd_caps.pr_info.max_deviation_line,
2057                         sizeof(link->dpcd_caps.pr_info.max_deviation_line));
2058 }
2059
2060 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)
2061 {
2062         struct link_encoder *link_enc = NULL;
2063
2064         if (!max_link_enc_cap) {
2065                 DC_LOG_ERROR("%s: Could not return max link encoder caps", __func__);
2066                 return false;
2067         }
2068
2069         link_enc = link_enc_cfg_get_link_enc(link);
2070         ASSERT(link_enc);
2071
2072         if (link_enc && link_enc->funcs->get_max_link_cap) {
2073                 link_enc->funcs->get_max_link_cap(link_enc, max_link_enc_cap);
2074                 return true;
2075         }
2076
2077         DC_LOG_ERROR("%s: Max link encoder caps unknown", __func__);
2078         max_link_enc_cap->lane_count = 1;
2079         max_link_enc_cap->link_rate = 6;
2080         return false;
2081 }
2082
2083 const struct dc_link_settings *dp_get_verified_link_cap(
2084                 const struct dc_link *link)
2085 {
2086         if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
2087                         link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
2088                 return &link->preferred_link_setting;
2089         return &link->verified_link_cap;
2090 }
2091
2092 struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
2093 {
2094         struct dc_link_settings max_link_cap = {0};
2095         enum dc_link_rate lttpr_max_link_rate;
2096         enum dc_link_rate cable_max_link_rate;
2097         struct link_encoder *link_enc = NULL;
2098         bool is_uhbr13_5_supported = true;
2099
2100         link_enc = link_enc_cfg_get_link_enc(link);
2101         ASSERT(link_enc);
2102
2103         /* get max link encoder capability */
2104         if (link_enc)
2105                 link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap);
2106
2107         /* Lower link settings based on sink's link cap */
2108         if (link->reported_link_cap.lane_count < max_link_cap.lane_count)
2109                 max_link_cap.lane_count =
2110                                 link->reported_link_cap.lane_count;
2111         if (link->reported_link_cap.link_rate < max_link_cap.link_rate)
2112                 max_link_cap.link_rate =
2113                                 link->reported_link_cap.link_rate;
2114         if (link->reported_link_cap.link_spread <
2115                         max_link_cap.link_spread)
2116                 max_link_cap.link_spread =
2117                                 link->reported_link_cap.link_spread;
2118
2119         if (!link->dpcd_caps.dp_128b_132b_supported_link_rates.bits.UHBR13_5)
2120                 is_uhbr13_5_supported = false;
2121
2122         /* Lower link settings based on cable attributes
2123          * Cable ID is a DP2 feature to identify max certified link rate that
2124          * a cable can carry. The cable identification method requires both
2125          * cable and display hardware support. Since the specs comes late, it is
2126          * anticipated that the first round of DP2 cables and displays may not
2127          * be fully compatible to reliably return cable ID data. Therefore the
2128          * decision of our cable id policy is that if the cable can return non
2129          * zero cable id data, we will take cable's link rate capability into
2130          * account. However if we get zero data, the cable link rate capability
2131          * is considered inconclusive. In this case, we will not take cable's
2132          * capability into account to avoid of over limiting hardware capability
2133          * from users. The max overall link rate capability is still determined
2134          * after actual dp pre-training. Cable id is considered as an auxiliary
2135          * method of determining max link bandwidth capability.
2136          */
2137         cable_max_link_rate = get_cable_max_link_rate(link);
2138
2139         if (!link->dc->debug.ignore_cable_id &&
2140                         cable_max_link_rate != LINK_RATE_UNKNOWN) {
2141                 if (cable_max_link_rate < max_link_cap.link_rate)
2142                         max_link_cap.link_rate = cable_max_link_rate;
2143
2144                 if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY &&
2145                                 link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2)
2146                         is_uhbr13_5_supported = false;
2147         }
2148
2149         /* account for lttpr repeaters cap
2150          * notes: repeaters do not snoop in the DPRX Capabilities addresses (3.6.3).
2151          */
2152         if (dp_is_lttpr_present(link)) {
2153
2154                 /* Some LTTPR devices do not report valid DPCD revisions, if so, do not take it's link cap into consideration. */
2155                 if (link->dpcd_caps.lttpr_caps.revision.raw >= DPCD_REV_14) {
2156                         if (link->dpcd_caps.lttpr_caps.max_lane_count < max_link_cap.lane_count)
2157                                 max_link_cap.lane_count = link->dpcd_caps.lttpr_caps.max_lane_count;
2158                         lttpr_max_link_rate = get_lttpr_max_link_rate(link);
2159
2160                         if (lttpr_max_link_rate < max_link_cap.link_rate)
2161                                 max_link_cap.link_rate = lttpr_max_link_rate;
2162
2163                         if (!link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR13_5)
2164                                 is_uhbr13_5_supported = false;
2165                 }
2166
2167                 DC_LOG_HW_LINK_TRAINING("%s\n Training with LTTPR,  max_lane count %d max_link rate %d \n",
2168                                                 __func__,
2169                                                 max_link_cap.lane_count,
2170                                                 max_link_cap.link_rate);
2171         }
2172
2173         if (max_link_cap.link_rate == LINK_RATE_UHBR13_5 &&
2174                         !is_uhbr13_5_supported)
2175                 max_link_cap.link_rate = LINK_RATE_UHBR10;
2176
2177         if (link_dp_get_encoding_format(&max_link_cap) == DP_128b_132b_ENCODING &&
2178                         link->dc->debug.disable_uhbr)
2179                 max_link_cap.link_rate = LINK_RATE_HIGH3;
2180
2181         return max_link_cap;
2182 }
2183
2184 static bool dp_verify_link_cap(
2185         struct dc_link *link,
2186         struct dc_link_settings *known_limit_link_setting,
2187         int *fail_count)
2188 {
2189         struct dc_link_settings cur_link_settings = {0};
2190         struct dc_link_settings max_link_settings = *known_limit_link_setting;
2191         bool success = false;
2192         bool skip_video_pattern;
2193         enum clock_source_id dp_cs_id = get_clock_source_id(link);
2194         enum link_training_result status = LINK_TRAINING_SUCCESS;
2195         union hpd_irq_data irq_data;
2196         struct link_resource link_res;
2197
2198         memset(&irq_data, 0, sizeof(irq_data));
2199         cur_link_settings = max_link_settings;
2200
2201         /* Grant extended timeout request */
2202         if (dp_is_lttpr_present(link) && link->dpcd_caps.lttpr_caps.max_ext_timeout > 0) {
2203                 uint8_t grant = link->dpcd_caps.lttpr_caps.max_ext_timeout & 0x80;
2204
2205                 core_link_write_dpcd(link, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &grant, sizeof(grant));
2206         }
2207
2208         do {
2209                 if (!get_temp_dp_link_res(link, &link_res, &cur_link_settings))
2210                         continue;
2211
2212                 skip_video_pattern = cur_link_settings.link_rate != LINK_RATE_LOW;
2213                 dp_enable_link_phy(
2214                                 link,
2215                                 &link_res,
2216                                 link->connector_signal,
2217                                 dp_cs_id,
2218                                 &cur_link_settings);
2219
2220                 status = dp_perform_link_training(
2221                                 link,
2222                                 &link_res,
2223                                 &cur_link_settings,
2224                                 skip_video_pattern);
2225
2226                 if (status == LINK_TRAINING_SUCCESS) {
2227                         success = true;
2228                         fsleep(1000);
2229                         if (dp_read_hpd_rx_irq_data(link, &irq_data) == DC_OK &&
2230                                         dp_parse_link_loss_status(
2231                                                         link,
2232                                                         &irq_data))
2233                                 (*fail_count)++;
2234                 } else if (status == LINK_TRAINING_LINK_LOSS) {
2235                         success = true;
2236                         (*fail_count)++;
2237                 } else {
2238                         (*fail_count)++;
2239                 }
2240                 dp_trace_lt_total_count_increment(link, true);
2241                 dp_trace_lt_result_update(link, status, true);
2242                 dp_disable_link_phy(link, &link_res, link->connector_signal);
2243         } while (!success && decide_fallback_link_setting(link,
2244                         &max_link_settings, &cur_link_settings, status));
2245
2246         link->verified_link_cap = success ?
2247                         cur_link_settings : fail_safe_link_settings;
2248         return success;
2249 }
2250
2251 bool dp_verify_link_cap_with_retries(
2252         struct dc_link *link,
2253         struct dc_link_settings *known_limit_link_setting,
2254         int attempts)
2255 {
2256         int i = 0;
2257         bool success = false;
2258         int fail_count = 0;
2259         struct dc_link_settings last_verified_link_cap = fail_safe_link_settings;
2260
2261         dp_trace_detect_lt_init(link);
2262
2263         if (link->link_enc && link->link_enc->features.flags.bits.DP_IS_USB_C &&
2264                         link->dc->debug.usbc_combo_phy_reset_wa)
2265                 apply_usbc_combo_phy_reset_wa(link, known_limit_link_setting);
2266
2267         dp_trace_set_lt_start_timestamp(link, false);
2268         for (i = 0; i < attempts; i++) {
2269                 enum dc_connection_type type = dc_connection_none;
2270
2271                 memset(&link->verified_link_cap, 0,
2272                                 sizeof(struct dc_link_settings));
2273                 if (link->link_enc && (!link_detect_connection_type(link, &type) || type == dc_connection_none)) {
2274                         link->verified_link_cap = fail_safe_link_settings;
2275                         break;
2276                 } else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) {
2277                         last_verified_link_cap = link->verified_link_cap;
2278                         if (fail_count == 0) {
2279                                 success = true;
2280                                 break;
2281                         }
2282                 } else {
2283                         link->verified_link_cap = last_verified_link_cap;
2284                 }
2285                 fsleep(10 * 1000);
2286         }
2287
2288         dp_trace_lt_fail_count_update(link, fail_count, true);
2289         dp_trace_set_lt_end_timestamp(link, true);
2290
2291         return success;
2292 }
2293
2294 /*
2295  * Check if there is a native DP or passive DP-HDMI dongle connected
2296  */
2297 bool dp_is_sink_present(struct dc_link *link)
2298 {
2299         enum gpio_result gpio_result;
2300         uint32_t clock_pin = 0;
2301         uint8_t retry = 0;
2302         struct ddc *ddc;
2303
2304         enum connector_id connector_id =
2305                 dal_graphics_object_id_get_connector_id(link->link_id);
2306
2307         bool present =
2308                 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
2309                 (connector_id == CONNECTOR_ID_EDP) ||
2310                 (connector_id == CONNECTOR_ID_USBC));
2311
2312         ddc = get_ddc_pin(link->ddc);
2313
2314         if (!ddc) {
2315                 BREAK_TO_DEBUGGER();
2316                 return present;
2317         }
2318
2319         /* Open GPIO and set it to I2C mode */
2320         /* Note: this GpioMode_Input will be converted
2321          * to GpioConfigType_I2cAuxDualMode in GPIO component,
2322          * which indicates we need additional delay
2323          */
2324
2325         if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
2326                          GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
2327                 dal_ddc_close(ddc);
2328
2329                 return present;
2330         }
2331
2332         /*
2333          * Read GPIO: DP sink is present if both clock and data pins are zero
2334          *
2335          * [W/A] plug-unplug DP cable, sometimes customer board has
2336          * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
2337          * then monitor can't br light up. Add retry 3 times
2338          * But in real passive dongle, it need additional 3ms to detect
2339          */
2340         do {
2341                 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
2342                 ASSERT(gpio_result == GPIO_RESULT_OK);
2343                 if (clock_pin)
2344                         fsleep(1000);
2345                 else
2346                         break;
2347         } while (retry++ < 3);
2348
2349         present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
2350
2351         dal_ddc_close(ddc);
2352
2353         return present;
2354 }