drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright 2023 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include "display_mode_core.h"
  28 #include "dml2_internal_types.h"
  29 #include "dml2_translation_helper.h"
  30
  31 #define NUM_DCFCLK_STAS 5
  32 #define NUM_DCFCLK_STAS_NEW 8
  33
  34 void dml2_init_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out)
  35 {
  36         switch (dml2->v20.dml_core_ctx.project) {
  37         case dml_project_dcn32:
  38         case dml_project_dcn321:
  39         default:
  40                 // Hardcoded values for DCN32x
  41                 out->vblank_nom_default_us = 600;
  42                 out->rob_buffer_size_kbytes = 128;
  43                 out->config_return_buffer_size_in_kbytes = 1280;
  44                 out->config_return_buffer_segment_size_in_kbytes = 64;
  45                 out->compressed_buffer_segment_size_in_kbytes = 64;
  46                 out->meta_fifo_size_in_kentries = 22;
  47                 out->zero_size_buffer_entries = 512;
  48                 out->dpte_buffer_size_in_pte_reqs_luma = 68;
  49                 out->dpte_buffer_size_in_pte_reqs_chroma = 36;
  50                 out->dcc_meta_buffer_size_bytes = 6272;
  51                 out->gpuvm_max_page_table_levels = 4;
  52                 out->hostvm_max_page_table_levels = 0;
  53                 out->pixel_chunk_size_kbytes = 8;
  54                 //out->alpha_pixel_chunk_size_kbytes;
  55                 out->min_pixel_chunk_size_bytes = 1024;
  56                 out->meta_chunk_size_kbytes = 2;
  57                 out->min_meta_chunk_size_bytes = 256;
  58                 out->writeback_chunk_size_kbytes = 8;
  59                 out->line_buffer_size_bits = 1171920;
  60                 out->max_line_buffer_lines = 32;
  61                 out->writeback_interface_buffer_size_kbytes = 90;
  62                 //Number of pipes after DCN Pipe harvesting
  63                 out->max_num_dpp = dml2->config.dcn_pipe_count;
  64                 out->max_num_otg = dml2->config.dcn_pipe_count;
  65                 out->max_num_wb = 1;
  66                 out->max_dchub_pscl_bw_pix_per_clk = 4;
  67                 out->max_pscl_lb_bw_pix_per_clk = 2;
  68                 out->max_lb_vscl_bw_pix_per_clk = 4;
  69                 out->max_vscl_hscl_bw_pix_per_clk = 4;
  70                 out->max_hscl_ratio = 6;
  71                 out->max_vscl_ratio = 6;
  72                 out->max_hscl_taps = 8;
  73                 out->max_vscl_taps = 8;
  74                 out->dispclk_ramp_margin_percent = 1;
  75                 out->dppclk_delay_subtotal = 47;
  76                 out->dppclk_delay_scl = 50;
  77                 out->dppclk_delay_scl_lb_only = 16;
  78                 out->dppclk_delay_cnvc_formatter = 28;
  79                 out->dppclk_delay_cnvc_cursor = 6;
  80                 out->cursor_buffer_size = 16;
  81                 out->cursor_chunk_size = 2;
  82                 out->dispclk_delay_subtotal = 125;
  83                 out->max_inter_dcn_tile_repeaters = 8;
  84                 out->writeback_max_hscl_ratio = 1;
  85                 out->writeback_max_vscl_ratio = 1;
  86                 out->writeback_min_hscl_ratio = 1;
  87                 out->writeback_min_vscl_ratio = 1;
  88                 out->writeback_max_hscl_taps = 1;
  89                 out->writeback_max_vscl_taps = 1;
  90                 out->writeback_line_buffer_buffer_size = 0;
  91                 out->num_dsc = 4;
  92                 out->maximum_dsc_bits_per_component = 12;
  93                 out->maximum_pixels_per_line_per_dsc_unit = 6016;
  94                 out->dsc422_native_support = true;
  95                 out->dcc_supported = true;
  96                 out->ptoi_supported = false;
  97
  98                 out->gpuvm_enable = false;
  99                 out->hostvm_enable = false;
 100                 out->cursor_64bpp_support = false;
 101                 out->dynamic_metadata_vm_enabled = false;
 102
 103                 out->max_num_hdmi_frl_outputs = 1;
 104                 out->max_num_dp2p0_outputs = 2;
 105                 out->max_num_dp2p0_streams = 4;
 106                 break;
 107
 108         case dml_project_dcn35:
 109         case dml_project_dcn351:
 110                 out->rob_buffer_size_kbytes = 64;
 111                 out->config_return_buffer_size_in_kbytes = 1792;
 112                 out->compressed_buffer_segment_size_in_kbytes = 64;
 113                 out->meta_fifo_size_in_kentries = 32;
 114                 out->zero_size_buffer_entries = 512;
 115                 out->pixel_chunk_size_kbytes = 8;
 116                 out->alpha_pixel_chunk_size_kbytes = 4;
 117                 out->min_pixel_chunk_size_bytes = 1024;
 118                 out->meta_chunk_size_kbytes = 2;
 119                 out->min_meta_chunk_size_bytes = 256;
 120                 out->writeback_chunk_size_kbytes = 8;
 121                 out->dpte_buffer_size_in_pte_reqs_luma = 68;
 122                 out->dpte_buffer_size_in_pte_reqs_chroma = 36;
 123                 out->dcc_meta_buffer_size_bytes = 6272;
 124                 out->gpuvm_enable = 1;
 125                 out->hostvm_enable = 1;
 126                 out->gpuvm_max_page_table_levels = 1;
 127                 out->hostvm_max_page_table_levels = 2;
 128                 out->num_dsc = 4;
 129                 out->maximum_dsc_bits_per_component = 12;
 130                 out->maximum_pixels_per_line_per_dsc_unit = 6016;
 131                 out->dsc422_native_support = 1;
 132                 out->line_buffer_size_bits = 986880;
 133                 out->dcc_supported = 1;
 134                 out->max_line_buffer_lines = 32;
 135                 out->writeback_interface_buffer_size_kbytes = 90;
 136                 out->max_num_dpp = 4;
 137                 out->max_num_otg = 4;
 138                 out->max_num_hdmi_frl_outputs = 1;
 139                 out->max_num_dp2p0_outputs = 2;
 140                 out->max_num_dp2p0_streams = 4;
 141                 out->max_num_wb = 1;
 142
 143                 out->max_dchub_pscl_bw_pix_per_clk = 4;
 144                 out->max_pscl_lb_bw_pix_per_clk = 2;
 145                 out->max_lb_vscl_bw_pix_per_clk = 4;
 146                 out->max_vscl_hscl_bw_pix_per_clk = 4;
 147                 out->max_hscl_ratio = 6;
 148                 out->max_vscl_ratio = 6;
 149                 out->max_hscl_taps = 8;
 150                 out->max_vscl_taps = 8;
 151                 out->dispclk_ramp_margin_percent = 1.11;
 152
 153                 out->dppclk_delay_subtotal = 47;
 154                 out->dppclk_delay_scl = 50;
 155                 out->dppclk_delay_scl_lb_only = 16;
 156                 out->dppclk_delay_cnvc_formatter = 28;
 157                 out->dppclk_delay_cnvc_cursor = 6;
 158                 out->dispclk_delay_subtotal = 125;
 159
 160                 out->dynamic_metadata_vm_enabled = false;
 161                 out->max_inter_dcn_tile_repeaters = 8;
 162                 out->cursor_buffer_size = 16; // kBytes
 163                 out->cursor_chunk_size = 2; // kBytes
 164
 165                 out->writeback_line_buffer_buffer_size = 0;
 166                 out->writeback_max_hscl_ratio = 1;
 167                 out->writeback_max_vscl_ratio = 1;
 168                 out->writeback_min_hscl_ratio = 1;
 169                 out->writeback_min_vscl_ratio = 1;
 170                 out->writeback_max_hscl_taps  = 1;
 171                 out->writeback_max_vscl_taps  = 1;
 172                 out->ptoi_supported     = 0;
 173
 174                 out->vblank_nom_default_us = 668; /*not in dml, but in programming guide, hard coded in dml2_translate_ip_params*/
 175                 out->config_return_buffer_segment_size_in_kbytes = 64; /*required, but not exist,, hard coded in dml2_translate_ip_params*/
 176                 break;
 177
 178         case dml_project_dcn401:
 179                 // Hardcoded values for DCN4m
 180                 out->vblank_nom_default_us = 668;       //600;
 181                 out->rob_buffer_size_kbytes = 192;      //128;
 182                 out->config_return_buffer_size_in_kbytes = 1344;        //1280;
 183                 out->config_return_buffer_segment_size_in_kbytes = 64;
 184                 out->compressed_buffer_segment_size_in_kbytes = 64;
 185                 out->meta_fifo_size_in_kentries = 22;
 186                 out->dpte_buffer_size_in_pte_reqs_luma = 68;
 187                 out->dpte_buffer_size_in_pte_reqs_chroma = 36;
 188                 out->gpuvm_max_page_table_levels = 4;
 189                 out->pixel_chunk_size_kbytes = 8;
 190                 out->alpha_pixel_chunk_size_kbytes = 4;
 191                 out->min_pixel_chunk_size_bytes = 1024;
 192                 out->writeback_chunk_size_kbytes = 8;
 193                 out->line_buffer_size_bits = 1171920;
 194                 out->max_line_buffer_lines = 32;
 195                 out->writeback_interface_buffer_size_kbytes = 90;
 196                 //Number of pipes after DCN Pipe harvesting
 197                 out->max_num_dpp = dml2->config.dcn_pipe_count;
 198                 out->max_num_otg = dml2->config.dcn_pipe_count;
 199                 out->max_num_wb = 1;
 200                 out->max_dchub_pscl_bw_pix_per_clk = 4;
 201                 out->max_pscl_lb_bw_pix_per_clk = 2;
 202                 out->max_lb_vscl_bw_pix_per_clk = 4;
 203                 out->max_vscl_hscl_bw_pix_per_clk = 4;
 204                 out->max_hscl_ratio = 6;
 205                 out->max_vscl_ratio = 6;
 206                 out->max_hscl_taps = 8;
 207                 out->max_vscl_taps = 8;
 208                 out->dispclk_ramp_margin_percent = 1;
 209                 out->dppclk_delay_subtotal = 47;
 210                 out->dppclk_delay_scl = 50;
 211                 out->dppclk_delay_scl_lb_only = 16;
 212                 out->dppclk_delay_cnvc_formatter = 28;
 213                 out->dppclk_delay_cnvc_cursor = 6;
 214                 out->dispclk_delay_subtotal = 125;
 215                 out->cursor_buffer_size = 24;   //16
 216                 out->cursor_chunk_size = 2;
 217                 out->max_inter_dcn_tile_repeaters = 8;
 218                 out->writeback_max_hscl_ratio = 1;
 219                 out->writeback_max_vscl_ratio = 1;
 220                 out->writeback_min_hscl_ratio = 1;
 221                 out->writeback_min_vscl_ratio = 1;
 222                 out->writeback_max_hscl_taps = 1;
 223                 out->writeback_max_vscl_taps = 1;
 224                 out->writeback_line_buffer_buffer_size = 0;
 225                 out->num_dsc = 4;
 226                 out->maximum_dsc_bits_per_component = 12;
 227                 out->maximum_pixels_per_line_per_dsc_unit = 5760;
 228                 out->dsc422_native_support = true;
 229                 out->dcc_supported = true;
 230                 out->ptoi_supported = false;
 231
 232                 out->gpuvm_enable = false;
 233                 out->hostvm_enable = false;
 234                 out->cursor_64bpp_support = true;       //false;
 235                 out->dynamic_metadata_vm_enabled = false;
 236
 237                 out->max_num_hdmi_frl_outputs = 1;
 238                 out->max_num_dp2p0_outputs = 4;         //2;
 239                 out->max_num_dp2p0_streams = 4;
 240                 break;
 241         }
 242 }
 243
 244 void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out)
 245 {
 246         out->dprefclk_mhz = dml2->config.bbox_overrides.dprefclk_mhz;
 247         out->xtalclk_mhz = dml2->config.bbox_overrides.xtalclk_mhz;
 248         out->pcierefclk_mhz = 100;
 249         out->refclk_mhz = dml2->config.bbox_overrides.dchub_refclk_mhz;
 250
 251         out->max_outstanding_reqs = 512;
 252         out->pct_ideal_sdp_bw_after_urgent = 100;
 253         out->pct_ideal_fabric_bw_after_urgent = 67;
 254         out->pct_ideal_dram_bw_after_urgent_pixel_only = 20;
 255         out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = 60;
 256         out->pct_ideal_dram_bw_after_urgent_vm_only = 30;
 257         out->pct_ideal_dram_bw_after_urgent_strobe = 67;
 258         out->max_avg_sdp_bw_use_normal_percent = 80;
 259         out->max_avg_fabric_bw_use_normal_percent = 60;
 260         out->max_avg_dram_bw_use_normal_percent = 15;
 261         out->max_avg_dram_bw_use_normal_strobe_percent = 50;
 262
 263         out->urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096;
 264         out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096;
 265         out->urgent_out_of_order_return_per_channel_vm_only_bytes = 4096;
 266         out->return_bus_width_bytes = 64;
 267         out->dram_channel_width_bytes = 2;
 268         out->fabric_datapath_to_dcn_data_return_bytes = 64;
 269         out->hostvm_min_page_size_kbytes = 0;
 270         out->gpuvm_min_page_size_kbytes = 256;
 271         out->phy_downspread_percent = 0.38;
 272         out->dcn_downspread_percent = 0.5;
 273         out->dispclk_dppclk_vco_speed_mhz = dml2->config.bbox_overrides.disp_pll_vco_speed_mhz;
 274         out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64 or 32 MB;
 275
 276         out->do_urgent_latency_adjustment = true;
 277
 278         switch (dml2->v20.dml_core_ctx.project) {
 279
 280         case dml_project_dcn32:
 281         default:
 282                 out->num_chans = 24;
 283                 out->round_trip_ping_latency_dcfclk_cycles = 263;
 284                 out->smn_latency_us = 2;
 285                 break;
 286
 287         case dml_project_dcn321:
 288                 out->num_chans = 8;
 289                 out->round_trip_ping_latency_dcfclk_cycles = 207;
 290                 out->smn_latency_us = 0;
 291                 break;
 292
 293         case dml_project_dcn35:
 294         case dml_project_dcn351:
 295                 out->num_chans = 4;
 296                 out->round_trip_ping_latency_dcfclk_cycles = 106;
 297                 out->smn_latency_us = 2;
 298                 out->dispclk_dppclk_vco_speed_mhz = 3600;
 299                 out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0;
 300                 break;
 301
 302         case dml_project_dcn401:
 303                 out->pct_ideal_fabric_bw_after_urgent = 76;                     //67;
 304                 out->max_avg_sdp_bw_use_normal_percent = 75;            //80;
 305                 out->max_avg_fabric_bw_use_normal_percent = 57;         //60;
 306
 307                 out->urgent_out_of_order_return_per_channel_pixel_only_bytes = 0;       //4096;
 308                 out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 0;     //4096;
 309                 out->urgent_out_of_order_return_per_channel_vm_only_bytes = 0;          //4096;
 310
 311                 out->num_chans = 16;
 312                 out->round_trip_ping_latency_dcfclk_cycles = 1000;      //263;
 313                 out->smn_latency_us = 0;                                                        //2 us
 314                 out->mall_allocated_for_dcn_mbytes = dml2->config.mall_cfg.max_cab_allocation_bytes / 1048576; // 64;
 315                 break;
 316         }
 317         /* ---Overrides if available--- */
 318         if (dml2->config.bbox_overrides.dram_num_chan)
 319                 out->num_chans = dml2->config.bbox_overrides.dram_num_chan;
 320
 321         if (dml2->config.bbox_overrides.dram_chanel_width_bytes)
 322                 out->dram_channel_width_bytes = dml2->config.bbox_overrides.dram_chanel_width_bytes;
 323 }
 324
 325 void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
 326         const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out)
 327 {
 328         struct dml2_policy_build_synthetic_soc_states_scratch *s = &dml2->v20.scratch.create_scratch.build_synthetic_socbb_scratch;
 329         struct dml2_policy_build_synthetic_soc_states_params *p = &dml2->v20.scratch.build_synthetic_socbb_params;
 330         unsigned int dcfclk_stas_mhz[NUM_DCFCLK_STAS] = {0};
 331         unsigned int dcfclk_stas_mhz_new[NUM_DCFCLK_STAS_NEW] = {0};
 332         unsigned int dml_project = dml2->v20.dml_core_ctx.project;
 333
 334         unsigned int i = 0;
 335         unsigned int transactions_per_mem_clock = 16; // project specific, depends on used Memory type
 336
 337         if (dml_project == dml_project_dcn351) {
 338                 p->dcfclk_stas_mhz = dcfclk_stas_mhz_new;
 339                 p->num_dcfclk_stas = NUM_DCFCLK_STAS_NEW;
 340         } else {
 341                 p->dcfclk_stas_mhz = dcfclk_stas_mhz;
 342                 p->num_dcfclk_stas = NUM_DCFCLK_STAS;
 343         }
 344
 345         p->in_bbox = in_bbox;
 346         p->out_states = out;
 347         p->in_states = &dml2->v20.scratch.create_scratch.in_states;
 348
 349
 350         /* Initial hardcoded values */
 351         switch (dml2->v20.dml_core_ctx.project) {
 352
 353         case dml_project_dcn32:
 354         default:
 355                 p->in_states->num_states = 2;
 356                 transactions_per_mem_clock = 16;
 357                 p->in_states->state_array[0].socclk_mhz = 620.0;
 358                 p->in_states->state_array[0].dscclk_mhz = 716.667;
 359                 p->in_states->state_array[0].phyclk_mhz = 810;
 360                 p->in_states->state_array[0].phyclk_d18_mhz = 667;
 361                 p->in_states->state_array[0].phyclk_d32_mhz = 625;
 362                 p->in_states->state_array[0].dtbclk_mhz = 1564.0;
 363                 p->in_states->state_array[0].fabricclk_mhz = 450.0;
 364                 p->in_states->state_array[0].dcfclk_mhz = 300.0;
 365                 p->in_states->state_array[0].dispclk_mhz = 2150.0;
 366                 p->in_states->state_array[0].dppclk_mhz = 2150.0;
 367                 p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock;
 368
 369                 p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4;
 370                 p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;
 371                 p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0;
 372                 p->in_states->state_array[0].writeback_latency_us = 12;
 373                 p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;
 374                 p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 3000;
 375                 p->in_states->state_array[0].sr_exit_z8_time_us = 0;
 376                 p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0;
 377                 p->in_states->state_array[0].dram_clock_change_latency_us = 400;
 378                 p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;
 379                 p->in_states->state_array[0].sr_exit_time_us = 42.97;
 380                 p->in_states->state_array[0].sr_enter_plus_exit_time_us = 49.94;
 381                 p->in_states->state_array[0].fclk_change_latency_us = 20;
 382                 p->in_states->state_array[0].usr_retraining_latency_us = 2;
 383
 384                 p->in_states->state_array[1].socclk_mhz = 1200.0;
 385                 p->in_states->state_array[1].fabricclk_mhz = 2500.0;
 386                 p->in_states->state_array[1].dcfclk_mhz = 1564.0;
 387                 p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock;
 388                 break;
 389
 390         case dml_project_dcn321:
 391                 p->in_states->num_states = 2;
 392                 transactions_per_mem_clock = 16;
 393                 p->in_states->state_array[0].socclk_mhz = 582.0;
 394                 p->in_states->state_array[0].dscclk_mhz = 573.333;
 395                 p->in_states->state_array[0].phyclk_mhz = 810;
 396                 p->in_states->state_array[0].phyclk_d18_mhz = 667;
 397                 p->in_states->state_array[0].phyclk_d32_mhz = 313;
 398                 p->in_states->state_array[0].dtbclk_mhz = 1564.0;
 399                 p->in_states->state_array[0].fabricclk_mhz = 450.0;
 400                 p->in_states->state_array[0].dcfclk_mhz = 300.0;
 401                 p->in_states->state_array[0].dispclk_mhz = 1720.0;
 402                 p->in_states->state_array[0].dppclk_mhz = 1720.0;
 403                 p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock;
 404
 405                 p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4;
 406                 p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;
 407                 p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0;
 408                 p->in_states->state_array[0].writeback_latency_us = 12;
 409                 p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;
 410                 p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 3000;
 411                 p->in_states->state_array[0].sr_exit_z8_time_us = 0;
 412                 p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0;
 413                 p->in_states->state_array[0].dram_clock_change_latency_us = 400;
 414                 p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;
 415                 p->in_states->state_array[0].sr_exit_time_us = 19.95;
 416                 p->in_states->state_array[0].sr_enter_plus_exit_time_us = 24.36;
 417                 p->in_states->state_array[0].fclk_change_latency_us = 7;
 418                 p->in_states->state_array[0].usr_retraining_latency_us = 0;
 419
 420                 p->in_states->state_array[1].socclk_mhz = 1200.0;
 421                 p->in_states->state_array[1].fabricclk_mhz = 2250.0;
 422                 p->in_states->state_array[1].dcfclk_mhz = 1434.0;
 423                 p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock;
 424                 break;
 425         case dml_project_dcn401:
 426                 p->in_states->num_states = 2;
 427                 transactions_per_mem_clock = 16;
 428                 p->in_states->state_array[0].socclk_mhz = 300;          //620.0;
 429                 p->in_states->state_array[0].dscclk_mhz = 666.667;      //716.667;
 430                 p->in_states->state_array[0].phyclk_mhz = 810;
 431                 p->in_states->state_array[0].phyclk_d18_mhz = 667;
 432                 p->in_states->state_array[0].phyclk_d32_mhz = 625;
 433                 p->in_states->state_array[0].dtbclk_mhz = 2000;         //1564.0;
 434                 p->in_states->state_array[0].fabricclk_mhz = 300;       //450.0;
 435                 p->in_states->state_array[0].dcfclk_mhz = 200;          //300.0;
 436                 p->in_states->state_array[0].dispclk_mhz = 2000;        //2150.0;
 437                 p->in_states->state_array[0].dppclk_mhz = 2000;         //2150.0;
 438                 p->in_states->state_array[0].dram_speed_mts = 97 * transactions_per_mem_clock; //100 *
 439
 440                 p->in_states->state_array[0].urgent_latency_pixel_data_only_us = 4;
 441                 p->in_states->state_array[0].urgent_latency_pixel_mixed_with_vm_data_us = 0;
 442                 p->in_states->state_array[0].urgent_latency_vm_data_only_us = 0;
 443                 p->in_states->state_array[0].writeback_latency_us = 12;
 444                 p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_component_us = 1;
 445                 p->in_states->state_array[0].urgent_latency_adjustment_fabric_clock_reference_mhz = 1000;       //3000;
 446                 p->in_states->state_array[0].sr_exit_z8_time_us = 0;
 447                 p->in_states->state_array[0].sr_enter_plus_exit_z8_time_us = 0;
 448                 p->in_states->state_array[0].dram_clock_change_latency_us = 400;
 449                 p->in_states->state_array[0].use_ideal_dram_bw_strobe = true;
 450                 p->in_states->state_array[0].sr_exit_time_us = 15.70;   //42.97;
 451                 p->in_states->state_array[0].sr_enter_plus_exit_time_us = 20.20;        //49.94;
 452                 p->in_states->state_array[0].fclk_change_latency_us = 0;        //20;
 453                 p->in_states->state_array[0].usr_retraining_latency_us = 0;     //2;
 454
 455                 p->in_states->state_array[1].socclk_mhz = 1600;         //1200.0;
 456                 p->in_states->state_array[1].fabricclk_mhz = 2500;      //2500.0;
 457                 p->in_states->state_array[1].dcfclk_mhz = 1800;         //1564.0;
 458                 p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock;
 459                 break;
 460         }
 461
 462         /* Override from passed values, if available */
 463         for (i = 0; i < p->in_states->num_states; i++) {
 464                 if (dml2->config.bbox_overrides.sr_exit_latency_us) {
 465                         p->in_states->state_array[i].sr_exit_time_us =
 466                                 dml2->config.bbox_overrides.sr_exit_latency_us;
 467                 }
 468
 469                 if (dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us) {
 470                         p->in_states->state_array[i].sr_enter_plus_exit_time_us =
 471                                 dml2->config.bbox_overrides.sr_enter_plus_exit_latency_us;
 472                 }
 473
 474                 if (dml2->config.bbox_overrides.sr_exit_z8_time_us) {
 475                         p->in_states->state_array[i].sr_exit_z8_time_us =
 476                                 dml2->config.bbox_overrides.sr_exit_z8_time_us;
 477                 }
 478
 479                 if (dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us) {
 480                         p->in_states->state_array[i].sr_enter_plus_exit_z8_time_us =
 481                                 dml2->config.bbox_overrides.sr_enter_plus_exit_z8_time_us;
 482                 }
 483
 484                 if (dml2->config.bbox_overrides.urgent_latency_us) {
 485                         p->in_states->state_array[i].urgent_latency_pixel_data_only_us =
 486                                 dml2->config.bbox_overrides.urgent_latency_us;
 487                 }
 488
 489                 if (dml2->config.bbox_overrides.dram_clock_change_latency_us) {
 490                         p->in_states->state_array[i].dram_clock_change_latency_us =
 491                                 dml2->config.bbox_overrides.dram_clock_change_latency_us;
 492                 }
 493
 494                 if (dml2->config.bbox_overrides.fclk_change_latency_us) {
 495                         p->in_states->state_array[i].fclk_change_latency_us =
 496                                 dml2->config.bbox_overrides.fclk_change_latency_us;
 497                 }
 498         }
 499
 500         /* DCFCLK stas values are project specific */
 501         if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) ||
 502                 (dml2->v20.dml_core_ctx.project == dml_project_dcn321)) {
 503                 p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz;
 504                 p->dcfclk_stas_mhz[1] = 615;
 505                 p->dcfclk_stas_mhz[2] = 906;
 506                 p->dcfclk_stas_mhz[3] = 1324;
 507                 p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz;
 508         } else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
 509                         dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
 510                 p->dcfclk_stas_mhz[0] = 300;
 511                 p->dcfclk_stas_mhz[1] = 615;
 512                 p->dcfclk_stas_mhz[2] = 906;
 513                 p->dcfclk_stas_mhz[3] = 1324;
 514                 p->dcfclk_stas_mhz[4] = 1500;
 515         }
 516         /* Copy clocks tables entries, if available */
 517         if (dml2->config.bbox_overrides.clks_table.num_states) {
 518                 p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states;
 519                 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) {
 520                         p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz;
 521                 }
 522
 523                 p->dcfclk_stas_mhz[0] = dml2->config.bbox_overrides.clks_table.clk_entries[0].dcfclk_mhz;
 524                 if (i > 1)
 525                         p->dcfclk_stas_mhz[4] = dml2->config.bbox_overrides.clks_table.clk_entries[i-1].dcfclk_mhz;
 526
 527                 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_fclk_levels; i++) {
 528                         p->in_states->state_array[i].fabricclk_mhz =
 529                                 dml2->config.bbox_overrides.clks_table.clk_entries[i].fclk_mhz;
 530                 }
 531
 532                 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_memclk_levels; i++) {
 533                         p->in_states->state_array[i].dram_speed_mts =
 534                                 dml2->config.bbox_overrides.clks_table.clk_entries[i].memclk_mhz * transactions_per_mem_clock;
 535                 }
 536
 537                 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_socclk_levels; i++) {
 538                         p->in_states->state_array[i].socclk_mhz =
 539                                 dml2->config.bbox_overrides.clks_table.clk_entries[i].socclk_mhz;
 540                 }
 541
 542                 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dtbclk_levels; i++) {
 543                         if (dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz > 0)
 544                                 p->in_states->state_array[i].dtbclk_mhz =
 545                                         dml2->config.bbox_overrides.clks_table.clk_entries[i].dtbclk_mhz;
 546                 }
 547
 548                 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dispclk_levels; i++) {
 549                         p->in_states->state_array[i].dispclk_mhz =
 550                                 dml2->config.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz;
 551                         p->in_states->state_array[i].dppclk_mhz =
 552                                 dml2->config.bbox_overrides.clks_table.clk_entries[i].dppclk_mhz;
 553                 }
 554         }
 555
 556         dml2_policy_build_synthetic_soc_states(s, p);
 557         if (dml2->v20.dml_core_ctx.project == dml_project_dcn35) {
 558                 // Override last out_state with data from last in_state
 559                 // This will ensure that out_state contains max fclk
 560                 memcpy(&p->out_states->state_array[p->out_states->num_states - 1],
 561                                 &p->in_states->state_array[p->in_states->num_states - 1],
 562                                 sizeof(struct soc_state_bounding_box_st));
 563         }
 564 }
 565
 566 void dml2_translate_ip_params(const struct dc *in, struct ip_params_st *out)
 567 {
 568         const struct _vcs_dpi_ip_params_st *in_ip_params = &in->dml.ip;
 569         /* Copy over the IP params tp dml2_ctx */
 570         out->compressed_buffer_segment_size_in_kbytes = in_ip_params->compressed_buffer_segment_size_in_kbytes;
 571         out->config_return_buffer_size_in_kbytes = in_ip_params->config_return_buffer_size_in_kbytes;
 572         out->cursor_buffer_size = in_ip_params->cursor_buffer_size;
 573         out->cursor_chunk_size = in_ip_params->cursor_chunk_size;
 574         out->dcc_meta_buffer_size_bytes = in_ip_params->dcc_meta_buffer_size_bytes;
 575         out->dcc_supported = in_ip_params->dcc_supported;
 576         out->dispclk_delay_subtotal = in_ip_params->dispclk_delay_subtotal;
 577         out->dispclk_ramp_margin_percent = in_ip_params->dispclk_ramp_margin_percent;
 578         out->dppclk_delay_cnvc_cursor = in_ip_params->dppclk_delay_cnvc_cursor;
 579         out->dppclk_delay_cnvc_formatter = in_ip_params->dppclk_delay_cnvc_formatter;
 580         out->dppclk_delay_scl = in_ip_params->dppclk_delay_scl;
 581         out->dppclk_delay_scl_lb_only = in_ip_params->dppclk_delay_scl_lb_only;
 582         out->dppclk_delay_subtotal = in_ip_params->dppclk_delay_subtotal;
 583         out->dpte_buffer_size_in_pte_reqs_chroma = in_ip_params->dpte_buffer_size_in_pte_reqs_chroma;
 584         out->dpte_buffer_size_in_pte_reqs_luma = in_ip_params->dpte_buffer_size_in_pte_reqs_luma;
 585         out->dsc422_native_support = in_ip_params->dsc422_native_support;
 586         out->dynamic_metadata_vm_enabled = in_ip_params->dynamic_metadata_vm_enabled;
 587         out->gpuvm_enable = in_ip_params->gpuvm_enable;
 588         out->gpuvm_max_page_table_levels = in_ip_params->gpuvm_max_page_table_levels;
 589         out->hostvm_enable = in_ip_params->hostvm_enable;
 590         out->hostvm_max_page_table_levels = in_ip_params->hostvm_max_page_table_levels;
 591         out->line_buffer_size_bits = in_ip_params->line_buffer_size_bits;
 592         out->maximum_dsc_bits_per_component = in_ip_params->maximum_dsc_bits_per_component;
 593         out->maximum_pixels_per_line_per_dsc_unit = in_ip_params->maximum_pixels_per_line_per_dsc_unit;
 594         out->max_dchub_pscl_bw_pix_per_clk = in_ip_params->max_dchub_pscl_bw_pix_per_clk;
 595         out->max_hscl_ratio = in_ip_params->max_hscl_ratio;
 596         out->max_hscl_taps = in_ip_params->max_hscl_taps;
 597         out->max_inter_dcn_tile_repeaters = in_ip_params->max_inter_dcn_tile_repeaters;
 598         out->max_lb_vscl_bw_pix_per_clk = in_ip_params->max_lb_vscl_bw_pix_per_clk;
 599         out->max_line_buffer_lines = in_ip_params->max_line_buffer_lines;
 600         out->max_num_dp2p0_outputs = in_ip_params->max_num_dp2p0_outputs;
 601         out->max_num_dp2p0_streams = in_ip_params->max_num_dp2p0_streams;
 602         out->max_num_dpp = in_ip_params->max_num_dpp;
 603         out->max_num_hdmi_frl_outputs = in_ip_params->max_num_hdmi_frl_outputs;
 604         out->max_num_otg = in_ip_params->max_num_otg;
 605         out->max_num_wb = in_ip_params->max_num_wb;
 606         out->max_pscl_lb_bw_pix_per_clk = in_ip_params->max_pscl_lb_bw_pix_per_clk;
 607         out->max_vscl_hscl_bw_pix_per_clk = in_ip_params->max_vscl_hscl_bw_pix_per_clk;
 608         out->max_vscl_ratio = in_ip_params->max_vscl_ratio;
 609         out->max_vscl_taps = in_ip_params->max_vscl_taps;
 610         out->meta_chunk_size_kbytes = in_ip_params->meta_chunk_size_kbytes;
 611         out->meta_fifo_size_in_kentries = in_ip_params->meta_fifo_size_in_kentries;
 612         out->min_meta_chunk_size_bytes = in_ip_params->min_meta_chunk_size_bytes;
 613         out->min_pixel_chunk_size_bytes = in_ip_params->min_pixel_chunk_size_bytes;
 614         out->num_dsc = in_ip_params->num_dsc;
 615         out->pixel_chunk_size_kbytes = in_ip_params->pixel_chunk_size_kbytes;
 616         out->ptoi_supported = in_ip_params->ptoi_supported;
 617         out->rob_buffer_size_kbytes = in_ip_params->rob_buffer_size_kbytes;
 618         out->writeback_chunk_size_kbytes = in_ip_params->writeback_chunk_size_kbytes;
 619         out->writeback_interface_buffer_size_kbytes = in_ip_params->writeback_interface_buffer_size_kbytes;
 620         out->writeback_line_buffer_buffer_size = in_ip_params->writeback_line_buffer_buffer_size;
 621         out->writeback_max_hscl_ratio = in_ip_params->writeback_max_hscl_ratio;
 622         out->writeback_max_hscl_taps = in_ip_params->writeback_max_hscl_taps;
 623         out->writeback_max_vscl_ratio = in_ip_params->writeback_max_vscl_ratio;
 624         out->writeback_max_vscl_taps = in_ip_params->writeback_max_vscl_taps;
 625         out->writeback_min_hscl_ratio = in_ip_params->writeback_min_hscl_ratio;
 626         out->writeback_min_vscl_ratio = in_ip_params->writeback_min_vscl_ratio;
 627         out->zero_size_buffer_entries = in_ip_params->zero_size_buffer_entries;
 628
 629         /* As per hardcoded reference / discussions */
 630         out->config_return_buffer_segment_size_in_kbytes = 64;
 631         //out->vblank_nom_default_us = 600;
 632         out->vblank_nom_default_us = in_ip_params->VBlankNomDefaultUS;
 633 }
 634
 635 void dml2_translate_socbb_params(const struct dc *in, struct soc_bounding_box_st *out)
 636 {
 637         const struct _vcs_dpi_soc_bounding_box_st *in_soc_params = &in->dml.soc;
 638         /* Copy over the SOCBB params to dml2_ctx */
 639         out->dispclk_dppclk_vco_speed_mhz = in_soc_params->dispclk_dppclk_vco_speed_mhz;
 640         out->do_urgent_latency_adjustment = in_soc_params->do_urgent_latency_adjustment;
 641         out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes;
 642         out->fabric_datapath_to_dcn_data_return_bytes = (dml_uint_t)in_soc_params->fabric_datapath_to_dcn_data_return_bytes;
 643         out->gpuvm_min_page_size_kbytes = in_soc_params->gpuvm_min_page_size_bytes / 1024;
 644         out->hostvm_min_page_size_kbytes = in_soc_params->hostvm_min_page_size_bytes / 1024;
 645         out->mall_allocated_for_dcn_mbytes = (dml_uint_t)in_soc_params->mall_allocated_for_dcn_mbytes;
 646         out->max_avg_dram_bw_use_normal_percent = in_soc_params->max_avg_dram_bw_use_normal_percent;
 647         out->max_avg_fabric_bw_use_normal_percent = in_soc_params->max_avg_fabric_bw_use_normal_percent;
 648         out->max_avg_dram_bw_use_normal_strobe_percent = in_soc_params->max_avg_dram_bw_use_normal_strobe_percent;
 649         out->max_avg_sdp_bw_use_normal_percent = in_soc_params->max_avg_sdp_bw_use_normal_percent;
 650         out->max_outstanding_reqs = in_soc_params->max_request_size_bytes;
 651         out->num_chans = in_soc_params->num_chans;
 652         out->pct_ideal_dram_bw_after_urgent_strobe = in_soc_params->pct_ideal_dram_bw_after_urgent_strobe;
 653         out->pct_ideal_dram_bw_after_urgent_vm_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_vm_only;
 654         out->pct_ideal_fabric_bw_after_urgent = in_soc_params->pct_ideal_fabric_bw_after_urgent;
 655         out->pct_ideal_sdp_bw_after_urgent = in_soc_params->pct_ideal_sdp_bw_after_urgent;
 656         out->phy_downspread_percent = in_soc_params->downspread_percent;
 657         out->refclk_mhz = 50; // As per hardcoded reference.
 658         out->return_bus_width_bytes = in_soc_params->return_bus_width_bytes;
 659         out->round_trip_ping_latency_dcfclk_cycles = in_soc_params->round_trip_ping_latency_dcfclk_cycles;
 660         out->smn_latency_us = in_soc_params->smn_latency_us;
 661         out->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
 662         out->urgent_out_of_order_return_per_channel_pixel_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_pixel_only_bytes;
 663         out->urgent_out_of_order_return_per_channel_vm_only_bytes = in_soc_params->urgent_out_of_order_return_per_channel_vm_only_bytes;
 664         out->pct_ideal_dram_bw_after_urgent_pixel_and_vm = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
 665         out->pct_ideal_dram_bw_after_urgent_pixel_only = in_soc_params->pct_ideal_dram_sdp_bw_after_urgent_pixel_only;
 666         out->dcn_downspread_percent = in_soc_params->dcn_downspread_percent;
 667 }
 668
 669 void dml2_translate_soc_states(const struct dc *dc, struct soc_states_st *out, int num_states)
 670 {
 671         unsigned int i = 0;
 672         out->num_states = num_states;
 673
 674         for (i = 0; i < out->num_states; i++) {
 675                 out->state_array[i].dcfclk_mhz = dc->dml.soc.clock_limits[i].dcfclk_mhz;
 676                 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz;
 677                 out->state_array[i].dppclk_mhz = dc->dml.soc.clock_limits[i].dppclk_mhz;
 678                 out->state_array[i].dram_speed_mts = dc->dml.soc.clock_limits[i].dram_speed_mts;
 679                 out->state_array[i].dtbclk_mhz = dc->dml.soc.clock_limits[i].dtbclk_mhz;
 680                 out->state_array[i].socclk_mhz = dc->dml.soc.clock_limits[i].socclk_mhz;
 681                 out->state_array[i].fabricclk_mhz = dc->dml.soc.clock_limits[i].fabricclk_mhz;
 682                 out->state_array[i].dscclk_mhz = dc->dml.soc.clock_limits[i].dscclk_mhz;
 683                 out->state_array[i].phyclk_d18_mhz = dc->dml.soc.clock_limits[i].phyclk_d18_mhz;
 684                 out->state_array[i].phyclk_d32_mhz = dc->dml.soc.clock_limits[i].phyclk_d32_mhz;
 685                 out->state_array[i].phyclk_mhz = dc->dml.soc.clock_limits[i].phyclk_mhz;
 686                 out->state_array[i].sr_enter_plus_exit_time_us = dc->dml.soc.sr_enter_plus_exit_time_us;
 687                 out->state_array[i].sr_exit_time_us = dc->dml.soc.sr_exit_time_us;
 688                 out->state_array[i].fclk_change_latency_us = dc->dml.soc.fclk_change_latency_us;
 689                 out->state_array[i].dram_clock_change_latency_us = dc->dml.soc.dram_clock_change_latency_us;
 690                 out->state_array[i].usr_retraining_latency_us = dc->dml.soc.usr_retraining_latency_us;
 691                 out->state_array[i].writeback_latency_us = dc->dml.soc.writeback_latency_us;
 692                 /* Driver initialized values for these are different than the spreadsheet. Use the
 693                  * spreadsheet ones for now. We need to decided which ones to use.
 694                  */
 695                 out->state_array[i].sr_exit_z8_time_us = dc->dml.soc.sr_exit_z8_time_us;
 696                 out->state_array[i].sr_enter_plus_exit_z8_time_us = dc->dml.soc.sr_enter_plus_exit_z8_time_us;
 697                 //out->state_array[i].sr_exit_z8_time_us = 5.20;
 698                 //out->state_array[i].sr_enter_plus_exit_z8_time_us = 9.60;
 699                 out->state_array[i].use_ideal_dram_bw_strobe = true;
 700                 out->state_array[i].urgent_latency_pixel_data_only_us = dc->dml.soc.urgent_latency_pixel_data_only_us;
 701                 out->state_array[i].urgent_latency_pixel_mixed_with_vm_data_us = dc->dml.soc.urgent_latency_pixel_mixed_with_vm_data_us;
 702                 out->state_array[i].urgent_latency_vm_data_only_us = dc->dml.soc.urgent_latency_vm_data_only_us;
 703                 out->state_array[i].urgent_latency_adjustment_fabric_clock_component_us = dc->dml.soc.urgent_latency_adjustment_fabric_clock_component_us;
 704                 out->state_array[i].urgent_latency_adjustment_fabric_clock_reference_mhz = dc->dml.soc.urgent_latency_adjustment_fabric_clock_reference_mhz;
 705         }
 706 }
 707
 708 static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
 709 {
 710         dml_uint_t hblank_start, vblank_start;
 711
 712         out->HActive[location] = in->timing.h_addressable + in->timing.h_border_left + in->timing.h_border_right;
 713         out->VActive[location] = in->timing.v_addressable + in->timing.v_border_bottom + in->timing.v_border_top;
 714         out->RefreshRate[location] = ((in->timing.pix_clk_100hz * 100) / in->timing.h_total) / in->timing.v_total;
 715         out->VFrontPorch[location] = in->timing.v_front_porch;
 716         out->PixelClock[location] = in->timing.pix_clk_100hz / 10000.00;
 717         if (in->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 718                 out->PixelClock[location] *= 2;
 719         out->HTotal[location] = in->timing.h_total;
 720         out->VTotal[location] = in->timing.v_total;
 721         out->Interlace[location] = in->timing.flags.INTERLACE;
 722         hblank_start = in->timing.h_total - in->timing.h_front_porch;
 723         out->HBlankEnd[location] = hblank_start
 724                                         - in->timing.h_addressable
 725                                         - in->timing.h_border_left
 726                                         - in->timing.h_border_right;
 727         vblank_start = in->timing.v_total - in->timing.v_front_porch;
 728         out->VBlankEnd[location] = vblank_start
 729                                         - in->timing.v_addressable
 730                                         - in->timing.v_border_top
 731                                         - in->timing.v_border_bottom;
 732         out->DRRDisplay[location] = false;
 733 }
 734
 735 static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *out, unsigned int location,
 736                                 const struct dc_stream_state *in, const struct pipe_ctx *pipe, struct dml2_context *dml2)
 737 {
 738         unsigned int output_bpc;
 739
 740         out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC;
 741         out->OutputLinkDPLanes[location] = 4; // As per code in dcn20_resource.c
 742         out->DSCInputBitPerComponent[location] = 12; // As per code in dcn20_resource.c
 743         out->DSCSlices[location] = in->timing.dsc_cfg.num_slices_h;
 744
 745         switch (in->signal) {
 746         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 747         case SIGNAL_TYPE_DISPLAY_PORT:
 748                 out->OutputEncoder[location] = dml_dp;
 749                 if (dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1)
 750                         out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0;
 751                 break;
 752         case SIGNAL_TYPE_EDP:
 753                 out->OutputEncoder[location] = dml_edp;
 754                 break;
 755         case SIGNAL_TYPE_HDMI_TYPE_A:
 756         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 757         case SIGNAL_TYPE_DVI_DUAL_LINK:
 758                 out->OutputEncoder[location] = dml_hdmi;
 759                 break;
 760         default:
 761                 out->OutputEncoder[location] = dml_dp;
 762         }
 763
 764         switch (in->timing.display_color_depth) {
 765         case COLOR_DEPTH_666:
 766                 output_bpc = 6;
 767                 break;
 768         case COLOR_DEPTH_888:
 769                 output_bpc = 8;
 770                 break;
 771         case COLOR_DEPTH_101010:
 772                 output_bpc = 10;
 773                 break;
 774         case COLOR_DEPTH_121212:
 775                 output_bpc = 12;
 776                 break;
 777         case COLOR_DEPTH_141414:
 778                 output_bpc = 14;
 779                 break;
 780         case COLOR_DEPTH_161616:
 781                 output_bpc = 16;
 782                 break;
 783         case COLOR_DEPTH_999:
 784                 output_bpc = 9;
 785                 break;
 786         case COLOR_DEPTH_111111:
 787                 output_bpc = 11;
 788                 break;
 789         default:
 790                 output_bpc = 8;
 791                 break;
 792         }
 793
 794         switch (in->timing.pixel_encoding) {
 795         case PIXEL_ENCODING_RGB:
 796         case PIXEL_ENCODING_YCBCR444:
 797                 out->OutputFormat[location] = dml_444;
 798                 out->OutputBpp[location] = (dml_float_t)output_bpc * 3;
 799                 break;
 800         case PIXEL_ENCODING_YCBCR420:
 801                 out->OutputFormat[location] = dml_420;
 802                 out->OutputBpp[location] = (output_bpc * 3.0) / 2;
 803                 break;
 804         case PIXEL_ENCODING_YCBCR422:
 805                 if (in->timing.flags.DSC && !in->timing.dsc_cfg.ycbcr422_simple)
 806                         out->OutputFormat[location] = dml_n422;
 807                 else
 808                         out->OutputFormat[location] = dml_s422;
 809                 out->OutputBpp[location] = (dml_float_t)output_bpc * 2;
 810                 break;
 811         default:
 812                 out->OutputFormat[location] = dml_444;
 813                 out->OutputBpp[location] = (dml_float_t)output_bpc * 3;
 814                 break;
 815         }
 816
 817         if (in->timing.flags.DSC) {
 818                 out->OutputBpp[location] = in->timing.dsc_cfg.bits_per_pixel / 16.0;
 819         }
 820
 821         // This has been false throughout DCN32x development. If needed we can change this later on.
 822         out->OutputMultistreamEn[location] = false;
 823
 824         switch (in->signal) {
 825         case SIGNAL_TYPE_NONE:
 826         case SIGNAL_TYPE_DVI_SINGLE_LINK:
 827         case SIGNAL_TYPE_DVI_DUAL_LINK:
 828         case SIGNAL_TYPE_HDMI_TYPE_A:
 829         case SIGNAL_TYPE_LVDS:
 830         case SIGNAL_TYPE_RGB:
 831         case SIGNAL_TYPE_DISPLAY_PORT:
 832         case SIGNAL_TYPE_DISPLAY_PORT_MST:
 833         case SIGNAL_TYPE_EDP:
 834         case SIGNAL_TYPE_VIRTUAL:
 835         default:
 836                 out->OutputLinkDPRate[location] = dml_dp_rate_na;
 837                 break;
 838         }
 839
 840         out->PixelClockBackEnd[location] = in->timing.pix_clk_100hz / 10000.00;
 841
 842         out->AudioSampleLayout[location] = in->audio_info.modes->sample_size;
 843         out->AudioSampleRate[location] = in->audio_info.modes->max_bit_rate;
 844
 845         out->OutputDisabled[location] = true;
 846 }
 847
 848 static void populate_dummy_dml_surface_cfg(struct dml_surface_cfg_st *out, unsigned int location, const struct dc_stream_state *in)
 849 {
 850         out->SurfaceWidthY[location] = in->timing.h_addressable;
 851         out->SurfaceHeightY[location] = in->timing.v_addressable;
 852         out->SurfaceWidthC[location] = in->timing.h_addressable;
 853         out->SurfaceHeightC[location] = in->timing.v_addressable;
 854         out->PitchY[location] = ((out->SurfaceWidthY[location] + 127) / 128) * 128;
 855         out->PitchC[location] = 0;
 856         out->DCCEnable[location] = false;
 857         out->DCCMetaPitchY[location] = 0;
 858         out->DCCMetaPitchC[location] = 0;
 859         out->DCCRateLuma[location] = 1.0;
 860         out->DCCRateChroma[location] = 1.0;
 861         out->DCCFractionOfZeroSizeRequestsLuma[location] = 0;
 862         out->DCCFractionOfZeroSizeRequestsChroma[location] = 0;
 863         out->SurfaceTiling[location] = dml_sw_64kb_r_x;
 864         out->SourcePixelFormat[location] = dml_444_32;
 865 }
 866
 867 static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_project, struct dml_surface_cfg_st *out, unsigned int location, const struct dc_plane_state *in)
 868 {
 869         out->PitchY[location] = in->plane_size.surface_pitch;
 870         out->SurfaceHeightY[location] = in->plane_size.surface_size.height;
 871         out->SurfaceWidthY[location] = in->plane_size.surface_size.width;
 872         out->SurfaceHeightC[location] = in->plane_size.chroma_size.height;
 873         out->SurfaceWidthC[location] = in->plane_size.chroma_size.width;
 874         out->PitchC[location] = in->plane_size.chroma_pitch;
 875         out->DCCEnable[location] = in->dcc.enable;
 876         out->DCCMetaPitchY[location] = in->dcc.meta_pitch;
 877         out->DCCMetaPitchC[location] = in->dcc.meta_pitch_c;
 878         out->DCCRateLuma[location] = 1.0;
 879         out->DCCRateChroma[location] = 1.0;
 880         out->DCCFractionOfZeroSizeRequestsLuma[location] = in->dcc.independent_64b_blks;
 881         out->DCCFractionOfZeroSizeRequestsChroma[location] = in->dcc.independent_64b_blks_c;
 882
 883         switch (dml2_project) {
 884         default:
 885                 out->SurfaceTiling[location] = (enum dml_swizzle_mode)in->tiling_info.gfx9.swizzle;
 886                 break;
 887         case dml_project_dcn401:
 888                 // Temporary use gfx11 swizzle in dml, until proper dml for DCN4x is integrated/implemented
 889                 switch (in->tiling_info.gfx_addr3.swizzle) {
 890                 case DC_ADDR3_SW_4KB_2D:
 891                 case DC_ADDR3_SW_64KB_2D:
 892                 case DC_ADDR3_SW_256KB_2D:
 893                 default:
 894                         out->SurfaceTiling[location] = dml_sw_64kb_r_x;
 895                         break;
 896                 case DC_ADDR3_SW_LINEAR:
 897                         out->SurfaceTiling[location] = dml_sw_linear;
 898                         break;
 899                 }
 900         }
 901
 902         switch (in->format) {
 903         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 904         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 905                 out->SourcePixelFormat[location] = dml_420_8;
 906                 break;
 907         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 908         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 909                 out->SourcePixelFormat[location] = dml_420_10;
 910                 break;
 911         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 912         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 913         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 914                 out->SourcePixelFormat[location] = dml_444_64;
 915                 break;
 916         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 917         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 918                 out->SourcePixelFormat[location] = dml_444_16;
 919                 break;
 920         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
 921                 out->SourcePixelFormat[location] = dml_444_8;
 922                 break;
 923         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 924                 out->SourcePixelFormat[location] = dml_rgbe_alpha;
 925                 break;
 926         default:
 927                 out->SourcePixelFormat[location] = dml_444_32;
 928                 break;
 929         }
 930 }
 931
 932 static void get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context, struct scaler_data *out)
 933 {
 934         int i;
 935         struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;
 936
 937         memset(temp_pipe, 0, sizeof(struct pipe_ctx));
 938
 939         for (i = 0; i < MAX_PIPES; i++) {
 940                 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 941
 942                 if (pipe->plane_state == in && !pipe->prev_odm_pipe) {
 943                         temp_pipe->stream = pipe->stream;
 944                         temp_pipe->plane_state = pipe->plane_state;
 945                         temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps;
 946                         temp_pipe->stream_res = pipe->stream_res;
 947                         resource_build_scaling_params(temp_pipe);
 948                         break;
 949                 }
 950         }
 951
 952         ASSERT(i < MAX_PIPES);
 953         memcpy(out, &temp_pipe->plane_res.scl_data, sizeof(*out));
 954 }
 955
 956 static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location,
 957                                          const struct dc_stream_state *in,
 958                                          const struct soc_bounding_box_st *soc)
 959 {
 960         dml_uint_t width, height;
 961
 962         if (in->timing.h_addressable > 3840)
 963                 width = 3840;
 964         else
 965                 width = in->timing.h_addressable;       // 4K max
 966
 967         if (in->timing.v_addressable > 2160)
 968                 height = 2160;
 969         else
 970                 height = in->timing.v_addressable;      // 4K max
 971
 972         out->CursorBPP[location] = dml_cur_32bit;
 973         out->CursorWidth[location] = 256;
 974
 975         out->GPUVMMinPageSizeKBytes[location] = soc->gpuvm_min_page_size_kbytes;
 976
 977         out->ViewportWidth[location] = width;
 978         out->ViewportHeight[location] = height;
 979         out->ViewportStationary[location] = false;
 980         out->ViewportWidthChroma[location] = 0;
 981         out->ViewportHeightChroma[location] = 0;
 982         out->ViewportXStart[location] = 0;
 983         out->ViewportXStartC[location] = 0;
 984         out->ViewportYStart[location] = 0;
 985         out->ViewportYStartC[location] = 0;
 986
 987         out->ScalerEnabled[location] = false;
 988         out->HRatio[location] = 1.0;
 989         out->VRatio[location] = 1.0;
 990         out->HRatioChroma[location] = 0;
 991         out->VRatioChroma[location] = 0;
 992         out->HTaps[location] = 1;
 993         out->VTaps[location] = 1;
 994         out->HTapsChroma[location] = 0;
 995         out->VTapsChroma[location] = 0;
 996         out->SourceScan[location] = dml_rotation_0;
 997         out->ScalerRecoutWidth[location] = width;
 998
 999         out->LBBitPerPixel[location] = 57;
1000
1001         out->DynamicMetadataEnable[location] = false;
1002
1003         out->NumberOfCursors[location] = 1;
1004         out->UseMALLForStaticScreen[location] = dml_use_mall_static_screen_disable;
1005         out->UseMALLForPStateChange[location] = dml_use_mall_pstate_change_disable;
1006
1007         out->DETSizeOverride[location] = 256;
1008
1009         out->ScalerEnabled[location] = false;
1010 }
1011
1012 static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location,
1013                                                     const struct dc_plane_state *in, struct dc_state *context,
1014                                                     const struct soc_bounding_box_st *soc)
1015 {
1016         struct scaler_data *scaler_data = kzalloc(sizeof(*scaler_data), GFP_KERNEL);
1017         if (!scaler_data)
1018                 return;
1019
1020         get_scaler_data_for_plane(in, context, scaler_data);
1021
1022         out->CursorBPP[location] = dml_cur_32bit;
1023         out->CursorWidth[location] = 256;
1024
1025         out->GPUVMMinPageSizeKBytes[location] = soc->gpuvm_min_page_size_kbytes;
1026
1027         out->ViewportWidth[location] = scaler_data->viewport.width;
1028         out->ViewportHeight[location] = scaler_data->viewport.height;
1029         out->ViewportWidthChroma[location] = scaler_data->viewport_c.width;
1030         out->ViewportHeightChroma[location] = scaler_data->viewport_c.height;
1031         out->ViewportXStart[location] = scaler_data->viewport.x;
1032         out->ViewportYStart[location] = scaler_data->viewport.y;
1033         out->ViewportXStartC[location] = scaler_data->viewport_c.x;
1034         out->ViewportYStartC[location] = scaler_data->viewport_c.y;
1035         out->ViewportStationary[location] = false;
1036
1037         out->ScalerEnabled[location] = scaler_data->ratios.horz.value != dc_fixpt_one.value ||
1038                                 scaler_data->ratios.horz_c.value != dc_fixpt_one.value ||
1039                                 scaler_data->ratios.vert.value != dc_fixpt_one.value ||
1040                                 scaler_data->ratios.vert_c.value != dc_fixpt_one.value;
1041
1042         /* Current driver code base uses LBBitPerPixel as 57. There is a discrepancy
1043          * from the HW/DML teams about this value. Initialize LBBitPerPixel with the
1044          * value current used in Navi3x .
1045          */
1046
1047         out->LBBitPerPixel[location] = 57;
1048
1049         if (out->ScalerEnabled[location] == false) {
1050                 out->HRatio[location] = 1;
1051                 out->HRatioChroma[location] = 1;
1052                 out->VRatio[location] = 1;
1053                 out->VRatioChroma[location] = 1;
1054         } else {
1055                 /* Follow the original dml_wrapper.c code direction to fix scaling issues */
1056                 out->HRatio[location] = (dml_float_t)scaler_data->ratios.horz.value / (1ULL << 32);
1057                 out->HRatioChroma[location] = (dml_float_t)scaler_data->ratios.horz_c.value / (1ULL << 32);
1058                 out->VRatio[location] = (dml_float_t)scaler_data->ratios.vert.value / (1ULL << 32);
1059                 out->VRatioChroma[location] = (dml_float_t)scaler_data->ratios.vert_c.value / (1ULL << 32);
1060         }
1061
1062         if (!scaler_data->taps.h_taps) {
1063                 out->HTaps[location] = 1;
1064                 out->HTapsChroma[location] = 1;
1065         } else {
1066                 out->HTaps[location] = scaler_data->taps.h_taps;
1067                 out->HTapsChroma[location] = scaler_data->taps.h_taps_c;
1068         }
1069         if (!scaler_data->taps.v_taps) {
1070                 out->VTaps[location] = 1;
1071                 out->VTapsChroma[location] = 1;
1072         } else {
1073                 out->VTaps[location] = scaler_data->taps.v_taps;
1074                 out->VTapsChroma[location] = scaler_data->taps.v_taps_c;
1075         }
1076
1077         out->SourceScan[location] = (enum dml_rotation_angle)in->rotation;
1078         out->ScalerRecoutWidth[location] = in->dst_rect.width;
1079
1080         out->DynamicMetadataEnable[location] = false;
1081         out->DynamicMetadataLinesBeforeActiveRequired[location] = 0;
1082         out->DynamicMetadataTransmittedBytes[location] = 0;
1083
1084         out->NumberOfCursors[location] = 1;
1085
1086         kfree(scaler_data);
1087 }
1088
1089 static unsigned int map_stream_to_dml_display_cfg(const struct dml2_context *dml2,
1090                 const struct dc_stream_state *stream, const struct dml_display_cfg_st *dml_dispcfg)
1091 {
1092         int i = 0;
1093         int location = -1;
1094
1095         for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1096                 if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == stream->stream_id) {
1097                         location = i;
1098                         break;
1099                 }
1100         }
1101
1102         return location;
1103 }
1104
1105 static bool get_plane_id(struct dml2_context *dml2, const struct dc_state *context, const struct dc_plane_state *plane,
1106                 unsigned int stream_id, unsigned int plane_index, unsigned int *plane_id)
1107 {
1108         int i, j;
1109         bool is_plane_duplicate = dml2->v20.scratch.plane_duplicate_exists;
1110
1111         if (!plane_id)
1112                 return false;
1113
1114         for (i = 0; i < context->stream_count; i++) {
1115                 if (context->streams[i]->stream_id == stream_id) {
1116                         for (j = 0; j < context->stream_status[i].plane_count; j++) {
1117                                 if (context->stream_status[i].plane_states[j] == plane &&
1118                                         (!is_plane_duplicate || (j == plane_index))) {
1119                                         *plane_id = (i << 16) | j;
1120                                         return true;
1121                                 }
1122                         }
1123                 }
1124         }
1125
1126         return false;
1127 }
1128
1129 static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2, const struct dc_plane_state *plane,
1130                 const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index)
1131 {
1132         unsigned int plane_id;
1133         int i = 0;
1134         int location = -1;
1135
1136         if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {
1137                 ASSERT(false);
1138                 return -1;
1139         }
1140
1141         for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1142                 if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] && dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i] == plane_id) {
1143                         location = i;
1144                         break;
1145                 }
1146         }
1147
1148         return location;
1149 }
1150
1151 static void apply_legacy_svp_drr_settings(struct dml2_context *dml2, const struct dc_state *state, struct dml_display_cfg_st *dml_dispcfg)
1152 {
1153         int i;
1154
1155         if (state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
1156                 ASSERT(state->stream_count == 1);
1157                 dml_dispcfg->timing.DRRDisplay[0] = true;
1158         } else if (state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid) {
1159
1160                 for (i = 0; i < dml_dispcfg->num_timings; i++) {
1161                         if (dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i] == state->streams[state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index]->stream_id)
1162                                 dml_dispcfg->timing.DRRDisplay[i] = true;
1163                 }
1164         }
1165 }
1166
1167 static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, struct dc_state *state)
1168 {
1169         unsigned int i;
1170         unsigned int pipe_index = 0;
1171         unsigned int plane_index = 0;
1172         struct dml2_dml_to_dc_pipe_mapping *dml_to_dc_pipe_mapping = &dml2->v20.scratch.dml_to_dc_pipe_mapping;
1173
1174         for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1175                 dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[i] = false;
1176                 dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[i] = 0;
1177         }
1178
1179         for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1180                 struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i];
1181
1182                 if (!pipe || !pipe->stream || !pipe->plane_state)
1183                         continue;
1184
1185                 while (pipe) {
1186                         pipe_index = pipe->pipe_idx;
1187
1188                         if (pipe->stream && dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] == false) {
1189                                 dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index[pipe_index] = plane_index;
1190                                 plane_index++;
1191                                 dml_to_dc_pipe_mapping->dml_pipe_idx_to_plane_index_valid[pipe_index] = true;
1192                         }
1193
1194                         pipe = pipe->bottom_pipe;
1195                 }
1196
1197                 plane_index = 0;
1198         }
1199 }
1200
1201 static void populate_dml_writeback_cfg_from_stream_state(struct dml_writeback_cfg_st *out,
1202                 unsigned int location, const struct dc_stream_state *in)
1203 {
1204         if (in->num_wb_info > 0) {
1205                 for (int i = 0; i < __DML_NUM_DMB__; i++) {
1206                         const struct dc_writeback_info *wb_info = &in->writeback_info[i];
1207                         /*current dml support 1 dwb per stream, limitation*/
1208                         if (wb_info->wb_enabled) {
1209                                 out->WritebackEnable[location] = wb_info->wb_enabled;
1210                                 out->ActiveWritebacksPerSurface[location] = wb_info->dwb_params.cnv_params.src_width;
1211                                 out->WritebackDestinationWidth[location] = wb_info->dwb_params.dest_width;
1212                                 out->WritebackDestinationHeight[location] = wb_info->dwb_params.dest_height;
1213
1214                                 out->WritebackSourceWidth[location] = wb_info->dwb_params.cnv_params.crop_en ?
1215                                         wb_info->dwb_params.cnv_params.crop_width :
1216                                         wb_info->dwb_params.cnv_params.src_width;
1217
1218                                 out->WritebackSourceHeight[location] = wb_info->dwb_params.cnv_params.crop_en ?
1219                                         wb_info->dwb_params.cnv_params.crop_height :
1220                                         wb_info->dwb_params.cnv_params.src_height;
1221                                 /*current design does not have chroma scaling, need to follow up*/
1222                                 out->WritebackHTaps[location] = wb_info->dwb_params.scaler_taps.h_taps > 0 ?
1223                                         wb_info->dwb_params.scaler_taps.h_taps : 1;
1224                                 out->WritebackVTaps[location] = wb_info->dwb_params.scaler_taps.v_taps > 0 ?
1225                                         wb_info->dwb_params.scaler_taps.v_taps : 1;
1226
1227                                 out->WritebackHRatio[location] = wb_info->dwb_params.cnv_params.crop_en ?
1228                                         (double)wb_info->dwb_params.cnv_params.crop_width /
1229                                                 (double)wb_info->dwb_params.dest_width :
1230                                         (double)wb_info->dwb_params.cnv_params.src_width /
1231                                                 (double)wb_info->dwb_params.dest_width;
1232                                 out->WritebackVRatio[location] = wb_info->dwb_params.cnv_params.crop_en ?
1233                                         (double)wb_info->dwb_params.cnv_params.crop_height /
1234                                                 (double)wb_info->dwb_params.dest_height :
1235                                         (double)wb_info->dwb_params.cnv_params.src_height /
1236                                                 (double)wb_info->dwb_params.dest_height;
1237                         }
1238                 }
1239         }
1240 }
1241
1242 static void dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(struct dml2_context *dml2, struct dc_state *context)
1243 {
1244         int i;
1245         struct pipe_ctx *current_pipe_context;
1246
1247         /* Scratch gets reset to zero in dml, but link encoder instance can be zero, so reset to -1 */
1248         for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) {
1249                 dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1;
1250         }
1251
1252         /* If an HPO stream encoder is allocated to a pipe, get the instance of it's allocated HPO Link encoder */
1253         for (i = 0; i < MAX_PIPES; i++) {
1254                 current_pipe_context = &context->res_ctx.pipe_ctx[i];
1255                 if (current_pipe_context->stream &&
1256                         current_pipe_context->stream_res.hpo_dp_stream_enc &&
1257                         current_pipe_context->link_res.hpo_dp_link_enc &&
1258                         dc_is_dp_signal(current_pipe_context->stream->signal)) {
1259                                 dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst] =
1260                                         current_pipe_context->link_res.hpo_dp_link_enc->inst;
1261                         }
1262         }
1263 }
1264
1265 void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg)
1266 {
1267         int i = 0, j = 0, k = 0;
1268         int disp_cfg_stream_location, disp_cfg_plane_location;
1269         enum mall_stream_type stream_mall_type;
1270         struct pipe_ctx *current_pipe_context;
1271
1272         for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {
1273                 dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[i] = false;
1274                 dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[i] = false;
1275                 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[i] = false;
1276                 dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[i] = false;
1277         }
1278
1279         //Generally these are set by referencing our latest BB/IP params in dcn32_resource.c file
1280         dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable;
1281         dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels;
1282         dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable;
1283         dml_dispcfg->plane.HostVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.hostvm_max_page_table_levels;
1284         if (dml2->v20.dml_core_ctx.ip.hostvm_enable)
1285                 dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter;
1286
1287         dml2_populate_pipe_to_plane_index_mapping(dml2, context);
1288         dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(dml2, context);
1289
1290         for (i = 0; i < context->stream_count; i++) {
1291                 current_pipe_context = NULL;
1292                 for (k = 0; k < MAX_PIPES; k++) {
1293                         /* find one pipe allocated to this stream for the purpose of getting
1294                         info about the link later */
1295                         if (context->streams[i] == context->res_ctx.pipe_ctx[k].stream) {
1296                                 current_pipe_context = &context->res_ctx.pipe_ctx[k];
1297                                 break;
1298                         }
1299                 }
1300                 disp_cfg_stream_location = map_stream_to_dml_display_cfg(dml2, context->streams[i], dml_dispcfg);
1301                 stream_mall_type = dc_state_get_stream_subvp_type(context, context->streams[i]);
1302
1303                 if (disp_cfg_stream_location < 0)
1304                         disp_cfg_stream_location = dml_dispcfg->num_timings++;
1305
1306                 ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1307
1308                 populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]);
1309                 populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2);
1310                 /*Call site for populate_dml_writeback_cfg_from_stream_state*/
1311                 populate_dml_writeback_cfg_from_stream_state(&dml_dispcfg->writeback,
1312                         disp_cfg_stream_location, context->streams[i]);
1313
1314                 switch (context->streams[i]->debug.force_odm_combine_segments) {
1315                 case 2:
1316                         dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_2to1;
1317                         break;
1318                 case 4:
1319                         dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_stream_location] = dml_odm_use_policy_combine_4to1;
1320                         break;
1321                 default:
1322                         break;
1323                 }
1324
1325                 dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_stream_location] = context->streams[i]->stream_id;
1326                 dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_stream_location] = true;
1327
1328                 if (context->stream_status[i].plane_count == 0) {
1329                         disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
1330
1331                         populate_dummy_dml_surface_cfg(&dml_dispcfg->surface, disp_cfg_plane_location, context->streams[i]);
1332                         populate_dummy_dml_plane_cfg(&dml_dispcfg->plane, disp_cfg_plane_location,
1333                                                      context->streams[i], &dml2->v20.dml_core_ctx.soc);
1334
1335                         dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;
1336
1337                         dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;
1338                 } else {
1339                         for (j = 0; j < context->stream_status[i].plane_count; j++) {
1340                                 disp_cfg_plane_location = map_plane_to_dml_display_cfg(dml2,
1341                                         context->stream_status[i].plane_states[j], context, dml_dispcfg, context->streams[i]->stream_id, j);
1342
1343                                 if (disp_cfg_plane_location < 0)
1344                                         disp_cfg_plane_location = dml_dispcfg->num_surfaces++;
1345
1346                                 ASSERT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__);
1347
1348                                 populate_dml_surface_cfg_from_plane_state(dml2->v20.dml_core_ctx.project, &dml_dispcfg->surface, disp_cfg_plane_location, context->stream_status[i].plane_states[j]);
1349                                 populate_dml_plane_cfg_from_plane_state(
1350                                         &dml_dispcfg->plane, disp_cfg_plane_location,
1351                                         context->stream_status[i].plane_states[j], context,
1352                                         &dml2->v20.dml_core_ctx.soc);
1353
1354                                 if (stream_mall_type == SUBVP_MAIN) {
1355                                         dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;
1356                                         dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;
1357                                 } else if (stream_mall_type == SUBVP_PHANTOM) {
1358                                         dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;
1359                                         dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_disable;
1360                                         dml2->v20.dml_core_ctx.policy.ImmediateFlipRequirement[disp_cfg_plane_location] = dml_immediate_flip_not_required;
1361                                 } else {
1362                                         dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_disable;
1363                                         dml_dispcfg->plane.UseMALLForStaticScreen[disp_cfg_plane_location] = dml_use_mall_static_screen_optimize;
1364                                 }
1365
1366                                 dml_dispcfg->plane.BlendingAndTiming[disp_cfg_plane_location] = disp_cfg_stream_location;
1367
1368                                 if (get_plane_id(dml2, context, context->stream_status[i].plane_states[j], context->streams[i]->stream_id, j,
1369                                         &dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[disp_cfg_plane_location]))
1370                                         dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id_valid[disp_cfg_plane_location] = true;
1371
1372                                 if (j >= 1) {
1373                                         populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_plane_location, context->streams[i]);
1374                                         populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_plane_location, context->streams[i], current_pipe_context, dml2);
1375                                         switch (context->streams[i]->debug.force_odm_combine_segments) {
1376                                         case 2:
1377                                                 dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_2to1;
1378                                                 break;
1379                                         case 4:
1380                                                 dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_4to1;
1381                                                 break;
1382                                         default:
1383                                                 break;
1384                                         }
1385
1386                                         if (stream_mall_type == SUBVP_MAIN)
1387                                                 dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_sub_viewport;
1388                                         else if (stream_mall_type == SUBVP_PHANTOM)
1389                                                 dml_dispcfg->plane.UseMALLForPStateChange[disp_cfg_plane_location] = dml_use_mall_pstate_change_phantom_pipe;
1390
1391                                         dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[disp_cfg_plane_location] = context->streams[i]->stream_id;
1392                                         dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id_valid[disp_cfg_plane_location] = true;
1393
1394                                         dml_dispcfg->num_timings++;
1395                                 }
1396                         }
1397                 }
1398         }
1399
1400         if (!dml2->config.use_native_pstate_optimization)
1401                 apply_legacy_svp_drr_settings(dml2, context, dml_dispcfg);
1402 }
1403
1404 void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs,
1405         struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs,
1406         struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs,
1407         struct pipe_ctx *out)
1408 {
1409         memset(&out->rq_regs, 0, sizeof(out->rq_regs));
1410         out->rq_regs.rq_regs_l.chunk_size = rq_regs->rq_regs_l.chunk_size;
1411         out->rq_regs.rq_regs_l.min_chunk_size = rq_regs->rq_regs_l.min_chunk_size;
1412         out->rq_regs.rq_regs_l.meta_chunk_size = rq_regs->rq_regs_l.meta_chunk_size;
1413         out->rq_regs.rq_regs_l.min_meta_chunk_size = rq_regs->rq_regs_l.min_meta_chunk_size;
1414         out->rq_regs.rq_regs_l.dpte_group_size = rq_regs->rq_regs_l.dpte_group_size;
1415         out->rq_regs.rq_regs_l.mpte_group_size = rq_regs->rq_regs_l.mpte_group_size;
1416         out->rq_regs.rq_regs_l.swath_height = rq_regs->rq_regs_l.swath_height;
1417         out->rq_regs.rq_regs_l.pte_row_height_linear = rq_regs->rq_regs_l.pte_row_height_linear;
1418
1419         out->rq_regs.rq_regs_c.chunk_size = rq_regs->rq_regs_c.chunk_size;
1420         out->rq_regs.rq_regs_c.min_chunk_size = rq_regs->rq_regs_c.min_chunk_size;
1421         out->rq_regs.rq_regs_c.meta_chunk_size = rq_regs->rq_regs_c.meta_chunk_size;
1422         out->rq_regs.rq_regs_c.min_meta_chunk_size = rq_regs->rq_regs_c.min_meta_chunk_size;
1423         out->rq_regs.rq_regs_c.dpte_group_size = rq_regs->rq_regs_c.dpte_group_size;
1424         out->rq_regs.rq_regs_c.mpte_group_size = rq_regs->rq_regs_c.mpte_group_size;
1425         out->rq_regs.rq_regs_c.swath_height = rq_regs->rq_regs_c.swath_height;
1426         out->rq_regs.rq_regs_c.pte_row_height_linear = rq_regs->rq_regs_c.pte_row_height_linear;
1427
1428         out->rq_regs.drq_expansion_mode = rq_regs->drq_expansion_mode;
1429         out->rq_regs.prq_expansion_mode = rq_regs->prq_expansion_mode;
1430         out->rq_regs.mrq_expansion_mode = rq_regs->mrq_expansion_mode;
1431         out->rq_regs.crq_expansion_mode = rq_regs->crq_expansion_mode;
1432         out->rq_regs.plane1_base_address = rq_regs->plane1_base_address;
1433
1434         memset(&out->dlg_regs, 0, sizeof(out->dlg_regs));
1435         out->dlg_regs.refcyc_h_blank_end = disp_dlg_regs->refcyc_h_blank_end;
1436         out->dlg_regs.dlg_vblank_end = disp_dlg_regs->dlg_vblank_end;
1437         out->dlg_regs.min_dst_y_next_start = disp_dlg_regs->min_dst_y_next_start;
1438         out->dlg_regs.refcyc_per_htotal = disp_dlg_regs->refcyc_per_htotal;
1439         out->dlg_regs.refcyc_x_after_scaler = disp_dlg_regs->refcyc_x_after_scaler;
1440         out->dlg_regs.dst_y_after_scaler = disp_dlg_regs->dst_y_after_scaler;
1441         out->dlg_regs.dst_y_prefetch = disp_dlg_regs->dst_y_prefetch;
1442         out->dlg_regs.dst_y_per_vm_vblank = disp_dlg_regs->dst_y_per_vm_vblank;
1443         out->dlg_regs.dst_y_per_row_vblank = disp_dlg_regs->dst_y_per_row_vblank;
1444         out->dlg_regs.dst_y_per_vm_flip = disp_dlg_regs->dst_y_per_vm_flip;
1445         out->dlg_regs.dst_y_per_row_flip = disp_dlg_regs->dst_y_per_row_flip;
1446         out->dlg_regs.ref_freq_to_pix_freq = disp_dlg_regs->ref_freq_to_pix_freq;
1447         out->dlg_regs.vratio_prefetch = disp_dlg_regs->vratio_prefetch;
1448         out->dlg_regs.vratio_prefetch_c = disp_dlg_regs->vratio_prefetch_c;
1449         out->dlg_regs.refcyc_per_pte_group_vblank_l = disp_dlg_regs->refcyc_per_pte_group_vblank_l;
1450         out->dlg_regs.refcyc_per_pte_group_vblank_c = disp_dlg_regs->refcyc_per_pte_group_vblank_c;
1451         out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;
1452         out->dlg_regs.refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_c;
1453         out->dlg_regs.refcyc_per_pte_group_flip_l = disp_dlg_regs->refcyc_per_pte_group_flip_l;
1454         out->dlg_regs.refcyc_per_pte_group_flip_c = disp_dlg_regs->refcyc_per_pte_group_flip_c;
1455         out->dlg_regs.refcyc_per_meta_chunk_flip_l = disp_dlg_regs->refcyc_per_meta_chunk_flip_l;
1456         out->dlg_regs.refcyc_per_meta_chunk_flip_c = disp_dlg_regs->refcyc_per_meta_chunk_flip_c;
1457         out->dlg_regs.dst_y_per_pte_row_nom_l = disp_dlg_regs->dst_y_per_pte_row_nom_l;
1458         out->dlg_regs.dst_y_per_pte_row_nom_c = disp_dlg_regs->dst_y_per_pte_row_nom_c;
1459         out->dlg_regs.refcyc_per_pte_group_nom_l = disp_dlg_regs->refcyc_per_pte_group_nom_l;
1460         out->dlg_regs.refcyc_per_pte_group_nom_c = disp_dlg_regs->refcyc_per_pte_group_nom_c;
1461         out->dlg_regs.dst_y_per_meta_row_nom_l = disp_dlg_regs->dst_y_per_meta_row_nom_l;
1462         out->dlg_regs.dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_c;
1463         out->dlg_regs.refcyc_per_meta_chunk_nom_l = disp_dlg_regs->refcyc_per_meta_chunk_nom_l;
1464         out->dlg_regs.refcyc_per_meta_chunk_nom_c = disp_dlg_regs->refcyc_per_meta_chunk_nom_c;
1465         out->dlg_regs.refcyc_per_line_delivery_pre_l = disp_dlg_regs->refcyc_per_line_delivery_pre_l;
1466         out->dlg_regs.refcyc_per_line_delivery_pre_c = disp_dlg_regs->refcyc_per_line_delivery_pre_c;
1467         out->dlg_regs.refcyc_per_line_delivery_l = disp_dlg_regs->refcyc_per_line_delivery_l;
1468         out->dlg_regs.refcyc_per_line_delivery_c = disp_dlg_regs->refcyc_per_line_delivery_c;
1469         out->dlg_regs.refcyc_per_vm_group_vblank = disp_dlg_regs->refcyc_per_vm_group_vblank;
1470         out->dlg_regs.refcyc_per_vm_group_flip = disp_dlg_regs->refcyc_per_vm_group_flip;
1471         out->dlg_regs.refcyc_per_vm_req_vblank = disp_dlg_regs->refcyc_per_vm_req_vblank;
1472         out->dlg_regs.refcyc_per_vm_req_flip = disp_dlg_regs->refcyc_per_vm_req_flip;
1473         out->dlg_regs.dst_y_offset_cur0 = disp_dlg_regs->dst_y_offset_cur0;
1474         out->dlg_regs.chunk_hdl_adjust_cur0 = disp_dlg_regs->chunk_hdl_adjust_cur0;
1475         out->dlg_regs.dst_y_offset_cur1 = disp_dlg_regs->dst_y_offset_cur1;
1476         out->dlg_regs.chunk_hdl_adjust_cur1 = disp_dlg_regs->chunk_hdl_adjust_cur1;
1477         out->dlg_regs.vready_after_vcount0 = disp_dlg_regs->vready_after_vcount0;
1478         out->dlg_regs.dst_y_delta_drq_limit = disp_dlg_regs->dst_y_delta_drq_limit;
1479         out->dlg_regs.refcyc_per_vm_dmdata = disp_dlg_regs->refcyc_per_vm_dmdata;
1480         out->dlg_regs.dmdata_dl_delta = disp_dlg_regs->dmdata_dl_delta;
1481
1482         memset(&out->ttu_regs, 0, sizeof(out->ttu_regs));
1483         out->ttu_regs.qos_level_low_wm = disp_ttu_regs->qos_level_low_wm;
1484         out->ttu_regs.qos_level_high_wm = disp_ttu_regs->qos_level_high_wm;
1485         out->ttu_regs.min_ttu_vblank = disp_ttu_regs->min_ttu_vblank;
1486         out->ttu_regs.qos_level_flip = disp_ttu_regs->qos_level_flip;
1487         out->ttu_regs.refcyc_per_req_delivery_l = disp_ttu_regs->refcyc_per_req_delivery_l;
1488         out->ttu_regs.refcyc_per_req_delivery_c = disp_ttu_regs->refcyc_per_req_delivery_c;
1489         out->ttu_regs.refcyc_per_req_delivery_cur0 = disp_ttu_regs->refcyc_per_req_delivery_cur0;
1490         out->ttu_regs.refcyc_per_req_delivery_cur1 = disp_ttu_regs->refcyc_per_req_delivery_cur1;
1491         out->ttu_regs.refcyc_per_req_delivery_pre_l = disp_ttu_regs->refcyc_per_req_delivery_pre_l;
1492         out->ttu_regs.refcyc_per_req_delivery_pre_c = disp_ttu_regs->refcyc_per_req_delivery_pre_c;
1493         out->ttu_regs.refcyc_per_req_delivery_pre_cur0 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur0;
1494         out->ttu_regs.refcyc_per_req_delivery_pre_cur1 = disp_ttu_regs->refcyc_per_req_delivery_pre_cur1;
1495         out->ttu_regs.qos_level_fixed_l = disp_ttu_regs->qos_level_fixed_l;
1496         out->ttu_regs.qos_level_fixed_c = disp_ttu_regs->qos_level_fixed_c;
1497         out->ttu_regs.qos_level_fixed_cur0 = disp_ttu_regs->qos_level_fixed_cur0;
1498         out->ttu_regs.qos_level_fixed_cur1 = disp_ttu_regs->qos_level_fixed_cur1;
1499         out->ttu_regs.qos_ramp_disable_l = disp_ttu_regs->qos_ramp_disable_l;
1500         out->ttu_regs.qos_ramp_disable_c = disp_ttu_regs->qos_ramp_disable_c;
1501         out->ttu_regs.qos_ramp_disable_cur0 = disp_ttu_regs->qos_ramp_disable_cur0;
1502         out->ttu_regs.qos_ramp_disable_cur1 = disp_ttu_regs->qos_ramp_disable_cur1;
1503 }