drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright 2022 Advanced Micro Devices, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26 #include <drm/drm_vblank.h>
  27 #include <drm/drm_atomic_helper.h>
  28
  29 #include "dc.h"
  30 #include "amdgpu.h"
  31 #include "amdgpu_dm_psr.h"
  32 #include "amdgpu_dm_replay.h"
  33 #include "amdgpu_dm_crtc.h"
  34 #include "amdgpu_dm_plane.h"
  35 #include "amdgpu_dm_trace.h"
  36 #include "amdgpu_dm_debugfs.h"
  37
  38 #define HPD_DETECTION_PERIOD_uS 5000000
  39 #define HPD_DETECTION_TIME_uS 1000
  40
  41 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
  42 {
  43         struct drm_crtc *crtc = &acrtc->base;
  44         struct drm_device *dev = crtc->dev;
  45         unsigned long flags;
  46
  47         drm_crtc_handle_vblank(crtc);
  48
  49         spin_lock_irqsave(&dev->event_lock, flags);
  50
  51         /* Send completion event for cursor-only commits */
  52         if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
  53                 drm_crtc_send_vblank_event(crtc, acrtc->event);
  54                 drm_crtc_vblank_put(crtc);
  55                 acrtc->event = NULL;
  56         }
  57
  58         spin_unlock_irqrestore(&dev->event_lock, flags);
  59 }
  60
  61 bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
  62                              struct dc_stream_state *new_stream,
  63                              struct dc_stream_state *old_stream)
  64 {
  65         return crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
  66 }
  67
  68 bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
  69
  70 {
  71         return acrtc->dm_irq_params.freesync_config.state ==
  72                        VRR_STATE_ACTIVE_VARIABLE ||
  73                acrtc->dm_irq_params.freesync_config.state ==
  74                        VRR_STATE_ACTIVE_FIXED;
  75 }
  76
  77 int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
  78 {
  79         enum dc_irq_source irq_source;
  80         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  81         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
  82         int rc;
  83
  84         if (acrtc->otg_inst == -1)
  85                 return 0;
  86
  87         irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
  88
  89         rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
  90
  91         DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
  92                       acrtc->crtc_id, enable ? "en" : "dis", rc);
  93         return rc;
  94 }
  95
  96 bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
  97 {
  98         return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
  99                dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 100 }
 101
 102 /**
 103  * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features.
 104  *
 105  * @vblank_work:    is a pointer to a struct vblank_control_work object.
 106  * @vblank_enabled: indicates whether the DRM vblank counter is currently
 107  *                  enabled (true) or disabled (false).
 108  * @allow_sr_entry: represents whether entry into the self-refresh mode is
 109  *                  allowed (true) or not allowed (false).
 110  *
 111  * The DRM vblank counter enable/disable action is used as the trigger to enable
 112  * or disable various panel self-refresh features:
 113  *
 114  * Panel Replay and PSR SU
 115  * - Enable when:
 116  *      - vblank counter is disabled
 117  *      - entry is allowed: usermode demonstrates an adequate number of fast
 118  *        commits)
 119  *     - CRC capture window isn't active
 120  * - Keep enabled even when vblank counter gets enabled
 121  *
 122  * PSR1
 123  * - Enable condition same as above
 124  * - Disable when vblank counter is enabled
 125  */
 126 static void amdgpu_dm_crtc_set_panel_sr_feature(
 127         struct vblank_control_work *vblank_work,
 128         bool vblank_enabled, bool allow_sr_entry)
 129 {
 130         struct dc_link *link = vblank_work->stream->link;
 131         bool is_sr_active = (link->replay_settings.replay_allow_active ||
 132                                  link->psr_settings.psr_allow_active);
 133         bool is_crc_window_active = false;
 134
 135 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
 136         is_crc_window_active =
 137                 amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);
 138 #endif
 139
 140         if (link->replay_settings.replay_feature_enabled &&
 141                 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
 142                 amdgpu_dm_replay_enable(vblank_work->stream, true);
 143         } else if (vblank_enabled) {
 144                 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
 145                         amdgpu_dm_psr_disable(vblank_work->stream);
 146         } else if (link->psr_settings.psr_feature_enabled &&
 147                 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
 148
 149                 struct amdgpu_dm_connector *aconn =
 150                         (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
 151
 152                 if (!aconn->disallow_edp_enter_psr) {
 153                         struct amdgpu_display_manager *dm = vblank_work->dm;
 154
 155                         amdgpu_dm_psr_enable(vblank_work->stream);
 156                         if (dm->idle_workqueue &&
 157                             dm->dc->idle_optimizations_allowed &&
 158                             dm->idle_workqueue->enable &&
 159                             !dm->idle_workqueue->running)
 160                                 schedule_work(&dm->idle_workqueue->work);
 161                 }
 162         }
 163 }
 164
 165 bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
 166 {
 167         struct drm_connector *connector;
 168         struct drm_connector_list_iter iter;
 169         struct drm_device *dev;
 170         bool is_headless = true;
 171
 172         if (adev == NULL)
 173                 return true;
 174
 175         dev = adev->dm.ddev;
 176
 177         drm_connector_list_iter_begin(dev, &iter);
 178         drm_for_each_connector_iter(connector, &iter) {
 179
 180                 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
 181                         continue;
 182
 183                 if (connector->status == connector_status_connected) {
 184                         is_headless = false;
 185                         break;
 186                 }
 187         }
 188         drm_connector_list_iter_end(&iter);
 189         return is_headless;
 190 }
 191
 192 static void amdgpu_dm_idle_worker(struct work_struct *work)
 193 {
 194         struct idle_workqueue *idle_work;
 195
 196         idle_work = container_of(work, struct idle_workqueue, work);
 197         idle_work->dm->idle_workqueue->running = true;
 198
 199         while (idle_work->enable) {
 200                 fsleep(HPD_DETECTION_PERIOD_uS);
 201                 mutex_lock(&idle_work->dm->dc_lock);
 202                 if (!idle_work->dm->dc->idle_optimizations_allowed) {
 203                         mutex_unlock(&idle_work->dm->dc_lock);
 204                         break;
 205                 }
 206                 dc_allow_idle_optimizations(idle_work->dm->dc, false);
 207
 208                 mutex_unlock(&idle_work->dm->dc_lock);
 209                 fsleep(HPD_DETECTION_TIME_uS);
 210                 mutex_lock(&idle_work->dm->dc_lock);
 211
 212                 if (!amdgpu_dm_is_headless(idle_work->dm->adev) &&
 213                     !amdgpu_dm_psr_is_active_allowed(idle_work->dm)) {
 214                         mutex_unlock(&idle_work->dm->dc_lock);
 215                         break;
 216                 }
 217
 218                 if (idle_work->enable)
 219                         dc_allow_idle_optimizations(idle_work->dm->dc, true);
 220                 mutex_unlock(&idle_work->dm->dc_lock);
 221         }
 222         idle_work->dm->idle_workqueue->running = false;
 223 }
 224
 225 struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
 226 {
 227         struct idle_workqueue *idle_work;
 228
 229         idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL);
 230         if (ZERO_OR_NULL_PTR(idle_work))
 231                 return NULL;
 232
 233         idle_work->dm = &adev->dm;
 234         idle_work->enable = false;
 235         idle_work->running = false;
 236         INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
 237
 238         return idle_work;
 239 }
 240
 241 static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
 242 {
 243         struct vblank_control_work *vblank_work =
 244                 container_of(work, struct vblank_control_work, work);
 245         struct amdgpu_display_manager *dm = vblank_work->dm;
 246
 247         mutex_lock(&dm->dc_lock);
 248
 249         if (vblank_work->enable)
 250                 dm->active_vblank_irq_count++;
 251         else if (dm->active_vblank_irq_count)
 252                 dm->active_vblank_irq_count--;
 253
 254         if (dm->active_vblank_irq_count > 0) {
 255                 DRM_DEBUG_KMS("Allow idle optimizations (MALL): false\n");
 256                 dc_allow_idle_optimizations(dm->dc, false);
 257         }
 258
 259         /*
 260          * Control PSR based on vblank requirements from OS
 261          *
 262          * If panel supports PSR SU, there's no need to disable PSR when OS is
 263          * submitting fast atomic commits (we infer this by whether the OS
 264          * requests vblank events). Fast atomic commits will simply trigger a
 265          * full-frame-update (FFU); a specific case of selective-update (SU)
 266          * where the SU region is the full hactive*vactive region. See
 267          * fill_dc_dirty_rects().
 268          */
 269         if (vblank_work->stream && vblank_work->stream->link) {
 270                 amdgpu_dm_crtc_set_panel_sr_feature(
 271                         vblank_work, vblank_work->enable,
 272                         vblank_work->acrtc->dm_irq_params.allow_psr_entry ||
 273                         vblank_work->stream->link->replay_settings.replay_feature_enabled);
 274         }
 275
 276         if (dm->active_vblank_irq_count == 0) {
 277                 DRM_DEBUG_KMS("Allow idle optimizations (MALL): true\n");
 278                 dc_allow_idle_optimizations(dm->dc, true);
 279         }
 280
 281         mutex_unlock(&dm->dc_lock);
 282
 283         dc_stream_release(vblank_work->stream);
 284
 285         kfree(vblank_work);
 286 }
 287
 288 static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
 289 {
 290         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 291         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 292         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
 293         struct amdgpu_display_manager *dm = &adev->dm;
 294         struct vblank_control_work *work;
 295         int irq_type;
 296         int rc = 0;
 297
 298         if (acrtc->otg_inst == -1)
 299                 goto skip;
 300
 301         irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
 302
 303         if (enable) {
 304                 /* vblank irq on -> Only need vupdate irq in vrr mode */
 305                 if (amdgpu_dm_crtc_vrr_active(acrtc_state))
 306                         rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
 307         } else {
 308                 /* vblank irq off -> vupdate irq off */
 309                 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
 310         }
 311
 312         if (rc)
 313                 return rc;
 314
 315         /* crtc vblank or vstartup interrupt */
 316         if (enable) {
 317                 rc = amdgpu_irq_get(adev, &adev->crtc_irq, irq_type);
 318                 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc);
 319         } else {
 320                 rc = amdgpu_irq_put(adev, &adev->crtc_irq, irq_type);
 321                 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc);
 322         }
 323
 324         if (rc)
 325                 return rc;
 326
 327         /*
 328          * hubp surface flip interrupt
 329          *
 330          * We have no guarantee that the frontend index maps to the same
 331          * backend index - some even map to more than one.
 332          *
 333          * TODO: Use a different interrupt or check DC itself for the mapping.
 334          */
 335         if (enable) {
 336                 rc = amdgpu_irq_get(adev, &adev->pageflip_irq, irq_type);
 337                 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc);
 338         } else {
 339                 rc = amdgpu_irq_put(adev, &adev->pageflip_irq, irq_type);
 340                 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc);
 341         }
 342
 343         if (rc)
 344                 return rc;
 345
 346 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 347         /* crtc vline0 interrupt, only available on DCN+ */
 348         if (amdgpu_ip_version(adev, DCE_HWIP, 0) != 0) {
 349                 if (enable) {
 350                         rc = amdgpu_irq_get(adev, &adev->vline0_irq, irq_type);
 351                         drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc);
 352                 } else {
 353                         rc = amdgpu_irq_put(adev, &adev->vline0_irq, irq_type);
 354                         drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc);
 355                 }
 356
 357                 if (rc)
 358                         return rc;
 359         }
 360 #endif
 361 skip:
 362         if (amdgpu_in_reset(adev))
 363                 return 0;
 364
 365         if (dm->vblank_control_workqueue) {
 366                 work = kzalloc(sizeof(*work), GFP_ATOMIC);
 367                 if (!work)
 368                         return -ENOMEM;
 369
 370                 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
 371                 work->dm = dm;
 372                 work->acrtc = acrtc;
 373                 work->enable = enable;
 374
 375                 if (acrtc_state->stream) {
 376                         dc_stream_retain(acrtc_state->stream);
 377                         work->stream = acrtc_state->stream;
 378                 }
 379
 380                 queue_work(dm->vblank_control_workqueue, &work->work);
 381         }
 382
 383         return 0;
 384 }
 385
 386 int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
 387 {
 388         return amdgpu_dm_crtc_set_vblank(crtc, true);
 389 }
 390
 391 void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
 392 {
 393         amdgpu_dm_crtc_set_vblank(crtc, false);
 394 }
 395
 396 static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
 397                                   struct drm_crtc_state *state)
 398 {
 399         struct dm_crtc_state *cur = to_dm_crtc_state(state);
 400
 401         /* TODO Destroy dc_stream objects are stream object is flattened */
 402         if (cur->stream)
 403                 dc_stream_release(cur->stream);
 404
 405
 406         __drm_atomic_helper_crtc_destroy_state(state);
 407
 408
 409         kfree(state);
 410 }
 411
 412 static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
 413 {
 414         struct dm_crtc_state *state, *cur;
 415
 416         cur = to_dm_crtc_state(crtc->state);
 417
 418         if (WARN_ON(!crtc->state))
 419                 return NULL;
 420
 421         state = kzalloc(sizeof(*state), GFP_KERNEL);
 422         if (!state)
 423                 return NULL;
 424
 425         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 426
 427         if (cur->stream) {
 428                 state->stream = cur->stream;
 429                 dc_stream_retain(state->stream);
 430         }
 431
 432         state->active_planes = cur->active_planes;
 433         state->vrr_infopacket = cur->vrr_infopacket;
 434         state->abm_level = cur->abm_level;
 435         state->vrr_supported = cur->vrr_supported;
 436         state->freesync_config = cur->freesync_config;
 437         state->cm_has_degamma = cur->cm_has_degamma;
 438         state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
 439         state->regamma_tf = cur->regamma_tf;
 440         state->crc_skip_count = cur->crc_skip_count;
 441         state->mpo_requested = cur->mpo_requested;
 442         state->cursor_mode = cur->cursor_mode;
 443         /* TODO Duplicate dc_stream after objects are stream object is flattened */
 444
 445         return &state->base;
 446 }
 447
 448 static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
 449 {
 450         drm_crtc_cleanup(crtc);
 451         kfree(crtc);
 452 }
 453
 454 static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
 455 {
 456         struct dm_crtc_state *state;
 457
 458         if (crtc->state)
 459                 amdgpu_dm_crtc_destroy_state(crtc, crtc->state);
 460
 461         state = kzalloc(sizeof(*state), GFP_KERNEL);
 462         if (WARN_ON(!state))
 463                 return;
 464
 465         __drm_atomic_helper_crtc_reset(crtc, &state->base);
 466 }
 467
 468 #ifdef CONFIG_DEBUG_FS
 469 static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
 470 {
 471         crtc_debugfs_init(crtc);
 472
 473         return 0;
 474 }
 475 #endif
 476
 477 #ifdef AMD_PRIVATE_COLOR
 478 /**
 479  * dm_crtc_additional_color_mgmt - enable additional color properties
 480  * @crtc: DRM CRTC
 481  *
 482  * This function lets the driver enable post-blending CRTC regamma transfer
 483  * function property in addition to DRM CRTC gamma LUT. Default value means
 484  * linear transfer function, which is the default CRTC gamma LUT behaviour
 485  * without this property.
 486  */
 487 static void
 488 dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
 489 {
 490         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 491
 492         if (adev->dm.dc->caps.color.mpc.ogam_ram)
 493                 drm_object_attach_property(&crtc->base,
 494                                            adev->mode_info.regamma_tf_property,
 495                                            AMDGPU_TRANSFER_FUNCTION_DEFAULT);
 496 }
 497
 498 static int
 499 amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
 500                                    struct drm_crtc_state *state,
 501                                    struct drm_property *property,
 502                                    uint64_t val)
 503 {
 504         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 505         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
 506
 507         if (property == adev->mode_info.regamma_tf_property) {
 508                 if (acrtc_state->regamma_tf != val) {
 509                         acrtc_state->regamma_tf = val;
 510                         acrtc_state->base.color_mgmt_changed |= 1;
 511                 }
 512         } else {
 513                 drm_dbg_atomic(crtc->dev,
 514                                "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
 515                                crtc->base.id, crtc->name,
 516                                property->base.id, property->name);
 517                 return -EINVAL;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int
 524 amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
 525                                    const struct drm_crtc_state *state,
 526                                    struct drm_property *property,
 527                                    uint64_t *val)
 528 {
 529         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 530         struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
 531
 532         if (property == adev->mode_info.regamma_tf_property)
 533                 *val = acrtc_state->regamma_tf;
 534         else
 535                 return -EINVAL;
 536
 537         return 0;
 538 }
 539 #endif
 540
 541 /* Implemented only the options currently available for the driver */
 542 static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
 543         .reset = amdgpu_dm_crtc_reset_state,
 544         .destroy = amdgpu_dm_crtc_destroy,
 545         .set_config = drm_atomic_helper_set_config,
 546         .page_flip = drm_atomic_helper_page_flip,
 547         .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
 548         .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
 549         .set_crc_source = amdgpu_dm_crtc_set_crc_source,
 550         .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
 551         .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
 552         .get_vblank_counter = amdgpu_get_vblank_counter_kms,
 553         .enable_vblank = amdgpu_dm_crtc_enable_vblank,
 554         .disable_vblank = amdgpu_dm_crtc_disable_vblank,
 555         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
 556 #if defined(CONFIG_DEBUG_FS)
 557         .late_register = amdgpu_dm_crtc_late_register,
 558 #endif
 559 #ifdef AMD_PRIVATE_COLOR
 560         .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
 561         .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
 562 #endif
 563 };
 564
 565 static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
 566 {
 567 }
 568
 569 static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
 570 {
 571         struct drm_atomic_state *state = new_crtc_state->state;
 572         struct drm_plane *plane;
 573         int num_active = 0;
 574
 575         drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
 576                 struct drm_plane_state *new_plane_state;
 577
 578                 /* Cursor planes are "fake". */
 579                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
 580                         continue;
 581
 582                 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
 583
 584                 if (!new_plane_state) {
 585                         /*
 586                          * The plane is enable on the CRTC and hasn't changed
 587                          * state. This means that it previously passed
 588                          * validation and is therefore enabled.
 589                          */
 590                         num_active += 1;
 591                         continue;
 592                 }
 593
 594                 /* We need a framebuffer to be considered enabled. */
 595                 num_active += (new_plane_state->fb != NULL);
 596         }
 597
 598         return num_active;
 599 }
 600
 601 static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
 602                                                      struct drm_crtc_state *new_crtc_state)
 603 {
 604         struct dm_crtc_state *dm_new_crtc_state =
 605                 to_dm_crtc_state(new_crtc_state);
 606
 607         dm_new_crtc_state->active_planes = 0;
 608
 609         if (!dm_new_crtc_state->stream)
 610                 return;
 611
 612         dm_new_crtc_state->active_planes =
 613                 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
 614 }
 615
 616 static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
 617                                       const struct drm_display_mode *mode,
 618                                       struct drm_display_mode *adjusted_mode)
 619 {
 620         return true;
 621 }
 622
 623 static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
 624                                               struct drm_atomic_state *state)
 625 {
 626         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 627                                                                                 crtc);
 628         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 629         struct dc *dc = adev->dm.dc;
 630         struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
 631         int ret = -EINVAL;
 632
 633         trace_amdgpu_dm_crtc_atomic_check(crtc_state);
 634
 635         amdgpu_dm_crtc_update_crtc_active_planes(crtc, crtc_state);
 636
 637         if (WARN_ON(unlikely(!dm_crtc_state->stream &&
 638                         amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
 639                 return ret;
 640         }
 641
 642         /*
 643          * We require the primary plane to be enabled whenever the CRTC is, otherwise
 644          * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
 645          * planes are disabled, which is not supported by the hardware. And there is legacy
 646          * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
 647          */
 648         if (crtc_state->enable &&
 649                 !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) {
 650                 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
 651                 return -EINVAL;
 652         }
 653
 654         /*
 655          * Only allow async flips for fast updates that don't change the FB
 656          * pitch, the DCC state, rotation, etc.
 657          */
 658         if (crtc_state->async_flip &&
 659             dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
 660                 drm_dbg_atomic(crtc->dev,
 661                                "[CRTC:%d:%s] async flips are only supported for fast updates\n",
 662                                crtc->base.id, crtc->name);
 663                 return -EINVAL;
 664         }
 665
 666         /* In some use cases, like reset, no stream is attached */
 667         if (!dm_crtc_state->stream)
 668                 return 0;
 669
 670         if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
 671                 return 0;
 672
 673         DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
 674         return ret;
 675 }
 676
 677 static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
 678         .disable = amdgpu_dm_crtc_helper_disable,
 679         .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
 680         .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
 681         .get_scanout_position = amdgpu_crtc_get_scanout_position,
 682 };
 683
 684 int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 685                                struct drm_plane *plane,
 686                                uint32_t crtc_index)
 687 {
 688         struct amdgpu_crtc *acrtc = NULL;
 689         struct drm_plane *cursor_plane;
 690         bool is_dcn;
 691         int res = -ENOMEM;
 692
 693         cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
 694         if (!cursor_plane)
 695                 goto fail;
 696
 697         cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
 698         res = amdgpu_dm_plane_init(dm, cursor_plane, 0, NULL);
 699
 700         acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
 701         if (!acrtc)
 702                 goto fail;
 703
 704         res = drm_crtc_init_with_planes(
 705                         dm->ddev,
 706                         &acrtc->base,
 707                         plane,
 708                         cursor_plane,
 709                         &amdgpu_dm_crtc_funcs, NULL);
 710
 711         if (res)
 712                 goto fail;
 713
 714         drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs);
 715
 716         /* Create (reset) the plane state */
 717         if (acrtc->base.funcs->reset)
 718                 acrtc->base.funcs->reset(&acrtc->base);
 719
 720         acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
 721         acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
 722
 723         acrtc->crtc_id = crtc_index;
 724         acrtc->base.enabled = false;
 725         acrtc->otg_inst = -1;
 726
 727         dm->adev->mode_info.crtcs[crtc_index] = acrtc;
 728
 729         /* Don't enable DRM CRTC degamma property for DCE since it doesn't
 730          * support programmable degamma anywhere.
 731          */
 732         is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
 733         drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
 734                                    true, MAX_COLOR_LUT_ENTRIES);
 735
 736         drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
 737
 738 #ifdef AMD_PRIVATE_COLOR
 739         dm_crtc_additional_color_mgmt(&acrtc->base);
 740 #endif
 741         return 0;
 742
 743 fail:
 744         kfree(acrtc);
 745         kfree(cursor_plane);
 746         return res;
 747 }
 748