drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drm_drv.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_vcn.h"
  29 #include "amdgpu_pm.h"
  30 #include "soc15.h"
  31 #include "soc15d.h"
  32 #include "soc15_hw_ip.h"
  33 #include "vcn_v2_0.h"
  34 #include "mmsch_v4_0_3.h"
  35
  36 #include "vcn/vcn_4_0_3_offset.h"
  37 #include "vcn/vcn_4_0_3_sh_mask.h"
  38 #include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
  39
  40 #define mmUVD_DPG_LMA_CTL               regUVD_DPG_LMA_CTL
  41 #define mmUVD_DPG_LMA_CTL_BASE_IDX      regUVD_DPG_LMA_CTL_BASE_IDX
  42 #define mmUVD_DPG_LMA_DATA              regUVD_DPG_LMA_DATA
  43 #define mmUVD_DPG_LMA_DATA_BASE_IDX     regUVD_DPG_LMA_DATA_BASE_IDX
  44
  45 #define VCN_VID_SOC_ADDRESS_2_0         0x1fb00
  46 #define VCN1_VID_SOC_ADDRESS_3_0        0x48300
  47
  48 static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
  49         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
  50         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
  51         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
  52         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2),
  53         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
  54         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
  55         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
  56         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
  57         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
  58         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
  59         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
  60         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
  61         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
  62         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
  63         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
  64         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
  65         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
  66         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
  67         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
  68         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
  69         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
  70         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
  71         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
  72         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
  73         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
  74         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
  75         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
  76         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG),
  77         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS),
  78         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
  79         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
  80         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
  81         SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE)
  82 };
  83
  84 #define NORMALIZE_VCN_REG_OFFSET(offset) \
  85                 (offset & 0x1FFFF)
  86
  87 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
  88 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
  89 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
  90 static int vcn_v4_0_3_set_powergating_state(void *handle,
  91                 enum amd_powergating_state state);
  92 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
  93                 int inst_idx, struct dpg_pause_state *new_state);
  94 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring);
  95 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
  96 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
  97                                   int inst_idx, bool indirect);
  98 /**
  99  * vcn_v4_0_3_early_init - set function pointers
 100  *
 101  * @handle: amdgpu_device pointer
 102  *
 103  * Set ring and irq function pointers
 104  */
 105 static int vcn_v4_0_3_early_init(void *handle)
 106 {
 107         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 108
 109         /* re-use enc ring as unified ring */
 110         adev->vcn.num_enc_rings = 1;
 111
 112         vcn_v4_0_3_set_unified_ring_funcs(adev);
 113         vcn_v4_0_3_set_irq_funcs(adev);
 114         vcn_v4_0_3_set_ras_funcs(adev);
 115
 116         return amdgpu_vcn_early_init(adev);
 117 }
 118
 119 /**
 120  * vcn_v4_0_3_sw_init - sw init for VCN block
 121  *
 122  * @handle: amdgpu_device pointer
 123  *
 124  * Load firmware and sw initialization
 125  */
 126 static int vcn_v4_0_3_sw_init(void *handle)
 127 {
 128         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 129         struct amdgpu_ring *ring;
 130         int i, r, vcn_inst;
 131         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
 132         uint32_t *ptr;
 133
 134         r = amdgpu_vcn_sw_init(adev);
 135         if (r)
 136                 return r;
 137
 138         amdgpu_vcn_setup_ucode(adev);
 139
 140         r = amdgpu_vcn_resume(adev);
 141         if (r)
 142                 return r;
 143
 144         /* VCN DEC TRAP */
 145         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
 146                 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq);
 147         if (r)
 148                 return r;
 149
 150         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 151                 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 152
 153                 vcn_inst = GET_INST(VCN, i);
 154
 155                 ring = &adev->vcn.inst[i].ring_enc[0];
 156                 ring->use_doorbell = true;
 157
 158                 if (!amdgpu_sriov_vf(adev))
 159                         ring->doorbell_index =
 160                                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 161                                 9 * vcn_inst;
 162                 else
 163                         ring->doorbell_index =
 164                                 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 165                                 32 * vcn_inst;
 166
 167                 ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
 168                 sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
 169                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
 170                                      AMDGPU_RING_PRIO_DEFAULT,
 171                                      &adev->vcn.inst[i].sched_score);
 172                 if (r)
 173                         return r;
 174
 175                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 176                 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
 177                 fw_shared->sq.is_enabled = true;
 178
 179                 if (amdgpu_vcnfw_log)
 180                         amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
 181         }
 182
 183         if (amdgpu_sriov_vf(adev)) {
 184                 r = amdgpu_virt_alloc_mm_table(adev);
 185                 if (r)
 186                         return r;
 187         }
 188
 189         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 190                 adev->vcn.pause_dpg_mode = vcn_v4_0_3_pause_dpg_mode;
 191
 192         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
 193                 r = amdgpu_vcn_ras_sw_init(adev);
 194                 if (r) {
 195                         dev_err(adev->dev, "Failed to initialize vcn ras block!\n");
 196                         return r;
 197                 }
 198         }
 199
 200         /* Allocate memory for VCN IP Dump buffer */
 201         ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
 202         if (!ptr) {
 203                 DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
 204                 adev->vcn.ip_dump = NULL;
 205         } else {
 206                 adev->vcn.ip_dump = ptr;
 207         }
 208
 209         return 0;
 210 }
 211
 212 /**
 213  * vcn_v4_0_3_sw_fini - sw fini for VCN block
 214  *
 215  * @handle: amdgpu_device pointer
 216  *
 217  * VCN suspend and free up sw allocation
 218  */
 219 static int vcn_v4_0_3_sw_fini(void *handle)
 220 {
 221         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 222         int i, r, idx;
 223
 224         if (drm_dev_enter(&adev->ddev, &idx)) {
 225                 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 226                         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 227
 228                         fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
 229                         fw_shared->present_flag_0 = 0;
 230                         fw_shared->sq.is_enabled = cpu_to_le32(false);
 231                 }
 232                 drm_dev_exit(idx);
 233         }
 234
 235         if (amdgpu_sriov_vf(adev))
 236                 amdgpu_virt_free_mm_table(adev);
 237
 238         r = amdgpu_vcn_suspend(adev);
 239         if (r)
 240                 return r;
 241
 242         r = amdgpu_vcn_sw_fini(adev);
 243
 244         kfree(adev->vcn.ip_dump);
 245
 246         return r;
 247 }
 248
 249 /**
 250  * vcn_v4_0_3_hw_init - start and test VCN block
 251  *
 252  * @handle: amdgpu_device pointer
 253  *
 254  * Initialize the hardware, boot up the VCPU and do some testing
 255  */
 256 static int vcn_v4_0_3_hw_init(void *handle)
 257 {
 258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 259         struct amdgpu_ring *ring;
 260         int i, r, vcn_inst;
 261
 262         if (amdgpu_sriov_vf(adev)) {
 263                 r = vcn_v4_0_3_start_sriov(adev);
 264                 if (r)
 265                         return r;
 266
 267                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 268                         ring = &adev->vcn.inst[i].ring_enc[0];
 269                         ring->wptr = 0;
 270                         ring->wptr_old = 0;
 271                         vcn_v4_0_3_unified_ring_set_wptr(ring);
 272                         ring->sched.ready = true;
 273                 }
 274         } else {
 275                 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
 276                         vcn_inst = GET_INST(VCN, i);
 277                         ring = &adev->vcn.inst[i].ring_enc[0];
 278
 279                         if (ring->use_doorbell) {
 280                                 adev->nbio.funcs->vcn_doorbell_range(
 281                                         adev, ring->use_doorbell,
 282                                         (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
 283                                                 9 * vcn_inst,
 284                                         adev->vcn.inst[i].aid_id);
 285
 286                                 WREG32_SOC15(
 287                                         VCN, GET_INST(VCN, ring->me),
 288                                         regVCN_RB1_DB_CTRL,
 289                                         ring->doorbell_index
 290                                                         << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
 291                                                 VCN_RB1_DB_CTRL__EN_MASK);
 292
 293                                 /* Read DB_CTRL to flush the write DB_CTRL command. */
 294                                 RREG32_SOC15(
 295                                         VCN, GET_INST(VCN, ring->me),
 296                                         regVCN_RB1_DB_CTRL);
 297                         }
 298
 299                         r = amdgpu_ring_test_helper(ring);
 300                         if (r)
 301                                 return r;
 302                 }
 303         }
 304
 305         return r;
 306 }
 307
 308 /**
 309  * vcn_v4_0_3_hw_fini - stop the hardware block
 310  *
 311  * @handle: amdgpu_device pointer
 312  *
 313  * Stop the VCN block, mark ring as not ready any more
 314  */
 315 static int vcn_v4_0_3_hw_fini(void *handle)
 316 {
 317         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 318
 319         cancel_delayed_work_sync(&adev->vcn.idle_work);
 320
 321         if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
 322                 vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
 323
 324         return 0;
 325 }
 326
 327 /**
 328  * vcn_v4_0_3_suspend - suspend VCN block
 329  *
 330  * @handle: amdgpu_device pointer
 331  *
 332  * HW fini and suspend VCN block
 333  */
 334 static int vcn_v4_0_3_suspend(void *handle)
 335 {
 336         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 337         int r;
 338
 339         r = vcn_v4_0_3_hw_fini(adev);
 340         if (r)
 341                 return r;
 342
 343         r = amdgpu_vcn_suspend(adev);
 344
 345         return r;
 346 }
 347
 348 /**
 349  * vcn_v4_0_3_resume - resume VCN block
 350  *
 351  * @handle: amdgpu_device pointer
 352  *
 353  * Resume firmware and hw init VCN block
 354  */
 355 static int vcn_v4_0_3_resume(void *handle)
 356 {
 357         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 358         int r;
 359
 360         r = amdgpu_vcn_resume(adev);
 361         if (r)
 362                 return r;
 363
 364         r = vcn_v4_0_3_hw_init(adev);
 365
 366         return r;
 367 }
 368
 369 /**
 370  * vcn_v4_0_3_mc_resume - memory controller programming
 371  *
 372  * @adev: amdgpu_device pointer
 373  * @inst_idx: instance number
 374  *
 375  * Let the VCN memory controller know it's offsets
 376  */
 377 static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx)
 378 {
 379         uint32_t offset, size, vcn_inst;
 380         const struct common_firmware_header *hdr;
 381
 382         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
 383         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 384
 385         vcn_inst = GET_INST(VCN, inst_idx);
 386         /* cache window 0: fw */
 387         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 388                 WREG32_SOC15(
 389                         VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 390                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx]
 391                                  .tmr_mc_addr_lo));
 392                 WREG32_SOC15(
 393                         VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 394                         (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx]
 395                                  .tmr_mc_addr_hi));
 396                 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0);
 397                 offset = 0;
 398         } else {
 399                 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 400                              lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
 401                 WREG32_SOC15(VCN, vcn_inst,
 402                              regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 403                              upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
 404                 offset = size;
 405                 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0,
 406                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 407         }
 408         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size);
 409
 410         /* cache window 1: stack */
 411         WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 412                      lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
 413         WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 414                      upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
 415         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0);
 416         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1,
 417                      AMDGPU_VCN_STACK_SIZE);
 418
 419         /* cache window 2: context */
 420         WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 421                      lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
 422                                    AMDGPU_VCN_STACK_SIZE));
 423         WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 424                      upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
 425                                    AMDGPU_VCN_STACK_SIZE));
 426         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0);
 427         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2,
 428                      AMDGPU_VCN_CONTEXT_SIZE);
 429
 430         /* non-cache window */
 431         WREG32_SOC15(
 432                 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
 433                 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
 434         WREG32_SOC15(
 435                 VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
 436                 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
 437         WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
 438         WREG32_SOC15(
 439                 VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0,
 440                 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
 441 }
 442
 443 /**
 444  * vcn_v4_0_3_mc_resume_dpg_mode - memory controller programming for dpg mode
 445  *
 446  * @adev: amdgpu_device pointer
 447  * @inst_idx: instance number index
 448  * @indirect: indirectly write sram
 449  *
 450  * Let the VCN memory controller know it's offsets with dpg mode
 451  */
 452 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 453 {
 454         uint32_t offset, size;
 455         const struct common_firmware_header *hdr;
 456
 457         hdr = (const struct common_firmware_header *)adev->vcn.fw[inst_idx]->data;
 458         size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
 459
 460         /* cache window 0: fw */
 461         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 462                 if (!indirect) {
 463                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 464                                 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 465                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
 466                                         inst_idx].tmr_mc_addr_lo), 0, indirect);
 467                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 468                                 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 469                                 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
 470                                         inst_idx].tmr_mc_addr_hi), 0, indirect);
 471                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 472                                 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 473                 } else {
 474                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 475                                 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
 476                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 477                                 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
 478                         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 479                                 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
 480                 }
 481                 offset = 0;
 482         } else {
 483                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 484                         VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 485                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 486                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 487                         VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 488                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
 489                 offset = size;
 490                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 491                         VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
 492                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
 493         }
 494
 495         if (!indirect)
 496                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 497                         VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
 498         else
 499                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 500                         VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
 501
 502         /* cache window 1: stack */
 503         if (!indirect) {
 504                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 505                         VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 506                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 507                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 508                         VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 509                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
 510                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 511                         VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 512         } else {
 513                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 514                         VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
 515                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 516                         VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
 517                 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 518                         VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
 519         }
 520         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 521                         VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
 522
 523         /* cache window 2: context */
 524         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 525                         VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 526                         lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
 527                                 AMDGPU_VCN_STACK_SIZE), 0, indirect);
 528         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 529                         VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 530                         upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
 531                                 AMDGPU_VCN_STACK_SIZE), 0, indirect);
 532         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 533                         VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
 534         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 535                         VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
 536
 537         /* non-cache window */
 538         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 539                         VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
 540                         lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 541         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 542                         VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
 543                         upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
 544         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 545                         VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
 546         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 547                         VCN, 0, regUVD_VCPU_NONCACHE_SIZE0),
 548                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
 549
 550         /* VCN global tiling registers */
 551         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 552                 VCN, 0, regUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 553         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 554                 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
 555 }
 556
 557 /**
 558  * vcn_v4_0_3_disable_clock_gating - disable VCN clock gating
 559  *
 560  * @adev: amdgpu_device pointer
 561  * @inst_idx: instance number
 562  *
 563  * Disable clock gating for VCN block
 564  */
 565 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx)
 566 {
 567         uint32_t data;
 568         int vcn_inst;
 569
 570         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 571                 return;
 572
 573         vcn_inst = GET_INST(VCN, inst_idx);
 574
 575         /* VCN disable CGC */
 576         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
 577         data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 578         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 579         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 580         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
 581
 582         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE);
 583         data &= ~(UVD_CGC_GATE__SYS_MASK
 584                 | UVD_CGC_GATE__MPEG2_MASK
 585                 | UVD_CGC_GATE__REGS_MASK
 586                 | UVD_CGC_GATE__RBC_MASK
 587                 | UVD_CGC_GATE__LMI_MC_MASK
 588                 | UVD_CGC_GATE__LMI_UMC_MASK
 589                 | UVD_CGC_GATE__MPC_MASK
 590                 | UVD_CGC_GATE__LBSI_MASK
 591                 | UVD_CGC_GATE__LRBBM_MASK
 592                 | UVD_CGC_GATE__WCB_MASK
 593                 | UVD_CGC_GATE__VCPU_MASK
 594                 | UVD_CGC_GATE__MMSCH_MASK);
 595
 596         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_GATE, data);
 597         SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
 598
 599         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
 600         data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK
 601                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 602                 | UVD_CGC_CTRL__REGS_MODE_MASK
 603                 | UVD_CGC_CTRL__RBC_MODE_MASK
 604                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 605                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 606                 | UVD_CGC_CTRL__MPC_MODE_MASK
 607                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 608                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 609                 | UVD_CGC_CTRL__WCB_MODE_MASK
 610                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 611                 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
 612         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
 613
 614         data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE);
 615         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 616                 | UVD_SUVD_CGC_GATE__SIT_MASK
 617                 | UVD_SUVD_CGC_GATE__SMP_MASK
 618                 | UVD_SUVD_CGC_GATE__SCM_MASK
 619                 | UVD_SUVD_CGC_GATE__SDB_MASK
 620                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 621                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 622                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 623                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 624                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 625                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 626                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 627                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 628                 | UVD_SUVD_CGC_GATE__ENT_MASK
 629                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 630                 | UVD_SUVD_CGC_GATE__SITE_MASK
 631                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 632                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 633                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 634                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 635                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 636         WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_GATE, data);
 637
 638         data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);
 639         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 640                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 641                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 642                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 643                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 644                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 645                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 646                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 647         WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data);
 648 }
 649
 650 /**
 651  * vcn_v4_0_3_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
 652  *
 653  * @adev: amdgpu_device pointer
 654  * @sram_sel: sram select
 655  * @inst_idx: instance number index
 656  * @indirect: indirectly write sram
 657  *
 658  * Disable clock gating for VCN block with dpg mode
 659  */
 660 static void vcn_v4_0_3_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
 661                                 int inst_idx, uint8_t indirect)
 662 {
 663         uint32_t reg_data = 0;
 664
 665         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 666                 return;
 667
 668         /* enable sw clock gating control */
 669         reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 670         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 671         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 672         reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK |
 673                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 674                  UVD_CGC_CTRL__REGS_MODE_MASK |
 675                  UVD_CGC_CTRL__RBC_MODE_MASK |
 676                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 677                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 678                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 679                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 680                  UVD_CGC_CTRL__MPC_MODE_MASK |
 681                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 682                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 683                  UVD_CGC_CTRL__WCB_MODE_MASK |
 684                  UVD_CGC_CTRL__VCPU_MODE_MASK);
 685         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 686                 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
 687
 688         /* turn off clock gating */
 689         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 690                 VCN, 0, regUVD_CGC_GATE), 0, sram_sel, indirect);
 691
 692         /* turn on SUVD clock gating */
 693         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 694                 VCN, 0, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
 695
 696         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 697         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 698                 VCN, 0, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
 699 }
 700
 701 /**
 702  * vcn_v4_0_3_enable_clock_gating - enable VCN clock gating
 703  *
 704  * @adev: amdgpu_device pointer
 705  * @inst_idx: instance number
 706  *
 707  * Enable clock gating for VCN block
 708  */
 709 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx)
 710 {
 711         uint32_t data;
 712         int vcn_inst;
 713
 714         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 715                 return;
 716
 717         vcn_inst = GET_INST(VCN, inst_idx);
 718
 719         /* enable VCN CGC */
 720         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
 721         data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 722         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 723         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 724         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
 725
 726         data = RREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL);
 727         data |= (UVD_CGC_CTRL__SYS_MODE_MASK
 728                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 729                 | UVD_CGC_CTRL__REGS_MODE_MASK
 730                 | UVD_CGC_CTRL__RBC_MODE_MASK
 731                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 732                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 733                 | UVD_CGC_CTRL__MPC_MODE_MASK
 734                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 735                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 736                 | UVD_CGC_CTRL__WCB_MODE_MASK
 737                 | UVD_CGC_CTRL__VCPU_MODE_MASK);
 738         WREG32_SOC15(VCN, vcn_inst, regUVD_CGC_CTRL, data);
 739
 740         data = RREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL);
 741         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 742                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 743                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 744                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 745                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 746                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 747                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 748                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 749         WREG32_SOC15(VCN, vcn_inst, regUVD_SUVD_CGC_CTRL, data);
 750 }
 751
 752 /**
 753  * vcn_v4_0_3_start_dpg_mode - VCN start with dpg mode
 754  *
 755  * @adev: amdgpu_device pointer
 756  * @inst_idx: instance number index
 757  * @indirect: indirectly write sram
 758  *
 759  * Start VCN block with dpg mode
 760  */
 761 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
 762 {
 763         volatile struct amdgpu_vcn4_fw_shared *fw_shared =
 764                                                 adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
 765         struct amdgpu_ring *ring;
 766         int vcn_inst;
 767         uint32_t tmp;
 768
 769         vcn_inst = GET_INST(VCN, inst_idx);
 770         /* disable register anti-hang mechanism */
 771         WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1,
 772                  ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
 773         /* enable dynamic power gating mode */
 774         tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS);
 775         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 776         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 777         WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp);
 778
 779         if (indirect) {
 780                 DRM_DEV_DEBUG(adev->dev, "VCN %d start: on AID %d",
 781                         inst_idx, adev->vcn.inst[inst_idx].aid_id);
 782                 adev->vcn.inst[inst_idx].dpg_sram_curr_addr =
 783                                 (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
 784                 /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */
 785                 WREG32_SOC15_DPG_MODE(inst_idx, 0xDEADBEEF,
 786                         adev->vcn.inst[inst_idx].aid_id, 0, true);
 787         }
 788
 789         /* enable clock gating */
 790         vcn_v4_0_3_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
 791
 792         /* enable VCPU clock */
 793         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 794         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 795         tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
 796
 797         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 798                 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
 799
 800         /* disable master interrupt */
 801         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 802                 VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect);
 803
 804         /* setup regUVD_LMI_CTRL */
 805         tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 806                 UVD_LMI_CTRL__REQ_MODE_MASK |
 807                 UVD_LMI_CTRL__CRC_RESET_MASK |
 808                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 809                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 810                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 811                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 812                 0x00100000L);
 813         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 814                 VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect);
 815
 816         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 817                 VCN, 0, regUVD_MPC_CNTL),
 818                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
 819
 820         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 821                 VCN, 0, regUVD_MPC_SET_MUXA0),
 822                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 823                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 824                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 825                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
 826
 827         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 828                 VCN, 0, regUVD_MPC_SET_MUXB0),
 829                  ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 830                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 831                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 832                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
 833
 834         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 835                 VCN, 0, regUVD_MPC_SET_MUX),
 836                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 837                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 838                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
 839
 840         vcn_v4_0_3_mc_resume_dpg_mode(adev, inst_idx, indirect);
 841
 842         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 843         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 844         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 845                 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect);
 846
 847         /* enable LMI MC and UMC channels */
 848         tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
 849         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 850                 VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect);
 851
 852         vcn_v4_0_3_enable_ras(adev, inst_idx, indirect);
 853
 854         /* enable master interrupt */
 855         WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
 856                 VCN, 0, regUVD_MASTINT_EN),
 857                 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
 858
 859         if (indirect)
 860                 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM);
 861
 862         ring = &adev->vcn.inst[inst_idx].ring_enc[0];
 863
 864         /* program the RB_BASE for ring buffer */
 865         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
 866                      lower_32_bits(ring->gpu_addr));
 867         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
 868                      upper_32_bits(ring->gpu_addr));
 869
 870         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
 871                      ring->ring_size / sizeof(uint32_t));
 872
 873         /* resetting ring, fw should not check RB ring */
 874         tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
 875         tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
 876         WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
 877         fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
 878
 879         /* Initialize the ring buffer's read and write pointers */
 880         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
 881         WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
 882         ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
 883
 884         tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
 885         tmp |= VCN_RB_ENABLE__RB_EN_MASK;
 886         WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
 887         fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
 888
 889         /*resetting done, fw can check RB ring */
 890         fw_shared->sq.queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
 891
 892         return 0;
 893 }
 894
 895 static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
 896 {
 897         int i, vcn_inst;
 898         struct amdgpu_ring *ring_enc;
 899         uint64_t cache_addr;
 900         uint64_t rb_enc_addr;
 901         uint64_t ctx_addr;
 902         uint32_t param, resp, expected;
 903         uint32_t offset, cache_size;
 904         uint32_t tmp, timeout;
 905
 906         struct amdgpu_mm_table *table = &adev->virt.mm_table;
 907         uint32_t *table_loc;
 908         uint32_t table_size;
 909         uint32_t size, size_dw;
 910         uint32_t init_status;
 911         uint32_t enabled_vcn;
 912
 913         struct mmsch_v4_0_cmd_direct_write
 914                 direct_wt = { {0} };
 915         struct mmsch_v4_0_cmd_direct_read_modify_write
 916                 direct_rd_mod_wt = { {0} };
 917         struct mmsch_v4_0_cmd_end end = { {0} };
 918         struct mmsch_v4_0_3_init_header header;
 919
 920         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
 921         volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
 922
 923         direct_wt.cmd_header.command_type =
 924                 MMSCH_COMMAND__DIRECT_REG_WRITE;
 925         direct_rd_mod_wt.cmd_header.command_type =
 926                 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 927         end.cmd_header.command_type = MMSCH_COMMAND__END;
 928
 929         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
 930                 vcn_inst = GET_INST(VCN, i);
 931
 932                 memset(&header, 0, sizeof(struct mmsch_v4_0_3_init_header));
 933                 header.version = MMSCH_VERSION;
 934                 header.total_size = sizeof(struct mmsch_v4_0_3_init_header) >> 2;
 935
 936                 table_loc = (uint32_t *)table->cpu_addr;
 937                 table_loc += header.total_size;
 938
 939                 table_size = 0;
 940
 941                 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, 0, regUVD_STATUS),
 942                         ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
 943
 944                 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw[i]->size + 4);
 945
 946                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 947                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 948                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 949                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
 950
 951                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 952                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 953                                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
 954
 955                         offset = 0;
 956                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 957                                 regUVD_VCPU_CACHE_OFFSET0), 0);
 958                 } else {
 959                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 960                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 961                                 lower_32_bits(adev->vcn.inst[i].gpu_addr));
 962                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 963                                 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 964                                 upper_32_bits(adev->vcn.inst[i].gpu_addr));
 965                         offset = cache_size;
 966                         MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 967                                 regUVD_VCPU_CACHE_OFFSET0),
 968                                 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 969                 }
 970
 971                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 972                         regUVD_VCPU_CACHE_SIZE0),
 973                         cache_size);
 974
 975                 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset;
 976                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 977                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr));
 978                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 979                         regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
 980                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 981                         regUVD_VCPU_CACHE_OFFSET1), 0);
 982                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 983                         regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE);
 984
 985                 cache_addr = adev->vcn.inst[vcn_inst].gpu_addr + offset +
 986                         AMDGPU_VCN_STACK_SIZE;
 987
 988                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 989                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(cache_addr));
 990
 991                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 992                         regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(cache_addr));
 993
 994                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 995                         regUVD_VCPU_CACHE_OFFSET2), 0);
 996
 997                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
 998                         regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE);
 999
1000                 fw_shared = adev->vcn.inst[vcn_inst].fw_shared.cpu_addr;
1001                 rb_setup = &fw_shared->rb_setup;
1002
1003                 ring_enc = &adev->vcn.inst[vcn_inst].ring_enc[0];
1004                 ring_enc->wptr = 0;
1005                 rb_enc_addr = ring_enc->gpu_addr;
1006
1007                 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
1008                 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
1009                 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
1010                 rb_setup->rb_size = ring_enc->ring_size / 4;
1011                 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1012
1013                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1014                         regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
1015                         lower_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
1016                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1017                         regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
1018                         upper_32_bits(adev->vcn.inst[vcn_inst].fw_shared.gpu_addr));
1019                 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, 0,
1020                         regUVD_VCPU_NONCACHE_SIZE0),
1021                         AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
1022                 MMSCH_V4_0_INSERT_END();
1023
1024                 header.vcn0.init_status = 0;
1025                 header.vcn0.table_offset = header.total_size;
1026                 header.vcn0.table_size = table_size;
1027                 header.total_size += table_size;
1028
1029                 /* Send init table to mmsch */
1030                 size = sizeof(struct mmsch_v4_0_3_init_header);
1031                 table_loc = (uint32_t *)table->cpu_addr;
1032                 memcpy((void *)table_loc, &header, size);
1033
1034                 ctx_addr = table->gpu_addr;
1035                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1036                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1037
1038                 tmp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID);
1039                 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1040                 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1041                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_VMID, tmp);
1042
1043                 size = header.total_size;
1044                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_CTX_SIZE, size);
1045
1046                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0);
1047
1048                 param = 0x00000001;
1049                 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_HOST, param);
1050                 tmp = 0;
1051                 timeout = 1000;
1052                 resp = 0;
1053                 expected = MMSCH_VF_MAILBOX_RESP__OK;
1054                 while (resp != expected) {
1055                         resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP);
1056                         if (resp != 0)
1057                                 break;
1058
1059                         udelay(10);
1060                         tmp = tmp + 10;
1061                         if (tmp >= timeout) {
1062                                 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1063                                         " waiting for regMMSCH_VF_MAILBOX_RESP "\
1064                                         "(expected=0x%08x, readback=0x%08x)\n",
1065                                         tmp, expected, resp);
1066                                 return -EBUSY;
1067                         }
1068                 }
1069
1070                 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1071                 init_status = ((struct mmsch_v4_0_3_init_header *)(table_loc))->vcn0.init_status;
1072                 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1073                                         && init_status != MMSCH_VF_ENGINE_STATUS__PASS) {
1074                         DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1075                                 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1076                 }
1077         }
1078
1079         return 0;
1080 }
1081
1082 /**
1083  * vcn_v4_0_3_start - VCN start
1084  *
1085  * @adev: amdgpu_device pointer
1086  *
1087  * Start VCN block
1088  */
1089 static int vcn_v4_0_3_start(struct amdgpu_device *adev)
1090 {
1091         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1092         struct amdgpu_ring *ring;
1093         int i, j, k, r, vcn_inst;
1094         uint32_t tmp;
1095
1096         if (adev->pm.dpm_enabled)
1097                 amdgpu_dpm_enable_uvd(adev, true);
1098
1099         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1100                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1101                         r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1102                         continue;
1103                 }
1104
1105                 vcn_inst = GET_INST(VCN, i);
1106                 /* set VCN status busy */
1107                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
1108                       UVD_STATUS__UVD_BUSY;
1109                 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
1110
1111                 /*SW clock gating */
1112                 vcn_v4_0_3_disable_clock_gating(adev, i);
1113
1114                 /* enable VCPU clock */
1115                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
1116                          UVD_VCPU_CNTL__CLK_EN_MASK,
1117                          ~UVD_VCPU_CNTL__CLK_EN_MASK);
1118
1119                 /* disable master interrupt */
1120                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
1121                          ~UVD_MASTINT_EN__VCPU_EN_MASK);
1122
1123                 /* enable LMI MC and UMC channels */
1124                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
1125                          ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1126
1127                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1128                 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1129                 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1130                 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1131
1132                 /* setup regUVD_LMI_CTRL */
1133                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
1134                 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
1135                              tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1136                                      UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1137                                      UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1138                                      UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1139
1140                 /* setup regUVD_MPC_CNTL */
1141                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
1142                 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1143                 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1144                 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
1145
1146                 /* setup UVD_MPC_SET_MUXA0 */
1147                 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
1148                              ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1149                               (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1150                               (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1151                               (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1152
1153                 /* setup UVD_MPC_SET_MUXB0 */
1154                 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
1155                              ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1156                               (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1157                               (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1158                               (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1159
1160                 /* setup UVD_MPC_SET_MUX */
1161                 WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
1162                              ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1163                               (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1164                               (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1165
1166                 vcn_v4_0_3_mc_resume(adev, i);
1167
1168                 /* VCN global tiling registers */
1169                 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
1170                              adev->gfx.config.gb_addr_config);
1171                 WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
1172                              adev->gfx.config.gb_addr_config);
1173
1174                 /* unblock VCPU register access */
1175                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
1176                          ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1177
1178                 /* release VCPU reset to boot */
1179                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
1180                          ~UVD_VCPU_CNTL__BLK_RST_MASK);
1181
1182                 for (j = 0; j < 10; ++j) {
1183                         uint32_t status;
1184
1185                         for (k = 0; k < 100; ++k) {
1186                                 status = RREG32_SOC15(VCN, vcn_inst,
1187                                                       regUVD_STATUS);
1188                                 if (status & 2)
1189                                         break;
1190                                 mdelay(10);
1191                         }
1192                         r = 0;
1193                         if (status & 2)
1194                                 break;
1195
1196                         DRM_DEV_ERROR(adev->dev,
1197                                 "VCN decode not responding, trying to reset the VCPU!!!\n");
1198                         WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
1199                                                   regUVD_VCPU_CNTL),
1200                                  UVD_VCPU_CNTL__BLK_RST_MASK,
1201                                  ~UVD_VCPU_CNTL__BLK_RST_MASK);
1202                         mdelay(10);
1203                         WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
1204                                                   regUVD_VCPU_CNTL),
1205                                  0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
1206
1207                         mdelay(10);
1208                         r = -1;
1209                 }
1210
1211                 if (r) {
1212                         DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
1213                         return r;
1214                 }
1215
1216                 /* enable master interrupt */
1217                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
1218                          UVD_MASTINT_EN__VCPU_EN_MASK,
1219                          ~UVD_MASTINT_EN__VCPU_EN_MASK);
1220
1221                 /* clear the busy bit of VCN_STATUS */
1222                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
1223                          ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1224
1225                 ring = &adev->vcn.inst[i].ring_enc[0];
1226                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1227
1228                 /* program the RB_BASE for ring buffer */
1229                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
1230                              lower_32_bits(ring->gpu_addr));
1231                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
1232                              upper_32_bits(ring->gpu_addr));
1233
1234                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
1235                              ring->ring_size / sizeof(uint32_t));
1236
1237                 /* resetting ring, fw should not check RB ring */
1238                 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
1239                 tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
1240                 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
1241
1242                 /* Initialize the ring buffer's read and write pointers */
1243                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
1244                 WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
1245
1246                 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
1247                 tmp |= VCN_RB_ENABLE__RB_EN_MASK;
1248                 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
1249
1250                 ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
1251                 fw_shared->sq.queue_mode &=
1252                         cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
1253
1254         }
1255         return 0;
1256 }
1257
1258 /**
1259  * vcn_v4_0_3_stop_dpg_mode - VCN stop with dpg mode
1260  *
1261  * @adev: amdgpu_device pointer
1262  * @inst_idx: instance number index
1263  *
1264  * Stop VCN block with dpg mode
1265  */
1266 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1267 {
1268         uint32_t tmp;
1269         int vcn_inst;
1270
1271         vcn_inst = GET_INST(VCN, inst_idx);
1272
1273         /* Wait for power status to be 1 */
1274         SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,
1275                            UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1276
1277         /* wait for read ptr to be equal to write ptr */
1278         tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
1279         SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1280
1281         SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,
1282                            UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1283
1284         /* disable dynamic power gating mode */
1285         WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0,
1286                  ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1287         return 0;
1288 }
1289
1290 /**
1291  * vcn_v4_0_3_stop - VCN stop
1292  *
1293  * @adev: amdgpu_device pointer
1294  *
1295  * Stop VCN block
1296  */
1297 static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
1298 {
1299         volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1300         int i, r = 0, vcn_inst;
1301         uint32_t tmp;
1302
1303         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1304                 vcn_inst = GET_INST(VCN, i);
1305
1306                 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1307                 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1308
1309                 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1310                         vcn_v4_0_3_stop_dpg_mode(adev, i);
1311                         continue;
1312                 }
1313
1314                 /* wait for vcn idle */
1315                 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
1316                                        UVD_STATUS__IDLE, 0x7);
1317                 if (r)
1318                         goto Done;
1319
1320                 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1321                         UVD_LMI_STATUS__READ_CLEAN_MASK |
1322                         UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1323                         UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1324                 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
1325                                        tmp);
1326                 if (r)
1327                         goto Done;
1328
1329                 /* stall UMC channel */
1330                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
1331                 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1332                 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
1333                 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1334                         UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1335                 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
1336                                        tmp);
1337                 if (r)
1338                         goto Done;
1339
1340                 /* Unblock VCPU Register access */
1341                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
1342                          UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1343                          ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1344
1345                 /* release VCPU reset to boot */
1346                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
1347                          UVD_VCPU_CNTL__BLK_RST_MASK,
1348                          ~UVD_VCPU_CNTL__BLK_RST_MASK);
1349
1350                 /* disable VCPU clock */
1351                 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
1352                          ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1353
1354                 /* reset LMI UMC/LMI/VCPU */
1355                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1356                 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1357                 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1358
1359                 tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
1360                 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1361                 WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
1362
1363                 /* clear VCN status */
1364                 WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
1365
1366                 /* apply HW clock gating */
1367                 vcn_v4_0_3_enable_clock_gating(adev, i);
1368         }
1369 Done:
1370         if (adev->pm.dpm_enabled)
1371                 amdgpu_dpm_enable_uvd(adev, false);
1372
1373         return 0;
1374 }
1375
1376 /**
1377  * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode
1378  *
1379  * @adev: amdgpu_device pointer
1380  * @inst_idx: instance number index
1381  * @new_state: pause state
1382  *
1383  * Pause dpg mode for VCN block
1384  */
1385 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1386                                 struct dpg_pause_state *new_state)
1387 {
1388
1389         return 0;
1390 }
1391
1392 /**
1393  * vcn_v4_0_3_unified_ring_get_rptr - get unified read pointer
1394  *
1395  * @ring: amdgpu_ring pointer
1396  *
1397  * Returns the current hardware unified read pointer
1398  */
1399 static uint64_t vcn_v4_0_3_unified_ring_get_rptr(struct amdgpu_ring *ring)
1400 {
1401         struct amdgpu_device *adev = ring->adev;
1402
1403         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1404                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1405
1406         return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR);
1407 }
1408
1409 /**
1410  * vcn_v4_0_3_unified_ring_get_wptr - get unified write pointer
1411  *
1412  * @ring: amdgpu_ring pointer
1413  *
1414  * Returns the current hardware unified write pointer
1415  */
1416 static uint64_t vcn_v4_0_3_unified_ring_get_wptr(struct amdgpu_ring *ring)
1417 {
1418         struct amdgpu_device *adev = ring->adev;
1419
1420         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1421                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1422
1423         if (ring->use_doorbell)
1424                 return *ring->wptr_cpu_addr;
1425         else
1426                 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me),
1427                                     regUVD_RB_WPTR);
1428 }
1429
1430 static void vcn_v4_0_3_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1431                                 uint32_t val, uint32_t mask)
1432 {
1433         /* For VF, only local offsets should be used */
1434         if (amdgpu_sriov_vf(ring->adev))
1435                 reg = NORMALIZE_VCN_REG_OFFSET(reg);
1436
1437         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1438         amdgpu_ring_write(ring, reg << 2);
1439         amdgpu_ring_write(ring, mask);
1440         amdgpu_ring_write(ring, val);
1441 }
1442
1443 static void vcn_v4_0_3_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
1444 {
1445         /* For VF, only local offsets should be used */
1446         if (amdgpu_sriov_vf(ring->adev))
1447                 reg = NORMALIZE_VCN_REG_OFFSET(reg);
1448
1449         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1450         amdgpu_ring_write(ring, reg << 2);
1451         amdgpu_ring_write(ring, val);
1452 }
1453
1454 static void vcn_v4_0_3_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1455                                 unsigned int vmid, uint64_t pd_addr)
1456 {
1457         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1458
1459         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1460
1461         /* wait for reg writes */
1462         vcn_v4_0_3_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1463                                         vmid * hub->ctx_addr_distance,
1464                                         lower_32_bits(pd_addr), 0xffffffff);
1465 }
1466
1467 static void vcn_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1468 {
1469         /* VCN engine access for HDP flush doesn't work when RRMT is enabled.
1470          * This is a workaround to avoid any HDP flush through VCN ring.
1471          */
1472 }
1473
1474 /**
1475  * vcn_v4_0_3_unified_ring_set_wptr - set enc write pointer
1476  *
1477  * @ring: amdgpu_ring pointer
1478  *
1479  * Commits the enc write pointer to the hardware
1480  */
1481 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring)
1482 {
1483         struct amdgpu_device *adev = ring->adev;
1484
1485         if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1486                 DRM_ERROR("wrong ring id is identified in %s", __func__);
1487
1488         if (ring->use_doorbell) {
1489                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1490                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1491         } else {
1492                 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR,
1493                              lower_32_bits(ring->wptr));
1494         }
1495 }
1496
1497 static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = {
1498         .type = AMDGPU_RING_TYPE_VCN_ENC,
1499         .align_mask = 0x3f,
1500         .nop = VCN_ENC_CMD_NO_OP,
1501         .get_rptr = vcn_v4_0_3_unified_ring_get_rptr,
1502         .get_wptr = vcn_v4_0_3_unified_ring_get_wptr,
1503         .set_wptr = vcn_v4_0_3_unified_ring_set_wptr,
1504         .emit_frame_size =
1505                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1506                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1507                 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1508                 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1509                 1, /* vcn_v2_0_enc_ring_insert_end */
1510         .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1511         .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1512         .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1513         .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush,
1514         .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush,
1515         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1516         .test_ib = amdgpu_vcn_unified_ring_test_ib,
1517         .insert_nop = amdgpu_ring_insert_nop,
1518         .insert_end = vcn_v2_0_enc_ring_insert_end,
1519         .pad_ib = amdgpu_ring_generic_pad_ib,
1520         .begin_use = amdgpu_vcn_ring_begin_use,
1521         .end_use = amdgpu_vcn_ring_end_use,
1522         .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg,
1523         .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait,
1524         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1525 };
1526
1527 /**
1528  * vcn_v4_0_3_set_unified_ring_funcs - set unified ring functions
1529  *
1530  * @adev: amdgpu_device pointer
1531  *
1532  * Set unified ring functions
1533  */
1534 static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
1535 {
1536         int i, vcn_inst;
1537
1538         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1539                 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_3_unified_ring_vm_funcs;
1540                 adev->vcn.inst[i].ring_enc[0].me = i;
1541                 vcn_inst = GET_INST(VCN, i);
1542                 adev->vcn.inst[i].aid_id =
1543                         vcn_inst / adev->vcn.num_inst_per_aid;
1544         }
1545 }
1546
1547 /**
1548  * vcn_v4_0_3_is_idle - check VCN block is idle
1549  *
1550  * @handle: amdgpu_device pointer
1551  *
1552  * Check whether VCN block is idle
1553  */
1554 static bool vcn_v4_0_3_is_idle(void *handle)
1555 {
1556         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1557         int i, ret = 1;
1558
1559         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1560                 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==
1561                         UVD_STATUS__IDLE);
1562         }
1563
1564         return ret;
1565 }
1566
1567 /**
1568  * vcn_v4_0_3_wait_for_idle - wait for VCN block idle
1569  *
1570  * @handle: amdgpu_device pointer
1571  *
1572  * Wait for VCN block idle
1573  */
1574 static int vcn_v4_0_3_wait_for_idle(void *handle)
1575 {
1576         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1577         int i, ret = 0;
1578
1579         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1580                 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,
1581                                          UVD_STATUS__IDLE, UVD_STATUS__IDLE);
1582                 if (ret)
1583                         return ret;
1584         }
1585
1586         return ret;
1587 }
1588
1589 /* vcn_v4_0_3_set_clockgating_state - set VCN block clockgating state
1590  *
1591  * @handle: amdgpu_device pointer
1592  * @state: clock gating state
1593  *
1594  * Set VCN block clockgating state
1595  */
1596 static int vcn_v4_0_3_set_clockgating_state(void *handle,
1597                                           enum amd_clockgating_state state)
1598 {
1599         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1600         bool enable = state == AMD_CG_STATE_GATE;
1601         int i;
1602
1603         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1604                 if (enable) {
1605                         if (RREG32_SOC15(VCN, GET_INST(VCN, i),
1606                                          regUVD_STATUS) != UVD_STATUS__IDLE)
1607                                 return -EBUSY;
1608                         vcn_v4_0_3_enable_clock_gating(adev, i);
1609                 } else {
1610                         vcn_v4_0_3_disable_clock_gating(adev, i);
1611                 }
1612         }
1613         return 0;
1614 }
1615
1616 /**
1617  * vcn_v4_0_3_set_powergating_state - set VCN block powergating state
1618  *
1619  * @handle: amdgpu_device pointer
1620  * @state: power gating state
1621  *
1622  * Set VCN block powergating state
1623  */
1624 static int vcn_v4_0_3_set_powergating_state(void *handle,
1625                                           enum amd_powergating_state state)
1626 {
1627         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1628         int ret;
1629
1630         /* for SRIOV, guest should not control VCN Power-gating
1631          * MMSCH FW should control Power-gating and clock-gating
1632          * guest should avoid touching CGC and PG
1633          */
1634         if (amdgpu_sriov_vf(adev)) {
1635                 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1636                 return 0;
1637         }
1638
1639         if (state == adev->vcn.cur_state)
1640                 return 0;
1641
1642         if (state == AMD_PG_STATE_GATE)
1643                 ret = vcn_v4_0_3_stop(adev);
1644         else
1645                 ret = vcn_v4_0_3_start(adev);
1646
1647         if (!ret)
1648                 adev->vcn.cur_state = state;
1649
1650         return ret;
1651 }
1652
1653 /**
1654  * vcn_v4_0_3_set_interrupt_state - set VCN block interrupt state
1655  *
1656  * @adev: amdgpu_device pointer
1657  * @source: interrupt sources
1658  * @type: interrupt types
1659  * @state: interrupt states
1660  *
1661  * Set VCN block interrupt state
1662  */
1663 static int vcn_v4_0_3_set_interrupt_state(struct amdgpu_device *adev,
1664                                         struct amdgpu_irq_src *source,
1665                                         unsigned int type,
1666                                         enum amdgpu_interrupt_state state)
1667 {
1668         return 0;
1669 }
1670
1671 /**
1672  * vcn_v4_0_3_process_interrupt - process VCN block interrupt
1673  *
1674  * @adev: amdgpu_device pointer
1675  * @source: interrupt sources
1676  * @entry: interrupt entry from clients and sources
1677  *
1678  * Process VCN block interrupt
1679  */
1680 static int vcn_v4_0_3_process_interrupt(struct amdgpu_device *adev,
1681                                       struct amdgpu_irq_src *source,
1682                                       struct amdgpu_iv_entry *entry)
1683 {
1684         uint32_t i, inst;
1685
1686         i = node_id_to_phys_map[entry->node_id];
1687
1688         DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n");
1689
1690         for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst)
1691                 if (adev->vcn.inst[inst].aid_id == i)
1692                         break;
1693
1694         if (inst >= adev->vcn.num_vcn_inst) {
1695                 dev_WARN_ONCE(adev->dev, 1,
1696                               "Interrupt received for unknown VCN instance %d",
1697                               entry->node_id);
1698                 return 0;
1699         }
1700
1701         switch (entry->src_id) {
1702         case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
1703                 amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]);
1704                 break;
1705         default:
1706                 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
1707                           entry->src_id, entry->src_data[0]);
1708                 break;
1709         }
1710
1711         return 0;
1712 }
1713
1714 static const struct amdgpu_irq_src_funcs vcn_v4_0_3_irq_funcs = {
1715         .set = vcn_v4_0_3_set_interrupt_state,
1716         .process = vcn_v4_0_3_process_interrupt,
1717 };
1718
1719 /**
1720  * vcn_v4_0_3_set_irq_funcs - set VCN block interrupt irq functions
1721  *
1722  * @adev: amdgpu_device pointer
1723  *
1724  * Set VCN block interrupt irq functions
1725  */
1726 static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
1727 {
1728         int i;
1729
1730         for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1731                 adev->vcn.inst->irq.num_types++;
1732         }
1733         adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
1734 }
1735
1736 static void vcn_v4_0_3_print_ip_state(void *handle, struct drm_printer *p)
1737 {
1738         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1739         int i, j;
1740         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
1741         uint32_t inst_off, is_powered;
1742
1743         if (!adev->vcn.ip_dump)
1744                 return;
1745
1746         drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
1747         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1748                 if (adev->vcn.harvest_config & (1 << i)) {
1749                         drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
1750                         continue;
1751                 }
1752
1753                 inst_off = i * reg_count;
1754                 is_powered = (adev->vcn.ip_dump[inst_off] &
1755                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1756
1757                 if (is_powered) {
1758                         drm_printf(p, "\nActive Instance:VCN%d\n", i);
1759                         for (j = 0; j < reg_count; j++)
1760                                 drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
1761                                            adev->vcn.ip_dump[inst_off + j]);
1762                 } else {
1763                         drm_printf(p, "\nInactive Instance:VCN%d\n", i);
1764                 }
1765         }
1766 }
1767
1768 static void vcn_v4_0_3_dump_ip_state(void *handle)
1769 {
1770         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1771         int i, j;
1772         bool is_powered;
1773         uint32_t inst_off, inst_id;
1774         uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
1775
1776         if (!adev->vcn.ip_dump)
1777                 return;
1778
1779         for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1780                 if (adev->vcn.harvest_config & (1 << i))
1781                         continue;
1782
1783                 inst_id = GET_INST(VCN, i);
1784                 inst_off = i * reg_count;
1785                 /* mmUVD_POWER_STATUS is always readable and is first element of the array */
1786                 adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS);
1787                 is_powered = (adev->vcn.ip_dump[inst_off] &
1788                                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
1789
1790                 if (is_powered)
1791                         for (j = 1; j < reg_count; j++)
1792                                 adev->vcn.ip_dump[inst_off + j] =
1793                                         RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j],
1794                                                                            inst_id));
1795         }
1796 }
1797
1798 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
1799         .name = "vcn_v4_0_3",
1800         .early_init = vcn_v4_0_3_early_init,
1801         .late_init = NULL,
1802         .sw_init = vcn_v4_0_3_sw_init,
1803         .sw_fini = vcn_v4_0_3_sw_fini,
1804         .hw_init = vcn_v4_0_3_hw_init,
1805         .hw_fini = vcn_v4_0_3_hw_fini,
1806         .suspend = vcn_v4_0_3_suspend,
1807         .resume = vcn_v4_0_3_resume,
1808         .is_idle = vcn_v4_0_3_is_idle,
1809         .wait_for_idle = vcn_v4_0_3_wait_for_idle,
1810         .check_soft_reset = NULL,
1811         .pre_soft_reset = NULL,
1812         .soft_reset = NULL,
1813         .post_soft_reset = NULL,
1814         .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
1815         .set_powergating_state = vcn_v4_0_3_set_powergating_state,
1816         .dump_ip_state = vcn_v4_0_3_dump_ip_state,
1817         .print_ip_state = vcn_v4_0_3_print_ip_state,
1818 };
1819
1820 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
1821         .type = AMD_IP_BLOCK_TYPE_VCN,
1822         .major = 4,
1823         .minor = 0,
1824         .rev = 3,
1825         .funcs = &vcn_v4_0_3_ip_funcs,
1826 };
1827
1828 static const struct amdgpu_ras_err_status_reg_entry vcn_v4_0_3_ue_reg_list[] = {
1829         {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDD, regVCN_UE_ERR_STATUS_HI_VIDD),
1830         1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDD"},
1831         {AMDGPU_RAS_REG_ENTRY(VCN, 0, regVCN_UE_ERR_STATUS_LO_VIDV, regVCN_UE_ERR_STATUS_HI_VIDV),
1832         1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "VIDV"},
1833 };
1834
1835 static void vcn_v4_0_3_inst_query_ras_error_count(struct amdgpu_device *adev,
1836                                                   uint32_t vcn_inst,
1837                                                   void *ras_err_status)
1838 {
1839         struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
1840
1841         /* vcn v4_0_3 only support query uncorrectable errors */
1842         amdgpu_ras_inst_query_ras_error_count(adev,
1843                         vcn_v4_0_3_ue_reg_list,
1844                         ARRAY_SIZE(vcn_v4_0_3_ue_reg_list),
1845                         NULL, 0, GET_INST(VCN, vcn_inst),
1846                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1847                         &err_data->ue_count);
1848 }
1849
1850 static void vcn_v4_0_3_query_ras_error_count(struct amdgpu_device *adev,
1851                                              void *ras_err_status)
1852 {
1853         uint32_t i;
1854
1855         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
1856                 dev_warn(adev->dev, "VCN RAS is not supported\n");
1857                 return;
1858         }
1859
1860         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1861                 vcn_v4_0_3_inst_query_ras_error_count(adev, i, ras_err_status);
1862 }
1863
1864 static void vcn_v4_0_3_inst_reset_ras_error_count(struct amdgpu_device *adev,
1865                                                   uint32_t vcn_inst)
1866 {
1867         amdgpu_ras_inst_reset_ras_error_count(adev,
1868                                         vcn_v4_0_3_ue_reg_list,
1869                                         ARRAY_SIZE(vcn_v4_0_3_ue_reg_list),
1870                                         GET_INST(VCN, vcn_inst));
1871 }
1872
1873 static void vcn_v4_0_3_reset_ras_error_count(struct amdgpu_device *adev)
1874 {
1875         uint32_t i;
1876
1877         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) {
1878                 dev_warn(adev->dev, "VCN RAS is not supported\n");
1879                 return;
1880         }
1881
1882         for (i = 0; i < adev->vcn.num_vcn_inst; i++)
1883                 vcn_v4_0_3_inst_reset_ras_error_count(adev, i);
1884 }
1885
1886 static const struct amdgpu_ras_block_hw_ops vcn_v4_0_3_ras_hw_ops = {
1887         .query_ras_error_count = vcn_v4_0_3_query_ras_error_count,
1888         .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count,
1889 };
1890
1891 static struct amdgpu_vcn_ras vcn_v4_0_3_ras = {
1892         .ras_block = {
1893                 .hw_ops = &vcn_v4_0_3_ras_hw_ops,
1894         },
1895 };
1896
1897 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev)
1898 {
1899         adev->vcn.ras = &vcn_v4_0_3_ras;
1900 }
1901
1902 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
1903                                   int inst_idx, bool indirect)
1904 {
1905         uint32_t tmp;
1906
1907         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
1908                 return;
1909
1910         tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
1911               VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
1912               VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
1913               VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
1914         WREG32_SOC15_DPG_MODE(inst_idx,
1915                               SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
1916                               tmp, 0, indirect);
1917
1918         tmp = UVD_VCPU_INT_EN2__RASCNTL_VCPU_VCODEC_EN_MASK;
1919         WREG32_SOC15_DPG_MODE(inst_idx,
1920                               SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_VCPU_INT_EN2),
1921                               tmp, 0, indirect);
1922
1923         tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
1924         WREG32_SOC15_DPG_MODE(inst_idx,
1925                               SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
1926                               tmp, 0, indirect);
1927 }