drivers/base/regmap/regmap-irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // regmap based irq_chip
   4 //
   5 // Copyright 2011 Wolfson Microelectronics plc
   6 //
   7 // Author: Mark Brown <[email protected]>
   8
   9 #include <linux/device.h>
  10 #include <linux/export.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/irqdomain.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17
  18 #include "internal.h"
  19
  20 struct regmap_irq_chip_data {
  21         struct mutex lock;
  22         struct irq_chip irq_chip;
  23
  24         struct regmap *map;
  25         const struct regmap_irq_chip *chip;
  26
  27         int irq_base;
  28         struct irq_domain *domain;
  29
  30         int irq;
  31         int wake_count;
  32
  33         void *status_reg_buf;
  34         unsigned int *main_status_buf;
  35         unsigned int *status_buf;
  36         unsigned int *mask_buf;
  37         unsigned int *mask_buf_def;
  38         unsigned int *wake_buf;
  39         unsigned int *type_buf;
  40         unsigned int *type_buf_def;
  41         unsigned int **config_buf;
  42
  43         unsigned int irq_reg_stride;
  44
  45         unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data,
  46                                     unsigned int base, int index);
  47
  48         unsigned int clear_status:1;
  49 };
  50
  51 static inline const
  52 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
  53                                      int irq)
  54 {
  55         return &data->chip->irqs[irq];
  56 }
  57
  58 static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data)
  59 {
  60         struct regmap *map = data->map;
  61
  62         /*
  63          * While possible that a user-defined ->get_irq_reg() callback might
  64          * be linear enough to support bulk reads, most of the time it won't.
  65          * Therefore only allow them if the default callback is being used.
  66          */
  67         return data->irq_reg_stride == 1 && map->reg_stride == 1 &&
  68                data->get_irq_reg == regmap_irq_get_irq_reg_linear &&
  69                !map->use_single_read;
  70 }
  71
  72 static void regmap_irq_lock(struct irq_data *data)
  73 {
  74         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  75
  76         mutex_lock(&d->lock);
  77 }
  78
  79 static void regmap_irq_sync_unlock(struct irq_data *data)
  80 {
  81         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  82         struct regmap *map = d->map;
  83         int i, j, ret;
  84         u32 reg;
  85         u32 val;
  86
  87         if (d->chip->runtime_pm) {
  88                 ret = pm_runtime_get_sync(map->dev);
  89                 if (ret < 0)
  90                         dev_err(map->dev, "IRQ sync failed to resume: %d\n",
  91                                 ret);
  92         }
  93
  94         if (d->clear_status) {
  95                 for (i = 0; i < d->chip->num_regs; i++) {
  96                         reg = d->get_irq_reg(d, d->chip->status_base, i);
  97
  98                         ret = regmap_read(map, reg, &val);
  99                         if (ret)
 100                                 dev_err(d->map->dev,
 101                                         "Failed to clear the interrupt status bits\n");
 102                 }
 103
 104                 d->clear_status = false;
 105         }
 106
 107         /*
 108          * If there's been a change in the mask write it back to the
 109          * hardware.  We rely on the use of the regmap core cache to
 110          * suppress pointless writes.
 111          */
 112         for (i = 0; i < d->chip->num_regs; i++) {
 113                 if (d->chip->handle_mask_sync)
 114                         d->chip->handle_mask_sync(i, d->mask_buf_def[i],
 115                                                   d->mask_buf[i],
 116                                                   d->chip->irq_drv_data);
 117
 118                 if (d->chip->mask_base && !d->chip->handle_mask_sync) {
 119                         reg = d->get_irq_reg(d, d->chip->mask_base, i);
 120                         ret = regmap_update_bits(d->map, reg,
 121                                                  d->mask_buf_def[i],
 122                                                  d->mask_buf[i]);
 123                         if (ret)
 124                                 dev_err(d->map->dev, "Failed to sync masks in %x\n", reg);
 125                 }
 126
 127                 if (d->chip->unmask_base && !d->chip->handle_mask_sync) {
 128                         reg = d->get_irq_reg(d, d->chip->unmask_base, i);
 129                         ret = regmap_update_bits(d->map, reg,
 130                                         d->mask_buf_def[i], ~d->mask_buf[i]);
 131                         if (ret)
 132                                 dev_err(d->map->dev, "Failed to sync masks in %x\n",
 133                                         reg);
 134                 }
 135
 136                 reg = d->get_irq_reg(d, d->chip->wake_base, i);
 137                 if (d->wake_buf) {
 138                         if (d->chip->wake_invert)
 139                                 ret = regmap_update_bits(d->map, reg,
 140                                                          d->mask_buf_def[i],
 141                                                          ~d->wake_buf[i]);
 142                         else
 143                                 ret = regmap_update_bits(d->map, reg,
 144                                                          d->mask_buf_def[i],
 145                                                          d->wake_buf[i]);
 146                         if (ret != 0)
 147                                 dev_err(d->map->dev,
 148                                         "Failed to sync wakes in %x: %d\n",
 149                                         reg, ret);
 150                 }
 151
 152                 if (!d->chip->init_ack_masked)
 153                         continue;
 154                 /*
 155                  * Ack all the masked interrupts unconditionally,
 156                  * OR if there is masked interrupt which hasn't been Acked,
 157                  * it'll be ignored in irq handler, then may introduce irq storm
 158                  */
 159                 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
 160                         reg = d->get_irq_reg(d, d->chip->ack_base, i);
 161
 162                         /* some chips ack by write 0 */
 163                         if (d->chip->ack_invert)
 164                                 ret = regmap_write(map, reg, ~d->mask_buf[i]);
 165                         else
 166                                 ret = regmap_write(map, reg, d->mask_buf[i]);
 167                         if (d->chip->clear_ack) {
 168                                 if (d->chip->ack_invert && !ret)
 169                                         ret = regmap_write(map, reg, UINT_MAX);
 170                                 else if (!ret)
 171                                         ret = regmap_write(map, reg, 0);
 172                         }
 173                         if (ret != 0)
 174                                 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
 175                                         reg, ret);
 176                 }
 177         }
 178
 179         for (i = 0; i < d->chip->num_config_bases; i++) {
 180                 for (j = 0; j < d->chip->num_config_regs; j++) {
 181                         reg = d->get_irq_reg(d, d->chip->config_base[i], j);
 182                         ret = regmap_write(map, reg, d->config_buf[i][j]);
 183                         if (ret)
 184                                 dev_err(d->map->dev,
 185                                         "Failed to write config %x: %d\n",
 186                                         reg, ret);
 187                 }
 188         }
 189
 190         if (d->chip->runtime_pm)
 191                 pm_runtime_put(map->dev);
 192
 193         /* If we've changed our wakeup count propagate it to the parent */
 194         if (d->wake_count < 0)
 195                 for (i = d->wake_count; i < 0; i++)
 196                         irq_set_irq_wake(d->irq, 0);
 197         else if (d->wake_count > 0)
 198                 for (i = 0; i < d->wake_count; i++)
 199                         irq_set_irq_wake(d->irq, 1);
 200
 201         d->wake_count = 0;
 202
 203         mutex_unlock(&d->lock);
 204 }
 205
 206 static void regmap_irq_enable(struct irq_data *data)
 207 {
 208         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 209         struct regmap *map = d->map;
 210         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 211         unsigned int reg = irq_data->reg_offset / map->reg_stride;
 212         unsigned int mask;
 213
 214         /*
 215          * The type_in_mask flag means that the underlying hardware uses
 216          * separate mask bits for each interrupt trigger type, but we want
 217          * to have a single logical interrupt with a configurable type.
 218          *
 219          * If the interrupt we're enabling defines any supported types
 220          * then instead of using the regular mask bits for this interrupt,
 221          * use the value previously written to the type buffer at the
 222          * corresponding offset in regmap_irq_set_type().
 223          */
 224         if (d->chip->type_in_mask && irq_data->type.types_supported)
 225                 mask = d->type_buf[reg] & irq_data->mask;
 226         else
 227                 mask = irq_data->mask;
 228
 229         if (d->chip->clear_on_unmask)
 230                 d->clear_status = true;
 231
 232         d->mask_buf[reg] &= ~mask;
 233 }
 234
 235 static void regmap_irq_disable(struct irq_data *data)
 236 {
 237         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 238         struct regmap *map = d->map;
 239         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 240
 241         d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
 242 }
 243
 244 static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 245 {
 246         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 247         struct regmap *map = d->map;
 248         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 249         int reg, ret;
 250         const struct regmap_irq_type *t = &irq_data->type;
 251
 252         if ((t->types_supported & type) != type)
 253                 return 0;
 254
 255         reg = t->type_reg_offset / map->reg_stride;
 256
 257         if (d->chip->type_in_mask) {
 258                 ret = regmap_irq_set_type_config_simple(&d->type_buf, type,
 259                                                         irq_data, reg, d->chip->irq_drv_data);
 260                 if (ret)
 261                         return ret;
 262         }
 263
 264         if (d->chip->set_type_config) {
 265                 ret = d->chip->set_type_config(d->config_buf, type, irq_data,
 266                                                reg, d->chip->irq_drv_data);
 267                 if (ret)
 268                         return ret;
 269         }
 270
 271         return 0;
 272 }
 273
 274 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
 275 {
 276         struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 277         struct regmap *map = d->map;
 278         const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 279
 280         if (on) {
 281                 if (d->wake_buf)
 282                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 283                                 &= ~irq_data->mask;
 284                 d->wake_count++;
 285         } else {
 286                 if (d->wake_buf)
 287                         d->wake_buf[irq_data->reg_offset / map->reg_stride]
 288                                 |= irq_data->mask;
 289                 d->wake_count--;
 290         }
 291
 292         return 0;
 293 }
 294
 295 static const struct irq_chip regmap_irq_chip = {
 296         .irq_bus_lock           = regmap_irq_lock,
 297         .irq_bus_sync_unlock    = regmap_irq_sync_unlock,
 298         .irq_disable            = regmap_irq_disable,
 299         .irq_enable             = regmap_irq_enable,
 300         .irq_set_type           = regmap_irq_set_type,
 301         .irq_set_wake           = regmap_irq_set_wake,
 302 };
 303
 304 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 305                                            unsigned int b)
 306 {
 307         const struct regmap_irq_chip *chip = data->chip;
 308         const struct regmap_irq_sub_irq_map *subreg;
 309         struct regmap *map = data->map;
 310         unsigned int reg;
 311         int i, ret = 0;
 312
 313         if (!chip->sub_reg_offsets) {
 314                 reg = data->get_irq_reg(data, chip->status_base, b);
 315                 ret = regmap_read(map, reg, &data->status_buf[b]);
 316         } else {
 317                 /*
 318                  * Note we can't use ->get_irq_reg() here because the offsets
 319                  * in 'subreg' are *not* interchangeable with indices.
 320                  */
 321                 subreg = &chip->sub_reg_offsets[b];
 322                 for (i = 0; i < subreg->num_regs; i++) {
 323                         unsigned int offset = subreg->offset[i];
 324                         unsigned int index = offset / map->reg_stride;
 325
 326                         ret = regmap_read(map, chip->status_base + offset,
 327                                           &data->status_buf[index]);
 328                         if (ret)
 329                                 break;
 330                 }
 331         }
 332         return ret;
 333 }
 334
 335 static irqreturn_t regmap_irq_thread(int irq, void *d)
 336 {
 337         struct regmap_irq_chip_data *data = d;
 338         const struct regmap_irq_chip *chip = data->chip;
 339         struct regmap *map = data->map;
 340         int ret, i;
 341         bool handled = false;
 342         u32 reg;
 343
 344         if (chip->handle_pre_irq)
 345                 chip->handle_pre_irq(chip->irq_drv_data);
 346
 347         if (chip->runtime_pm) {
 348                 ret = pm_runtime_get_sync(map->dev);
 349                 if (ret < 0) {
 350                         dev_err(map->dev, "IRQ thread failed to resume: %d\n",
 351                                 ret);
 352                         goto exit;
 353                 }
 354         }
 355
 356         /*
 357          * Read only registers with active IRQs if the chip has 'main status
 358          * register'. Else read in the statuses, using a single bulk read if
 359          * possible in order to reduce the I/O overheads.
 360          */
 361
 362         if (chip->no_status) {
 363                 /* no status register so default to all active */
 364                 memset32(data->status_buf, GENMASK(31, 0), chip->num_regs);
 365         } else if (chip->num_main_regs) {
 366                 unsigned int max_main_bits;
 367                 unsigned long size;
 368
 369                 size = chip->num_regs * sizeof(unsigned int);
 370
 371                 max_main_bits = (chip->num_main_status_bits) ?
 372                                  chip->num_main_status_bits : chip->num_regs;
 373                 /* Clear the status buf as we don't read all status regs */
 374                 memset(data->status_buf, 0, size);
 375
 376                 /* We could support bulk read for main status registers
 377                  * but I don't expect to see devices with really many main
 378                  * status registers so let's only support single reads for the
 379                  * sake of simplicity. and add bulk reads only if needed
 380                  */
 381                 for (i = 0; i < chip->num_main_regs; i++) {
 382                         reg = data->get_irq_reg(data, chip->main_status, i);
 383                         ret = regmap_read(map, reg, &data->main_status_buf[i]);
 384                         if (ret) {
 385                                 dev_err(map->dev,
 386                                         "Failed to read IRQ status %d\n",
 387                                         ret);
 388                                 goto exit;
 389                         }
 390                 }
 391
 392                 /* Read sub registers with active IRQs */
 393                 for (i = 0; i < chip->num_main_regs; i++) {
 394                         unsigned int b;
 395                         const unsigned long mreg = data->main_status_buf[i];
 396
 397                         for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
 398                                 if (i * map->format.val_bytes * 8 + b >
 399                                     max_main_bits)
 400                                         break;
 401                                 ret = read_sub_irq_data(data, b);
 402
 403                                 if (ret != 0) {
 404                                         dev_err(map->dev,
 405                                                 "Failed to read IRQ status %d\n",
 406                                                 ret);
 407                                         goto exit;
 408                                 }
 409                         }
 410
 411                 }
 412         } else if (regmap_irq_can_bulk_read_status(data)) {
 413
 414                 u8 *buf8 = data->status_reg_buf;
 415                 u16 *buf16 = data->status_reg_buf;
 416                 u32 *buf32 = data->status_reg_buf;
 417
 418                 BUG_ON(!data->status_reg_buf);
 419
 420                 ret = regmap_bulk_read(map, chip->status_base,
 421                                        data->status_reg_buf,
 422                                        chip->num_regs);
 423                 if (ret != 0) {
 424                         dev_err(map->dev, "Failed to read IRQ status: %d\n",
 425                                 ret);
 426                         goto exit;
 427                 }
 428
 429                 for (i = 0; i < data->chip->num_regs; i++) {
 430                         switch (map->format.val_bytes) {
 431                         case 1:
 432                                 data->status_buf[i] = buf8[i];
 433                                 break;
 434                         case 2:
 435                                 data->status_buf[i] = buf16[i];
 436                                 break;
 437                         case 4:
 438                                 data->status_buf[i] = buf32[i];
 439                                 break;
 440                         default:
 441                                 BUG();
 442                                 goto exit;
 443                         }
 444                 }
 445
 446         } else {
 447                 for (i = 0; i < data->chip->num_regs; i++) {
 448                         unsigned int reg = data->get_irq_reg(data,
 449                                         data->chip->status_base, i);
 450                         ret = regmap_read(map, reg, &data->status_buf[i]);
 451
 452                         if (ret != 0) {
 453                                 dev_err(map->dev,
 454                                         "Failed to read IRQ status: %d\n",
 455                                         ret);
 456                                 goto exit;
 457                         }
 458                 }
 459         }
 460
 461         if (chip->status_invert)
 462                 for (i = 0; i < data->chip->num_regs; i++)
 463                         data->status_buf[i] = ~data->status_buf[i];
 464
 465         /*
 466          * Ignore masked IRQs and ack if we need to; we ack early so
 467          * there is no race between handling and acknowledging the
 468          * interrupt.  We assume that typically few of the interrupts
 469          * will fire simultaneously so don't worry about overhead from
 470          * doing a write per register.
 471          */
 472         for (i = 0; i < data->chip->num_regs; i++) {
 473                 data->status_buf[i] &= ~data->mask_buf[i];
 474
 475                 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 476                         reg = data->get_irq_reg(data, data->chip->ack_base, i);
 477
 478                         if (chip->ack_invert)
 479                                 ret = regmap_write(map, reg,
 480                                                 ~data->status_buf[i]);
 481                         else
 482                                 ret = regmap_write(map, reg,
 483                                                 data->status_buf[i]);
 484                         if (chip->clear_ack) {
 485                                 if (chip->ack_invert && !ret)
 486                                         ret = regmap_write(map, reg, UINT_MAX);
 487                                 else if (!ret)
 488                                         ret = regmap_write(map, reg, 0);
 489                         }
 490                         if (ret != 0)
 491                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 492                                         reg, ret);
 493                 }
 494         }
 495
 496         for (i = 0; i < chip->num_irqs; i++) {
 497                 if (data->status_buf[chip->irqs[i].reg_offset /
 498                                      map->reg_stride] & chip->irqs[i].mask) {
 499                         handle_nested_irq(irq_find_mapping(data->domain, i));
 500                         handled = true;
 501                 }
 502         }
 503
 504 exit:
 505         if (chip->handle_post_irq)
 506                 chip->handle_post_irq(chip->irq_drv_data);
 507
 508         if (chip->runtime_pm)
 509                 pm_runtime_put(map->dev);
 510
 511         if (handled)
 512                 return IRQ_HANDLED;
 513         else
 514                 return IRQ_NONE;
 515 }
 516
 517 static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
 518                           irq_hw_number_t hw)
 519 {
 520         struct regmap_irq_chip_data *data = h->host_data;
 521
 522         irq_set_chip_data(virq, data);
 523         irq_set_chip(virq, &data->irq_chip);
 524         irq_set_nested_thread(virq, 1);
 525         irq_set_parent(virq, data->irq);
 526         irq_set_noprobe(virq);
 527
 528         return 0;
 529 }
 530
 531 static const struct irq_domain_ops regmap_domain_ops = {
 532         .map    = regmap_irq_map,
 533         .xlate  = irq_domain_xlate_onetwocell,
 534 };
 535
 536 /**
 537  * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback.
 538  * @data: Data for the &struct regmap_irq_chip
 539  * @base: Base register
 540  * @index: Register index
 541  *
 542  * Returns the register address corresponding to the given @base and @index
 543  * by the formula ``base + index * regmap_stride * irq_reg_stride``.
 544  */
 545 unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data,
 546                                            unsigned int base, int index)
 547 {
 548         struct regmap *map = data->map;
 549
 550         return base + index * map->reg_stride * data->irq_reg_stride;
 551 }
 552 EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear);
 553
 554 /**
 555  * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback.
 556  * @buf: Buffer containing configuration register values, this is a 2D array of
 557  *       `num_config_bases` rows, each of `num_config_regs` elements.
 558  * @type: The requested IRQ type.
 559  * @irq_data: The IRQ being configured.
 560  * @idx: Index of the irq's config registers within each array `buf[i]`
 561  * @irq_drv_data: Driver specific IRQ data
 562  *
 563  * This is a &struct regmap_irq_chip->set_type_config callback suitable for
 564  * chips with one config register. Register values are updated according to
 565  * the &struct regmap_irq_type data associated with an IRQ.
 566  */
 567 int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type,
 568                                       const struct regmap_irq *irq_data,
 569                                       int idx, void *irq_drv_data)
 570 {
 571         const struct regmap_irq_type *t = &irq_data->type;
 572
 573         if (t->type_reg_mask)
 574                 buf[0][idx] &= ~t->type_reg_mask;
 575         else
 576                 buf[0][idx] &= ~(t->type_falling_val |
 577                                  t->type_rising_val |
 578                                  t->type_level_low_val |
 579                                  t->type_level_high_val);
 580
 581         switch (type) {
 582         case IRQ_TYPE_EDGE_FALLING:
 583                 buf[0][idx] |= t->type_falling_val;
 584                 break;
 585
 586         case IRQ_TYPE_EDGE_RISING:
 587                 buf[0][idx] |= t->type_rising_val;
 588                 break;
 589
 590         case IRQ_TYPE_EDGE_BOTH:
 591                 buf[0][idx] |= (t->type_falling_val |
 592                                 t->type_rising_val);
 593                 break;
 594
 595         case IRQ_TYPE_LEVEL_HIGH:
 596                 buf[0][idx] |= t->type_level_high_val;
 597                 break;
 598
 599         case IRQ_TYPE_LEVEL_LOW:
 600                 buf[0][idx] |= t->type_level_low_val;
 601                 break;
 602
 603         default:
 604                 return -EINVAL;
 605         }
 606
 607         return 0;
 608 }
 609 EXPORT_SYMBOL_GPL(regmap_irq_set_type_config_simple);
 610
 611 static int regmap_irq_create_domain(struct fwnode_handle *fwnode, int irq_base,
 612                                     const struct regmap_irq_chip *chip,
 613                                     struct regmap_irq_chip_data *d)
 614 {
 615         struct irq_domain_info info = {
 616                 .fwnode = fwnode,
 617                 .size = chip->num_irqs,
 618                 .hwirq_max = chip->num_irqs,
 619                 .virq_base = irq_base,
 620                 .ops = &regmap_domain_ops,
 621                 .host_data = d,
 622                 .name_suffix = chip->domain_suffix,
 623         };
 624
 625         d->domain = irq_domain_instantiate(&info);
 626         if (IS_ERR(d->domain)) {
 627                 dev_err(d->map->dev, "Failed to create IRQ domain\n");
 628                 return PTR_ERR(d->domain);
 629         }
 630
 631         return 0;
 632 }
 633
 634
 635 /**
 636  * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
 637  *
 638  * @fwnode: The firmware node where the IRQ domain should be added to.
 639  * @map: The regmap for the device.
 640  * @irq: The IRQ the device uses to signal interrupts.
 641  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 642  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 643  * @chip: Configuration for the interrupt controller.
 644  * @data: Runtime data structure for the controller, allocated on success.
 645  *
 646  * Returns 0 on success or an errno on failure.
 647  *
 648  * In order for this to be efficient the chip really should use a
 649  * register cache.  The chip driver is responsible for restoring the
 650  * register values used by the IRQ controller over suspend and resume.
 651  */
 652 int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode,
 653                                struct regmap *map, int irq,
 654                                int irq_flags, int irq_base,
 655                                const struct regmap_irq_chip *chip,
 656                                struct regmap_irq_chip_data **data)
 657 {
 658         struct regmap_irq_chip_data *d;
 659         int i;
 660         int ret = -ENOMEM;
 661         u32 reg;
 662
 663         if (chip->num_regs <= 0)
 664                 return -EINVAL;
 665
 666         if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
 667                 return -EINVAL;
 668
 669         if (chip->mask_base && chip->unmask_base && !chip->mask_unmask_non_inverted)
 670                 return -EINVAL;
 671
 672         for (i = 0; i < chip->num_irqs; i++) {
 673                 if (chip->irqs[i].reg_offset % map->reg_stride)
 674                         return -EINVAL;
 675                 if (chip->irqs[i].reg_offset / map->reg_stride >=
 676                     chip->num_regs)
 677                         return -EINVAL;
 678         }
 679
 680         if (irq_base) {
 681                 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
 682                 if (irq_base < 0) {
 683                         dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
 684                                  irq_base);
 685                         return irq_base;
 686                 }
 687         }
 688
 689         d = kzalloc(sizeof(*d), GFP_KERNEL);
 690         if (!d)
 691                 return -ENOMEM;
 692
 693         if (chip->num_main_regs) {
 694                 d->main_status_buf = kcalloc(chip->num_main_regs,
 695                                              sizeof(*d->main_status_buf),
 696                                              GFP_KERNEL);
 697
 698                 if (!d->main_status_buf)
 699                         goto err_alloc;
 700         }
 701
 702         d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf),
 703                                 GFP_KERNEL);
 704         if (!d->status_buf)
 705                 goto err_alloc;
 706
 707         d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf),
 708                               GFP_KERNEL);
 709         if (!d->mask_buf)
 710                 goto err_alloc;
 711
 712         d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def),
 713                                   GFP_KERNEL);
 714         if (!d->mask_buf_def)
 715                 goto err_alloc;
 716
 717         if (chip->wake_base) {
 718                 d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf),
 719                                       GFP_KERNEL);
 720                 if (!d->wake_buf)
 721                         goto err_alloc;
 722         }
 723
 724         if (chip->type_in_mask) {
 725                 d->type_buf_def = kcalloc(chip->num_regs,
 726                                           sizeof(*d->type_buf_def), GFP_KERNEL);
 727                 if (!d->type_buf_def)
 728                         goto err_alloc;
 729
 730                 d->type_buf = kcalloc(chip->num_regs, sizeof(*d->type_buf), GFP_KERNEL);
 731                 if (!d->type_buf)
 732                         goto err_alloc;
 733         }
 734
 735         if (chip->num_config_bases && chip->num_config_regs) {
 736                 /*
 737                  * Create config_buf[num_config_bases][num_config_regs]
 738                  */
 739                 d->config_buf = kcalloc(chip->num_config_bases,
 740                                         sizeof(*d->config_buf), GFP_KERNEL);
 741                 if (!d->config_buf)
 742                         goto err_alloc;
 743
 744                 for (i = 0; i < chip->num_config_bases; i++) {
 745                         d->config_buf[i] = kcalloc(chip->num_config_regs,
 746                                                    sizeof(**d->config_buf),
 747                                                    GFP_KERNEL);
 748                         if (!d->config_buf[i])
 749                                 goto err_alloc;
 750                 }
 751         }
 752
 753         d->irq_chip = regmap_irq_chip;
 754         d->irq_chip.name = chip->name;
 755         d->irq = irq;
 756         d->map = map;
 757         d->chip = chip;
 758         d->irq_base = irq_base;
 759
 760         if (chip->irq_reg_stride)
 761                 d->irq_reg_stride = chip->irq_reg_stride;
 762         else
 763                 d->irq_reg_stride = 1;
 764
 765         if (chip->get_irq_reg)
 766                 d->get_irq_reg = chip->get_irq_reg;
 767         else
 768                 d->get_irq_reg = regmap_irq_get_irq_reg_linear;
 769
 770         if (regmap_irq_can_bulk_read_status(d)) {
 771                 d->status_reg_buf = kmalloc_array(chip->num_regs,
 772                                                   map->format.val_bytes,
 773                                                   GFP_KERNEL);
 774                 if (!d->status_reg_buf)
 775                         goto err_alloc;
 776         }
 777
 778         mutex_init(&d->lock);
 779
 780         for (i = 0; i < chip->num_irqs; i++)
 781                 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
 782                         |= chip->irqs[i].mask;
 783
 784         /* Mask all the interrupts by default */
 785         for (i = 0; i < chip->num_regs; i++) {
 786                 d->mask_buf[i] = d->mask_buf_def[i];
 787
 788                 if (chip->handle_mask_sync) {
 789                         ret = chip->handle_mask_sync(i, d->mask_buf_def[i],
 790                                                      d->mask_buf[i],
 791                                                      chip->irq_drv_data);
 792                         if (ret)
 793                                 goto err_alloc;
 794                 }
 795
 796                 if (chip->mask_base && !chip->handle_mask_sync) {
 797                         reg = d->get_irq_reg(d, chip->mask_base, i);
 798                         ret = regmap_update_bits(d->map, reg,
 799                                                  d->mask_buf_def[i],
 800                                                  d->mask_buf[i]);
 801                         if (ret) {
 802                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 803                                         reg, ret);
 804                                 goto err_alloc;
 805                         }
 806                 }
 807
 808                 if (chip->unmask_base && !chip->handle_mask_sync) {
 809                         reg = d->get_irq_reg(d, chip->unmask_base, i);
 810                         ret = regmap_update_bits(d->map, reg,
 811                                         d->mask_buf_def[i], ~d->mask_buf[i]);
 812                         if (ret) {
 813                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 814                                         reg, ret);
 815                                 goto err_alloc;
 816                         }
 817                 }
 818
 819                 if (!chip->init_ack_masked)
 820                         continue;
 821
 822                 /* Ack masked but set interrupts */
 823                 if (d->chip->no_status) {
 824                         /* no status register so default to all active */
 825                         d->status_buf[i] = GENMASK(31, 0);
 826                 } else {
 827                         reg = d->get_irq_reg(d, d->chip->status_base, i);
 828                         ret = regmap_read(map, reg, &d->status_buf[i]);
 829                         if (ret != 0) {
 830                                 dev_err(map->dev, "Failed to read IRQ status: %d\n",
 831                                         ret);
 832                                 goto err_alloc;
 833                         }
 834                 }
 835
 836                 if (chip->status_invert)
 837                         d->status_buf[i] = ~d->status_buf[i];
 838
 839                 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 840                         reg = d->get_irq_reg(d, d->chip->ack_base, i);
 841                         if (chip->ack_invert)
 842                                 ret = regmap_write(map, reg,
 843                                         ~(d->status_buf[i] & d->mask_buf[i]));
 844                         else
 845                                 ret = regmap_write(map, reg,
 846                                         d->status_buf[i] & d->mask_buf[i]);
 847                         if (chip->clear_ack) {
 848                                 if (chip->ack_invert && !ret)
 849                                         ret = regmap_write(map, reg, UINT_MAX);
 850                                 else if (!ret)
 851                                         ret = regmap_write(map, reg, 0);
 852                         }
 853                         if (ret != 0) {
 854                                 dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 855                                         reg, ret);
 856                                 goto err_alloc;
 857                         }
 858                 }
 859         }
 860
 861         /* Wake is disabled by default */
 862         if (d->wake_buf) {
 863                 for (i = 0; i < chip->num_regs; i++) {
 864                         d->wake_buf[i] = d->mask_buf_def[i];
 865                         reg = d->get_irq_reg(d, d->chip->wake_base, i);
 866
 867                         if (chip->wake_invert)
 868                                 ret = regmap_update_bits(d->map, reg,
 869                                                          d->mask_buf_def[i],
 870                                                          0);
 871                         else
 872                                 ret = regmap_update_bits(d->map, reg,
 873                                                          d->mask_buf_def[i],
 874                                                          d->wake_buf[i]);
 875                         if (ret != 0) {
 876                                 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 877                                         reg, ret);
 878                                 goto err_alloc;
 879                         }
 880                 }
 881         }
 882
 883         ret = regmap_irq_create_domain(fwnode, irq_base, chip, d);
 884         if (ret)
 885                 goto err_alloc;
 886
 887         ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
 888                                    irq_flags | IRQF_ONESHOT,
 889                                    chip->name, d);
 890         if (ret != 0) {
 891                 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
 892                         irq, chip->name, ret);
 893                 goto err_domain;
 894         }
 895
 896         *data = d;
 897
 898         return 0;
 899
 900 err_domain:
 901         /* Should really dispose of the domain but... */
 902 err_alloc:
 903         kfree(d->type_buf);
 904         kfree(d->type_buf_def);
 905         kfree(d->wake_buf);
 906         kfree(d->mask_buf_def);
 907         kfree(d->mask_buf);
 908         kfree(d->status_buf);
 909         kfree(d->status_reg_buf);
 910         if (d->config_buf) {
 911                 for (i = 0; i < chip->num_config_bases; i++)
 912                         kfree(d->config_buf[i]);
 913                 kfree(d->config_buf);
 914         }
 915         kfree(d);
 916         return ret;
 917 }
 918 EXPORT_SYMBOL_GPL(regmap_add_irq_chip_fwnode);
 919
 920 /**
 921  * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
 922  *
 923  * @map: The regmap for the device.
 924  * @irq: The IRQ the device uses to signal interrupts.
 925  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 926  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 927  * @chip: Configuration for the interrupt controller.
 928  * @data: Runtime data structure for the controller, allocated on success.
 929  *
 930  * Returns 0 on success or an errno on failure.
 931  *
 932  * This is the same as regmap_add_irq_chip_fwnode, except that the firmware
 933  * node of the regmap is used.
 934  */
 935 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 936                         int irq_base, const struct regmap_irq_chip *chip,
 937                         struct regmap_irq_chip_data **data)
 938 {
 939         return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq,
 940                                           irq_flags, irq_base, chip, data);
 941 }
 942 EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 943
 944 /**
 945  * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
 946  *
 947  * @irq: Primary IRQ for the device
 948  * @d: &regmap_irq_chip_data allocated by regmap_add_irq_chip()
 949  *
 950  * This function also disposes of all mapped IRQs on the chip.
 951  */
 952 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 953 {
 954         unsigned int virq;
 955         int i, hwirq;
 956
 957         if (!d)
 958                 return;
 959
 960         free_irq(irq, d);
 961
 962         /* Dispose all virtual irq from irq domain before removing it */
 963         for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
 964                 /* Ignore hwirq if holes in the IRQ list */
 965                 if (!d->chip->irqs[hwirq].mask)
 966                         continue;
 967
 968                 /*
 969                  * Find the virtual irq of hwirq on chip and if it is
 970                  * there then dispose it
 971                  */
 972                 virq = irq_find_mapping(d->domain, hwirq);
 973                 if (virq)
 974                         irq_dispose_mapping(virq);
 975         }
 976
 977         irq_domain_remove(d->domain);
 978         kfree(d->type_buf);
 979         kfree(d->type_buf_def);
 980         kfree(d->wake_buf);
 981         kfree(d->mask_buf_def);
 982         kfree(d->mask_buf);
 983         kfree(d->status_reg_buf);
 984         kfree(d->status_buf);
 985         if (d->config_buf) {
 986                 for (i = 0; i < d->chip->num_config_bases; i++)
 987                         kfree(d->config_buf[i]);
 988                 kfree(d->config_buf);
 989         }
 990         kfree(d);
 991 }
 992 EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
 993
 994 static void devm_regmap_irq_chip_release(struct device *dev, void *res)
 995 {
 996         struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
 997
 998         regmap_del_irq_chip(d->irq, d);
 999 }
1000
1001 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
1002
1003 {
1004         struct regmap_irq_chip_data **r = res;
1005
1006         if (!r || !*r) {
1007                 WARN_ON(!r || !*r);
1008                 return 0;
1009         }
1010         return *r == data;
1011 }
1012
1013 /**
1014  * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1015  *
1016  * @dev: The device pointer on which irq_chip belongs to.
1017  * @fwnode: The firmware node where the IRQ domain should be added to.
1018  * @map: The regmap for the device.
1019  * @irq: The IRQ the device uses to signal interrupts
1020  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
1021  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
1022  * @chip: Configuration for the interrupt controller.
1023  * @data: Runtime data structure for the controller, allocated on success
1024  *
1025  * Returns 0 on success or an errno on failure.
1026  *
1027  * The &regmap_irq_chip_data will be automatically released when the device is
1028  * unbound.
1029  */
1030 int devm_regmap_add_irq_chip_fwnode(struct device *dev,
1031                                     struct fwnode_handle *fwnode,
1032                                     struct regmap *map, int irq,
1033                                     int irq_flags, int irq_base,
1034                                     const struct regmap_irq_chip *chip,
1035                                     struct regmap_irq_chip_data **data)
1036 {
1037         struct regmap_irq_chip_data **ptr, *d;
1038         int ret;
1039
1040         ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
1041                            GFP_KERNEL);
1042         if (!ptr)
1043                 return -ENOMEM;
1044
1045         ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base,
1046                                          chip, &d);
1047         if (ret < 0) {
1048                 devres_free(ptr);
1049                 return ret;
1050         }
1051
1052         *ptr = d;
1053         devres_add(dev, ptr);
1054         *data = d;
1055         return 0;
1056 }
1057 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip_fwnode);
1058
1059 /**
1060  * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip()
1061  *
1062  * @dev: The device pointer on which irq_chip belongs to.
1063  * @map: The regmap for the device.
1064  * @irq: The IRQ the device uses to signal interrupts
1065  * @irq_flags: The IRQF_ flags to use for the primary interrupt.
1066  * @irq_base: Allocate at specific IRQ number if irq_base > 0.
1067  * @chip: Configuration for the interrupt controller.
1068  * @data: Runtime data structure for the controller, allocated on success
1069  *
1070  * Returns 0 on success or an errno on failure.
1071  *
1072  * The &regmap_irq_chip_data will be automatically released when the device is
1073  * unbound.
1074  */
1075 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
1076                              int irq_flags, int irq_base,
1077                              const struct regmap_irq_chip *chip,
1078                              struct regmap_irq_chip_data **data)
1079 {
1080         return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map,
1081                                                irq, irq_flags, irq_base, chip,
1082                                                data);
1083 }
1084 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
1085
1086 /**
1087  * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1088  *
1089  * @dev: Device for which the resource was allocated.
1090  * @irq: Primary IRQ for the device.
1091  * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
1092  *
1093  * A resource managed version of regmap_del_irq_chip().
1094  */
1095 void devm_regmap_del_irq_chip(struct device *dev, int irq,
1096                               struct regmap_irq_chip_data *data)
1097 {
1098         int rc;
1099
1100         WARN_ON(irq != data->irq);
1101         rc = devres_release(dev, devm_regmap_irq_chip_release,
1102                             devm_regmap_irq_chip_match, data);
1103
1104         if (rc != 0)
1105                 WARN_ON(rc);
1106 }
1107 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
1108
1109 /**
1110  * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1111  *
1112  * @data: regmap irq controller to operate on.
1113  *
1114  * Useful for drivers to request their own IRQs.
1115  */
1116 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
1117 {
1118         WARN_ON(!data->irq_base);
1119         return data->irq_base;
1120 }
1121 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
1122
1123 /**
1124  * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1125  *
1126  * @data: regmap irq controller to operate on.
1127  * @irq: index of the interrupt requested in the chip IRQs.
1128  *
1129  * Useful for drivers to request their own IRQs.
1130  */
1131 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
1132 {
1133         /* Handle holes in the IRQ list */
1134         if (!data->chip->irqs[irq].mask)
1135                 return -EINVAL;
1136
1137         return irq_create_mapping(data->domain, irq);
1138 }
1139 EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
1140
1141 /**
1142  * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1143  *
1144  * @data: regmap_irq controller to operate on.
1145  *
1146  * Useful for drivers to request their own IRQs and for integration
1147  * with subsystems.  For ease of integration NULL is accepted as a
1148  * domain, allowing devices to just call this even if no domain is
1149  * allocated.
1150  */
1151 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
1152 {
1153         if (data)
1154                 return data->domain;
1155         else
1156                 return NULL;
1157 }
1158 EXPORT_SYMBOL_GPL(regmap_irq_get_domain);