drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/power_supply.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34
  35
  36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  37
  38 static const struct cg_flag_name clocks[] = {
  39         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  40         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  41         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  46         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  49         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  50         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  51         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  52         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  54         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  55         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  58         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  61         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  63         {0, NULL},
  64 };
  65
  66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  67 {
  68         if (adev->pm.dpm_enabled) {
  69                 mutex_lock(&adev->pm.mutex);
  70                 if (power_supply_is_system_supplied() > 0)
  71                         adev->pm.dpm.ac_power = true;
  72                 else
  73                         adev->pm.dpm.ac_power = false;
  74                 if (adev->powerplay.pp_funcs->enable_bapm)
  75                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  76                 mutex_unlock(&adev->pm.mutex);
  77         }
  78 }
  79
  80 /**
  81  * DOC: power_dpm_state
  82  *
  83  * This is a legacy interface and is only provided for backwards compatibility.
  84  * The amdgpu driver provides a sysfs API for adjusting certain power
  85  * related parameters.  The file power_dpm_state is used for this.
  86  * It accepts the following arguments:
  87  * - battery
  88  * - balanced
  89  * - performance
  90  *
  91  * battery
  92  *
  93  * On older GPUs, the vbios provided a special power state for battery
  94  * operation.  Selecting battery switched to this state.  This is no
  95  * longer provided on newer GPUs so the option does nothing in that case.
  96  *
  97  * balanced
  98  *
  99  * On older GPUs, the vbios provided a special power state for balanced
 100  * operation.  Selecting balanced switched to this state.  This is no
 101  * longer provided on newer GPUs so the option does nothing in that case.
 102  *
 103  * performance
 104  *
 105  * On older GPUs, the vbios provided a special power state for performance
 106  * operation.  Selecting performance switched to this state.  This is no
 107  * longer provided on newer GPUs so the option does nothing in that case.
 108  *
 109  */
 110
 111 static ssize_t amdgpu_get_dpm_state(struct device *dev,
 112                                     struct device_attribute *attr,
 113                                     char *buf)
 114 {
 115         struct drm_device *ddev = dev_get_drvdata(dev);
 116         struct amdgpu_device *adev = ddev->dev_private;
 117         enum amd_pm_state_type pm;
 118
 119         if (adev->powerplay.pp_funcs->get_current_power_state)
 120                 pm = amdgpu_dpm_get_current_power_state(adev);
 121         else
 122                 pm = adev->pm.dpm.user_state;
 123
 124         return snprintf(buf, PAGE_SIZE, "%s\n",
 125                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 126                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 127 }
 128
 129 static ssize_t amdgpu_set_dpm_state(struct device *dev,
 130                                     struct device_attribute *attr,
 131                                     const char *buf,
 132                                     size_t count)
 133 {
 134         struct drm_device *ddev = dev_get_drvdata(dev);
 135         struct amdgpu_device *adev = ddev->dev_private;
 136         enum amd_pm_state_type  state;
 137
 138         if (strncmp("battery", buf, strlen("battery")) == 0)
 139                 state = POWER_STATE_TYPE_BATTERY;
 140         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 141                 state = POWER_STATE_TYPE_BALANCED;
 142         else if (strncmp("performance", buf, strlen("performance")) == 0)
 143                 state = POWER_STATE_TYPE_PERFORMANCE;
 144         else {
 145                 count = -EINVAL;
 146                 goto fail;
 147         }
 148
 149         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 150                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 151         } else {
 152                 mutex_lock(&adev->pm.mutex);
 153                 adev->pm.dpm.user_state = state;
 154                 mutex_unlock(&adev->pm.mutex);
 155
 156                 /* Can't set dpm state when the card is off */
 157                 if (!(adev->flags & AMD_IS_PX) ||
 158                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 159                         amdgpu_pm_compute_clocks(adev);
 160         }
 161 fail:
 162         return count;
 163 }
 164
 165
 166 /**
 167  * DOC: power_dpm_force_performance_level
 168  *
 169  * The amdgpu driver provides a sysfs API for adjusting certain power
 170  * related parameters.  The file power_dpm_force_performance_level is
 171  * used for this.  It accepts the following arguments:
 172  * - auto
 173  * - low
 174  * - high
 175  * - manual
 176  * - GPU fan
 177  * - profile_standard
 178  * - profile_min_sclk
 179  * - profile_min_mclk
 180  * - profile_peak
 181  *
 182  * auto
 183  *
 184  * When auto is selected, the driver will attempt to dynamically select
 185  * the optimal power profile for current conditions in the driver.
 186  *
 187  * low
 188  *
 189  * When low is selected, the clocks are forced to the lowest power state.
 190  *
 191  * high
 192  *
 193  * When high is selected, the clocks are forced to the highest power state.
 194  *
 195  * manual
 196  *
 197  * When manual is selected, the user can manually adjust which power states
 198  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 199  * and pp_dpm_pcie files and adjust the power state transition heuristics
 200  * via the pp_power_profile_mode sysfs file.
 201  *
 202  * profile_standard
 203  * profile_min_sclk
 204  * profile_min_mclk
 205  * profile_peak
 206  *
 207  * When the profiling modes are selected, clock and power gating are
 208  * disabled and the clocks are set for different profiling cases. This
 209  * mode is recommended for profiling specific work loads where you do
 210  * not want clock or power gating for clock fluctuation to interfere
 211  * with your results. profile_standard sets the clocks to a fixed clock
 212  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 213  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 214  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 215  *
 216  */
 217
 218 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 219                                                 struct device_attribute *attr,
 220                                                                 char *buf)
 221 {
 222         struct drm_device *ddev = dev_get_drvdata(dev);
 223         struct amdgpu_device *adev = ddev->dev_private;
 224         enum amd_dpm_forced_level level = 0xff;
 225
 226         if  ((adev->flags & AMD_IS_PX) &&
 227              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 228                 return snprintf(buf, PAGE_SIZE, "off\n");
 229
 230         if (adev->powerplay.pp_funcs->get_performance_level)
 231                 level = amdgpu_dpm_get_performance_level(adev);
 232         else
 233                 level = adev->pm.dpm.forced_level;
 234
 235         return snprintf(buf, PAGE_SIZE, "%s\n",
 236                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 237                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 238                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 239                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 240                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 241                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 242                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 243                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 244                         "unknown");
 245 }
 246
 247 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 248                                                        struct device_attribute *attr,
 249                                                        const char *buf,
 250                                                        size_t count)
 251 {
 252         struct drm_device *ddev = dev_get_drvdata(dev);
 253         struct amdgpu_device *adev = ddev->dev_private;
 254         enum amd_dpm_forced_level level;
 255         enum amd_dpm_forced_level current_level = 0xff;
 256         int ret = 0;
 257
 258         /* Can't force performance level when the card is off */
 259         if  ((adev->flags & AMD_IS_PX) &&
 260              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 261                 return -EINVAL;
 262
 263         if (adev->powerplay.pp_funcs->get_performance_level)
 264                 current_level = amdgpu_dpm_get_performance_level(adev);
 265
 266         if (strncmp("low", buf, strlen("low")) == 0) {
 267                 level = AMD_DPM_FORCED_LEVEL_LOW;
 268         } else if (strncmp("high", buf, strlen("high")) == 0) {
 269                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 270         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 271                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 272         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 273                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 274         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 275                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 276         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 277                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 278         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 279                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 280         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 281                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 282         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 283                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 284         }  else {
 285                 count = -EINVAL;
 286                 goto fail;
 287         }
 288
 289         if (current_level == level)
 290                 return count;
 291
 292         if (adev->powerplay.pp_funcs->force_performance_level) {
 293                 mutex_lock(&adev->pm.mutex);
 294                 if (adev->pm.dpm.thermal_active) {
 295                         count = -EINVAL;
 296                         mutex_unlock(&adev->pm.mutex);
 297                         goto fail;
 298                 }
 299                 ret = amdgpu_dpm_force_performance_level(adev, level);
 300                 if (ret)
 301                         count = -EINVAL;
 302                 else
 303                         adev->pm.dpm.forced_level = level;
 304                 mutex_unlock(&adev->pm.mutex);
 305         }
 306
 307 fail:
 308         return count;
 309 }
 310
 311 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 312                 struct device_attribute *attr,
 313                 char *buf)
 314 {
 315         struct drm_device *ddev = dev_get_drvdata(dev);
 316         struct amdgpu_device *adev = ddev->dev_private;
 317         struct pp_states_info data;
 318         int i, buf_len;
 319
 320         if (adev->powerplay.pp_funcs->get_pp_num_states)
 321                 amdgpu_dpm_get_pp_num_states(adev, &data);
 322
 323         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 324         for (i = 0; i < data.nums; i++)
 325                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 326                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 327                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 328                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 329                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 330
 331         return buf_len;
 332 }
 333
 334 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 335                 struct device_attribute *attr,
 336                 char *buf)
 337 {
 338         struct drm_device *ddev = dev_get_drvdata(dev);
 339         struct amdgpu_device *adev = ddev->dev_private;
 340         struct pp_states_info data;
 341         enum amd_pm_state_type pm = 0;
 342         int i = 0;
 343
 344         if (adev->powerplay.pp_funcs->get_current_power_state
 345                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 346                 pm = amdgpu_dpm_get_current_power_state(adev);
 347                 amdgpu_dpm_get_pp_num_states(adev, &data);
 348
 349                 for (i = 0; i < data.nums; i++) {
 350                         if (pm == data.states[i])
 351                                 break;
 352                 }
 353
 354                 if (i == data.nums)
 355                         i = -EINVAL;
 356         }
 357
 358         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 359 }
 360
 361 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 362                 struct device_attribute *attr,
 363                 char *buf)
 364 {
 365         struct drm_device *ddev = dev_get_drvdata(dev);
 366         struct amdgpu_device *adev = ddev->dev_private;
 367
 368         if (adev->pp_force_state_enabled)
 369                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 370         else
 371                 return snprintf(buf, PAGE_SIZE, "\n");
 372 }
 373
 374 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 375                 struct device_attribute *attr,
 376                 const char *buf,
 377                 size_t count)
 378 {
 379         struct drm_device *ddev = dev_get_drvdata(dev);
 380         struct amdgpu_device *adev = ddev->dev_private;
 381         enum amd_pm_state_type state = 0;
 382         unsigned long idx;
 383         int ret;
 384
 385         if (strlen(buf) == 1)
 386                 adev->pp_force_state_enabled = false;
 387         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 388                         adev->powerplay.pp_funcs->get_pp_num_states) {
 389                 struct pp_states_info data;
 390
 391                 ret = kstrtoul(buf, 0, &idx);
 392                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 393                         count = -EINVAL;
 394                         goto fail;
 395                 }
 396
 397                 amdgpu_dpm_get_pp_num_states(adev, &data);
 398                 state = data.states[idx];
 399                 /* only set user selected power states */
 400                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 401                     state != POWER_STATE_TYPE_DEFAULT) {
 402                         amdgpu_dpm_dispatch_task(adev,
 403                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 404                         adev->pp_force_state_enabled = true;
 405                 }
 406         }
 407 fail:
 408         return count;
 409 }
 410
 411 /**
 412  * DOC: pp_table
 413  *
 414  * The amdgpu driver provides a sysfs API for uploading new powerplay
 415  * tables.  The file pp_table is used for this.  Reading the file
 416  * will dump the current power play table.  Writing to the file
 417  * will attempt to upload a new powerplay table and re-initialize
 418  * powerplay using that new table.
 419  *
 420  */
 421
 422 static ssize_t amdgpu_get_pp_table(struct device *dev,
 423                 struct device_attribute *attr,
 424                 char *buf)
 425 {
 426         struct drm_device *ddev = dev_get_drvdata(dev);
 427         struct amdgpu_device *adev = ddev->dev_private;
 428         char *table = NULL;
 429         int size;
 430
 431         if (adev->powerplay.pp_funcs->get_pp_table)
 432                 size = amdgpu_dpm_get_pp_table(adev, &table);
 433         else
 434                 return 0;
 435
 436         if (size >= PAGE_SIZE)
 437                 size = PAGE_SIZE - 1;
 438
 439         memcpy(buf, table, size);
 440
 441         return size;
 442 }
 443
 444 static ssize_t amdgpu_set_pp_table(struct device *dev,
 445                 struct device_attribute *attr,
 446                 const char *buf,
 447                 size_t count)
 448 {
 449         struct drm_device *ddev = dev_get_drvdata(dev);
 450         struct amdgpu_device *adev = ddev->dev_private;
 451
 452         if (adev->powerplay.pp_funcs->set_pp_table)
 453                 amdgpu_dpm_set_pp_table(adev, buf, count);
 454
 455         return count;
 456 }
 457
 458 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 459                 struct device_attribute *attr,
 460                 const char *buf,
 461                 size_t count)
 462 {
 463         struct drm_device *ddev = dev_get_drvdata(dev);
 464         struct amdgpu_device *adev = ddev->dev_private;
 465         int ret;
 466         uint32_t parameter_size = 0;
 467         long parameter[64];
 468         char buf_cpy[128];
 469         char *tmp_str;
 470         char *sub_str;
 471         const char delimiter[3] = {' ', '\n', '\0'};
 472         uint32_t type;
 473
 474         if (count > 127)
 475                 return -EINVAL;
 476
 477         if (*buf == 's')
 478                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 479         else if (*buf == 'm')
 480                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 481         else if(*buf == 'r')
 482                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 483         else if (*buf == 'c')
 484                 type = PP_OD_COMMIT_DPM_TABLE;
 485         else
 486                 return -EINVAL;
 487
 488         memcpy(buf_cpy, buf, count+1);
 489
 490         tmp_str = buf_cpy;
 491
 492         while (isspace(*++tmp_str));
 493
 494         while (tmp_str[0]) {
 495                 sub_str = strsep(&tmp_str, delimiter);
 496                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 497                 if (ret)
 498                         return -EINVAL;
 499                 parameter_size++;
 500
 501                 while (isspace(*tmp_str))
 502                         tmp_str++;
 503         }
 504
 505         if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
 506                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 507                                                 parameter, parameter_size);
 508
 509         if (ret)
 510                 return -EINVAL;
 511
 512         if (type == PP_OD_COMMIT_DPM_TABLE) {
 513                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 514                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 515                         return count;
 516                 } else {
 517                         return -EINVAL;
 518                 }
 519         }
 520
 521         return count;
 522 }
 523
 524 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 525                 struct device_attribute *attr,
 526                 char *buf)
 527 {
 528         struct drm_device *ddev = dev_get_drvdata(dev);
 529         struct amdgpu_device *adev = ddev->dev_private;
 530         uint32_t size = 0;
 531
 532         if (adev->powerplay.pp_funcs->print_clock_levels) {
 533                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 534                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 535                 return size;
 536         } else {
 537                 return snprintf(buf, PAGE_SIZE, "\n");
 538         }
 539
 540 }
 541
 542 /**
 543  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
 544  *
 545  * The amdgpu driver provides a sysfs API for adjusting what power levels
 546  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 547  * and pp_dpm_pcie are used for this.
 548  *
 549  * Reading back the files will show you the available power levels within
 550  * the power state and the clock information for those levels.
 551  *
 552  * To manually adjust these states, first select manual using
 553  * power_dpm_force_performance_level.  Writing a string of the level
 554  * numbers to the file will select which levels you want to enable.
 555  * E.g., writing 456 to the file will enable levels 4, 5, and 6.
 556  *
 557  */
 558
 559 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 560                 struct device_attribute *attr,
 561                 char *buf)
 562 {
 563         struct drm_device *ddev = dev_get_drvdata(dev);
 564         struct amdgpu_device *adev = ddev->dev_private;
 565
 566         if (adev->powerplay.pp_funcs->print_clock_levels)
 567                 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 568         else
 569                 return snprintf(buf, PAGE_SIZE, "\n");
 570 }
 571
 572 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 573                 struct device_attribute *attr,
 574                 const char *buf,
 575                 size_t count)
 576 {
 577         struct drm_device *ddev = dev_get_drvdata(dev);
 578         struct amdgpu_device *adev = ddev->dev_private;
 579         int ret;
 580         long level;
 581         uint32_t i, mask = 0;
 582         char sub_str[2];
 583
 584         for (i = 0; i < strlen(buf); i++) {
 585                 if (*(buf + i) == '\n')
 586                         continue;
 587                 sub_str[0] = *(buf + i);
 588                 sub_str[1] = '\0';
 589                 ret = kstrtol(sub_str, 0, &level);
 590
 591                 if (ret) {
 592                         count = -EINVAL;
 593                         goto fail;
 594                 }
 595                 mask |= 1 << level;
 596         }
 597
 598         if (adev->powerplay.pp_funcs->force_clock_level)
 599                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 600
 601 fail:
 602         return count;
 603 }
 604
 605 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 606                 struct device_attribute *attr,
 607                 char *buf)
 608 {
 609         struct drm_device *ddev = dev_get_drvdata(dev);
 610         struct amdgpu_device *adev = ddev->dev_private;
 611
 612         if (adev->powerplay.pp_funcs->print_clock_levels)
 613                 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 614         else
 615                 return snprintf(buf, PAGE_SIZE, "\n");
 616 }
 617
 618 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 619                 struct device_attribute *attr,
 620                 const char *buf,
 621                 size_t count)
 622 {
 623         struct drm_device *ddev = dev_get_drvdata(dev);
 624         struct amdgpu_device *adev = ddev->dev_private;
 625         int ret;
 626         long level;
 627         uint32_t i, mask = 0;
 628         char sub_str[2];
 629
 630         for (i = 0; i < strlen(buf); i++) {
 631                 if (*(buf + i) == '\n')
 632                         continue;
 633                 sub_str[0] = *(buf + i);
 634                 sub_str[1] = '\0';
 635                 ret = kstrtol(sub_str, 0, &level);
 636
 637                 if (ret) {
 638                         count = -EINVAL;
 639                         goto fail;
 640                 }
 641                 mask |= 1 << level;
 642         }
 643         if (adev->powerplay.pp_funcs->force_clock_level)
 644                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 645
 646 fail:
 647         return count;
 648 }
 649
 650 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 651                 struct device_attribute *attr,
 652                 char *buf)
 653 {
 654         struct drm_device *ddev = dev_get_drvdata(dev);
 655         struct amdgpu_device *adev = ddev->dev_private;
 656
 657         if (adev->powerplay.pp_funcs->print_clock_levels)
 658                 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 659         else
 660                 return snprintf(buf, PAGE_SIZE, "\n");
 661 }
 662
 663 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 664                 struct device_attribute *attr,
 665                 const char *buf,
 666                 size_t count)
 667 {
 668         struct drm_device *ddev = dev_get_drvdata(dev);
 669         struct amdgpu_device *adev = ddev->dev_private;
 670         int ret;
 671         long level;
 672         uint32_t i, mask = 0;
 673         char sub_str[2];
 674
 675         for (i = 0; i < strlen(buf); i++) {
 676                 if (*(buf + i) == '\n')
 677                         continue;
 678                 sub_str[0] = *(buf + i);
 679                 sub_str[1] = '\0';
 680                 ret = kstrtol(sub_str, 0, &level);
 681
 682                 if (ret) {
 683                         count = -EINVAL;
 684                         goto fail;
 685                 }
 686                 mask |= 1 << level;
 687         }
 688         if (adev->powerplay.pp_funcs->force_clock_level)
 689                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 690
 691 fail:
 692         return count;
 693 }
 694
 695 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 696                 struct device_attribute *attr,
 697                 char *buf)
 698 {
 699         struct drm_device *ddev = dev_get_drvdata(dev);
 700         struct amdgpu_device *adev = ddev->dev_private;
 701         uint32_t value = 0;
 702
 703         if (adev->powerplay.pp_funcs->get_sclk_od)
 704                 value = amdgpu_dpm_get_sclk_od(adev);
 705
 706         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 707 }
 708
 709 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 710                 struct device_attribute *attr,
 711                 const char *buf,
 712                 size_t count)
 713 {
 714         struct drm_device *ddev = dev_get_drvdata(dev);
 715         struct amdgpu_device *adev = ddev->dev_private;
 716         int ret;
 717         long int value;
 718
 719         ret = kstrtol(buf, 0, &value);
 720
 721         if (ret) {
 722                 count = -EINVAL;
 723                 goto fail;
 724         }
 725         if (adev->powerplay.pp_funcs->set_sclk_od)
 726                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 727
 728         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 729                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 730         } else {
 731                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 732                 amdgpu_pm_compute_clocks(adev);
 733         }
 734
 735 fail:
 736         return count;
 737 }
 738
 739 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 740                 struct device_attribute *attr,
 741                 char *buf)
 742 {
 743         struct drm_device *ddev = dev_get_drvdata(dev);
 744         struct amdgpu_device *adev = ddev->dev_private;
 745         uint32_t value = 0;
 746
 747         if (adev->powerplay.pp_funcs->get_mclk_od)
 748                 value = amdgpu_dpm_get_mclk_od(adev);
 749
 750         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 751 }
 752
 753 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 754                 struct device_attribute *attr,
 755                 const char *buf,
 756                 size_t count)
 757 {
 758         struct drm_device *ddev = dev_get_drvdata(dev);
 759         struct amdgpu_device *adev = ddev->dev_private;
 760         int ret;
 761         long int value;
 762
 763         ret = kstrtol(buf, 0, &value);
 764
 765         if (ret) {
 766                 count = -EINVAL;
 767                 goto fail;
 768         }
 769         if (adev->powerplay.pp_funcs->set_mclk_od)
 770                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 771
 772         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 773                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
 774         } else {
 775                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 776                 amdgpu_pm_compute_clocks(adev);
 777         }
 778
 779 fail:
 780         return count;
 781 }
 782
 783 /**
 784  * DOC: pp_power_profile_mode
 785  *
 786  * The amdgpu driver provides a sysfs API for adjusting the heuristics
 787  * related to switching between power levels in a power state.  The file
 788  * pp_power_profile_mode is used for this.
 789  *
 790  * Reading this file outputs a list of all of the predefined power profiles
 791  * and the relevant heuristics settings for that profile.
 792  *
 793  * To select a profile or create a custom profile, first select manual using
 794  * power_dpm_force_performance_level.  Writing the number of a predefined
 795  * profile to pp_power_profile_mode will enable those heuristics.  To
 796  * create a custom set of heuristics, write a string of numbers to the file
 797  * starting with the number of the custom profile along with a setting
 798  * for each heuristic parameter.  Due to differences across asic families
 799  * the heuristic parameters vary from family to family.
 800  *
 801  */
 802
 803 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
 804                 struct device_attribute *attr,
 805                 char *buf)
 806 {
 807         struct drm_device *ddev = dev_get_drvdata(dev);
 808         struct amdgpu_device *adev = ddev->dev_private;
 809
 810         if (adev->powerplay.pp_funcs->get_power_profile_mode)
 811                 return amdgpu_dpm_get_power_profile_mode(adev, buf);
 812
 813         return snprintf(buf, PAGE_SIZE, "\n");
 814 }
 815
 816
 817 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
 818                 struct device_attribute *attr,
 819                 const char *buf,
 820                 size_t count)
 821 {
 822         int ret = 0xff;
 823         struct drm_device *ddev = dev_get_drvdata(dev);
 824         struct amdgpu_device *adev = ddev->dev_private;
 825         uint32_t parameter_size = 0;
 826         long parameter[64];
 827         char *sub_str, buf_cpy[128];
 828         char *tmp_str;
 829         uint32_t i = 0;
 830         char tmp[2];
 831         long int profile_mode = 0;
 832         const char delimiter[3] = {' ', '\n', '\0'};
 833
 834         tmp[0] = *(buf);
 835         tmp[1] = '\0';
 836         ret = kstrtol(tmp, 0, &profile_mode);
 837         if (ret)
 838                 goto fail;
 839
 840         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
 841                 if (count < 2 || count > 127)
 842                         return -EINVAL;
 843                 while (isspace(*++buf))
 844                         i++;
 845                 memcpy(buf_cpy, buf, count-i);
 846                 tmp_str = buf_cpy;
 847                 while (tmp_str[0]) {
 848                         sub_str = strsep(&tmp_str, delimiter);
 849                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 850                         if (ret) {
 851                                 count = -EINVAL;
 852                                 goto fail;
 853                         }
 854                         parameter_size++;
 855                         while (isspace(*tmp_str))
 856                                 tmp_str++;
 857                 }
 858         }
 859         parameter[parameter_size] = profile_mode;
 860         if (adev->powerplay.pp_funcs->set_power_profile_mode)
 861                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
 862
 863         if (!ret)
 864                 return count;
 865 fail:
 866         return -EINVAL;
 867 }
 868
 869 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 870 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 871                    amdgpu_get_dpm_forced_performance_level,
 872                    amdgpu_set_dpm_forced_performance_level);
 873 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 874 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 875 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 876                 amdgpu_get_pp_force_state,
 877                 amdgpu_set_pp_force_state);
 878 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 879                 amdgpu_get_pp_table,
 880                 amdgpu_set_pp_table);
 881 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 882                 amdgpu_get_pp_dpm_sclk,
 883                 amdgpu_set_pp_dpm_sclk);
 884 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 885                 amdgpu_get_pp_dpm_mclk,
 886                 amdgpu_set_pp_dpm_mclk);
 887 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 888                 amdgpu_get_pp_dpm_pcie,
 889                 amdgpu_set_pp_dpm_pcie);
 890 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 891                 amdgpu_get_pp_sclk_od,
 892                 amdgpu_set_pp_sclk_od);
 893 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 894                 amdgpu_get_pp_mclk_od,
 895                 amdgpu_set_pp_mclk_od);
 896 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
 897                 amdgpu_get_pp_power_profile_mode,
 898                 amdgpu_set_pp_power_profile_mode);
 899 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
 900                 amdgpu_get_pp_od_clk_voltage,
 901                 amdgpu_set_pp_od_clk_voltage);
 902
 903 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 904                                       struct device_attribute *attr,
 905                                       char *buf)
 906 {
 907         struct amdgpu_device *adev = dev_get_drvdata(dev);
 908         struct drm_device *ddev = adev->ddev;
 909         int r, temp, size = sizeof(temp);
 910
 911         /* Can't get temperature when the card is off */
 912         if  ((adev->flags & AMD_IS_PX) &&
 913              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 914                 return -EINVAL;
 915
 916         /* sanity check PP is enabled */
 917         if (!(adev->powerplay.pp_funcs &&
 918               adev->powerplay.pp_funcs->read_sensor))
 919                 return -EINVAL;
 920
 921         /* get the temperature */
 922         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
 923                                    (void *)&temp, &size);
 924         if (r)
 925                 return r;
 926
 927         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 928 }
 929
 930 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 931                                              struct device_attribute *attr,
 932                                              char *buf)
 933 {
 934         struct amdgpu_device *adev = dev_get_drvdata(dev);
 935         int hyst = to_sensor_dev_attr(attr)->index;
 936         int temp;
 937
 938         if (hyst)
 939                 temp = adev->pm.dpm.thermal.min_temp;
 940         else
 941                 temp = adev->pm.dpm.thermal.max_temp;
 942
 943         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 944 }
 945
 946 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 947                                             struct device_attribute *attr,
 948                                             char *buf)
 949 {
 950         struct amdgpu_device *adev = dev_get_drvdata(dev);
 951         u32 pwm_mode = 0;
 952
 953         if (!adev->powerplay.pp_funcs->get_fan_control_mode)
 954                 return -EINVAL;
 955
 956         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 957
 958         return sprintf(buf, "%i\n", pwm_mode);
 959 }
 960
 961 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 962                                             struct device_attribute *attr,
 963                                             const char *buf,
 964                                             size_t count)
 965 {
 966         struct amdgpu_device *adev = dev_get_drvdata(dev);
 967         int err;
 968         int value;
 969
 970         /* Can't adjust fan when the card is off */
 971         if  ((adev->flags & AMD_IS_PX) &&
 972              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 973                 return -EINVAL;
 974
 975         if (!adev->powerplay.pp_funcs->set_fan_control_mode)
 976                 return -EINVAL;
 977
 978         err = kstrtoint(buf, 10, &value);
 979         if (err)
 980                 return err;
 981
 982         amdgpu_dpm_set_fan_control_mode(adev, value);
 983
 984         return count;
 985 }
 986
 987 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 988                                          struct device_attribute *attr,
 989                                          char *buf)
 990 {
 991         return sprintf(buf, "%i\n", 0);
 992 }
 993
 994 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 995                                          struct device_attribute *attr,
 996                                          char *buf)
 997 {
 998         return sprintf(buf, "%i\n", 255);
 999 }
1000
1001 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
1002                                      struct device_attribute *attr,
1003                                      const char *buf, size_t count)
1004 {
1005         struct amdgpu_device *adev = dev_get_drvdata(dev);
1006         int err;
1007         u32 value;
1008
1009         /* Can't adjust fan when the card is off */
1010         if  ((adev->flags & AMD_IS_PX) &&
1011              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1012                 return -EINVAL;
1013
1014         err = kstrtou32(buf, 10, &value);
1015         if (err)
1016                 return err;
1017
1018         value = (value * 100) / 255;
1019
1020         if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
1021                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
1022                 if (err)
1023                         return err;
1024         }
1025
1026         return count;
1027 }
1028
1029 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
1030                                      struct device_attribute *attr,
1031                                      char *buf)
1032 {
1033         struct amdgpu_device *adev = dev_get_drvdata(dev);
1034         int err;
1035         u32 speed = 0;
1036
1037         /* Can't adjust fan when the card is off */
1038         if  ((adev->flags & AMD_IS_PX) &&
1039              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1040                 return -EINVAL;
1041
1042         if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
1043                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
1044                 if (err)
1045                         return err;
1046         }
1047
1048         speed = (speed * 255) / 100;
1049
1050         return sprintf(buf, "%i\n", speed);
1051 }
1052
1053 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
1054                                            struct device_attribute *attr,
1055                                            char *buf)
1056 {
1057         struct amdgpu_device *adev = dev_get_drvdata(dev);
1058         int err;
1059         u32 speed = 0;
1060
1061         /* Can't adjust fan when the card is off */
1062         if  ((adev->flags & AMD_IS_PX) &&
1063              (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1064                 return -EINVAL;
1065
1066         if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
1067                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
1068                 if (err)
1069                         return err;
1070         }
1071
1072         return sprintf(buf, "%i\n", speed);
1073 }
1074
1075 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
1076                                         struct device_attribute *attr,
1077                                         char *buf)
1078 {
1079         struct amdgpu_device *adev = dev_get_drvdata(dev);
1080         struct drm_device *ddev = adev->ddev;
1081         u32 vddgfx;
1082         int r, size = sizeof(vddgfx);
1083
1084         /* Can't get voltage when the card is off */
1085         if  ((adev->flags & AMD_IS_PX) &&
1086              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1087                 return -EINVAL;
1088
1089         /* sanity check PP is enabled */
1090         if (!(adev->powerplay.pp_funcs &&
1091               adev->powerplay.pp_funcs->read_sensor))
1092               return -EINVAL;
1093
1094         /* get the voltage */
1095         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
1096                                    (void *)&vddgfx, &size);
1097         if (r)
1098                 return r;
1099
1100         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
1101 }
1102
1103 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
1104                                               struct device_attribute *attr,
1105                                               char *buf)
1106 {
1107         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
1108 }
1109
1110 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
1111                                        struct device_attribute *attr,
1112                                        char *buf)
1113 {
1114         struct amdgpu_device *adev = dev_get_drvdata(dev);
1115         struct drm_device *ddev = adev->ddev;
1116         u32 vddnb;
1117         int r, size = sizeof(vddnb);
1118
1119         /* only APUs have vddnb */
1120         if  (adev->flags & AMD_IS_APU)
1121                 return -EINVAL;
1122
1123         /* Can't get voltage when the card is off */
1124         if  ((adev->flags & AMD_IS_PX) &&
1125              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1126                 return -EINVAL;
1127
1128         /* sanity check PP is enabled */
1129         if (!(adev->powerplay.pp_funcs &&
1130               adev->powerplay.pp_funcs->read_sensor))
1131               return -EINVAL;
1132
1133         /* get the voltage */
1134         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
1135                                    (void *)&vddnb, &size);
1136         if (r)
1137                 return r;
1138
1139         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
1140 }
1141
1142 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
1143                                               struct device_attribute *attr,
1144                                               char *buf)
1145 {
1146         return snprintf(buf, PAGE_SIZE, "vddnb\n");
1147 }
1148
1149 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
1150                                            struct device_attribute *attr,
1151                                            char *buf)
1152 {
1153         struct amdgpu_device *adev = dev_get_drvdata(dev);
1154         struct drm_device *ddev = adev->ddev;
1155         u32 query = 0;
1156         int r, size = sizeof(u32);
1157         unsigned uw;
1158
1159         /* Can't get power when the card is off */
1160         if  ((adev->flags & AMD_IS_PX) &&
1161              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
1162                 return -EINVAL;
1163
1164         /* sanity check PP is enabled */
1165         if (!(adev->powerplay.pp_funcs &&
1166               adev->powerplay.pp_funcs->read_sensor))
1167               return -EINVAL;
1168
1169         /* get the voltage */
1170         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
1171                                    (void *)&query, &size);
1172         if (r)
1173                 return r;
1174
1175         /* convert to microwatts */
1176         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
1177
1178         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
1179 }
1180
1181 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
1182                                          struct device_attribute *attr,
1183                                          char *buf)
1184 {
1185         return sprintf(buf, "%i\n", 0);
1186 }
1187
1188 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
1189                                          struct device_attribute *attr,
1190                                          char *buf)
1191 {
1192         struct amdgpu_device *adev = dev_get_drvdata(dev);
1193         uint32_t limit = 0;
1194
1195         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1196                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
1197                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1198         } else {
1199                 return snprintf(buf, PAGE_SIZE, "\n");
1200         }
1201 }
1202
1203 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
1204                                          struct device_attribute *attr,
1205                                          char *buf)
1206 {
1207         struct amdgpu_device *adev = dev_get_drvdata(dev);
1208         uint32_t limit = 0;
1209
1210         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
1211                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
1212                 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
1213         } else {
1214                 return snprintf(buf, PAGE_SIZE, "\n");
1215         }
1216 }
1217
1218
1219 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
1220                 struct device_attribute *attr,
1221                 const char *buf,
1222                 size_t count)
1223 {
1224         struct amdgpu_device *adev = dev_get_drvdata(dev);
1225         int err;
1226         u32 value;
1227
1228         err = kstrtou32(buf, 10, &value);
1229         if (err)
1230                 return err;
1231
1232         value = value / 1000000; /* convert to Watt */
1233         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) {
1234                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
1235                 if (err)
1236                         return err;
1237         } else {
1238                 return -EINVAL;
1239         }
1240
1241         return count;
1242 }
1243
1244
1245 /**
1246  * DOC: hwmon
1247  *
1248  * The amdgpu driver exposes the following sensor interfaces:
1249  * - GPU temperature (via the on-die sensor)
1250  * - GPU voltage
1251  * - Northbridge voltage (APUs only)
1252  * - GPU power
1253  * - GPU fan
1254  *
1255  * hwmon interfaces for GPU temperature:
1256  * - temp1_input: the on die GPU temperature in millidegrees Celsius
1257  * - temp1_crit: temperature critical max value in millidegrees Celsius
1258  * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
1259  *
1260  * hwmon interfaces for GPU voltage:
1261  * - in0_input: the voltage on the GPU in millivolts
1262  * - in1_input: the voltage on the Northbridge in millivolts
1263  *
1264  * hwmon interfaces for GPU power:
1265  * - power1_average: average power used by the GPU in microWatts
1266  * - power1_cap_min: minimum cap supported in microWatts
1267  * - power1_cap_max: maximum cap supported in microWatts
1268  * - power1_cap: selected power cap in microWatts
1269  *
1270  * hwmon interfaces for GPU fan:
1271  * - pwm1: pulse width modulation fan level (0-255)
1272  * - pwm1_enable: pulse width modulation fan control method
1273  *                0: no fan speed control
1274  *                1: manual fan speed control using pwm interface
1275  *                2: automatic fan speed control
1276  * - pwm1_min: pulse width modulation fan control minimum level (0)
1277  * - pwm1_max: pulse width modulation fan control maximum level (255)
1278  * - fan1_input: fan speed in RPM
1279  *
1280  * You can use hwmon tools like sensors to view this information on your system.
1281  *
1282  */
1283
1284 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
1285 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
1286 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
1287 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
1288 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
1289 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
1290 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
1291 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
1292 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
1293 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
1294 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
1295 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
1296 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
1297 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
1298 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
1299 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
1300
1301 static struct attribute *hwmon_attributes[] = {
1302         &sensor_dev_attr_temp1_input.dev_attr.attr,
1303         &sensor_dev_attr_temp1_crit.dev_attr.attr,
1304         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
1305         &sensor_dev_attr_pwm1.dev_attr.attr,
1306         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
1307         &sensor_dev_attr_pwm1_min.dev_attr.attr,
1308         &sensor_dev_attr_pwm1_max.dev_attr.attr,
1309         &sensor_dev_attr_fan1_input.dev_attr.attr,
1310         &sensor_dev_attr_in0_input.dev_attr.attr,
1311         &sensor_dev_attr_in0_label.dev_attr.attr,
1312         &sensor_dev_attr_in1_input.dev_attr.attr,
1313         &sensor_dev_attr_in1_label.dev_attr.attr,
1314         &sensor_dev_attr_power1_average.dev_attr.attr,
1315         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
1316         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
1317         &sensor_dev_attr_power1_cap.dev_attr.attr,
1318         NULL
1319 };
1320
1321 static umode_t hwmon_attributes_visible(struct kobject *kobj,
1322                                         struct attribute *attr, int index)
1323 {
1324         struct device *dev = kobj_to_dev(kobj);
1325         struct amdgpu_device *adev = dev_get_drvdata(dev);
1326         umode_t effective_mode = attr->mode;
1327
1328         /* handle non-powerplay limitations */
1329         if (!adev->powerplay.pp_handle) {
1330                 /* Skip fan attributes if fan is not present */
1331                 if (adev->pm.no_fan &&
1332                     (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1333                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1334                      attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1335                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1336                         return 0;
1337                 /* requires powerplay */
1338                 if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1339                         return 0;
1340         }
1341
1342         /* Skip limit attributes if DPM is not enabled */
1343         if (!adev->pm.dpm_enabled &&
1344             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
1345              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
1346              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1347              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1348              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1349              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1350                 return 0;
1351
1352         /* mask fan attributes if we have no bindings for this asic to expose */
1353         if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
1354              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1355             (!adev->powerplay.pp_funcs->get_fan_control_mode &&
1356              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1357                 effective_mode &= ~S_IRUGO;
1358
1359         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1360              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1361             (!adev->powerplay.pp_funcs->set_fan_control_mode &&
1362              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1363                 effective_mode &= ~S_IWUSR;
1364
1365         if ((adev->flags & AMD_IS_APU) &&
1366             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
1367              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
1368              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
1369                 return 0;
1370
1371         /* hide max/min values if we can't both query and manage the fan */
1372         if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
1373              !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
1374             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1375              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1376                 return 0;
1377
1378         /* only APUs have vddnb */
1379         if (!(adev->flags & AMD_IS_APU) &&
1380             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
1381              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
1382                 return 0;
1383
1384         return effective_mode;
1385 }
1386
1387 static const struct attribute_group hwmon_attrgroup = {
1388         .attrs = hwmon_attributes,
1389         .is_visible = hwmon_attributes_visible,
1390 };
1391
1392 static const struct attribute_group *hwmon_groups[] = {
1393         &hwmon_attrgroup,
1394         NULL
1395 };
1396
1397 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1398 {
1399         struct amdgpu_device *adev =
1400                 container_of(work, struct amdgpu_device,
1401                              pm.dpm.thermal.work);
1402         /* switch to the thermal state */
1403         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1404         int temp, size = sizeof(temp);
1405
1406         if (!adev->pm.dpm_enabled)
1407                 return;
1408
1409         if (adev->powerplay.pp_funcs &&
1410             adev->powerplay.pp_funcs->read_sensor &&
1411             !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
1412                                     (void *)&temp, &size)) {
1413                 if (temp < adev->pm.dpm.thermal.min_temp)
1414                         /* switch back the user state */
1415                         dpm_state = adev->pm.dpm.user_state;
1416         } else {
1417                 if (adev->pm.dpm.thermal.high_to_low)
1418                         /* switch back the user state */
1419                         dpm_state = adev->pm.dpm.user_state;
1420         }
1421         mutex_lock(&adev->pm.mutex);
1422         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1423                 adev->pm.dpm.thermal_active = true;
1424         else
1425                 adev->pm.dpm.thermal_active = false;
1426         adev->pm.dpm.state = dpm_state;
1427         mutex_unlock(&adev->pm.mutex);
1428
1429         amdgpu_pm_compute_clocks(adev);
1430 }
1431
1432 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1433                                                      enum amd_pm_state_type dpm_state)
1434 {
1435         int i;
1436         struct amdgpu_ps *ps;
1437         u32 ui_class;
1438         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1439                 true : false;
1440
1441         /* check if the vblank period is too short to adjust the mclk */
1442         if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
1443                 if (amdgpu_dpm_vblank_too_short(adev))
1444                         single_display = false;
1445         }
1446
1447         /* certain older asics have a separare 3D performance state,
1448          * so try that first if the user selected performance
1449          */
1450         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1451                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1452         /* balanced states don't exist at the moment */
1453         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1454                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1455
1456 restart_search:
1457         /* Pick the best power state based on current conditions */
1458         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1459                 ps = &adev->pm.dpm.ps[i];
1460                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1461                 switch (dpm_state) {
1462                 /* user states */
1463                 case POWER_STATE_TYPE_BATTERY:
1464                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1465                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1466                                         if (single_display)
1467                                                 return ps;
1468                                 } else
1469                                         return ps;
1470                         }
1471                         break;
1472                 case POWER_STATE_TYPE_BALANCED:
1473                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1474                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1475                                         if (single_display)
1476                                                 return ps;
1477                                 } else
1478                                         return ps;
1479                         }
1480                         break;
1481                 case POWER_STATE_TYPE_PERFORMANCE:
1482                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1483                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1484                                         if (single_display)
1485                                                 return ps;
1486                                 } else
1487                                         return ps;
1488                         }
1489                         break;
1490                 /* internal states */
1491                 case POWER_STATE_TYPE_INTERNAL_UVD:
1492                         if (adev->pm.dpm.uvd_ps)
1493                                 return adev->pm.dpm.uvd_ps;
1494                         else
1495                                 break;
1496                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1497                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1498                                 return ps;
1499                         break;
1500                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1501                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1502                                 return ps;
1503                         break;
1504                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1505                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1506                                 return ps;
1507                         break;
1508                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1509                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1510                                 return ps;
1511                         break;
1512                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1513                         return adev->pm.dpm.boot_ps;
1514                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1515                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1516                                 return ps;
1517                         break;
1518                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1519                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1520                                 return ps;
1521                         break;
1522                 case POWER_STATE_TYPE_INTERNAL_ULV:
1523                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1524                                 return ps;
1525                         break;
1526                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1527                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1528                                 return ps;
1529                         break;
1530                 default:
1531                         break;
1532                 }
1533         }
1534         /* use a fallback state if we didn't match */
1535         switch (dpm_state) {
1536         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1537                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1538                 goto restart_search;
1539         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1540         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1541         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1542                 if (adev->pm.dpm.uvd_ps) {
1543                         return adev->pm.dpm.uvd_ps;
1544                 } else {
1545                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1546                         goto restart_search;
1547                 }
1548         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1549                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1550                 goto restart_search;
1551         case POWER_STATE_TYPE_INTERNAL_ACPI:
1552                 dpm_state = POWER_STATE_TYPE_BATTERY;
1553                 goto restart_search;
1554         case POWER_STATE_TYPE_BATTERY:
1555         case POWER_STATE_TYPE_BALANCED:
1556         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1557                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1558                 goto restart_search;
1559         default:
1560                 break;
1561         }
1562
1563         return NULL;
1564 }
1565
1566 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1567 {
1568         struct amdgpu_ps *ps;
1569         enum amd_pm_state_type dpm_state;
1570         int ret;
1571         bool equal = false;
1572
1573         /* if dpm init failed */
1574         if (!adev->pm.dpm_enabled)
1575                 return;
1576
1577         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1578                 /* add other state override checks here */
1579                 if ((!adev->pm.dpm.thermal_active) &&
1580                     (!adev->pm.dpm.uvd_active))
1581                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1582         }
1583         dpm_state = adev->pm.dpm.state;
1584
1585         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1586         if (ps)
1587                 adev->pm.dpm.requested_ps = ps;
1588         else
1589                 return;
1590
1591         if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
1592                 printk("switching from power state:\n");
1593                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1594                 printk("switching to power state:\n");
1595                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1596         }
1597
1598         /* update whether vce is active */
1599         ps->vce_active = adev->pm.dpm.vce_active;
1600         if (adev->powerplay.pp_funcs->display_configuration_changed)
1601                 amdgpu_dpm_display_configuration_changed(adev);
1602
1603         ret = amdgpu_dpm_pre_set_power_state(adev);
1604         if (ret)
1605                 return;
1606
1607         if (adev->powerplay.pp_funcs->check_state_equal) {
1608                 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
1609                         equal = false;
1610         }
1611
1612         if (equal)
1613                 return;
1614
1615         amdgpu_dpm_set_power_state(adev);
1616         amdgpu_dpm_post_set_power_state(adev);
1617
1618         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1619         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1620
1621         if (adev->powerplay.pp_funcs->force_performance_level) {
1622                 if (adev->pm.dpm.thermal_active) {
1623                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1624                         /* force low perf level for thermal */
1625                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1626                         /* save the user's level */
1627                         adev->pm.dpm.forced_level = level;
1628                 } else {
1629                         /* otherwise, user selected level */
1630                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1631                 }
1632         }
1633 }
1634
1635 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1636 {
1637         if (adev->powerplay.pp_funcs->powergate_uvd) {
1638                 /* enable/disable UVD */
1639                 mutex_lock(&adev->pm.mutex);
1640                 amdgpu_dpm_powergate_uvd(adev, !enable);
1641                 mutex_unlock(&adev->pm.mutex);
1642         } else {
1643                 if (enable) {
1644                         mutex_lock(&adev->pm.mutex);
1645                         adev->pm.dpm.uvd_active = true;
1646                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1647                         mutex_unlock(&adev->pm.mutex);
1648                 } else {
1649                         mutex_lock(&adev->pm.mutex);
1650                         adev->pm.dpm.uvd_active = false;
1651                         mutex_unlock(&adev->pm.mutex);
1652                 }
1653                 amdgpu_pm_compute_clocks(adev);
1654         }
1655 }
1656
1657 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1658 {
1659         if (adev->powerplay.pp_funcs->powergate_vce) {
1660                 /* enable/disable VCE */
1661                 mutex_lock(&adev->pm.mutex);
1662                 amdgpu_dpm_powergate_vce(adev, !enable);
1663                 mutex_unlock(&adev->pm.mutex);
1664         } else {
1665                 if (enable) {
1666                         mutex_lock(&adev->pm.mutex);
1667                         adev->pm.dpm.vce_active = true;
1668                         /* XXX select vce level based on ring/task */
1669                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1670                         mutex_unlock(&adev->pm.mutex);
1671                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1672                                                                AMD_CG_STATE_UNGATE);
1673                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1674                                                                AMD_PG_STATE_UNGATE);
1675                         amdgpu_pm_compute_clocks(adev);
1676                 } else {
1677                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1678                                                                AMD_PG_STATE_GATE);
1679                         amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1680                                                                AMD_CG_STATE_GATE);
1681                         mutex_lock(&adev->pm.mutex);
1682                         adev->pm.dpm.vce_active = false;
1683                         mutex_unlock(&adev->pm.mutex);
1684                         amdgpu_pm_compute_clocks(adev);
1685                 }
1686
1687         }
1688 }
1689
1690 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1691 {
1692         int i;
1693
1694         if (adev->powerplay.pp_funcs->print_power_state == NULL)
1695                 return;
1696
1697         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1698                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1699
1700 }
1701
1702 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1703 {
1704         int ret;
1705
1706         if (adev->pm.sysfs_initialized)
1707                 return 0;
1708
1709         if (adev->pm.dpm_enabled == 0)
1710                 return 0;
1711
1712         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1713                                                                    DRIVER_NAME, adev,
1714                                                                    hwmon_groups);
1715         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1716                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1717                 dev_err(adev->dev,
1718                         "Unable to register hwmon device: %d\n", ret);
1719                 return ret;
1720         }
1721
1722         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1723         if (ret) {
1724                 DRM_ERROR("failed to create device file for dpm state\n");
1725                 return ret;
1726         }
1727         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1728         if (ret) {
1729                 DRM_ERROR("failed to create device file for dpm state\n");
1730                 return ret;
1731         }
1732
1733
1734         ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1735         if (ret) {
1736                 DRM_ERROR("failed to create device file pp_num_states\n");
1737                 return ret;
1738         }
1739         ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1740         if (ret) {
1741                 DRM_ERROR("failed to create device file pp_cur_state\n");
1742                 return ret;
1743         }
1744         ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1745         if (ret) {
1746                 DRM_ERROR("failed to create device file pp_force_state\n");
1747                 return ret;
1748         }
1749         ret = device_create_file(adev->dev, &dev_attr_pp_table);
1750         if (ret) {
1751                 DRM_ERROR("failed to create device file pp_table\n");
1752                 return ret;
1753         }
1754
1755         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1756         if (ret) {
1757                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1758                 return ret;
1759         }
1760         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1761         if (ret) {
1762                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1763                 return ret;
1764         }
1765         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1766         if (ret) {
1767                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1768                 return ret;
1769         }
1770         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1771         if (ret) {
1772                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1773                 return ret;
1774         }
1775         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1776         if (ret) {
1777                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1778                 return ret;
1779         }
1780         ret = device_create_file(adev->dev,
1781                         &dev_attr_pp_power_profile_mode);
1782         if (ret) {
1783                 DRM_ERROR("failed to create device file "
1784                                 "pp_power_profile_mode\n");
1785                 return ret;
1786         }
1787         ret = device_create_file(adev->dev,
1788                         &dev_attr_pp_od_clk_voltage);
1789         if (ret) {
1790                 DRM_ERROR("failed to create device file "
1791                                 "pp_od_clk_voltage\n");
1792                 return ret;
1793         }
1794         ret = amdgpu_debugfs_pm_init(adev);
1795         if (ret) {
1796                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1797                 return ret;
1798         }
1799
1800         adev->pm.sysfs_initialized = true;
1801
1802         return 0;
1803 }
1804
1805 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1806 {
1807         if (adev->pm.dpm_enabled == 0)
1808                 return;
1809
1810         if (adev->pm.int_hwmon_dev)
1811                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1812         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1813         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1814
1815         device_remove_file(adev->dev, &dev_attr_pp_num_states);
1816         device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1817         device_remove_file(adev->dev, &dev_attr_pp_force_state);
1818         device_remove_file(adev->dev, &dev_attr_pp_table);
1819
1820         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1821         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1822         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1823         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1824         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1825         device_remove_file(adev->dev,
1826                         &dev_attr_pp_power_profile_mode);
1827         device_remove_file(adev->dev,
1828                         &dev_attr_pp_od_clk_voltage);
1829 }
1830
1831 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1832 {
1833         int i = 0;
1834
1835         if (!adev->pm.dpm_enabled)
1836                 return;
1837
1838         if (adev->mode_info.num_crtc)
1839                 amdgpu_display_bandwidth_update(adev);
1840
1841         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1842                 struct amdgpu_ring *ring = adev->rings[i];
1843                 if (ring && ring->ready)
1844                         amdgpu_fence_wait_empty(ring);
1845         }
1846
1847         if (!amdgpu_device_has_dc_support(adev)) {
1848                 mutex_lock(&adev->pm.mutex);
1849                 amdgpu_dpm_get_active_displays(adev);
1850                 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtcs;
1851                 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1852                 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1853                 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */
1854                 if (adev->pm.pm_display_cfg.vrefresh > 120)
1855                         adev->pm.pm_display_cfg.min_vblank_time = 0;
1856                 if (adev->powerplay.pp_funcs->display_configuration_change)
1857                         adev->powerplay.pp_funcs->display_configuration_change(
1858                                                         adev->powerplay.pp_handle,
1859                                                         &adev->pm.pm_display_cfg);
1860                 mutex_unlock(&adev->pm.mutex);
1861         }
1862
1863         if (adev->powerplay.pp_funcs->dispatch_tasks) {
1864                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL);
1865         } else {
1866                 mutex_lock(&adev->pm.mutex);
1867                 /* update battery/ac status */
1868                 if (power_supply_is_system_supplied() > 0)
1869                         adev->pm.dpm.ac_power = true;
1870                 else
1871                         adev->pm.dpm.ac_power = false;
1872
1873                 amdgpu_dpm_change_power_state_locked(adev);
1874
1875                 mutex_unlock(&adev->pm.mutex);
1876         }
1877 }
1878
1879 /*
1880  * Debugfs info
1881  */
1882 #if defined(CONFIG_DEBUG_FS)
1883
1884 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1885 {
1886         uint32_t value;
1887         uint32_t query = 0;
1888         int size;
1889
1890         /* sanity check PP is enabled */
1891         if (!(adev->powerplay.pp_funcs &&
1892               adev->powerplay.pp_funcs->read_sensor))
1893               return -EINVAL;
1894
1895         /* GPU Clocks */
1896         size = sizeof(value);
1897         seq_printf(m, "GFX Clocks and Power:\n");
1898         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1899                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1900         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1901                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1902         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
1903                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
1904         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
1905                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
1906         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1907                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1908         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1909                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1910         size = sizeof(uint32_t);
1911         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
1912                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
1913         size = sizeof(value);
1914         seq_printf(m, "\n");
1915
1916         /* GPU Temp */
1917         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1918                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1919
1920         /* GPU Load */
1921         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1922                 seq_printf(m, "GPU Load: %u %%\n", value);
1923         seq_printf(m, "\n");
1924
1925         /* UVD clocks */
1926         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1927                 if (!value) {
1928                         seq_printf(m, "UVD: Disabled\n");
1929                 } else {
1930                         seq_printf(m, "UVD: Enabled\n");
1931                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1932                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1933                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1934                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1935                 }
1936         }
1937         seq_printf(m, "\n");
1938
1939         /* VCE clocks */
1940         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1941                 if (!value) {
1942                         seq_printf(m, "VCE: Disabled\n");
1943                 } else {
1944                         seq_printf(m, "VCE: Enabled\n");
1945                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1946                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1947                 }
1948         }
1949
1950         return 0;
1951 }
1952
1953 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1954 {
1955         int i;
1956
1957         for (i = 0; clocks[i].flag; i++)
1958                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1959                            (flags & clocks[i].flag) ? "On" : "Off");
1960 }
1961
1962 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1963 {
1964         struct drm_info_node *node = (struct drm_info_node *) m->private;
1965         struct drm_device *dev = node->minor->dev;
1966         struct amdgpu_device *adev = dev->dev_private;
1967         struct drm_device *ddev = adev->ddev;
1968         u32 flags = 0;
1969
1970         amdgpu_device_ip_get_clockgating_state(adev, &flags);
1971         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1972         amdgpu_parse_cg_state(m, flags);
1973         seq_printf(m, "\n");
1974
1975         if (!adev->pm.dpm_enabled) {
1976                 seq_printf(m, "dpm not enabled\n");
1977                 return 0;
1978         }
1979         if  ((adev->flags & AMD_IS_PX) &&
1980              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1981                 seq_printf(m, "PX asic powered off\n");
1982         } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
1983                 mutex_lock(&adev->pm.mutex);
1984                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
1985                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
1986                 else
1987                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1988                 mutex_unlock(&adev->pm.mutex);
1989         } else {
1990                 return amdgpu_debugfs_pm_info_pp(m, adev);
1991         }
1992
1993         return 0;
1994 }
1995
1996 static const struct drm_info_list amdgpu_pm_info_list[] = {
1997         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1998 };
1999 #endif
2000
2001 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
2002 {
2003 #if defined(CONFIG_DEBUG_FS)
2004         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
2005 #else
2006         return 0;
2007 #endif
2008 }