1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Definitions for EMU10K1 (SB Live!) chips
7 #ifndef __SOUND_EMU10K1_H
8 #define __SOUND_EMU10K1_H
11 #include <sound/pcm.h>
12 #include <sound/rawmidi.h>
13 #include <sound/hwdep.h>
14 #include <sound/ac97_codec.h>
15 #include <sound/util_mem.h>
16 #include <sound/pcm-indirect.h>
17 #include <sound/timer.h>
18 #include <linux/interrupt.h>
19 #include <linux/mutex.h>
20 #include <linux/firmware.h>
23 #include <uapi/sound/emu10k1.h>
25 /* ------------------- DEFINES -------------------- */
27 #define EMUPAGESIZE 4096
28 #define MAXPAGES0 4096 /* 32 bit mode */
29 #define MAXPAGES1 8192 /* 31 bit mode */
30 #define NUM_G 64 /* use all channels */
31 #define NUM_EFX_PLAYBACK 16
33 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
34 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
37 #define TMEMSIZE 256*1024
39 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
41 // Audigy specify registers are prefixed with 'A_'
43 /************************************************************************************************/
44 /* PCI function 0 registers, address = <val> + PCIBASE0 */
45 /************************************************************************************************/
47 #define PTR 0x00 /* Indexed register set pointer register */
48 /* NOTE: The CHANNELNUM and ADDRESS words can */
49 /* be modified independently of each other. */
50 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
51 /* channel number of the register to be */
52 /* accessed. For non per-channel registers the */
53 /* value should be set to zero. */
54 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
55 #define A_PTR_ADDRESS_MASK 0x0fff0000
57 #define DATA 0x04 /* Indexed register set data register */
59 #define IPR 0x08 /* Global interrupt pending register */
60 /* Clear pending interrupts by writing a 1 to */
61 /* the relevant bits and zero to the other bits */
62 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
64 #define IPR_WATERMARK_REACHED 0x40000000
65 #define IPR_A_GPIO 0x20000000 /* GPIO input pin change */
67 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
68 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
69 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
71 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
72 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
74 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
75 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
76 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
77 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
78 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
79 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
80 #define IPR_MUTE 0x00040000 /* Mute button pressed */
81 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
82 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
83 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
84 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
85 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
86 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
87 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
88 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
89 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
90 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
91 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
92 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
93 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
94 /* highest set channel in CLIPL, CLIPH, HLIPL, */
95 /* or HLIPH. When IPR is written with CL set, */
96 /* the bit in H/CLIPL or H/CLIPH corresponding */
97 /* to the CN value written will be cleared. */
99 #define INTE 0x0c /* Interrupt enable register */
100 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
101 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
102 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
103 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
104 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
105 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
106 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
107 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
108 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
109 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
110 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
111 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
112 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
113 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
114 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
115 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
116 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
117 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
119 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
120 /* NOTE: There is no reason to use this under */
121 /* Linux, and it will cause odd hardware */
122 /* behavior and possibly random segfaults and */
123 /* lockups if enabled. */
125 #define INTE_A_GPIOENABLE 0x00040000 /* Enable GPIO input change interrupts */
127 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
128 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
129 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
131 #define INTE_A_SPDIF_BUFFULL_ENABLE 0x00008000
132 #define INTE_A_SPDIF_HALFBUFFULL_ENABLE 0x00004000
134 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
135 /* NOTE: This bit must always be enabled */
136 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
137 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
138 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
139 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
140 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
141 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
142 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
143 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
144 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
145 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
146 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
147 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
148 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
150 #define WC 0x10 /* Wall Clock register */
151 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
152 #define WC_SAMPLECOUNTER 0x14060010
153 #define WC_CURRENTCHANNEL_MASK 0x0000003F /* Channel [0..63] currently being serviced */
154 /* NOTE: Each channel takes 1/64th of a sample */
155 /* period to be serviced. */
156 #define WC_CURRENTCHANNEL 0x06000010
158 #define HCFG 0x14 /* Hardware config register */
159 /* NOTE: There is no reason to use the legacy */
160 /* SoundBlaster emulation stuff described below */
161 /* under Linux, and all kinds of weird hardware */
162 /* behavior can result if you try. Don't. */
163 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
164 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
165 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
166 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
167 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
168 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
169 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
170 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
171 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
172 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
173 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
174 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
175 /* NOTE: The rest of the bits in this register */
176 /* _are_ relevant under Linux. */
177 #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
178 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
179 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
180 #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
182 /* Specific to Alice2, CA0102 */
184 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
185 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
186 #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
187 /* will automatically mute their output when */
188 /* they are not rate-locked to the external */
189 /* async audio source */
190 #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
191 /* will automatically mute their output when */
192 /* the SPDIF V-bit indicates invalid audio */
193 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
194 #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
195 /* 0x00000800 not used on Alice2 */
196 #define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
197 /* phase track the previous input. */
198 /* I2S0 can phase track the last S/PDIF input */
199 #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
200 /* conversion for the corresponding */
201 /* I2S format input */
202 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
206 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
207 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
208 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
209 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
210 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
211 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
212 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
213 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
214 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
215 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
216 /* 1 = Force all 3 async digital inputs to use */
217 /* the same async sample rate tracker (ZVIDEO) */
218 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
219 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
220 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
221 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
222 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
223 /* will automatically mute their output when */
224 /* they are not rate-locked to the external */
225 /* async audio source */
226 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
227 /* NOTE: This should generally never be used. */
228 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
229 /* NOTE: This should generally never be used. */
230 #define HCFG_LOCKTANKCACHE 0x01020014
231 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
232 /* NOTE: This is a 'cheap' way to implement a */
233 /* master mute function on the mute button, and */
234 /* in general should not be used unless a more */
235 /* sophisticated master mute function has not */
237 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
238 /* Should be set to 1 when the EMU10K1 is */
239 /* completely initialized. */
241 // On Audigy, the MPU port moved to the 0x70-0x74 ptr registers
243 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
245 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
246 #define MUCMD_RESET 0xff /* RESET command */
247 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
248 /* NOTE: All other commands are ignored */
250 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
251 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
252 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
254 #define A_GPIO 0x18 /* GPIO on Audigy card (16bits) */
255 #define A_GPINPUT_MASK 0xff00 /* Alice/2 has 8 input pins */
256 #define A3_GPINPUT_MASK 0x3f00 /* ... while Tina/2 has only 6 */
257 #define A_GPOUTPUT_MASK 0x00ff
259 // The GPIO port is used for I/O config on Sound Blasters;
260 // card-specific info can be found in the emu_chip_details table.
261 // On E-MU cards the port is used as the interface to the FPGA.
263 // Audigy output/GPIO stuff taken from the kX drivers
264 #define A_IOCFG A_GPIO
265 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
266 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
267 #define A_IOCFG_ENABLE_DIGITAL 0x0004
268 #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
269 #define A_IOCFG_UNKNOWN_20 0x0020
270 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
271 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
272 #define A_IOCFG_GPOUT2 0x0001 /* IR */
273 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
274 /* + digital for generic 10k2 */
275 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
276 #define A_IOCFG_FRONT_JACK 0x4000
277 #define A_IOCFG_REAR_JACK 0x8000
278 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
280 #define TIMER 0x1a /* Timer terminal count register */
281 /* NOTE: After the rate is changed, a maximum */
282 /* of 1024 sample periods should be allowed */
283 /* before the new rate is guaranteed accurate. */
284 #define TIMER_RATE_MASK 0x03ff /* Timer interrupt rate in sample periods */
285 /* 0 == 1024 periods, [1..4] are not useful */
287 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
289 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
290 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
291 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
293 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
294 #define PTR2 0x20 /* Indexed register set pointer register */
295 #define DATA2 0x24 /* Indexed register set data register */
296 #define IPR2 0x28 /* P16V interrupt pending register */
297 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
298 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
299 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
300 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
301 /* 0x00000100 Playback. Only in once per period.
302 * 0x00110000 Capture. Int on half buffer.
304 #define INTE2 0x2c /* P16V Interrupt enable register. */
305 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
306 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
307 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
308 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
309 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
310 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
311 #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
312 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
313 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
314 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
315 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
316 /* 0x00000000 2-channel output. */
317 /* 0x00000200 8-channel output. */
318 /* 0x00000004 pauses stream/irq fail. */
319 /* Rest of bits do nothing to sound output */
320 /* bit 0: Enable P16V audio.
321 * bit 1: Lock P16V record memory cache.
322 * bit 2: Lock P16V playback memory cache.
323 * bit 3: Dummy record insert zero samples.
324 * bit 8: Record 8-channel in phase.
325 * bit 9: Playback 8-channel in phase.
326 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
327 * bit 13: Playback mixer enable.
328 * bit 14: Route SRC48 mixer output to fx engine.
329 * bit 15: Enable IEEE 1394 chip.
331 #define IPR3 0x38 /* Cdif interrupt pending register */
332 #define INTE3 0x3c /* Cdif interrupt enable register. */
334 /************************************************************************************************/
335 /* PCI function 1 registers, address = <val> + PCIBASE1 */
336 /************************************************************************************************/
338 #define JOYSTICK1 0x00 /* Analog joystick port register */
339 #define JOYSTICK2 0x01 /* Analog joystick port register */
340 #define JOYSTICK3 0x02 /* Analog joystick port register */
341 #define JOYSTICK4 0x03 /* Analog joystick port register */
342 #define JOYSTICK5 0x04 /* Analog joystick port register */
343 #define JOYSTICK6 0x05 /* Analog joystick port register */
344 #define JOYSTICK7 0x06 /* Analog joystick port register */
345 #define JOYSTICK8 0x07 /* Analog joystick port register */
347 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
348 /* When reading, use these bitfields: */
349 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
350 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
352 /********************************************************************************************************/
353 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
354 /********************************************************************************************************/
356 // No official documentation was released for EMU10K1, but some info
357 // about playback can be extrapolated from the EMU8K documents:
358 // "AWE32/EMU8000 Programmer’s Guide" (emu8kpgm.pdf) - registers
359 // "AWE32 Developer's Information Pack" (adip301.pdf) - high-level view
361 // The short version:
362 // - The engine has 64 playback channels, also called voices. The channels
363 // operate independently, except when paired for stereo (see below).
364 // - PCM samples are fetched into the cache; see description of CD0 below.
365 // - Samples are consumed at the rate CPF_CURRENTPITCH.
366 // - 8-bit samples are transformed upon use: cooked = (raw ^ 0x80) << 8
367 // - 8 samples are read at CCR_READADDRESS:CPF_FRACADDRESS and interpolated
368 // according to CCCA_INTERPROM_*. With CCCA_INTERPROM_0 selected and a zero
369 // CPF_FRACADDRESS, this results in CCR_READADDRESS[3] being used verbatim.
370 // - The value is multiplied by CVCF_CURRENTVOL.
371 // - The value goes through a filter with cutoff CVCF_CURRENTFILTER;
372 // delay stages Z1 and Z2.
373 // - The value is added by so-called `sends` to 4 (EMU10K1) / 8 (EMU10K2)
374 // of the 16 (EMU10K1) / 64 (EMU10K2) FX bus accumulators via FXRT*,
375 // multiplied by a per-send amount (*_FXSENDAMOUNT_*).
376 // The scaling of the send amounts is exponential-ish.
377 // - The DSP has a go at FXBUS* and outputs the values to EXTOUT* or EMU32OUT*.
378 // - The pitch, volume, and filter cutoff can be modulated by two envelope
379 // engines and two low frequency oscillators.
380 // - To avoid abrupt changes to the parameters (which may cause audible
381 // distortion), the modulation engine sets the target registers, towards
382 // which the current registers "swerve" gradually.
384 #define CPF 0x00 /* Current pitch and fraction register */
385 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
386 #define CPF_CURRENTPITCH 0x10100000
387 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
388 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
389 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
391 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
392 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
393 #define PTRX_PITCHTARGET 0x10100001
394 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
395 #define PTRX_FXSENDAMOUNT_A 0x08080001
396 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
397 #define PTRX_FXSENDAMOUNT_B 0x08000001
399 #define CVCF 0x02 /* Current volume and filter cutoff register */
400 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
401 #define CVCF_CURRENTVOL 0x10100002
402 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
403 #define CVCF_CURRENTFILTER 0x10000002
405 #define VTFT 0x03 /* Volume target and filter cutoff target register */
406 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
407 #define VTFT_VOLUMETARGET 0x10100003
408 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
409 #define VTFT_FILTERTARGET 0x10000003
411 #define Z1 0x05 /* Filter delay memory 1 register */
413 #define Z2 0x04 /* Filter delay memory 2 register */
415 #define PSST 0x06 /* Send C amount and loop start address register */
416 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
418 #define PSST_FXSENDAMOUNT_C 0x08180006
420 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
421 #define PSST_LOOPSTARTADDR 0x18000006
423 #define DSL 0x07 /* Send D amount and loop end address register */
424 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
426 #define DSL_FXSENDAMOUNT_D 0x08180007
428 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
429 #define DSL_LOOPENDADDR 0x18000007
431 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
432 #define CCCA_RESONANCE_MASK 0xf0000000 /* Lowpass filter resonance (Q) height */
433 #define CCCA_RESONANCE 0x041c0008
434 #define CCCA_INTERPROM_MASK 0x0e000000 /* Selects passband of interpolation ROM */
435 /* 1 == full band, 7 == lowpass */
436 /* ROM 0 is used when pitch shifting downward or less */
437 /* then 3 semitones upward. Increasingly higher ROM */
438 /* numbers are used, typically in steps of 3 semitones, */
439 /* as upward pitch shifting is performed. */
440 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
441 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
442 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
443 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
444 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
445 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
446 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
447 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
448 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
449 /* 8-bit samples are unsigned, 16-bit ones signed */
450 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
451 #define CCCA_CURRADDR 0x18000008
453 #define CCR 0x09 /* Cache control register */
454 #define CCR_CACHEINVALIDSIZE 0x07190009
455 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples before the read address */
456 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
457 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
458 /* Auto-set from CPF_STEREO_MASK */
459 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
460 /* Auto-set from CCCA_8BITSELECT */
461 #define CCR_READADDRESS 0x06100009
462 #define CCR_READADDRESS_MASK 0x003f0000 /* Next cached sample to play */
463 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
464 /* NOTE: This is valid only if CACHELOOPFLAG is set */
465 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
466 #define CCR_CACHELOOPADDRHI 0x000000ff /* CLP_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
468 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
469 /* NOTE: This register is normally not used */
470 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address low word */
472 #define FXRT 0x0b /* Effects send routing register */
473 /* NOTE: It is illegal to assign the same routing to */
474 /* two effects sends. */
475 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
476 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
477 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
478 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
480 #define MAPA 0x0c /* Cache map A */
481 #define MAPB 0x0d /* Cache map B */
483 #define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */
484 #define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */
486 #define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
487 #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
489 /* 0x0e, 0x0f: Internal state, at least on Audigy */
491 #define ENVVOL 0x10 /* Volume envelope register */
492 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
493 /* 0x8000-n == 666*n usec delay */
495 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
496 #define ATKHLDV_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */
497 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
498 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
499 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
501 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
502 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */
503 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
504 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 0 = Inhibit envelope engine from writing values in */
505 /* this channel and from writing to pitch, filter and */
506 /* volume targets. */
507 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
508 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
510 #define LFOVAL1 0x13 /* Modulation LFO value */
511 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
512 /* 0x8000-n == 666*n usec delay */
514 #define ENVVAL 0x14 /* Modulation envelope register */
515 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
516 /* 0x8000-n == 666*n usec delay */
518 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
519 #define ATKHLDM_PHASE0_MASK 0x00008000 /* 0 = Begin attack phase */
520 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
521 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
522 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
524 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
525 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin decay phase, 1 = begin release phase */
526 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
527 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
528 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
530 #define LFOVAL2 0x17 /* Vibrato LFO register */
531 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
532 /* 0x8000-n == 666*n usec delay */
534 #define IP 0x18 /* Initial pitch register */
535 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
536 /* 4 bits of octave, 12 bits of fractional octave */
537 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
539 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
540 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
541 /* 6 most significant bits are semitones */
542 /* 2 least significant bits are fractions */
543 #define IFATN_FILTERCUTOFF 0x08080019
544 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
545 #define IFATN_ATTENUATION 0x08000019
547 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
548 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
549 /* Signed 2's complement, +/- one octave peak extremes */
550 #define PEFE_PITCHAMOUNT 0x0808001a
551 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
552 /* Signed 2's complement, +/- six octaves peak extremes */
553 #define PEFE_FILTERAMOUNT 0x0800001a
555 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
556 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
557 /* Signed 2's complement, +/- one octave extremes */
558 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
559 /* Signed 2's complement, +/- three octave extremes */
561 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
562 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
563 /* Signed 2's complement, with +/- 12dB extremes */
564 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
565 /* ??Hz steps, maximum of ?? Hz. */
567 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
568 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
569 /* Signed 2's complement, +/- one octave extremes */
570 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
571 /* 0.039Hz steps, maximum of 9.85 Hz. */
573 #define TEMPENV 0x1e /* Tempory envelope register */
574 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
575 /* NOTE: All channels contain internal variables; do */
576 /* not write to these locations. */
580 #define CD0 0x20 /* Cache data 0 register */
581 #define CD1 0x21 /* Cache data 1 register */
582 #define CD2 0x22 /* Cache data 2 register */
583 #define CD3 0x23 /* Cache data 3 register */
584 #define CD4 0x24 /* Cache data 4 register */
585 #define CD5 0x25 /* Cache data 5 register */
586 #define CD6 0x26 /* Cache data 6 register */
587 #define CD7 0x27 /* Cache data 7 register */
588 #define CD8 0x28 /* Cache data 8 register */
589 #define CD9 0x29 /* Cache data 9 register */
590 #define CDA 0x2a /* Cache data A register */
591 #define CDB 0x2b /* Cache data B register */
592 #define CDC 0x2c /* Cache data C register */
593 #define CDD 0x2d /* Cache data D register */
594 #define CDE 0x2e /* Cache data E register */
595 #define CDF 0x2f /* Cache data F register */
597 /* 0x30-3f seem to be the same as 0x20-2f */
599 #define PTB 0x40 /* Page table base register */
600 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
602 #define TCB 0x41 /* Tank cache base register */
603 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
605 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
606 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
607 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
608 /* NOTE: To guarantee phase coherency, both channels */
609 /* must be disabled prior to enabling both channels. */
610 #define A_ADCCR_RCHANENABLE 0x00000020
611 #define A_ADCCR_LCHANENABLE 0x00000010
613 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
614 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
615 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
616 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
617 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
618 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
619 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
620 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
621 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
622 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
623 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
624 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
625 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
627 #define FXWC 0x43 /* FX output write channels register */
628 /* When set, each bit enables the writing of the */
629 /* corresponding FX output channel (internal registers */
630 /* 0x20-0x3f) to host memory. This mode of recording */
631 /* is 16bit, 48KHz only. All 32 channels can be enabled */
632 /* simultaneously. */
634 #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
636 #define TCBS 0x44 /* Tank cache buffer size register */
637 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
638 #define TCBS_BUFFSIZE_16K 0x00000000
639 #define TCBS_BUFFSIZE_32K 0x00000001
640 #define TCBS_BUFFSIZE_64K 0x00000002
641 #define TCBS_BUFFSIZE_128K 0x00000003
642 #define TCBS_BUFFSIZE_256K 0x00000004
643 #define TCBS_BUFFSIZE_512K 0x00000005
644 #define TCBS_BUFFSIZE_1024K 0x00000006
645 #define TCBS_BUFFSIZE_2048K 0x00000007
647 #define MICBA 0x45 /* AC97 microphone buffer address register */
648 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
650 #define ADCBA 0x46 /* ADC buffer address register */
651 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
653 #define FXBA 0x47 /* FX Buffer Address */
654 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
656 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
658 #define MICBS 0x49 /* Microphone buffer size register */
660 #define ADCBS 0x4a /* ADC buffer size register */
662 #define FXBS 0x4b /* FX buffer size register */
664 /* The following mask values define the size of the ADC, MIC and FX buffers in bytes */
665 #define ADCBS_BUFSIZE_NONE 0x00000000
666 #define ADCBS_BUFSIZE_384 0x00000001
667 #define ADCBS_BUFSIZE_448 0x00000002
668 #define ADCBS_BUFSIZE_512 0x00000003
669 #define ADCBS_BUFSIZE_640 0x00000004
670 #define ADCBS_BUFSIZE_768 0x00000005
671 #define ADCBS_BUFSIZE_896 0x00000006
672 #define ADCBS_BUFSIZE_1024 0x00000007
673 #define ADCBS_BUFSIZE_1280 0x00000008
674 #define ADCBS_BUFSIZE_1536 0x00000009
675 #define ADCBS_BUFSIZE_1792 0x0000000a
676 #define ADCBS_BUFSIZE_2048 0x0000000b
677 #define ADCBS_BUFSIZE_2560 0x0000000c
678 #define ADCBS_BUFSIZE_3072 0x0000000d
679 #define ADCBS_BUFSIZE_3584 0x0000000e
680 #define ADCBS_BUFSIZE_4096 0x0000000f
681 #define ADCBS_BUFSIZE_5120 0x00000010
682 #define ADCBS_BUFSIZE_6144 0x00000011
683 #define ADCBS_BUFSIZE_7168 0x00000012
684 #define ADCBS_BUFSIZE_8192 0x00000013
685 #define ADCBS_BUFSIZE_10240 0x00000014
686 #define ADCBS_BUFSIZE_12288 0x00000015
687 #define ADCBS_BUFSIZE_14366 0x00000016
688 #define ADCBS_BUFSIZE_16384 0x00000017
689 #define ADCBS_BUFSIZE_20480 0x00000018
690 #define ADCBS_BUFSIZE_24576 0x00000019
691 #define ADCBS_BUFSIZE_28672 0x0000001a
692 #define ADCBS_BUFSIZE_32768 0x0000001b
693 #define ADCBS_BUFSIZE_40960 0x0000001c
694 #define ADCBS_BUFSIZE_49152 0x0000001d
695 #define ADCBS_BUFSIZE_57344 0x0000001e
696 #define ADCBS_BUFSIZE_65536 0x0000001f
698 #define A_CSBA 0x4c /* FX send B & A current amounts */
699 #define A_CSDC 0x4d /* FX send D & C current amounts */
700 #define A_CSFE 0x4e /* FX send F & E current amounts */
701 #define A_CSHG 0x4f /* FX send H & G current amounts */
703 // NOTE: 0x50,51,52: 64-bit (split over voices 0 & 1)
704 #define CDCS 0x50 /* CD-ROM digital channel status register */
706 #define GPSCS 0x51 /* General Purpose SPDIF channel status register */
708 // Corresponding EMU10K1_DBG_* constants are in the public header
711 #define A_SPSC 0x52 /* S/PDIF Input C Channel Status */
713 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
715 // Corresponding A_DBG_* constants are in the public header
718 // NOTE: 0x54,55,56: 64-bit (split over voices 0 & 1)
719 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
721 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
723 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
725 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
726 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
727 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
728 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
729 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
730 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
731 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
732 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
733 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
734 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
735 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
736 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
737 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
738 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
739 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
740 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
741 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
742 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
743 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
744 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
745 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
746 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
747 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
751 /* The 32-bit CLIx and SOLEx registers all have one bit per channel control/status */
752 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
753 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
755 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
756 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
758 #define SOLEL 0x5c /* Stop on loop enable low register */
759 #define SOLEH 0x5d /* Stop on loop enable high register */
761 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
762 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
763 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
764 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
765 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
767 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
768 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
769 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
770 #define AC97SLOT_CNTR 0x10 /* Center enable */
771 #define AC97SLOT_LFE 0x20 /* LFE enable */
773 #define A_PCB 0x5f /* PCB Revision */
775 // NOTE: 0x60,61,62: 64-bit
776 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
778 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
780 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
781 /* NOTE: This one has no SPDIFLOCKED field */
782 /* Assumes sample lock */
784 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
785 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
786 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
787 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
788 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
790 /* Note that these values can vary +/- by a small amount */
791 #define SRCS_SPDIFRATE_44 0x0003acd9
792 #define SRCS_SPDIFRATE_48 0x00040000
793 #define SRCS_SPDIFRATE_96 0x00080000
795 #define MICIDX 0x63 /* Microphone recording buffer index register */
796 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
797 #define MICIDX_IDX 0x10000063
799 #define ADCIDX 0x64 /* ADC recording buffer index register */
800 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
801 #define ADCIDX_IDX 0x10000064
803 #define A_ADCIDX 0x63
804 #define A_ADCIDX_IDX 0x10000063
806 #define A_MICIDX 0x64
807 #define A_MICIDX_IDX 0x10000064
809 #define FXIDX 0x65 /* FX recording buffer index register */
810 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
811 #define FXIDX_IDX 0x10000065
813 /* The 32-bit HLIEx and HLIPx registers all have one bit per channel control/status */
814 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */
815 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */
817 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */
818 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */
820 #define A_SPRI 0x6a /* S/PDIF Host Record Index (bypasses SRC) */
821 #define A_SPRA 0x6b /* S/PDIF Host Record Address */
822 #define A_SPRC 0x6c /* S/PDIF Host Record Control */
824 #define A_DICE 0x6d /* Delayed Interrupt Counter & Enable */
826 #define A_TTB 0x6e /* Tank Table Base */
827 #define A_TDOF 0x6f /* Tank Delay Offset */
829 /* This is the MPU port on the card (via the game port) */
830 #define A_MUDATA1 0x70
831 #define A_MUCMD1 0x71
832 #define A_MUSTAT1 A_MUCMD1
834 /* This is the MPU port on the Audigy Drive */
835 #define A_MUDATA2 0x72
836 #define A_MUCMD2 0x73
837 #define A_MUSTAT2 A_MUCMD2
839 /* The next two are the Audigy equivalent of FXWC */
840 /* the Audigy can record any output (16bit, 48kHz, up to 64 channels simultaneously) */
841 /* Each bit selects a channel for recording */
842 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
843 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
845 #define A_EHC 0x76 /* Extended Hardware Control */
847 #define A_SPDIF_SAMPLERATE A_EHC /* Set the sample rate of SPDIF output */
848 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
849 #define A_SPDIF_48000 0x00000000 /* kX calls this BYPASS */
850 #define A_SPDIF_192000 0x00000020
851 #define A_SPDIF_96000 0x00000040
852 #define A_SPDIF_44100 0x00000080
853 #define A_SPDIF_MUTED 0x000000c0
855 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
856 #define A_I2S_CAPTURE_RATE 0x03090076 /* unclear if this sets the ADC rate as well. */
857 #define A_I2S_CAPTURE_48000 0x0
858 #define A_I2S_CAPTURE_192000 0x1
859 #define A_I2S_CAPTURE_96000 0x2
860 #define A_I2S_CAPTURE_44100 0x4
862 #define A_EHC_SRC48_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
863 #define A_EHC_SRC48_BYPASS 0x00000000
864 #define A_EHC_SRC48_192 0x00002000
865 #define A_EHC_SRC48_96 0x00004000
866 #define A_EHC_SRC48_44 0x00008000
867 #define A_EHC_SRC48_MUTED 0x0000c000
869 #define A_EHC_P17V_TVM 0x00000001 /* Tank virtual memory mode */
870 #define A_EHC_P17V_SEL0_MASK 0x00030000 /* Aka A_EHC_P16V_PB_RATE; 00: 48, 01: 44.1, 10: 96, 11: 192 */
871 #define A_EHC_P17V_SEL1_MASK 0x000c0000
872 #define A_EHC_P17V_SEL2_MASK 0x00300000
873 #define A_EHC_P17V_SEL3_MASK 0x00c00000
875 #define A_EHC_ASYNC_BYPASS 0x80000000
877 #define A_SRT3 0x77 /* I2S0 Sample Rate Tracker Status */
878 #define A_SRT4 0x78 /* I2S1 Sample Rate Tracker Status */
879 #define A_SRT5 0x79 /* I2S2 Sample Rate Tracker Status */
880 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
882 #define A_SRT_ESTSAMPLERATE 0x001fffff
883 #define A_SRT_RATELOCKED 0x01000000
885 #define A_TTDA 0x7a /* Tank Table DMA Address */
886 #define A_TTDD 0x7b /* Tank Table DMA Data */
889 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
890 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
891 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
892 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
894 #define A_SENDAMOUNTS 0x7d
895 #define A_FXSENDAMOUNT_E_MASK 0xFF000000
896 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
897 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
898 #define A_FXSENDAMOUNT_H_MASK 0x000000FF
900 /* 0x7c, 0x7e "high bit is used for filtering" */
902 /* The send amounts for this one are the same as used with the emu10k1 */
904 #define A_FXRT_CHANNELA 0x0000003f
905 #define A_FXRT_CHANNELB 0x00003f00
906 #define A_FXRT_CHANNELC 0x003f0000
907 #define A_FXRT_CHANNELD 0x3f000000
911 /* The public header defines the GPR and TRAM base addresses that
912 * are valid for _both_ CPU and DSP addressing. */
914 /* Each DSP microcode instruction is mapped into 2 doublewords */
915 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
916 #define MICROCODEBASE 0x400 /* Microcode data base address */
917 #define A_MICROCODEBASE 0x600
920 /************************************************************************************************/
921 /* E-MU Digital Audio System overview */
922 /************************************************************************************************/
924 // - These cards use a regular PCI-attached Audigy chip (Alice2/Tina/Tina2);
925 // the PCIe variants simply put the Audigy chip behind a PCI bridge.
926 // - All physical PCM I/O is routed through an additional FPGA; the regular
927 // EXTIN/EXTOUT ports are unconnected.
928 // - The FPGA has a signal routing matrix, to connect each destination (output
929 // socket or capture channel) to a source (input socket or playback channel).
930 // - The FPGA is controlled via Audigy's GPIO port, while sample data is
931 // transmitted via proprietary EMU32 serial links. On first-generation
932 // E-MU 1010 cards, Audigy's I2S inputs are also used for sample data.
933 // - The Audio/Micro Dock is attached to Hana via EDI, a "network" link.
934 // - The Audigy chip operates in slave mode; the clock is supplied by the FPGA.
935 // Gen1 E-MU 1010 cards have two crystals (for 44.1 kHz and 48 kHz multiples),
936 // while the later cards use a single crystal and a PLL chip.
937 // - The whole card is switched to 2x/4x mode to achieve 88.2/96/176.4/192 kHz
938 // sample rates. Alice2/Tina keeps running at 44.1/48 kHz, but multiple channels
940 // - The number of available EMU32/EDI channels is hit in 2x/4x mode, so the total
941 // number of usable inputs/outputs is limited, esp. with ADAT in use.
942 // - S/PDIF is unavailable in 4x mode (only over TOSLINK on newer 1010 cards) due
943 // to being unspecified at 176.4/192 kHz. Therefore, the Dock's S/PDIF channels
944 // can overlap with the Dock's ADC/DAC's high channels.
945 // - The code names are mentioned below and in the emu_chip_details table.
947 /************************************************************************************************/
948 /* EMU1010 FPGA registers */
949 /************************************************************************************************/
951 #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
952 #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
954 #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
955 #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
957 #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
958 #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
960 #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
961 /* Must be written after power on to reset DLL */
962 /* One is unable to detect the Audio dock without this */
963 #define EMU_HANA_WCLOCK_SRC_MASK 0x07
964 #define EMU_HANA_WCLOCK_INT_48K 0x00
965 #define EMU_HANA_WCLOCK_INT_44_1K 0x01
966 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
967 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
968 #define EMU_HANA_WCLOCK_SYNC_BNC 0x04
969 #define EMU_HANA_WCLOCK_2ND_HANA 0x05
970 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
971 #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
972 #define EMU_HANA_WCLOCK_MULT_MASK 0x18
973 #define EMU_HANA_WCLOCK_1X 0x00
974 #define EMU_HANA_WCLOCK_2X 0x08
975 #define EMU_HANA_WCLOCK_4X 0x10
976 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
978 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
979 #define EMU_HANA_DEFCLOCK_48K 0x00
980 #define EMU_HANA_DEFCLOCK_44_1K 0x01
982 #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
983 #define EMU_MUTE 0x00
984 #define EMU_UNMUTE 0x01
986 #define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
987 #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
988 #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
990 #define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
991 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
992 #define EMU_HANA_IRQ_ADAT 0x02
993 #define EMU_HANA_IRQ_DOCK 0x04
994 #define EMU_HANA_IRQ_DOCK_LOST 0x08
996 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
997 #define EMU_HANA_SPDIF_MODE_TX_CONSUMER 0x00
998 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
999 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1000 #define EMU_HANA_SPDIF_MODE_RX_CONSUMER 0x00
1001 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1002 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1003 #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1005 #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
1006 #define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1007 #define EMU_HANA_OPTICAL_IN_ADAT 0x01
1008 #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1009 #define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1011 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1012 #define EMU_HANA_MIDI_INA_FROM_HAMOA 0x01 /* HAMOA MIDI in to Alice 2 MIDI A */
1013 #define EMU_HANA_MIDI_INA_FROM_DOCK1 0x02 /* Audio Dock-1 MIDI in to Alice 2 MIDI A */
1014 #define EMU_HANA_MIDI_INA_FROM_DOCK2 0x03 /* Audio Dock-2 MIDI in to Alice 2 MIDI A */
1015 #define EMU_HANA_MIDI_INB_FROM_HAMOA 0x08 /* HAMOA MIDI in to Alice 2 MIDI B */
1016 #define EMU_HANA_MIDI_INB_FROM_DOCK1 0x10 /* Audio Dock-1 MIDI in to Alice 2 MIDI B */
1017 #define EMU_HANA_MIDI_INB_FROM_DOCK2 0x18 /* Audio Dock-2 MIDI in to Alice 2 MIDI B */
1019 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
1020 #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
1021 #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
1022 #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
1023 #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
1025 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
1026 #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
1027 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1028 #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
1029 #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
1030 #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
1031 #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
1033 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
1034 #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
1035 #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
1036 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
1037 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
1038 #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
1039 #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
1041 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1042 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1043 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
1044 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
1045 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1047 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1048 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1049 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
1050 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
1051 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
1052 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1053 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1054 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1055 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1057 #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
1058 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
1059 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
1060 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
1061 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
1062 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
1064 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1065 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
1066 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
1067 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
1068 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
1069 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
1071 /* 0x14 - 0x1f Unused R/W registers */
1073 #define EMU_HANA_IRQ_STATUS 0x20 /* 00xxxxx 5 bits IRQ Status */
1074 /* Same bits as for EMU_HANA_IRQ_ENABLE */
1075 /* Reading the register resets it. */
1077 #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
1078 #define EMU_HANA_OPTION_HAMOA 0x01 /* Hamoa (analog I/O) card present */
1079 #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
1080 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio/Micro dock present and FPGA configured */
1081 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio/Micro dock present and FPGA not configured */
1083 #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 with Alice2 */
1084 /* 0010101 5 bits ID byte & 0x1f = 0x15 with Tina/2 */
1086 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1087 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1089 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1090 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1092 #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
1093 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1094 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1096 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1097 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1099 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1100 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1102 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1103 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1105 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1106 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1108 /* 0x30 - 0x3f Unused Read only registers */
1110 // The meaning of this is not clear; kX-project just calls it "lock" in some info-only code.
1111 #define EMU_HANA_LOCK_STS_LO 0x38 /* 0xxxxxx lower 6 bits */
1112 #define EMU_HANA_LOCK_STS_HI 0x39 /* 0xxxxxx upper 6 bits */
1114 /************************************************************************************************/
1115 /* EMU1010 Audio Destinations */
1116 /************************************************************************************************/
1117 /* Hana, original 1010,1212m,1820[m] using Alice2
1118 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1119 * 0x01, 0x00-0x1f: 32 EDI channels to Audio Dock
1120 * 0x00: Dock DAC 1 Left
1121 * 0x04: Dock DAC 1 Right
1122 * 0x08: Dock DAC 2 Left
1123 * 0x0c: Dock DAC 2 Right
1124 * 0x10: Dock DAC 3 Left
1125 * 0x12: PHONES Left (n/a in 2x/4x mode; output mirrors DAC4 Left)
1126 * 0x14: Dock DAC 3 Right
1127 * 0x16: PHONES Right (n/a in 2x/4x mode; output mirrors DAC4 Right)
1128 * 0x18: Dock DAC 4 Left
1130 * 0x1c: Dock DAC 4 Right
1131 * 0x1e: S/PDIF Right
1132 * 0x02, 0x00: Hana S/PDIF Left
1133 * 0x02, 0x01: Hana S/PDIF Right
1134 * 0x03, 0x00: Hamoa DAC Left
1135 * 0x03, 0x01: Hamoa DAC Right
1136 * 0x04, 0x00-0x07: Hana ADAT
1137 * 0x05, 0x00: I2S0 Left to Alice2
1138 * 0x05, 0x01: I2S0 Right to Alice2
1139 * 0x06, 0x00: I2S0 Left to Alice2
1140 * 0x06, 0x01: I2S0 Right to Alice2
1141 * 0x07, 0x00: I2S0 Left to Alice2
1142 * 0x07, 0x01: I2S0 Right to Alice2
1144 * Hana2 never released, but used Tina
1147 * Hana3, rev2 1010,1212m,1616[m] using Tina
1148 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1149 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1150 * 0x00: Dock DAC 1 Left
1151 * 0x04: Dock DAC 1 Right
1152 * 0x08: Dock DAC 2 Left
1153 * 0x0c: Dock DAC 2 Right
1154 * 0x10: Dock DAC 3 Left
1155 * 0x12: Dock S/PDIF Left
1156 * 0x14: Dock DAC 3 Right
1157 * 0x16: Dock S/PDIF Right
1158 * 0x18-0x1f: Dock ADAT 0-7
1159 * 0x02, 0x00: Hana3 S/PDIF Left
1160 * 0x02, 0x01: Hana3 S/PDIF Right
1161 * 0x03, 0x00: Hamoa DAC Left
1162 * 0x03, 0x01: Hamoa DAC Right
1163 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1164 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1165 * 0x06-0x07: Not used
1167 * HanaLite, rev1 0404 using Alice2
1168 * HanaLiteLite, rev2 0404 using Tina
1169 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2/Tina
1171 * 0x02, 0x00: S/PDIF Left
1172 * 0x02, 0x01: S/PDIF Right
1173 * 0x03, 0x00: DAC Left
1174 * 0x03, 0x01: DAC Right
1175 * 0x04-0x07: Not used
1177 * Mana, Cardbus 1616 using Tina2
1178 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1179 * 0x01, 0x00-0x1f: 32 EDI channels to Micro Dock
1180 * (same as rev2 1010)
1182 * 0x03, 0x00: Mana DAC Left
1183 * 0x03, 0x01: Mana DAC Right
1184 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1185 * 0x05-0x07: Not used
1188 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1189 * physical outputs of Hana, or outputs going to Alice2/Tina for capture -
1190 * 16 x EMU_DST_ALICE2_EMU32_X (2x on rev2 boards). Which data is fed into
1191 * a channel depends on the mixer control setting for each destination - see
1192 * emumixer.c - snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[]
1194 #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
1195 #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1196 #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1197 #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1198 #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1199 #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1200 #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1201 #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1202 #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1203 #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1204 #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1205 #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
1206 #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
1207 #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
1208 #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
1209 #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
1210 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1211 #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1212 #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1213 #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
1214 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1215 #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1216 #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1217 #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
1218 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1219 #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1220 #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1221 #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
1222 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1223 #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1224 #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1225 #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
1226 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1227 #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1228 #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1229 #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
1230 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1231 #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
1232 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1233 #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1234 #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1235 #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
1236 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1237 #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
1238 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1239 #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1240 #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1241 #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
1242 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1243 #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
1244 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1245 #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1246 #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1247 #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
1248 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1249 #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
1250 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1251 #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
1252 #define EMU_DST_HANA_SPDIF_LEFT3 0x0204 /* Hana SPDIF Left, 3rd or 192kHz */
1253 #define EMU_DST_HANA_SPDIF_LEFT4 0x0206 /* Hana SPDIF Left, 4th or 192kHz */
1254 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1255 #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
1256 #define EMU_DST_HANA_SPDIF_RIGHT3 0x0205 /* Hana SPDIF Right, 3rd or 192kHz */
1257 #define EMU_DST_HANA_SPDIF_RIGHT4 0x0207 /* Hana SPDIF Right, 4th or 192kHz */
1258 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1259 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1260 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1261 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1262 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1263 #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1264 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1265 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1266 // In S/MUX mode, the samples of one channel are adjacent.
1267 #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
1268 #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
1269 #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
1270 #define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
1271 #define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
1272 #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
1273 #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
1275 /* Additional destinations for 1616(M)/Microdock */
1277 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1278 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1279 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1280 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1281 #define EMU_DST_MDOCK_ADAT 0x0118 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */
1283 #define EMU_DST_MANA_DAC_LEFT 0x0300 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1284 #define EMU_DST_MANA_DAC_RIGHT 0x0301 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1286 /************************************************************************************************/
1287 /* EMU1010 Audio Sources */
1288 /************************************************************************************************/
1289 /* Hana, original 1010,1212m,1820[m] using Alice2
1290 * 0x00, 0x00-0x1f: Silence
1291 * 0x01, 0x00-0x1f: 32 EDI channels from Audio Dock
1294 * 0x08: Dock ADC 1 Left
1295 * 0x0c: Dock ADC 1 Right
1296 * 0x10: Dock ADC 2 Left
1297 * 0x14: Dock ADC 2 Right
1298 * 0x18: Dock ADC 3 Left
1299 * 0x1c: Dock ADC 3 Right
1300 * 0x02, 0x00: Hamoa ADC Left
1301 * 0x02, 0x01: Hamoa ADC Right
1302 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1303 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1304 * 0x04, 0x00-0x07: Hana ADAT
1305 * 0x05, 0x00: Hana S/PDIF Left
1306 * 0x05, 0x01: Hana S/PDIF Right
1307 * 0x06-0x07: Not used
1309 * Hana2 never released, but used Tina
1312 * Hana3, rev2 1010,1212m,1616[m] using Tina
1313 * 0x00, 0x00-0x1f: Silence
1314 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1317 * 0x08: Dock ADC 1 Left
1318 * 0x0c: Dock ADC 1 Right
1319 * 0x10: Dock ADC 2 Left
1320 * 0x12: Dock S/PDIF Left
1321 * 0x14: Dock ADC 2 Right
1322 * 0x16: Dock S/PDIF Right
1323 * 0x18-0x1f: Dock ADAT 0-7
1324 * 0x02, 0x00: Hamoa ADC Left
1325 * 0x02, 0x01: Hamoa ADC Right
1326 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1327 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1328 * 0x04, 0x00-0x07: Hana3 ADAT
1329 * 0x05, 0x00: Hana3 S/PDIF Left
1330 * 0x05, 0x01: Hana3 S/PDIF Right
1331 * 0x06-0x07: Not used
1333 * HanaLite, rev1 0404 using Alice2
1334 * HanaLiteLite, rev2 0404 using Tina
1335 * 0x00, 0x00-0x1f: Silence
1337 * 0x02, 0x00: ADC Left
1338 * 0x02, 0x01: ADC Right
1339 * 0x03, 0x00-0x0f: 16 inputs from Alice2/Tina Emu32A output
1340 * 0x03, 0x10-0x1f: 16 inputs from Alice2/Tina Emu32B output
1342 * 0x05, 0x00: S/PDIF Left
1343 * 0x05, 0x01: S/PDIF Right
1344 * 0x06-0x07: Not used
1346 * Mana, Cardbus 1616 using Tina2
1347 * 0x00, 0x00-0x1f: Silence
1348 * 0x01, 0x00-0x1f: 32 EDI channels from Micro Dock
1349 * (same as rev2 1010)
1351 * 0x03, 0x00-0x0f: 16 inputs from Tina2 Emu32A output
1352 * 0x03, 0x10-0x1f: 16 inputs from Tina2 Emu32B output
1353 * 0x04-0x07: Not used
1356 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1357 * destinations using a mixer control for each destination - see emumixer.c.
1358 * Sources are either physical inputs of Hana, or inputs from Alice2/Tina -
1359 * 16 x EMU_SRC_ALICE_EMU32A + 16 x EMU_SRC_ALICE_EMU32B.
1361 #define EMU_SRC_SILENCE 0x0000 /* Silence */
1362 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1363 #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
1364 #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
1365 #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
1366 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1367 #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
1368 #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
1369 #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
1370 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1371 #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
1372 #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
1373 #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
1374 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1375 #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
1376 #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
1377 #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
1378 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1379 #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
1380 #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
1381 #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
1382 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1383 #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
1384 #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
1385 #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
1386 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1387 #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
1388 #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
1389 #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
1390 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1391 #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
1392 #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
1393 #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
1394 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1395 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1396 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1397 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1398 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1399 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1400 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1401 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1402 #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
1403 #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
1404 // In S/MUX mode, the samples of one channel are adjacent.
1405 #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
1406 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1407 #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
1408 #define EMU_SRC_HANA_SPDIF_LEFT3 0x0504 /* Hana SPDIF Left, 3rd or 192kHz */
1409 #define EMU_SRC_HANA_SPDIF_LEFT4 0x0506 /* Hana SPDIF Left, 4th or 192kHz */
1410 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1411 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
1412 #define EMU_SRC_HANA_SPDIF_RIGHT3 0x0505 /* Hana SPDIF Right, 3rd or 192kHz */
1413 #define EMU_SRC_HANA_SPDIF_RIGHT4 0x0507 /* Hana SPDIF Right, 4th or 192kHz */
1415 /* Additional inputs for 1616(M)/Microdock */
1417 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 /* Microdock S/PDIF Left, 1st or 48kHz only */
1418 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 /* Microdock S/PDIF Left, 2nd or 96kHz */
1419 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 /* Microdock S/PDIF Right, 1st or 48kHz only */
1420 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 /* Microdock S/PDIF Right, 2nd or 96kHz */
1421 #define EMU_SRC_MDOCK_ADAT 0x0118 /* Microdock ADAT 8 channel in +8 to +f */
1423 /* 0x600 and 0x700 no used */
1425 /* ------------------- STRUCTURES -------------------- */
1436 struct snd_emu10k1_voice {
1438 unsigned int use: 1,
1443 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1445 struct snd_emu10k1_pcm *epcm;
1456 struct snd_emu10k1_pcm {
1457 struct snd_emu10k1 *emu;
1459 struct snd_pcm_substream *substream;
1460 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1461 struct snd_emu10k1_voice *extra;
1462 unsigned short running;
1463 unsigned short first_ptr;
1464 struct snd_util_memblk *memblk;
1465 unsigned int start_addr;
1466 unsigned int ccca_start_addr;
1467 unsigned int capture_ipr; /* interrupt acknowledge mask */
1468 unsigned int capture_inte; /* interrupt enable mask */
1469 unsigned int capture_ba_reg; /* buffer address register */
1470 unsigned int capture_bs_reg; /* buffer size register */
1471 unsigned int capture_idx_reg; /* buffer index register */
1472 unsigned int capture_cr_val; /* control value */
1473 unsigned int capture_cr_val2; /* control value2 (for audigy) */
1474 unsigned int capture_bs_val; /* buffer size value */
1475 unsigned int capture_bufsize; /* buffer size in bytes */
1478 struct snd_emu10k1_pcm_mixer {
1479 /* mono, left, right x 8 sends (4 on emu10k1) */
1480 unsigned char send_routing[3][8];
1481 unsigned char send_volume[3][8];
1482 unsigned short attn[3];
1483 struct snd_emu10k1_pcm *epcm;
1486 #define snd_emu10k1_compose_send_routing(route) \
1487 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1489 #define snd_emu10k1_compose_audigy_fxrt1(route) \
1490 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1492 #define snd_emu10k1_compose_audigy_fxrt2(route) \
1493 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1495 struct snd_emu10k1_memblk {
1496 struct snd_util_memblk mem;
1498 int first_page, last_page, pages, mapped_page;
1499 unsigned int map_locked;
1500 struct list_head mapped_link;
1501 struct list_head mapped_order_link;
1504 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1506 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1508 struct snd_emu10k1_fx8010_ctl {
1509 struct list_head list; /* list link container */
1510 unsigned int vcount;
1511 unsigned int count; /* count of GPR (1..16) */
1512 unsigned short gpr[32]; /* GPR number(s) */
1513 unsigned int value[32];
1514 unsigned int min; /* minimum range */
1515 unsigned int max; /* maximum range */
1516 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1517 struct snd_kcontrol *kcontrol;
1520 typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1522 struct snd_emu10k1_fx8010_irq {
1523 struct snd_emu10k1_fx8010_irq *next;
1524 snd_fx8010_irq_handler_t *handler;
1525 unsigned short gpr_running;
1529 struct snd_emu10k1_fx8010_pcm {
1530 unsigned int valid: 1,
1533 unsigned int channels; /* 16-bit channels count */
1534 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1535 unsigned int buffer_size; /* count of buffered samples */
1536 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1537 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1538 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1539 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1540 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1541 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1542 unsigned char etram[32]; /* external TRAM address & data */
1543 struct snd_pcm_indirect pcm_rec;
1544 unsigned int tram_pos;
1545 unsigned int tram_shift;
1546 struct snd_emu10k1_fx8010_irq irq;
1549 struct snd_emu10k1_fx8010 {
1550 unsigned short extin_mask; /* used external inputs (bitmask); not used for Audigy */
1551 unsigned short extout_mask; /* used external outputs (bitmask); not used for Audigy */
1552 unsigned int itram_size; /* internal TRAM size in samples */
1553 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1554 unsigned int dbg; /* FX debugger register */
1555 unsigned char name[128];
1556 int gpr_size; /* size of allocated GPR controls */
1557 int gpr_count; /* count of used kcontrols */
1558 struct list_head gpr_ctl; /* GPR controls */
1560 struct snd_emu10k1_fx8010_pcm pcm[8];
1561 spinlock_t irq_lock;
1562 struct snd_emu10k1_fx8010_irq *irq_handlers;
1565 struct snd_emu10k1_midi {
1566 struct snd_emu10k1 *emu;
1567 struct snd_rawmidi *rmidi;
1568 struct snd_rawmidi_substream *substream_input;
1569 struct snd_rawmidi_substream *substream_output;
1570 unsigned int midi_mode;
1571 spinlock_t input_lock;
1572 spinlock_t output_lock;
1573 spinlock_t open_lock;
1574 int tx_enable, rx_enable;
1577 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1589 // - All SB Live! cards use EMU10K1 chips
1590 // - All SB Audigy cards use CA* chips, termed "emu10k2" by the driver
1591 // - Original Audigy uses CA0100 "Alice"
1592 // - Audigy 2 uses CA0102/CA10200 "Alice2"
1593 // - Has an interface for CA0151 (P16V) "Alice3"
1594 // - Audigy 2 Value uses CA0108/CA10300 "Tina"
1595 // - Approximately a CA0102 with an on-chip CA0151 (P17V)
1596 // - Audigy 2 ZS NB uses CA0109 "Tina2"
1597 // - Cardbus version of CA0108
1598 struct snd_emu_chip_details {
1602 unsigned char revision;
1603 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1604 /* Redundant with emu10k2_chip being unset. */
1605 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1606 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1607 /* Redundant with ca0108_chip being unset. */
1608 unsigned char ca0108_chip; /* Audigy 2 Value */
1609 unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */
1610 unsigned char ca0151_chip; /* P16V */
1611 unsigned char spk71; /* Has 7.1 speakers */
1612 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1613 unsigned char spdif_bug; /* Has Spdif phasing bug */
1614 unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1615 unsigned char ecard; /* APS EEPROM */
1616 unsigned char emu_model; /* EMU model type */
1617 unsigned char spi_dac; /* SPI interface for DAC; requires ca0108_chip */
1618 unsigned char i2c_adc; /* I2C interface for ADC; requires ca0108_chip */
1619 unsigned char adc_1361t; /* Use Philips 1361T ADC */
1620 unsigned char invert_shared_spdif; /* analog/digital switch inverted */
1623 const char *id; /* for backward compatibility - can be NULL if not needed */
1626 struct snd_emu1010 {
1627 unsigned int output_source[64];
1628 unsigned int input_source[64];
1629 unsigned int adc_pads; /* bit mask */
1630 unsigned int dac_pads; /* bit mask */
1631 unsigned int internal_clock; /* 44100 or 48000 */
1632 unsigned int optical_in; /* 0:SPDIF, 1:ADAT */
1633 unsigned int optical_out; /* 0:SPDIF, 1:ADAT */
1634 struct delayed_work firmware_work;
1638 struct snd_emu10k1 {
1641 unsigned long port; /* I/O port number */
1642 unsigned int tos_link: 1, /* tos link detected */
1643 rear_ac97: 1, /* rear channels are on AC'97 */
1645 unsigned int support_tlv :1;
1646 /* Contains profile of card capabilities */
1647 const struct snd_emu_chip_details *card_capabilities;
1648 unsigned int audigy; /* is Audigy? */
1649 unsigned int revision; /* chip revision */
1650 unsigned int serial; /* serial number */
1651 unsigned short model; /* subsystem id */
1652 unsigned int ecard_ctrl; /* ecard control bits */
1653 unsigned int address_mode; /* address mode */
1654 unsigned long dma_mask; /* PCI DMA mask */
1655 bool iommu_workaround; /* IOMMU workaround needed */
1656 unsigned int delay_pcm_irq; /* in samples */
1657 int max_cache_pages; /* max memory size / PAGE_SIZE */
1658 struct snd_dma_buffer silent_page; /* silent page */
1659 struct snd_dma_buffer ptb_pages; /* page table pages */
1660 struct snd_dma_device p16v_dma_dev;
1661 struct snd_dma_buffer *p16v_buffer;
1663 struct snd_util_memhdr *memhdr; /* page allocation list */
1665 struct list_head mapped_link_head;
1666 struct list_head mapped_order_link_head;
1667 void **page_ptr_table;
1668 unsigned long *page_addr_table;
1669 spinlock_t memblk_lock;
1671 unsigned int spdif_bits[3]; /* s/pdif out setup */
1672 unsigned int i2c_capture_source;
1673 u8 i2c_capture_volume[4][2];
1675 struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */
1678 struct snd_ac97 *ac97;
1680 struct pci_dev *pci;
1681 struct snd_card *card;
1682 struct snd_pcm *pcm;
1683 struct snd_pcm *pcm_mic;
1684 struct snd_pcm *pcm_efx;
1685 struct snd_pcm *pcm_multi;
1686 struct snd_pcm *pcm_p16v;
1688 spinlock_t synth_lock;
1690 int (*get_synth_voice)(struct snd_emu10k1 *emu);
1692 spinlock_t reg_lock; // high-level driver lock
1693 spinlock_t emu_lock; // low-level i/o lock
1694 spinlock_t voice_lock; // voice allocator lock
1695 spinlock_t spi_lock; /* serialises access to spi port */
1696 spinlock_t i2c_lock; /* serialises access to i2c port */
1698 struct snd_emu10k1_voice voices[NUM_G];
1699 int p16v_device_offset;
1700 u32 p16v_capture_source;
1701 u32 p16v_capture_channel;
1702 struct snd_emu1010 emu1010;
1703 struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1704 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1705 struct snd_kcontrol *ctl_send_routing;
1706 struct snd_kcontrol *ctl_send_volume;
1707 struct snd_kcontrol *ctl_attn;
1708 struct snd_kcontrol *ctl_efx_send_routing;
1709 struct snd_kcontrol *ctl_efx_send_volume;
1710 struct snd_kcontrol *ctl_efx_attn;
1712 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1713 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1714 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1715 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1716 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1717 void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1718 void (*p16v_interrupt)(struct snd_emu10k1 *emu);
1720 struct snd_pcm_substream *pcm_capture_substream;
1721 struct snd_pcm_substream *pcm_capture_mic_substream;
1722 struct snd_pcm_substream *pcm_capture_efx_substream;
1724 struct snd_timer *timer;
1726 struct snd_emu10k1_midi midi;
1727 struct snd_emu10k1_midi midi2; /* for audigy */
1729 unsigned int efx_voices_mask[2];
1730 unsigned int next_free_voice;
1732 const struct firmware *firmware;
1733 const struct firmware *dock_fw;
1735 #ifdef CONFIG_PM_SLEEP
1736 unsigned int *saved_ptr;
1737 unsigned int *saved_gpr;
1738 unsigned int *tram_val_saved;
1739 unsigned int *tram_addr_saved;
1740 unsigned int *saved_icode;
1741 unsigned int *p16v_saved;
1742 unsigned int saved_a_iocfg, saved_hcfg;
1748 int snd_emu10k1_create(struct snd_card *card,
1749 struct pci_dev *pci,
1750 unsigned short extin_mask,
1751 unsigned short extout_mask,
1752 long max_cache_bytes,
1756 int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device);
1757 int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device);
1758 int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device);
1759 int snd_p16v_pcm(struct snd_emu10k1 *emu, int device);
1760 int snd_p16v_mixer(struct snd_emu10k1 * emu);
1761 int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device);
1762 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device);
1763 int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1764 int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1765 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device);
1767 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1769 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1770 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1771 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1772 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1773 int snd_emu10k1_done(struct snd_emu10k1 * emu);
1776 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1777 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1778 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1779 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1780 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1781 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1782 void snd_emu1010_fpga_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1783 void snd_emu1010_fpga_read(struct snd_emu10k1 *emu, u32 reg, u32 *value);
1784 void snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 *emu, u32 dst, u32 src);
1785 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1786 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1787 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1788 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1789 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1790 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1791 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1792 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1793 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1794 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1795 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1796 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
1797 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1798 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1799 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1800 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1802 #ifdef CONFIG_PM_SLEEP
1803 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1804 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1805 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1806 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1807 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1808 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1809 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1810 int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1811 void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1812 void snd_p16v_suspend(struct snd_emu10k1 *emu);
1813 void snd_p16v_resume(struct snd_emu10k1 *emu);
1816 /* memory allocation */
1817 struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1818 int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1819 int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size,
1820 struct snd_dma_buffer *dmab);
1821 struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1822 int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1823 int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
1824 int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
1825 int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1827 /* voice allocation */
1828 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
1829 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1832 int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1833 int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1835 /* proc interface */
1836 int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1838 /* fx8010 irq handler */
1839 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1840 snd_fx8010_irq_handler_t *handler,
1841 unsigned char gpr_running,
1843 struct snd_emu10k1_fx8010_irq *irq);
1844 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1845 struct snd_emu10k1_fx8010_irq *irq);
1847 #endif /* __SOUND_EMU10K1_H */
projects / linux.git / blob