drivers/tty/serial/zs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * zs.c: Serial port driver for IOASIC DECstations.
   4  *
   5  * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.
   6  * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.
   7  *
   8  * DECstation changes
   9  * Copyright (C) 1998-2000 Harald Koerfgen
  10  * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
  11  *
  12  * For the rest of the code the original Copyright applies:
  13  * Copyright (C) 1996 Paul Mackerras ([email protected])
  14  * Copyright (C) 1995 David S. Miller ([email protected])
  15  *
  16  *
  17  * Note: for IOASIC systems the wiring is as follows:
  18  *
  19  * mouse/keyboard:
  20  * DIN-7 MJ-4  signal        SCC
  21  * 2     1     TxD       <-  A.TxD
  22  * 3     4     RxD       ->  A.RxD
  23  *
  24  * EIA-232/EIA-423:
  25  * DB-25 MMJ-6 signal        SCC
  26  * 2     2     TxD       <-  B.TxD
  27  * 3     5     RxD       ->  B.RxD
  28  * 4           RTS       <- ~A.RTS
  29  * 5           CTS       -> ~B.CTS
  30  * 6     6     DSR       -> ~A.SYNC
  31  * 8           CD        -> ~B.DCD
  32  * 12          DSRS(DCE) -> ~A.CTS  (*)
  33  * 15          TxC       ->  B.TxC
  34  * 17          RxC       ->  B.RxC
  35  * 20    1     DTR       <- ~A.DTR
  36  * 22          RI        -> ~A.DCD
  37  * 23          DSRS(DTE) <- ~B.RTS
  38  *
  39  * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)
  40  *     is shared with DSRS(DTE) at pin 23.
  41  *
  42  * As you can immediately notice the wiring of the RTS, DTR and DSR signals
  43  * is a bit odd.  This makes the handling of port B unnecessarily
  44  * complicated and prevents the use of some automatic modes of operation.
  45  */
  46
  47 #include <linux/bug.h>
  48 #include <linux/console.h>
  49 #include <linux/delay.h>
  50 #include <linux/errno.h>
  51 #include <linux/init.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/io.h>
  54 #include <linux/ioport.h>
  55 #include <linux/irqflags.h>
  56 #include <linux/kernel.h>
  57 #include <linux/module.h>
  58 #include <linux/major.h>
  59 #include <linux/serial.h>
  60 #include <linux/serial_core.h>
  61 #include <linux/spinlock.h>
  62 #include <linux/sysrq.h>
  63 #include <linux/tty.h>
  64 #include <linux/tty_flip.h>
  65 #include <linux/types.h>
  66
  67 #include <linux/atomic.h>
  68
  69 #include <asm/dec/interrupts.h>
  70 #include <asm/dec/ioasic_addrs.h>
  71 #include <asm/dec/system.h>
  72
  73 #include "zs.h"
  74
  75
  76 MODULE_AUTHOR("Maciej W. Rozycki <[email protected]>");
  77 MODULE_DESCRIPTION("DECstation Z85C30 serial driver");
  78 MODULE_LICENSE("GPL");
  79
  80
  81 static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";
  82 static char zs_version[] __initdata = "0.10";
  83
  84 /*
  85  * It would be nice to dynamically allocate everything that
  86  * depends on ZS_NUM_SCCS, so we could support any number of
  87  * Z85C30s, but for now...
  88  */
  89 #define ZS_NUM_SCCS     2               /* Max # of ZS chips supported.  */
  90 #define ZS_NUM_CHAN     2               /* 2 channels per chip.  */
  91 #define ZS_CHAN_A       0               /* Index of the channel A.  */
  92 #define ZS_CHAN_B       1               /* Index of the channel B.  */
  93 #define ZS_CHAN_IO_SIZE 8               /* IOMEM space size.  */
  94 #define ZS_CHAN_IO_STRIDE 4             /* Register alignment.  */
  95 #define ZS_CHAN_IO_OFFSET 1             /* The SCC resides on the high byte
  96                                            of the 16-bit IOBUS.  */
  97 #define ZS_CLOCK        7372800         /* Z85C30 PCLK input clock rate.  */
  98
  99 #define to_zport(uport) container_of(uport, struct zs_port, port)
 100
 101 struct zs_parms {
 102         resource_size_t scc[ZS_NUM_SCCS];
 103         int irq[ZS_NUM_SCCS];
 104 };
 105
 106 static struct zs_scc zs_sccs[ZS_NUM_SCCS];
 107
 108 static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {
 109         0,                              /* write 0 */
 110         PAR_SPEC,                       /* write 1 */
 111         0,                              /* write 2 */
 112         0,                              /* write 3 */
 113         X16CLK | SB1,                   /* write 4 */
 114         0,                              /* write 5 */
 115         0, 0, 0,                        /* write 6, 7, 8 */
 116         MIE | DLC | NV,                 /* write 9 */
 117         NRZ,                            /* write 10 */
 118         TCBR | RCBR,                    /* write 11 */
 119         0, 0,                           /* BRG time constant, write 12 + 13 */
 120         BRSRC | BRENABL,                /* write 14 */
 121         0,                              /* write 15 */
 122 };
 123
 124 /*
 125  * Debugging.
 126  */
 127 #undef ZS_DEBUG_REGS
 128
 129
 130 /*
 131  * Reading and writing Z85C30 registers.
 132  */
 133 static void recovery_delay(void)
 134 {
 135         udelay(2);
 136 }
 137
 138 static u8 read_zsreg(struct zs_port *zport, int reg)
 139 {
 140         void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
 141         u8 retval;
 142
 143         if (reg != 0) {
 144                 writeb(reg & 0xf, control);
 145                 fast_iob();
 146                 recovery_delay();
 147         }
 148         retval = readb(control);
 149         recovery_delay();
 150         return retval;
 151 }
 152
 153 static void write_zsreg(struct zs_port *zport, int reg, u8 value)
 154 {
 155         void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
 156
 157         if (reg != 0) {
 158                 writeb(reg & 0xf, control);
 159                 fast_iob(); recovery_delay();
 160         }
 161         writeb(value, control);
 162         fast_iob();
 163         recovery_delay();
 164         return;
 165 }
 166
 167 static u8 read_zsdata(struct zs_port *zport)
 168 {
 169         void __iomem *data = zport->port.membase +
 170                              ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
 171         u8 retval;
 172
 173         retval = readb(data);
 174         recovery_delay();
 175         return retval;
 176 }
 177
 178 static void write_zsdata(struct zs_port *zport, u8 value)
 179 {
 180         void __iomem *data = zport->port.membase +
 181                              ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
 182
 183         writeb(value, data);
 184         fast_iob();
 185         recovery_delay();
 186         return;
 187 }
 188
 189 #ifdef ZS_DEBUG_REGS
 190 void zs_dump(void)
 191 {
 192         struct zs_port *zport;
 193         int i, j;
 194
 195         for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
 196                 zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];
 197
 198                 if (!zport->scc)
 199                         continue;
 200
 201                 for (j = 0; j < 16; j++)
 202                         printk("W%-2d = 0x%02x\t", j, zport->regs[j]);
 203                 printk("\n");
 204                 for (j = 0; j < 16; j++)
 205                         printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));
 206                 printk("\n\n");
 207         }
 208 }
 209 #endif
 210
 211
 212 static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)
 213 {
 214         if (irq)
 215                 spin_lock_irq(lock);
 216         else
 217                 spin_lock(lock);
 218 }
 219
 220 static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)
 221 {
 222         if (irq)
 223                 spin_unlock_irq(lock);
 224         else
 225                 spin_unlock(lock);
 226 }
 227
 228 static int zs_receive_drain(struct zs_port *zport)
 229 {
 230         int loops = 10000;
 231
 232         while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops)
 233                 read_zsdata(zport);
 234         return loops;
 235 }
 236
 237 static int zs_transmit_drain(struct zs_port *zport, int irq)
 238 {
 239         struct zs_scc *scc = zport->scc;
 240         int loops = 10000;
 241
 242         while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) {
 243                 zs_spin_unlock_cond_irq(&scc->zlock, irq);
 244                 udelay(2);
 245                 zs_spin_lock_cond_irq(&scc->zlock, irq);
 246         }
 247         return loops;
 248 }
 249
 250 static int zs_line_drain(struct zs_port *zport, int irq)
 251 {
 252         struct zs_scc *scc = zport->scc;
 253         int loops = 10000;
 254
 255         while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) {
 256                 zs_spin_unlock_cond_irq(&scc->zlock, irq);
 257                 udelay(2);
 258                 zs_spin_lock_cond_irq(&scc->zlock, irq);
 259         }
 260         return loops;
 261 }
 262
 263
 264 static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)
 265 {
 266         /* Let the current transmission finish.  */
 267         zs_line_drain(zport, irq);
 268         /* Load 'em up.  */
 269         write_zsreg(zport, R3, regs[3] & ~RxENABLE);
 270         write_zsreg(zport, R5, regs[5] & ~TxENAB);
 271         write_zsreg(zport, R4, regs[4]);
 272         write_zsreg(zport, R9, regs[9]);
 273         write_zsreg(zport, R1, regs[1]);
 274         write_zsreg(zport, R2, regs[2]);
 275         write_zsreg(zport, R10, regs[10]);
 276         write_zsreg(zport, R14, regs[14] & ~BRENABL);
 277         write_zsreg(zport, R11, regs[11]);
 278         write_zsreg(zport, R12, regs[12]);
 279         write_zsreg(zport, R13, regs[13]);
 280         write_zsreg(zport, R14, regs[14]);
 281         write_zsreg(zport, R15, regs[15]);
 282         if (regs[3] & RxENABLE)
 283                 write_zsreg(zport, R3, regs[3]);
 284         if (regs[5] & TxENAB)
 285                 write_zsreg(zport, R5, regs[5]);
 286         return;
 287 }
 288
 289
 290 /*
 291  * Status handling routines.
 292  */
 293
 294 /*
 295  * zs_tx_empty() -- get the transmitter empty status
 296  *
 297  * Purpose: Let user call ioctl() to get info when the UART physically
 298  *          is emptied.  On bus types like RS485, the transmitter must
 299  *          release the bus after transmitting.  This must be done when
 300  *          the transmit shift register is empty, not be done when the
 301  *          transmit holding register is empty.  This functionality
 302  *          allows an RS485 driver to be written in user space.
 303  */
 304 static unsigned int zs_tx_empty(struct uart_port *uport)
 305 {
 306         struct zs_port *zport = to_zport(uport);
 307         struct zs_scc *scc = zport->scc;
 308         unsigned long flags;
 309         u8 status;
 310
 311         spin_lock_irqsave(&scc->zlock, flags);
 312         status = read_zsreg(zport, R1);
 313         spin_unlock_irqrestore(&scc->zlock, flags);
 314
 315         return status & ALL_SNT ? TIOCSER_TEMT : 0;
 316 }
 317
 318 static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,
 319                                         struct zs_port *zport_b)
 320 {
 321         u8 status_a, status_b;
 322         unsigned int mctrl;
 323
 324         status_a = read_zsreg(zport_a, R0);
 325         status_b = read_zsreg(zport_b, R0);
 326
 327         mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |
 328                 ((status_b & DCD) ? TIOCM_CAR : 0) |
 329                 ((status_a & DCD) ? TIOCM_RNG : 0) |
 330                 ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);
 331
 332         return mctrl;
 333 }
 334
 335 static unsigned int zs_raw_get_mctrl(struct zs_port *zport)
 336 {
 337         struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
 338
 339         return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;
 340 }
 341
 342 static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)
 343 {
 344         struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
 345         unsigned int mmask, mctrl, delta;
 346         u8 mask_a, mask_b;
 347
 348         if (zport == zport_a)
 349                 return 0;
 350
 351         mask_a = zport_a->regs[15];
 352         mask_b = zport->regs[15];
 353
 354         mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |
 355                 ((mask_b & DCDIE) ? TIOCM_CAR : 0) |
 356                 ((mask_a & DCDIE) ? TIOCM_RNG : 0) |
 357                 ((mask_a & SYNCIE) ? TIOCM_DSR : 0);
 358
 359         mctrl = zport->mctrl;
 360         if (mmask) {
 361                 mctrl &= ~mmask;
 362                 mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;
 363         }
 364
 365         delta = mctrl ^ zport->mctrl;
 366         if (delta)
 367                 zport->mctrl = mctrl;
 368
 369         return delta;
 370 }
 371
 372 static unsigned int zs_get_mctrl(struct uart_port *uport)
 373 {
 374         struct zs_port *zport = to_zport(uport);
 375         struct zs_scc *scc = zport->scc;
 376         unsigned int mctrl;
 377
 378         spin_lock(&scc->zlock);
 379         mctrl = zs_raw_get_mctrl(zport);
 380         spin_unlock(&scc->zlock);
 381
 382         return mctrl;
 383 }
 384
 385 static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)
 386 {
 387         struct zs_port *zport = to_zport(uport);
 388         struct zs_scc *scc = zport->scc;
 389         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
 390         u8 oldloop, newloop;
 391
 392         spin_lock(&scc->zlock);
 393         if (zport != zport_a) {
 394                 if (mctrl & TIOCM_DTR)
 395                         zport_a->regs[5] |= DTR;
 396                 else
 397                         zport_a->regs[5] &= ~DTR;
 398                 if (mctrl & TIOCM_RTS)
 399                         zport_a->regs[5] |= RTS;
 400                 else
 401                         zport_a->regs[5] &= ~RTS;
 402                 write_zsreg(zport_a, R5, zport_a->regs[5]);
 403         }
 404
 405         /* Rarely modified, so don't poke at hardware unless necessary. */
 406         oldloop = zport->regs[14];
 407         newloop = oldloop;
 408         if (mctrl & TIOCM_LOOP)
 409                 newloop |= LOOPBAK;
 410         else
 411                 newloop &= ~LOOPBAK;
 412         if (newloop != oldloop) {
 413                 zport->regs[14] = newloop;
 414                 write_zsreg(zport, R14, zport->regs[14]);
 415         }
 416         spin_unlock(&scc->zlock);
 417 }
 418
 419 static void zs_raw_stop_tx(struct zs_port *zport)
 420 {
 421         write_zsreg(zport, R0, RES_Tx_P);
 422         zport->tx_stopped = 1;
 423 }
 424
 425 static void zs_stop_tx(struct uart_port *uport)
 426 {
 427         struct zs_port *zport = to_zport(uport);
 428         struct zs_scc *scc = zport->scc;
 429
 430         spin_lock(&scc->zlock);
 431         zs_raw_stop_tx(zport);
 432         spin_unlock(&scc->zlock);
 433 }
 434
 435 static void zs_raw_transmit_chars(struct zs_port *);
 436
 437 static void zs_start_tx(struct uart_port *uport)
 438 {
 439         struct zs_port *zport = to_zport(uport);
 440         struct zs_scc *scc = zport->scc;
 441
 442         spin_lock(&scc->zlock);
 443         if (zport->tx_stopped) {
 444                 zs_transmit_drain(zport, 0);
 445                 zport->tx_stopped = 0;
 446                 zs_raw_transmit_chars(zport);
 447         }
 448         spin_unlock(&scc->zlock);
 449 }
 450
 451 static void zs_stop_rx(struct uart_port *uport)
 452 {
 453         struct zs_port *zport = to_zport(uport);
 454         struct zs_scc *scc = zport->scc;
 455         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
 456
 457         spin_lock(&scc->zlock);
 458         zport->regs[15] &= ~BRKIE;
 459         zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
 460         zport->regs[1] |= RxINT_DISAB;
 461
 462         if (zport != zport_a) {
 463                 /* A-side DCD tracks RI and SYNC tracks DSR.  */
 464                 zport_a->regs[15] &= ~(DCDIE | SYNCIE);
 465                 write_zsreg(zport_a, R15, zport_a->regs[15]);
 466                 if (!(zport_a->regs[15] & BRKIE)) {
 467                         zport_a->regs[1] &= ~EXT_INT_ENAB;
 468                         write_zsreg(zport_a, R1, zport_a->regs[1]);
 469                 }
 470
 471                 /* This-side DCD tracks DCD and CTS tracks CTS.  */
 472                 zport->regs[15] &= ~(DCDIE | CTSIE);
 473                 zport->regs[1] &= ~EXT_INT_ENAB;
 474         } else {
 475                 /* DCD tracks RI and SYNC tracks DSR for the B side.  */
 476                 if (!(zport->regs[15] & (DCDIE | SYNCIE)))
 477                         zport->regs[1] &= ~EXT_INT_ENAB;
 478         }
 479
 480         write_zsreg(zport, R15, zport->regs[15]);
 481         write_zsreg(zport, R1, zport->regs[1]);
 482         spin_unlock(&scc->zlock);
 483 }
 484
 485 static void zs_enable_ms(struct uart_port *uport)
 486 {
 487         struct zs_port *zport = to_zport(uport);
 488         struct zs_scc *scc = zport->scc;
 489         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
 490
 491         if (zport == zport_a)
 492                 return;
 493
 494         spin_lock(&scc->zlock);
 495
 496         /* Clear Ext interrupts if not being handled already.  */
 497         if (!(zport_a->regs[1] & EXT_INT_ENAB))
 498                 write_zsreg(zport_a, R0, RES_EXT_INT);
 499
 500         /* A-side DCD tracks RI and SYNC tracks DSR.  */
 501         zport_a->regs[1] |= EXT_INT_ENAB;
 502         zport_a->regs[15] |= DCDIE | SYNCIE;
 503
 504         /* This-side DCD tracks DCD and CTS tracks CTS.  */
 505         zport->regs[15] |= DCDIE | CTSIE;
 506
 507         zs_raw_xor_mctrl(zport);
 508
 509         write_zsreg(zport_a, R1, zport_a->regs[1]);
 510         write_zsreg(zport_a, R15, zport_a->regs[15]);
 511         write_zsreg(zport, R15, zport->regs[15]);
 512         spin_unlock(&scc->zlock);
 513 }
 514
 515 static void zs_break_ctl(struct uart_port *uport, int break_state)
 516 {
 517         struct zs_port *zport = to_zport(uport);
 518         struct zs_scc *scc = zport->scc;
 519         unsigned long flags;
 520
 521         spin_lock_irqsave(&scc->zlock, flags);
 522         if (break_state == -1)
 523                 zport->regs[5] |= SND_BRK;
 524         else
 525                 zport->regs[5] &= ~SND_BRK;
 526         write_zsreg(zport, R5, zport->regs[5]);
 527         spin_unlock_irqrestore(&scc->zlock, flags);
 528 }
 529
 530
 531 /*
 532  * Interrupt handling routines.
 533  */
 534 #define Rx_BRK 0x0100                   /* BREAK event software flag.  */
 535 #define Rx_SYS 0x0200                   /* SysRq event software flag.  */
 536
 537 static void zs_receive_chars(struct zs_port *zport)
 538 {
 539         struct uart_port *uport = &zport->port;
 540         struct zs_scc *scc = zport->scc;
 541         struct uart_icount *icount;
 542         unsigned int avail, status, ch, flag;
 543         int count;
 544
 545         for (count = 16; count; count--) {
 546                 spin_lock(&scc->zlock);
 547                 avail = read_zsreg(zport, R0) & Rx_CH_AV;
 548                 spin_unlock(&scc->zlock);
 549                 if (!avail)
 550                         break;
 551
 552                 spin_lock(&scc->zlock);
 553                 status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);
 554                 ch = read_zsdata(zport);
 555                 spin_unlock(&scc->zlock);
 556
 557                 flag = TTY_NORMAL;
 558
 559                 icount = &uport->icount;
 560                 icount->rx++;
 561
 562                 /* Handle the null char got when BREAK is removed.  */
 563                 if (!ch)
 564                         status |= zport->tty_break;
 565                 if (unlikely(status &
 566                              (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {
 567                         zport->tty_break = 0;
 568
 569                         /* Reset the error indication.  */
 570                         if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {
 571                                 spin_lock(&scc->zlock);
 572                                 write_zsreg(zport, R0, ERR_RES);
 573                                 spin_unlock(&scc->zlock);
 574                         }
 575
 576                         if (status & (Rx_SYS | Rx_BRK)) {
 577                                 icount->brk++;
 578                                 /* SysRq discards the null char.  */
 579                                 if (status & Rx_SYS)
 580                                         continue;
 581                         } else if (status & FRM_ERR)
 582                                 icount->frame++;
 583                         else if (status & PAR_ERR)
 584                                 icount->parity++;
 585                         if (status & Rx_OVR)
 586                                 icount->overrun++;
 587
 588                         status &= uport->read_status_mask;
 589                         if (status & Rx_BRK)
 590                                 flag = TTY_BREAK;
 591                         else if (status & FRM_ERR)
 592                                 flag = TTY_FRAME;
 593                         else if (status & PAR_ERR)
 594                                 flag = TTY_PARITY;
 595                 }
 596
 597                 if (uart_handle_sysrq_char(uport, ch))
 598                         continue;
 599
 600                 uart_insert_char(uport, status, Rx_OVR, ch, flag);
 601         }
 602
 603         tty_flip_buffer_push(&uport->state->port);
 604 }
 605
 606 static void zs_raw_transmit_chars(struct zs_port *zport)
 607 {
 608         struct circ_buf *xmit = &zport->port.state->xmit;
 609
 610         /* XON/XOFF chars.  */
 611         if (zport->port.x_char) {
 612                 write_zsdata(zport, zport->port.x_char);
 613                 zport->port.icount.tx++;
 614                 zport->port.x_char = 0;
 615                 return;
 616         }
 617
 618         /* If nothing to do or stopped or hardware stopped.  */
 619         if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) {
 620                 zs_raw_stop_tx(zport);
 621                 return;
 622         }
 623
 624         /* Send char.  */
 625         write_zsdata(zport, xmit->buf[xmit->tail]);
 626         uart_xmit_advance(&zport->port, 1);
 627
 628         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 629                 uart_write_wakeup(&zport->port);
 630
 631         /* Are we are done?  */
 632         if (uart_circ_empty(xmit))
 633                 zs_raw_stop_tx(zport);
 634 }
 635
 636 static void zs_transmit_chars(struct zs_port *zport)
 637 {
 638         struct zs_scc *scc = zport->scc;
 639
 640         spin_lock(&scc->zlock);
 641         zs_raw_transmit_chars(zport);
 642         spin_unlock(&scc->zlock);
 643 }
 644
 645 static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)
 646 {
 647         struct uart_port *uport = &zport->port;
 648         struct zs_scc *scc = zport->scc;
 649         unsigned int delta;
 650         u8 status, brk;
 651
 652         spin_lock(&scc->zlock);
 653
 654         /* Get status from Read Register 0.  */
 655         status = read_zsreg(zport, R0);
 656
 657         if (zport->regs[15] & BRKIE) {
 658                 brk = status & BRK_ABRT;
 659                 if (brk && !zport->brk) {
 660                         spin_unlock(&scc->zlock);
 661                         if (uart_handle_break(uport))
 662                                 zport->tty_break = Rx_SYS;
 663                         else
 664                                 zport->tty_break = Rx_BRK;
 665                         spin_lock(&scc->zlock);
 666                 }
 667                 zport->brk = brk;
 668         }
 669
 670         if (zport != zport_a) {
 671                 delta = zs_raw_xor_mctrl(zport);
 672                 spin_unlock(&scc->zlock);
 673
 674                 if (delta & TIOCM_CTS)
 675                         uart_handle_cts_change(uport,
 676                                                zport->mctrl & TIOCM_CTS);
 677                 if (delta & TIOCM_CAR)
 678                         uart_handle_dcd_change(uport,
 679                                                zport->mctrl & TIOCM_CAR);
 680                 if (delta & TIOCM_RNG)
 681                         uport->icount.dsr++;
 682                 if (delta & TIOCM_DSR)
 683                         uport->icount.rng++;
 684
 685                 if (delta)
 686                         wake_up_interruptible(&uport->state->port.delta_msr_wait);
 687
 688                 spin_lock(&scc->zlock);
 689         }
 690
 691         /* Clear the status condition...  */
 692         write_zsreg(zport, R0, RES_EXT_INT);
 693
 694         spin_unlock(&scc->zlock);
 695 }
 696
 697 /*
 698  * This is the Z85C30 driver's generic interrupt routine.
 699  */
 700 static irqreturn_t zs_interrupt(int irq, void *dev_id)
 701 {
 702         struct zs_scc *scc = dev_id;
 703         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
 704         struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];
 705         irqreturn_t status = IRQ_NONE;
 706         u8 zs_intreg;
 707         int count;
 708
 709         /*
 710          * NOTE: The read register 3, which holds the irq status,
 711          *       does so for both channels on each chip.  Although
 712          *       the status value itself must be read from the A
 713          *       channel and is only valid when read from channel A.
 714          *       Yes... broken hardware...
 715          */
 716         for (count = 16; count; count--) {
 717                 spin_lock(&scc->zlock);
 718                 zs_intreg = read_zsreg(zport_a, R3);
 719                 spin_unlock(&scc->zlock);
 720                 if (!zs_intreg)
 721                         break;
 722
 723                 /*
 724                  * We do not like losing characters, so we prioritise
 725                  * interrupt sources a little bit differently than
 726                  * the SCC would, was it allowed to.
 727                  */
 728                 if (zs_intreg & CHBRxIP)
 729                         zs_receive_chars(zport_b);
 730                 if (zs_intreg & CHARxIP)
 731                         zs_receive_chars(zport_a);
 732                 if (zs_intreg & CHBEXT)
 733                         zs_status_handle(zport_b, zport_a);
 734                 if (zs_intreg & CHAEXT)
 735                         zs_status_handle(zport_a, zport_a);
 736                 if (zs_intreg & CHBTxIP)
 737                         zs_transmit_chars(zport_b);
 738                 if (zs_intreg & CHATxIP)
 739                         zs_transmit_chars(zport_a);
 740
 741                 status = IRQ_HANDLED;
 742         }
 743
 744         return status;
 745 }
 746
 747
 748 /*
 749  * Finally, routines used to initialize the serial port.
 750  */
 751 static int zs_startup(struct uart_port *uport)
 752 {
 753         struct zs_port *zport = to_zport(uport);
 754         struct zs_scc *scc = zport->scc;
 755         unsigned long flags;
 756         int irq_guard;
 757         int ret;
 758
 759         irq_guard = atomic_add_return(1, &scc->irq_guard);
 760         if (irq_guard == 1) {
 761                 ret = request_irq(zport->port.irq, zs_interrupt,
 762                                   IRQF_SHARED, "scc", scc);
 763                 if (ret) {
 764                         atomic_add(-1, &scc->irq_guard);
 765                         printk(KERN_ERR "zs: can't get irq %d\n",
 766                                zport->port.irq);
 767                         return ret;
 768                 }
 769         }
 770
 771         spin_lock_irqsave(&scc->zlock, flags);
 772
 773         /* Clear the receive FIFO.  */
 774         zs_receive_drain(zport);
 775
 776         /* Clear the interrupt registers.  */
 777         write_zsreg(zport, R0, ERR_RES);
 778         write_zsreg(zport, R0, RES_Tx_P);
 779         /* But Ext only if not being handled already.  */
 780         if (!(zport->regs[1] & EXT_INT_ENAB))
 781                 write_zsreg(zport, R0, RES_EXT_INT);
 782
 783         /* Finally, enable sequencing and interrupts.  */
 784         zport->regs[1] &= ~RxINT_MASK;
 785         zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;
 786         zport->regs[3] |= RxENABLE;
 787         zport->regs[15] |= BRKIE;
 788         write_zsreg(zport, R1, zport->regs[1]);
 789         write_zsreg(zport, R3, zport->regs[3]);
 790         write_zsreg(zport, R5, zport->regs[5]);
 791         write_zsreg(zport, R15, zport->regs[15]);
 792
 793         /* Record the current state of RR0.  */
 794         zport->mctrl = zs_raw_get_mctrl(zport);
 795         zport->brk = read_zsreg(zport, R0) & BRK_ABRT;
 796
 797         zport->tx_stopped = 1;
 798
 799         spin_unlock_irqrestore(&scc->zlock, flags);
 800
 801         return 0;
 802 }
 803
 804 static void zs_shutdown(struct uart_port *uport)
 805 {
 806         struct zs_port *zport = to_zport(uport);
 807         struct zs_scc *scc = zport->scc;
 808         unsigned long flags;
 809         int irq_guard;
 810
 811         spin_lock_irqsave(&scc->zlock, flags);
 812
 813         zport->regs[3] &= ~RxENABLE;
 814         write_zsreg(zport, R5, zport->regs[5]);
 815         write_zsreg(zport, R3, zport->regs[3]);
 816
 817         spin_unlock_irqrestore(&scc->zlock, flags);
 818
 819         irq_guard = atomic_add_return(-1, &scc->irq_guard);
 820         if (!irq_guard)
 821                 free_irq(zport->port.irq, scc);
 822 }
 823
 824
 825 static void zs_reset(struct zs_port *zport)
 826 {
 827         struct zs_scc *scc = zport->scc;
 828         int irq;
 829         unsigned long flags;
 830
 831         spin_lock_irqsave(&scc->zlock, flags);
 832         irq = !irqs_disabled_flags(flags);
 833         if (!scc->initialised) {
 834                 /* Reset the pointer first, just in case...  */
 835                 read_zsreg(zport, R0);
 836                 /* And let the current transmission finish.  */
 837                 zs_line_drain(zport, irq);
 838                 write_zsreg(zport, R9, FHWRES);
 839                 udelay(10);
 840                 write_zsreg(zport, R9, 0);
 841                 scc->initialised = 1;
 842         }
 843         load_zsregs(zport, zport->regs, irq);
 844         spin_unlock_irqrestore(&scc->zlock, flags);
 845 }
 846
 847 static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,
 848                            const struct ktermios *old_termios)
 849 {
 850         struct zs_port *zport = to_zport(uport);
 851         struct zs_scc *scc = zport->scc;
 852         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
 853         int irq;
 854         unsigned int baud, brg;
 855         unsigned long flags;
 856
 857         spin_lock_irqsave(&scc->zlock, flags);
 858         irq = !irqs_disabled_flags(flags);
 859
 860         /* Byte size.  */
 861         zport->regs[3] &= ~RxNBITS_MASK;
 862         zport->regs[5] &= ~TxNBITS_MASK;
 863         switch (termios->c_cflag & CSIZE) {
 864         case CS5:
 865                 zport->regs[3] |= Rx5;
 866                 zport->regs[5] |= Tx5;
 867                 break;
 868         case CS6:
 869                 zport->regs[3] |= Rx6;
 870                 zport->regs[5] |= Tx6;
 871                 break;
 872         case CS7:
 873                 zport->regs[3] |= Rx7;
 874                 zport->regs[5] |= Tx7;
 875                 break;
 876         case CS8:
 877         default:
 878                 zport->regs[3] |= Rx8;
 879                 zport->regs[5] |= Tx8;
 880                 break;
 881         }
 882
 883         /* Parity and stop bits.  */
 884         zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);
 885         if (termios->c_cflag & CSTOPB)
 886                 zport->regs[4] |= SB2;
 887         else
 888                 zport->regs[4] |= SB1;
 889         if (termios->c_cflag & PARENB)
 890                 zport->regs[4] |= PAR_ENA;
 891         if (!(termios->c_cflag & PARODD))
 892                 zport->regs[4] |= PAR_EVEN;
 893         switch (zport->clk_mode) {
 894         case 64:
 895                 zport->regs[4] |= X64CLK;
 896                 break;
 897         case 32:
 898                 zport->regs[4] |= X32CLK;
 899                 break;
 900         case 16:
 901                 zport->regs[4] |= X16CLK;
 902                 break;
 903         case 1:
 904                 zport->regs[4] |= X1CLK;
 905                 break;
 906         default:
 907                 BUG();
 908         }
 909
 910         baud = uart_get_baud_rate(uport, termios, old_termios, 0,
 911                                   uport->uartclk / zport->clk_mode / 4);
 912
 913         brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);
 914         zport->regs[12] = brg & 0xff;
 915         zport->regs[13] = (brg >> 8) & 0xff;
 916
 917         uart_update_timeout(uport, termios->c_cflag, baud);
 918
 919         uport->read_status_mask = Rx_OVR;
 920         if (termios->c_iflag & INPCK)
 921                 uport->read_status_mask |= FRM_ERR | PAR_ERR;
 922         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 923                 uport->read_status_mask |= Rx_BRK;
 924
 925         uport->ignore_status_mask = 0;
 926         if (termios->c_iflag & IGNPAR)
 927                 uport->ignore_status_mask |= FRM_ERR | PAR_ERR;
 928         if (termios->c_iflag & IGNBRK) {
 929                 uport->ignore_status_mask |= Rx_BRK;
 930                 if (termios->c_iflag & IGNPAR)
 931                         uport->ignore_status_mask |= Rx_OVR;
 932         }
 933
 934         if (termios->c_cflag & CREAD)
 935                 zport->regs[3] |= RxENABLE;
 936         else
 937                 zport->regs[3] &= ~RxENABLE;
 938
 939         if (zport != zport_a) {
 940                 if (!(termios->c_cflag & CLOCAL)) {
 941                         zport->regs[15] |= DCDIE;
 942                 } else
 943                         zport->regs[15] &= ~DCDIE;
 944                 if (termios->c_cflag & CRTSCTS) {
 945                         zport->regs[15] |= CTSIE;
 946                 } else
 947                         zport->regs[15] &= ~CTSIE;
 948                 zs_raw_xor_mctrl(zport);
 949         }
 950
 951         /* Load up the new values.  */
 952         load_zsregs(zport, zport->regs, irq);
 953
 954         spin_unlock_irqrestore(&scc->zlock, flags);
 955 }
 956
 957 /*
 958  * Hack alert!
 959  * Required solely so that the initial PROM-based console
 960  * works undisturbed in parallel with this one.
 961  */
 962 static void zs_pm(struct uart_port *uport, unsigned int state,
 963                   unsigned int oldstate)
 964 {
 965         struct zs_port *zport = to_zport(uport);
 966
 967         if (state < 3)
 968                 zport->regs[5] |= TxENAB;
 969         else
 970                 zport->regs[5] &= ~TxENAB;
 971         write_zsreg(zport, R5, zport->regs[5]);
 972 }
 973
 974
 975 static const char *zs_type(struct uart_port *uport)
 976 {
 977         return "Z85C30 SCC";
 978 }
 979
 980 static void zs_release_port(struct uart_port *uport)
 981 {
 982         iounmap(uport->membase);
 983         uport->membase = NULL;
 984         release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
 985 }
 986
 987 static int zs_map_port(struct uart_port *uport)
 988 {
 989         if (!uport->membase)
 990                 uport->membase = ioremap(uport->mapbase,
 991                                                  ZS_CHAN_IO_SIZE);
 992         if (!uport->membase) {
 993                 printk(KERN_ERR "zs: Cannot map MMIO\n");
 994                 return -ENOMEM;
 995         }
 996         return 0;
 997 }
 998
 999 static int zs_request_port(struct uart_port *uport)
1000 {
1001         int ret;
1002
1003         if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {
1004                 printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");
1005                 return -EBUSY;
1006         }
1007         ret = zs_map_port(uport);
1008         if (ret) {
1009                 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
1010                 return ret;
1011         }
1012         return 0;
1013 }
1014
1015 static void zs_config_port(struct uart_port *uport, int flags)
1016 {
1017         struct zs_port *zport = to_zport(uport);
1018
1019         if (flags & UART_CONFIG_TYPE) {
1020                 if (zs_request_port(uport))
1021                         return;
1022
1023                 uport->type = PORT_ZS;
1024
1025                 zs_reset(zport);
1026         }
1027 }
1028
1029 static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)
1030 {
1031         struct zs_port *zport = to_zport(uport);
1032         int ret = 0;
1033
1034         if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)
1035                 ret = -EINVAL;
1036         if (ser->irq != uport->irq)
1037                 ret = -EINVAL;
1038         if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)
1039                 ret = -EINVAL;
1040         return ret;
1041 }
1042
1043
1044 static const struct uart_ops zs_ops = {
1045         .tx_empty       = zs_tx_empty,
1046         .set_mctrl      = zs_set_mctrl,
1047         .get_mctrl      = zs_get_mctrl,
1048         .stop_tx        = zs_stop_tx,
1049         .start_tx       = zs_start_tx,
1050         .stop_rx        = zs_stop_rx,
1051         .enable_ms      = zs_enable_ms,
1052         .break_ctl      = zs_break_ctl,
1053         .startup        = zs_startup,
1054         .shutdown       = zs_shutdown,
1055         .set_termios    = zs_set_termios,
1056         .pm             = zs_pm,
1057         .type           = zs_type,
1058         .release_port   = zs_release_port,
1059         .request_port   = zs_request_port,
1060         .config_port    = zs_config_port,
1061         .verify_port    = zs_verify_port,
1062 };
1063
1064 /*
1065  * Initialize Z85C30 port structures.
1066  */
1067 static int __init zs_probe_sccs(void)
1068 {
1069         static int probed;
1070         struct zs_parms zs_parms;
1071         int chip, side, irq;
1072         int n_chips = 0;
1073         int i;
1074
1075         if (probed)
1076                 return 0;
1077
1078         irq = dec_interrupt[DEC_IRQ_SCC0];
1079         if (irq >= 0) {
1080                 zs_parms.scc[n_chips] = IOASIC_SCC0;
1081                 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];
1082                 n_chips++;
1083         }
1084         irq = dec_interrupt[DEC_IRQ_SCC1];
1085         if (irq >= 0) {
1086                 zs_parms.scc[n_chips] = IOASIC_SCC1;
1087                 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];
1088                 n_chips++;
1089         }
1090         if (!n_chips)
1091                 return -ENXIO;
1092
1093         probed = 1;
1094
1095         for (chip = 0; chip < n_chips; chip++) {
1096                 spin_lock_init(&zs_sccs[chip].zlock);
1097                 for (side = 0; side < ZS_NUM_CHAN; side++) {
1098                         struct zs_port *zport = &zs_sccs[chip].zport[side];
1099                         struct uart_port *uport = &zport->port;
1100
1101                         zport->scc      = &zs_sccs[chip];
1102                         zport->clk_mode = 16;
1103
1104                         uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_ZS_CONSOLE);
1105                         uport->irq      = zs_parms.irq[chip];
1106                         uport->uartclk  = ZS_CLOCK;
1107                         uport->fifosize = 1;
1108                         uport->iotype   = UPIO_MEM;
1109                         uport->flags    = UPF_BOOT_AUTOCONF;
1110                         uport->ops      = &zs_ops;
1111                         uport->line     = chip * ZS_NUM_CHAN + side;
1112                         uport->mapbase  = dec_kn_slot_base +
1113                                           zs_parms.scc[chip] +
1114                                           (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;
1115
1116                         for (i = 0; i < ZS_NUM_REGS; i++)
1117                                 zport->regs[i] = zs_init_regs[i];
1118                 }
1119         }
1120
1121         return 0;
1122 }
1123
1124
1125 #ifdef CONFIG_SERIAL_ZS_CONSOLE
1126 static void zs_console_putchar(struct uart_port *uport, unsigned char ch)
1127 {
1128         struct zs_port *zport = to_zport(uport);
1129         struct zs_scc *scc = zport->scc;
1130         int irq;
1131         unsigned long flags;
1132
1133         spin_lock_irqsave(&scc->zlock, flags);
1134         irq = !irqs_disabled_flags(flags);
1135         if (zs_transmit_drain(zport, irq))
1136                 write_zsdata(zport, ch);
1137         spin_unlock_irqrestore(&scc->zlock, flags);
1138 }
1139
1140 /*
1141  * Print a string to the serial port trying not to disturb
1142  * any possible real use of the port...
1143  */
1144 static void zs_console_write(struct console *co, const char *s,
1145                              unsigned int count)
1146 {
1147         int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1148         struct zs_port *zport = &zs_sccs[chip].zport[side];
1149         struct zs_scc *scc = zport->scc;
1150         unsigned long flags;
1151         u8 txint, txenb;
1152         int irq;
1153
1154         /* Disable transmit interrupts and enable the transmitter. */
1155         spin_lock_irqsave(&scc->zlock, flags);
1156         txint = zport->regs[1];
1157         txenb = zport->regs[5];
1158         if (txint & TxINT_ENAB) {
1159                 zport->regs[1] = txint & ~TxINT_ENAB;
1160                 write_zsreg(zport, R1, zport->regs[1]);
1161         }
1162         if (!(txenb & TxENAB)) {
1163                 zport->regs[5] = txenb | TxENAB;
1164                 write_zsreg(zport, R5, zport->regs[5]);
1165         }
1166         spin_unlock_irqrestore(&scc->zlock, flags);
1167
1168         uart_console_write(&zport->port, s, count, zs_console_putchar);
1169
1170         /* Restore transmit interrupts and the transmitter enable. */
1171         spin_lock_irqsave(&scc->zlock, flags);
1172         irq = !irqs_disabled_flags(flags);
1173         zs_line_drain(zport, irq);
1174         if (!(txenb & TxENAB)) {
1175                 zport->regs[5] &= ~TxENAB;
1176                 write_zsreg(zport, R5, zport->regs[5]);
1177         }
1178         if (txint & TxINT_ENAB) {
1179                 zport->regs[1] |= TxINT_ENAB;
1180                 write_zsreg(zport, R1, zport->regs[1]);
1181
1182                 /* Resume any transmission as the TxIP bit won't be set.  */
1183                 if (!zport->tx_stopped)
1184                         zs_raw_transmit_chars(zport);
1185         }
1186         spin_unlock_irqrestore(&scc->zlock, flags);
1187 }
1188
1189 /*
1190  * Setup serial console baud/bits/parity.  We do two things here:
1191  * - construct a cflag setting for the first uart_open()
1192  * - initialise the serial port
1193  * Return non-zero if we didn't find a serial port.
1194  */
1195 static int __init zs_console_setup(struct console *co, char *options)
1196 {
1197         int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1198         struct zs_port *zport = &zs_sccs[chip].zport[side];
1199         struct uart_port *uport = &zport->port;
1200         int baud = 9600;
1201         int bits = 8;
1202         int parity = 'n';
1203         int flow = 'n';
1204         int ret;
1205
1206         ret = zs_map_port(uport);
1207         if (ret)
1208                 return ret;
1209
1210         zs_reset(zport);
1211         zs_pm(uport, 0, -1);
1212
1213         if (options)
1214                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1215         return uart_set_options(uport, co, baud, parity, bits, flow);
1216 }
1217
1218 static struct uart_driver zs_reg;
1219 static struct console zs_console = {
1220         .name   = "ttyS",
1221         .write  = zs_console_write,
1222         .device = uart_console_device,
1223         .setup  = zs_console_setup,
1224         .flags  = CON_PRINTBUFFER,
1225         .index  = -1,
1226         .data   = &zs_reg,
1227 };
1228
1229 /*
1230  *      Register console.
1231  */
1232 static int __init zs_serial_console_init(void)
1233 {
1234         int ret;
1235
1236         ret = zs_probe_sccs();
1237         if (ret)
1238                 return ret;
1239         register_console(&zs_console);
1240
1241         return 0;
1242 }
1243
1244 console_initcall(zs_serial_console_init);
1245
1246 #define SERIAL_ZS_CONSOLE       &zs_console
1247 #else
1248 #define SERIAL_ZS_CONSOLE       NULL
1249 #endif /* CONFIG_SERIAL_ZS_CONSOLE */
1250
1251 static struct uart_driver zs_reg = {
1252         .owner                  = THIS_MODULE,
1253         .driver_name            = "serial",
1254         .dev_name               = "ttyS",
1255         .major                  = TTY_MAJOR,
1256         .minor                  = 64,
1257         .nr                     = ZS_NUM_SCCS * ZS_NUM_CHAN,
1258         .cons                   = SERIAL_ZS_CONSOLE,
1259 };
1260
1261 /* zs_init inits the driver. */
1262 static int __init zs_init(void)
1263 {
1264         int i, ret;
1265
1266         pr_info("%s%s\n", zs_name, zs_version);
1267
1268         /* Find out how many Z85C30 SCCs we have.  */
1269         ret = zs_probe_sccs();
1270         if (ret)
1271                 return ret;
1272
1273         ret = uart_register_driver(&zs_reg);
1274         if (ret)
1275                 return ret;
1276
1277         for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
1278                 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1279                 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1280                 struct uart_port *uport = &zport->port;
1281
1282                 if (zport->scc)
1283                         uart_add_one_port(&zs_reg, uport);
1284         }
1285
1286         return 0;
1287 }
1288
1289 static void __exit zs_exit(void)
1290 {
1291         int i;
1292
1293         for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {
1294                 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1295                 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1296                 struct uart_port *uport = &zport->port;
1297
1298                 if (zport->scc)
1299                         uart_remove_one_port(&zs_reg, uport);
1300         }
1301
1302         uart_unregister_driver(&zs_reg);
1303 }
1304
1305 module_init(zs_init);
1306 module_exit(zs_exit);