drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/console.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dmapool.h>
  16 #include <linux/io.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/irq.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/slab.h>
  27 #include <linux/tty_flip.h>
  28
  29 /* All registers are 8-bit width */
  30 #define UARTBDH                 0x00
  31 #define UARTBDL                 0x01
  32 #define UARTCR1                 0x02
  33 #define UARTCR2                 0x03
  34 #define UARTSR1                 0x04
  35 #define UARTCR3                 0x06
  36 #define UARTDR                  0x07
  37 #define UARTCR4                 0x0a
  38 #define UARTCR5                 0x0b
  39 #define UARTMODEM               0x0d
  40 #define UARTPFIFO               0x10
  41 #define UARTCFIFO               0x11
  42 #define UARTSFIFO               0x12
  43 #define UARTTWFIFO              0x13
  44 #define UARTTCFIFO              0x14
  45 #define UARTRWFIFO              0x15
  46
  47 #define UARTBDH_LBKDIE          0x80
  48 #define UARTBDH_RXEDGIE         0x40
  49 #define UARTBDH_SBR_MASK        0x1f
  50
  51 #define UARTCR1_LOOPS           0x80
  52 #define UARTCR1_RSRC            0x20
  53 #define UARTCR1_M               0x10
  54 #define UARTCR1_WAKE            0x08
  55 #define UARTCR1_ILT             0x04
  56 #define UARTCR1_PE              0x02
  57 #define UARTCR1_PT              0x01
  58
  59 #define UARTCR2_TIE             0x80
  60 #define UARTCR2_TCIE            0x40
  61 #define UARTCR2_RIE             0x20
  62 #define UARTCR2_ILIE            0x10
  63 #define UARTCR2_TE              0x08
  64 #define UARTCR2_RE              0x04
  65 #define UARTCR2_RWU             0x02
  66 #define UARTCR2_SBK             0x01
  67
  68 #define UARTSR1_TDRE            0x80
  69 #define UARTSR1_TC              0x40
  70 #define UARTSR1_RDRF            0x20
  71 #define UARTSR1_IDLE            0x10
  72 #define UARTSR1_OR              0x08
  73 #define UARTSR1_NF              0x04
  74 #define UARTSR1_FE              0x02
  75 #define UARTSR1_PE              0x01
  76
  77 #define UARTCR3_R8              0x80
  78 #define UARTCR3_T8              0x40
  79 #define UARTCR3_TXDIR           0x20
  80 #define UARTCR3_TXINV           0x10
  81 #define UARTCR3_ORIE            0x08
  82 #define UARTCR3_NEIE            0x04
  83 #define UARTCR3_FEIE            0x02
  84 #define UARTCR3_PEIE            0x01
  85
  86 #define UARTCR4_MAEN1           0x80
  87 #define UARTCR4_MAEN2           0x40
  88 #define UARTCR4_M10             0x20
  89 #define UARTCR4_BRFA_MASK       0x1f
  90 #define UARTCR4_BRFA_OFF        0
  91
  92 #define UARTCR5_TDMAS           0x80
  93 #define UARTCR5_RDMAS           0x20
  94
  95 #define UARTMODEM_RXRTSE        0x08
  96 #define UARTMODEM_TXRTSPOL      0x04
  97 #define UARTMODEM_TXRTSE        0x02
  98 #define UARTMODEM_TXCTSE        0x01
  99
 100 #define UARTPFIFO_TXFE          0x80
 101 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 102 #define UARTPFIFO_TXSIZE_OFF    4
 103 #define UARTPFIFO_RXFE          0x08
 104 #define UARTPFIFO_RXSIZE_OFF    0
 105
 106 #define UARTCFIFO_TXFLUSH       0x80
 107 #define UARTCFIFO_RXFLUSH       0x40
 108 #define UARTCFIFO_RXOFE         0x04
 109 #define UARTCFIFO_TXOFE         0x02
 110 #define UARTCFIFO_RXUFE         0x01
 111
 112 #define UARTSFIFO_TXEMPT        0x80
 113 #define UARTSFIFO_RXEMPT        0x40
 114 #define UARTSFIFO_RXOF          0x04
 115 #define UARTSFIFO_TXOF          0x02
 116 #define UARTSFIFO_RXUF          0x01
 117
 118 /* 32-bit global registers only for i.MX7ULP/i.MX8x
 119  * Used to reset all internal logic and registers, except the Global Register.
 120  */
 121 #define UART_GLOBAL             0x8
 122
 123 /* 32-bit register definition */
 124 #define UARTBAUD                0x00
 125 #define UARTSTAT                0x04
 126 #define UARTCTRL                0x08
 127 #define UARTDATA                0x0C
 128 #define UARTMATCH               0x10
 129 #define UARTMODIR               0x14
 130 #define UARTFIFO                0x18
 131 #define UARTWATER               0x1c
 132
 133 #define UARTBAUD_MAEN1          0x80000000
 134 #define UARTBAUD_MAEN2          0x40000000
 135 #define UARTBAUD_M10            0x20000000
 136 #define UARTBAUD_TDMAE          0x00800000
 137 #define UARTBAUD_RDMAE          0x00200000
 138 #define UARTBAUD_MATCFG         0x00400000
 139 #define UARTBAUD_BOTHEDGE       0x00020000
 140 #define UARTBAUD_RESYNCDIS      0x00010000
 141 #define UARTBAUD_LBKDIE         0x00008000
 142 #define UARTBAUD_RXEDGIE        0x00004000
 143 #define UARTBAUD_SBNS           0x00002000
 144 #define UARTBAUD_SBR            0x00000000
 145 #define UARTBAUD_SBR_MASK       0x1fff
 146 #define UARTBAUD_OSR_MASK       0x1f
 147 #define UARTBAUD_OSR_SHIFT      24
 148
 149 #define UARTSTAT_LBKDIF         0x80000000
 150 #define UARTSTAT_RXEDGIF        0x40000000
 151 #define UARTSTAT_MSBF           0x20000000
 152 #define UARTSTAT_RXINV          0x10000000
 153 #define UARTSTAT_RWUID          0x08000000
 154 #define UARTSTAT_BRK13          0x04000000
 155 #define UARTSTAT_LBKDE          0x02000000
 156 #define UARTSTAT_RAF            0x01000000
 157 #define UARTSTAT_TDRE           0x00800000
 158 #define UARTSTAT_TC             0x00400000
 159 #define UARTSTAT_RDRF           0x00200000
 160 #define UARTSTAT_IDLE           0x00100000
 161 #define UARTSTAT_OR             0x00080000
 162 #define UARTSTAT_NF             0x00040000
 163 #define UARTSTAT_FE             0x00020000
 164 #define UARTSTAT_PE             0x00010000
 165 #define UARTSTAT_MA1F           0x00008000
 166 #define UARTSTAT_M21F           0x00004000
 167
 168 #define UARTCTRL_R8T9           0x80000000
 169 #define UARTCTRL_R9T8           0x40000000
 170 #define UARTCTRL_TXDIR          0x20000000
 171 #define UARTCTRL_TXINV          0x10000000
 172 #define UARTCTRL_ORIE           0x08000000
 173 #define UARTCTRL_NEIE           0x04000000
 174 #define UARTCTRL_FEIE           0x02000000
 175 #define UARTCTRL_PEIE           0x01000000
 176 #define UARTCTRL_TIE            0x00800000
 177 #define UARTCTRL_TCIE           0x00400000
 178 #define UARTCTRL_RIE            0x00200000
 179 #define UARTCTRL_ILIE           0x00100000
 180 #define UARTCTRL_TE             0x00080000
 181 #define UARTCTRL_RE             0x00040000
 182 #define UARTCTRL_RWU            0x00020000
 183 #define UARTCTRL_SBK            0x00010000
 184 #define UARTCTRL_MA1IE          0x00008000
 185 #define UARTCTRL_MA2IE          0x00004000
 186 #define UARTCTRL_IDLECFG        GENMASK(10, 8)
 187 #define UARTCTRL_LOOPS          0x00000080
 188 #define UARTCTRL_DOZEEN         0x00000040
 189 #define UARTCTRL_RSRC           0x00000020
 190 #define UARTCTRL_M              0x00000010
 191 #define UARTCTRL_WAKE           0x00000008
 192 #define UARTCTRL_ILT            0x00000004
 193 #define UARTCTRL_PE             0x00000002
 194 #define UARTCTRL_PT             0x00000001
 195
 196 #define UARTDATA_NOISY          0x00008000
 197 #define UARTDATA_PARITYE        0x00004000
 198 #define UARTDATA_FRETSC         0x00002000
 199 #define UARTDATA_RXEMPT         0x00001000
 200 #define UARTDATA_IDLINE         0x00000800
 201 #define UARTDATA_MASK           0x3ff
 202
 203 #define UARTMODIR_IREN          0x00020000
 204 #define UARTMODIR_RTSWATER      GENMASK(10, 8)
 205 #define UARTMODIR_TXCTSSRC      0x00000020
 206 #define UARTMODIR_TXCTSC        0x00000010
 207 #define UARTMODIR_RXRTSE        0x00000008
 208 #define UARTMODIR_TXRTSPOL      0x00000004
 209 #define UARTMODIR_TXRTSE        0x00000002
 210 #define UARTMODIR_TXCTSE        0x00000001
 211
 212 #define UARTFIFO_TXEMPT         0x00800000
 213 #define UARTFIFO_RXEMPT         0x00400000
 214 #define UARTFIFO_TXOF           0x00020000
 215 #define UARTFIFO_RXUF           0x00010000
 216 #define UARTFIFO_TXFLUSH        0x00008000
 217 #define UARTFIFO_RXFLUSH        0x00004000
 218 #define UARTFIFO_RXIDEN GENMASK(12, 10)
 219 #define UARTFIFO_TXOFE          0x00000200
 220 #define UARTFIFO_RXUFE          0x00000100
 221 #define UARTFIFO_TXFE           0x00000080
 222 #define UARTFIFO_FIFOSIZE_MASK  0x7
 223 #define UARTFIFO_TXSIZE_OFF     4
 224 #define UARTFIFO_RXFE           0x00000008
 225 #define UARTFIFO_RXSIZE_OFF     0
 226 #define UARTFIFO_DEPTH(x)       (0x1 << ((x) ? ((x) + 1) : 0))
 227
 228 #define UARTWATER_COUNT_MASK    0xff
 229 #define UARTWATER_TXCNT_OFF     8
 230 #define UARTWATER_RXCNT_OFF     24
 231 #define UARTWATER_WATER_MASK    0xff
 232 #define UARTWATER_TXWATER_OFF   0
 233 #define UARTWATER_RXWATER_OFF   16
 234
 235 #define UART_GLOBAL_RST 0x2
 236 #define GLOBAL_RST_MIN_US       20
 237 #define GLOBAL_RST_MAX_US       40
 238
 239 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 240 #define DMA_RX_TIMEOUT          (10)
 241 #define UART_AUTOSUSPEND_TIMEOUT        3000
 242
 243 #define DRIVER_NAME     "fsl-lpuart"
 244 #define DEV_NAME        "ttyLP"
 245 #define UART_NR         8
 246
 247 /* IMX lpuart has four extra unused regs located at the beginning */
 248 #define IMX_REG_OFF     0x10
 249
 250 enum lpuart_type {
 251         VF610_LPUART,
 252         LS1021A_LPUART,
 253         LS1028A_LPUART,
 254         IMX7ULP_LPUART,
 255         IMX8ULP_LPUART,
 256         IMX8QXP_LPUART,
 257         IMXRT1050_LPUART,
 258 };
 259
 260 struct lpuart_port {
 261         struct uart_port        port;
 262         enum lpuart_type        devtype;
 263         struct clk              *ipg_clk;
 264         struct clk              *baud_clk;
 265         unsigned int            txfifo_size;
 266         unsigned int            rxfifo_size;
 267
 268         u8                      rx_watermark;
 269         bool                    lpuart_dma_tx_use;
 270         bool                    lpuart_dma_rx_use;
 271         struct dma_chan         *dma_tx_chan;
 272         struct dma_chan         *dma_rx_chan;
 273         struct dma_async_tx_descriptor  *dma_tx_desc;
 274         struct dma_async_tx_descriptor  *dma_rx_desc;
 275         dma_cookie_t            dma_tx_cookie;
 276         dma_cookie_t            dma_rx_cookie;
 277         unsigned int            dma_tx_bytes;
 278         unsigned int            dma_rx_bytes;
 279         bool                    dma_tx_in_progress;
 280         unsigned int            dma_rx_timeout;
 281         struct timer_list       lpuart_timer;
 282         struct scatterlist      rx_sgl, tx_sgl[2];
 283         struct circ_buf         rx_ring;
 284         int                     rx_dma_rng_buf_len;
 285         unsigned int            dma_tx_nents;
 286         wait_queue_head_t       dma_wait;
 287         bool                    is_cs7; /* Set to true when character size is 7 */
 288                                         /* and the parity is enabled            */
 289 };
 290
 291 struct lpuart_soc_data {
 292         enum lpuart_type devtype;
 293         char iotype;
 294         u8 reg_off;
 295         u8 rx_watermark;
 296 };
 297
 298 static const struct lpuart_soc_data vf_data = {
 299         .devtype = VF610_LPUART,
 300         .iotype = UPIO_MEM,
 301         .rx_watermark = 1,
 302 };
 303
 304 static const struct lpuart_soc_data ls1021a_data = {
 305         .devtype = LS1021A_LPUART,
 306         .iotype = UPIO_MEM32BE,
 307         .rx_watermark = 1,
 308 };
 309
 310 static const struct lpuart_soc_data ls1028a_data = {
 311         .devtype = LS1028A_LPUART,
 312         .iotype = UPIO_MEM32,
 313         .rx_watermark = 1,
 314 };
 315
 316 static struct lpuart_soc_data imx7ulp_data = {
 317         .devtype = IMX7ULP_LPUART,
 318         .iotype = UPIO_MEM32,
 319         .reg_off = IMX_REG_OFF,
 320         .rx_watermark = 1,
 321 };
 322
 323 static struct lpuart_soc_data imx8ulp_data = {
 324         .devtype = IMX8ULP_LPUART,
 325         .iotype = UPIO_MEM32,
 326         .reg_off = IMX_REG_OFF,
 327         .rx_watermark = 3,
 328 };
 329
 330 static struct lpuart_soc_data imx8qxp_data = {
 331         .devtype = IMX8QXP_LPUART,
 332         .iotype = UPIO_MEM32,
 333         .reg_off = IMX_REG_OFF,
 334         .rx_watermark = 31,
 335 };
 336 static struct lpuart_soc_data imxrt1050_data = {
 337         .devtype = IMXRT1050_LPUART,
 338         .iotype = UPIO_MEM32,
 339         .reg_off = IMX_REG_OFF,
 340         .rx_watermark = 1,
 341 };
 342
 343 static const struct of_device_id lpuart_dt_ids[] = {
 344         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 345         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls1021a_data, },
 346         { .compatible = "fsl,ls1028a-lpuart",   .data = &ls1028a_data, },
 347         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx7ulp_data, },
 348         { .compatible = "fsl,imx8ulp-lpuart",   .data = &imx8ulp_data, },
 349         { .compatible = "fsl,imx8qxp-lpuart",   .data = &imx8qxp_data, },
 350         { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
 351         { /* sentinel */ }
 352 };
 353 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 354
 355 /* Forward declare this for the dma callbacks*/
 356 static void lpuart_dma_tx_complete(void *arg);
 357
 358 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
 359 {
 360         return (sport->devtype == LS1021A_LPUART ||
 361                 sport->devtype == LS1028A_LPUART);
 362 }
 363
 364 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
 365 {
 366         return sport->devtype == IMX7ULP_LPUART;
 367 }
 368
 369 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport)
 370 {
 371         return sport->devtype == IMX8ULP_LPUART;
 372 }
 373
 374 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
 375 {
 376         return sport->devtype == IMX8QXP_LPUART;
 377 }
 378
 379 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 380 {
 381         switch (port->iotype) {
 382         case UPIO_MEM32:
 383                 return readl(port->membase + off);
 384         case UPIO_MEM32BE:
 385                 return ioread32be(port->membase + off);
 386         default:
 387                 return 0;
 388         }
 389 }
 390
 391 static inline void lpuart32_write(struct uart_port *port, u32 val,
 392                                   u32 off)
 393 {
 394         switch (port->iotype) {
 395         case UPIO_MEM32:
 396                 writel(val, port->membase + off);
 397                 break;
 398         case UPIO_MEM32BE:
 399                 iowrite32be(val, port->membase + off);
 400                 break;
 401         }
 402 }
 403
 404 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
 405 {
 406         int ret = 0;
 407
 408         if (is_en) {
 409                 ret = clk_prepare_enable(sport->ipg_clk);
 410                 if (ret)
 411                         return ret;
 412
 413                 ret = clk_prepare_enable(sport->baud_clk);
 414                 if (ret) {
 415                         clk_disable_unprepare(sport->ipg_clk);
 416                         return ret;
 417                 }
 418         } else {
 419                 clk_disable_unprepare(sport->baud_clk);
 420                 clk_disable_unprepare(sport->ipg_clk);
 421         }
 422
 423         return 0;
 424 }
 425
 426 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 427 {
 428         if (is_imx8qxp_lpuart(sport))
 429                 return clk_get_rate(sport->baud_clk);
 430
 431         return clk_get_rate(sport->ipg_clk);
 432 }
 433
 434 #define lpuart_enable_clks(x)   __lpuart_enable_clks(x, true)
 435 #define lpuart_disable_clks(x)  __lpuart_enable_clks(x, false)
 436
 437 static void lpuart_stop_tx(struct uart_port *port)
 438 {
 439         unsigned char temp;
 440
 441         temp = readb(port->membase + UARTCR2);
 442         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 443         writeb(temp, port->membase + UARTCR2);
 444 }
 445
 446 static void lpuart32_stop_tx(struct uart_port *port)
 447 {
 448         unsigned long temp;
 449
 450         temp = lpuart32_read(port, UARTCTRL);
 451         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 452         lpuart32_write(port, temp, UARTCTRL);
 453 }
 454
 455 static void lpuart_stop_rx(struct uart_port *port)
 456 {
 457         unsigned char temp;
 458
 459         temp = readb(port->membase + UARTCR2);
 460         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 461 }
 462
 463 static void lpuart32_stop_rx(struct uart_port *port)
 464 {
 465         unsigned long temp;
 466
 467         temp = lpuart32_read(port, UARTCTRL);
 468         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 469 }
 470
 471 static void lpuart_dma_tx(struct lpuart_port *sport)
 472 {
 473         struct circ_buf *xmit = &sport->port.state->xmit;
 474         struct scatterlist *sgl = sport->tx_sgl;
 475         struct device *dev = sport->port.dev;
 476         struct dma_chan *chan = sport->dma_tx_chan;
 477         int ret;
 478
 479         if (sport->dma_tx_in_progress)
 480                 return;
 481
 482         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 483
 484         if (xmit->tail < xmit->head || xmit->head == 0) {
 485                 sport->dma_tx_nents = 1;
 486                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 487         } else {
 488                 sport->dma_tx_nents = 2;
 489                 sg_init_table(sgl, 2);
 490                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 491                                 UART_XMIT_SIZE - xmit->tail);
 492                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 493         }
 494
 495         ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 496                          DMA_TO_DEVICE);
 497         if (!ret) {
 498                 dev_err(dev, "DMA mapping error for TX.\n");
 499                 return;
 500         }
 501
 502         sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
 503                                         ret, DMA_MEM_TO_DEV,
 504                                         DMA_PREP_INTERRUPT);
 505         if (!sport->dma_tx_desc) {
 506                 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 507                               DMA_TO_DEVICE);
 508                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 509                 return;
 510         }
 511
 512         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 513         sport->dma_tx_desc->callback_param = sport;
 514         sport->dma_tx_in_progress = true;
 515         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 516         dma_async_issue_pending(chan);
 517 }
 518
 519 static bool lpuart_stopped_or_empty(struct uart_port *port)
 520 {
 521         return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
 522 }
 523
 524 static void lpuart_dma_tx_complete(void *arg)
 525 {
 526         struct lpuart_port *sport = arg;
 527         struct scatterlist *sgl = &sport->tx_sgl[0];
 528         struct circ_buf *xmit = &sport->port.state->xmit;
 529         struct dma_chan *chan = sport->dma_tx_chan;
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&sport->port.lock, flags);
 533         if (!sport->dma_tx_in_progress) {
 534                 spin_unlock_irqrestore(&sport->port.lock, flags);
 535                 return;
 536         }
 537
 538         dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 539                      DMA_TO_DEVICE);
 540
 541         uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
 542         sport->dma_tx_in_progress = false;
 543         spin_unlock_irqrestore(&sport->port.lock, flags);
 544
 545         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 546                 uart_write_wakeup(&sport->port);
 547
 548         if (waitqueue_active(&sport->dma_wait)) {
 549                 wake_up(&sport->dma_wait);
 550                 return;
 551         }
 552
 553         spin_lock_irqsave(&sport->port.lock, flags);
 554
 555         if (!lpuart_stopped_or_empty(&sport->port))
 556                 lpuart_dma_tx(sport);
 557
 558         spin_unlock_irqrestore(&sport->port.lock, flags);
 559 }
 560
 561 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
 562 {
 563         switch (sport->port.iotype) {
 564         case UPIO_MEM32:
 565                 return sport->port.mapbase + UARTDATA;
 566         case UPIO_MEM32BE:
 567                 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
 568         }
 569         return sport->port.mapbase + UARTDR;
 570 }
 571
 572 static int lpuart_dma_tx_request(struct uart_port *port)
 573 {
 574         struct lpuart_port *sport = container_of(port,
 575                                         struct lpuart_port, port);
 576         struct dma_slave_config dma_tx_sconfig = {};
 577         int ret;
 578
 579         dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
 580         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 581         dma_tx_sconfig.dst_maxburst = 1;
 582         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 583         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 584
 585         if (ret) {
 586                 dev_err(sport->port.dev,
 587                                 "DMA slave config failed, err = %d\n", ret);
 588                 return ret;
 589         }
 590
 591         return 0;
 592 }
 593
 594 static bool lpuart_is_32(struct lpuart_port *sport)
 595 {
 596         return sport->port.iotype == UPIO_MEM32 ||
 597                sport->port.iotype ==  UPIO_MEM32BE;
 598 }
 599
 600 static void lpuart_flush_buffer(struct uart_port *port)
 601 {
 602         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 603         struct dma_chan *chan = sport->dma_tx_chan;
 604         u32 val;
 605
 606         if (sport->lpuart_dma_tx_use) {
 607                 if (sport->dma_tx_in_progress) {
 608                         dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
 609                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 610                         sport->dma_tx_in_progress = false;
 611                 }
 612                 dmaengine_terminate_async(chan);
 613         }
 614
 615         if (lpuart_is_32(sport)) {
 616                 val = lpuart32_read(&sport->port, UARTFIFO);
 617                 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 618                 lpuart32_write(&sport->port, val, UARTFIFO);
 619         } else {
 620                 val = readb(sport->port.membase + UARTCFIFO);
 621                 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
 622                 writeb(val, sport->port.membase + UARTCFIFO);
 623         }
 624 }
 625
 626 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
 627                                 u8 bit)
 628 {
 629         while (!(readb(port->membase + offset) & bit))
 630                 cpu_relax();
 631 }
 632
 633 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
 634                                   u32 bit)
 635 {
 636         while (!(lpuart32_read(port, offset) & bit))
 637                 cpu_relax();
 638 }
 639
 640 #if defined(CONFIG_CONSOLE_POLL)
 641
 642 static int lpuart_poll_init(struct uart_port *port)
 643 {
 644         struct lpuart_port *sport = container_of(port,
 645                                         struct lpuart_port, port);
 646         unsigned long flags;
 647         unsigned char temp;
 648
 649         sport->port.fifosize = 0;
 650
 651         spin_lock_irqsave(&sport->port.lock, flags);
 652         /* Disable Rx & Tx */
 653         writeb(0, sport->port.membase + UARTCR2);
 654
 655         temp = readb(sport->port.membase + UARTPFIFO);
 656         /* Enable Rx and Tx FIFO */
 657         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 658                         sport->port.membase + UARTPFIFO);
 659
 660         /* flush Tx and Rx FIFO */
 661         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 662                         sport->port.membase + UARTCFIFO);
 663
 664         /* explicitly clear RDRF */
 665         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 666                 readb(sport->port.membase + UARTDR);
 667                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 668         }
 669
 670         writeb(0, sport->port.membase + UARTTWFIFO);
 671         writeb(1, sport->port.membase + UARTRWFIFO);
 672
 673         /* Enable Rx and Tx */
 674         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 675         spin_unlock_irqrestore(&sport->port.lock, flags);
 676
 677         return 0;
 678 }
 679
 680 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 681 {
 682         /* drain */
 683         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
 684         writeb(c, port->membase + UARTDR);
 685 }
 686
 687 static int lpuart_poll_get_char(struct uart_port *port)
 688 {
 689         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 690                 return NO_POLL_CHAR;
 691
 692         return readb(port->membase + UARTDR);
 693 }
 694
 695 static int lpuart32_poll_init(struct uart_port *port)
 696 {
 697         unsigned long flags;
 698         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 699         u32 temp;
 700
 701         sport->port.fifosize = 0;
 702
 703         spin_lock_irqsave(&sport->port.lock, flags);
 704
 705         /* Disable Rx & Tx */
 706         lpuart32_write(&sport->port, 0, UARTCTRL);
 707
 708         temp = lpuart32_read(&sport->port, UARTFIFO);
 709
 710         /* Enable Rx and Tx FIFO */
 711         lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
 712
 713         /* flush Tx and Rx FIFO */
 714         lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
 715
 716         /* explicitly clear RDRF */
 717         if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
 718                 lpuart32_read(&sport->port, UARTDATA);
 719                 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
 720         }
 721
 722         /* Enable Rx and Tx */
 723         lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
 724         spin_unlock_irqrestore(&sport->port.lock, flags);
 725
 726         return 0;
 727 }
 728
 729 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 730 {
 731         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
 732         lpuart32_write(port, c, UARTDATA);
 733 }
 734
 735 static int lpuart32_poll_get_char(struct uart_port *port)
 736 {
 737         if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
 738                 return NO_POLL_CHAR;
 739
 740         return lpuart32_read(port, UARTDATA);
 741 }
 742 #endif
 743
 744 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 745 {
 746         struct uart_port *port = &sport->port;
 747         u8 ch;
 748
 749         uart_port_tx(port, ch,
 750                 readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
 751                 writeb(ch, port->membase + UARTDR));
 752 }
 753
 754 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 755 {
 756         struct circ_buf *xmit = &sport->port.state->xmit;
 757         unsigned long txcnt;
 758
 759         if (sport->port.x_char) {
 760                 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 761                 sport->port.icount.tx++;
 762                 sport->port.x_char = 0;
 763                 return;
 764         }
 765
 766         if (lpuart_stopped_or_empty(&sport->port)) {
 767                 lpuart32_stop_tx(&sport->port);
 768                 return;
 769         }
 770
 771         txcnt = lpuart32_read(&sport->port, UARTWATER);
 772         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 773         txcnt &= UARTWATER_COUNT_MASK;
 774         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 775                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 776                 uart_xmit_advance(&sport->port, 1);
 777                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 778                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 779                 txcnt &= UARTWATER_COUNT_MASK;
 780         }
 781
 782         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 783                 uart_write_wakeup(&sport->port);
 784
 785         if (uart_circ_empty(xmit))
 786                 lpuart32_stop_tx(&sport->port);
 787 }
 788
 789 static void lpuart_start_tx(struct uart_port *port)
 790 {
 791         struct lpuart_port *sport = container_of(port,
 792                         struct lpuart_port, port);
 793         unsigned char temp;
 794
 795         temp = readb(port->membase + UARTCR2);
 796         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 797
 798         if (sport->lpuart_dma_tx_use) {
 799                 if (!lpuart_stopped_or_empty(port))
 800                         lpuart_dma_tx(sport);
 801         } else {
 802                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 803                         lpuart_transmit_buffer(sport);
 804         }
 805 }
 806
 807 static void lpuart32_start_tx(struct uart_port *port)
 808 {
 809         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 810         unsigned long temp;
 811
 812         if (sport->lpuart_dma_tx_use) {
 813                 if (!lpuart_stopped_or_empty(port))
 814                         lpuart_dma_tx(sport);
 815         } else {
 816                 temp = lpuart32_read(port, UARTCTRL);
 817                 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 818
 819                 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 820                         lpuart32_transmit_buffer(sport);
 821         }
 822 }
 823
 824 static void
 825 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
 826 {
 827         switch (state) {
 828         case UART_PM_STATE_OFF:
 829                 pm_runtime_mark_last_busy(port->dev);
 830                 pm_runtime_put_autosuspend(port->dev);
 831                 break;
 832         default:
 833                 pm_runtime_get_sync(port->dev);
 834                 break;
 835         }
 836 }
 837
 838 /* return TIOCSER_TEMT when transmitter is not busy */
 839 static unsigned int lpuart_tx_empty(struct uart_port *port)
 840 {
 841         struct lpuart_port *sport = container_of(port,
 842                         struct lpuart_port, port);
 843         unsigned char sr1 = readb(port->membase + UARTSR1);
 844         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 845
 846         if (sport->dma_tx_in_progress)
 847                 return 0;
 848
 849         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 850                 return TIOCSER_TEMT;
 851
 852         return 0;
 853 }
 854
 855 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 856 {
 857         struct lpuart_port *sport = container_of(port,
 858                         struct lpuart_port, port);
 859         unsigned long stat = lpuart32_read(port, UARTSTAT);
 860         unsigned long sfifo = lpuart32_read(port, UARTFIFO);
 861         unsigned long ctrl = lpuart32_read(port, UARTCTRL);
 862
 863         if (sport->dma_tx_in_progress)
 864                 return 0;
 865
 866         /*
 867          * LPUART Transmission Complete Flag may never be set while queuing a break
 868          * character, so avoid checking for transmission complete when UARTCTRL_SBK
 869          * is asserted.
 870          */
 871         if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)
 872                 return TIOCSER_TEMT;
 873
 874         return 0;
 875 }
 876
 877 static void lpuart_txint(struct lpuart_port *sport)
 878 {
 879         spin_lock(&sport->port.lock);
 880         lpuart_transmit_buffer(sport);
 881         spin_unlock(&sport->port.lock);
 882 }
 883
 884 static void lpuart_rxint(struct lpuart_port *sport)
 885 {
 886         unsigned int flg, ignored = 0, overrun = 0;
 887         struct tty_port *port = &sport->port.state->port;
 888         unsigned char rx, sr;
 889
 890         spin_lock(&sport->port.lock);
 891
 892         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 893                 flg = TTY_NORMAL;
 894                 sport->port.icount.rx++;
 895                 /*
 896                  * to clear the FE, OR, NF, FE, PE flags,
 897                  * read SR1 then read DR
 898                  */
 899                 sr = readb(sport->port.membase + UARTSR1);
 900                 rx = readb(sport->port.membase + UARTDR);
 901
 902                 if (uart_prepare_sysrq_char(&sport->port, rx))
 903                         continue;
 904
 905                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 906                         if (sr & UARTSR1_PE)
 907                                 sport->port.icount.parity++;
 908                         else if (sr & UARTSR1_FE)
 909                                 sport->port.icount.frame++;
 910
 911                         if (sr & UARTSR1_OR)
 912                                 overrun++;
 913
 914                         if (sr & sport->port.ignore_status_mask) {
 915                                 if (++ignored > 100)
 916                                         goto out;
 917                                 continue;
 918                         }
 919
 920                         sr &= sport->port.read_status_mask;
 921
 922                         if (sr & UARTSR1_PE)
 923                                 flg = TTY_PARITY;
 924                         else if (sr & UARTSR1_FE)
 925                                 flg = TTY_FRAME;
 926
 927                         if (sr & UARTSR1_OR)
 928                                 flg = TTY_OVERRUN;
 929
 930                         sport->port.sysrq = 0;
 931                 }
 932
 933                 if (tty_insert_flip_char(port, rx, flg) == 0)
 934                         sport->port.icount.buf_overrun++;
 935         }
 936
 937 out:
 938         if (overrun) {
 939                 sport->port.icount.overrun += overrun;
 940
 941                 /*
 942                  * Overruns cause FIFO pointers to become missaligned.
 943                  * Flushing the receive FIFO reinitializes the pointers.
 944                  */
 945                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 946                 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
 947         }
 948
 949         uart_unlock_and_check_sysrq(&sport->port);
 950
 951         tty_flip_buffer_push(port);
 952 }
 953
 954 static void lpuart32_txint(struct lpuart_port *sport)
 955 {
 956         spin_lock(&sport->port.lock);
 957         lpuart32_transmit_buffer(sport);
 958         spin_unlock(&sport->port.lock);
 959 }
 960
 961 static void lpuart32_rxint(struct lpuart_port *sport)
 962 {
 963         unsigned int flg, ignored = 0;
 964         struct tty_port *port = &sport->port.state->port;
 965         unsigned long rx, sr;
 966         bool is_break;
 967
 968         spin_lock(&sport->port.lock);
 969
 970         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 971                 flg = TTY_NORMAL;
 972                 sport->port.icount.rx++;
 973                 /*
 974                  * to clear the FE, OR, NF, FE, PE flags,
 975                  * read STAT then read DATA reg
 976                  */
 977                 sr = lpuart32_read(&sport->port, UARTSTAT);
 978                 rx = lpuart32_read(&sport->port, UARTDATA);
 979                 rx &= UARTDATA_MASK;
 980
 981                 /*
 982                  * The LPUART can't distinguish between a break and a framing error,
 983                  * thus we assume it is a break if the received data is zero.
 984                  */
 985                 is_break = (sr & UARTSTAT_FE) && !rx;
 986
 987                 if (is_break && uart_handle_break(&sport->port))
 988                         continue;
 989
 990                 if (uart_prepare_sysrq_char(&sport->port, rx))
 991                         continue;
 992
 993                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 994                         if (sr & UARTSTAT_PE) {
 995                                 sport->port.icount.parity++;
 996                         } else if (sr & UARTSTAT_FE) {
 997                                 if (is_break)
 998                                         sport->port.icount.brk++;
 999                                 else
1000                                         sport->port.icount.frame++;
1001                         }
1002
1003                         if (sr & UARTSTAT_OR)
1004                                 sport->port.icount.overrun++;
1005
1006                         if (sr & sport->port.ignore_status_mask) {
1007                                 if (++ignored > 100)
1008                                         goto out;
1009                                 continue;
1010                         }
1011
1012                         sr &= sport->port.read_status_mask;
1013
1014                         if (sr & UARTSTAT_PE) {
1015                                 flg = TTY_PARITY;
1016                         } else if (sr & UARTSTAT_FE) {
1017                                 if (is_break)
1018                                         flg = TTY_BREAK;
1019                                 else
1020                                         flg = TTY_FRAME;
1021                         }
1022
1023                         if (sr & UARTSTAT_OR)
1024                                 flg = TTY_OVERRUN;
1025                 }
1026
1027                 if (sport->is_cs7)
1028                         rx &= 0x7F;
1029
1030                 if (tty_insert_flip_char(port, rx, flg) == 0)
1031                         sport->port.icount.buf_overrun++;
1032         }
1033
1034 out:
1035         uart_unlock_and_check_sysrq(&sport->port);
1036
1037         tty_flip_buffer_push(port);
1038 }
1039
1040 static irqreturn_t lpuart_int(int irq, void *dev_id)
1041 {
1042         struct lpuart_port *sport = dev_id;
1043         unsigned char sts;
1044
1045         sts = readb(sport->port.membase + UARTSR1);
1046
1047         /* SysRq, using dma, check for linebreak by framing err. */
1048         if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1049                 readb(sport->port.membase + UARTDR);
1050                 uart_handle_break(&sport->port);
1051                 /* linebreak produces some garbage, removing it */
1052                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1053                 return IRQ_HANDLED;
1054         }
1055
1056         if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1057                 lpuart_rxint(sport);
1058
1059         if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1060                 lpuart_txint(sport);
1061
1062         return IRQ_HANDLED;
1063 }
1064
1065 static irqreturn_t lpuart32_int(int irq, void *dev_id)
1066 {
1067         struct lpuart_port *sport = dev_id;
1068         unsigned long sts, rxcount;
1069
1070         sts = lpuart32_read(&sport->port, UARTSTAT);
1071         rxcount = lpuart32_read(&sport->port, UARTWATER);
1072         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1073
1074         if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1075                 lpuart32_rxint(sport);
1076
1077         if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1078                 lpuart32_txint(sport);
1079
1080         lpuart32_write(&sport->port, sts, UARTSTAT);
1081         return IRQ_HANDLED;
1082 }
1083
1084
1085 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1086                                              unsigned char *p, int count)
1087 {
1088         while (count--) {
1089                 if (*p && uart_handle_sysrq_char(port, *p))
1090                         return;
1091                 p++;
1092         }
1093 }
1094
1095 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1096 {
1097         struct circ_buf *ring = &sport->rx_ring;
1098         int count;
1099
1100         if (ring->head < ring->tail) {
1101                 count = sport->rx_sgl.length - ring->tail;
1102                 lpuart_handle_sysrq_chars(&sport->port,
1103                                           ring->buf + ring->tail, count);
1104                 ring->tail = 0;
1105         }
1106
1107         if (ring->head > ring->tail) {
1108                 count = ring->head - ring->tail;
1109                 lpuart_handle_sysrq_chars(&sport->port,
1110                                           ring->buf + ring->tail, count);
1111                 ring->tail = ring->head;
1112         }
1113 }
1114
1115 static int lpuart_tty_insert_flip_string(struct tty_port *port,
1116         unsigned char *chars, size_t size, bool is_cs7)
1117 {
1118         int i;
1119
1120         if (is_cs7)
1121                 for (i = 0; i < size; i++)
1122                         chars[i] &= 0x7F;
1123         return tty_insert_flip_string(port, chars, size);
1124 }
1125
1126 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1127 {
1128         struct tty_port *port = &sport->port.state->port;
1129         struct dma_tx_state state;
1130         enum dma_status dmastat;
1131         struct dma_chan *chan = sport->dma_rx_chan;
1132         struct circ_buf *ring = &sport->rx_ring;
1133         unsigned long flags;
1134         int count, copied;
1135
1136         if (lpuart_is_32(sport)) {
1137                 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1138
1139                 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1140                         /* Read DR to clear the error flags */
1141                         lpuart32_read(&sport->port, UARTDATA);
1142
1143                         if (sr & UARTSTAT_PE)
1144                                 sport->port.icount.parity++;
1145                         else if (sr & UARTSTAT_FE)
1146                                 sport->port.icount.frame++;
1147                 }
1148         } else {
1149                 unsigned char sr = readb(sport->port.membase + UARTSR1);
1150
1151                 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1152                         unsigned char cr2;
1153
1154                         /* Disable receiver during this operation... */
1155                         cr2 = readb(sport->port.membase + UARTCR2);
1156                         cr2 &= ~UARTCR2_RE;
1157                         writeb(cr2, sport->port.membase + UARTCR2);
1158
1159                         /* Read DR to clear the error flags */
1160                         readb(sport->port.membase + UARTDR);
1161
1162                         if (sr & UARTSR1_PE)
1163                                 sport->port.icount.parity++;
1164                         else if (sr & UARTSR1_FE)
1165                                 sport->port.icount.frame++;
1166                         /*
1167                          * At this point parity/framing error is
1168                          * cleared However, since the DMA already read
1169                          * the data register and we had to read it
1170                          * again after reading the status register to
1171                          * properly clear the flags, the FIFO actually
1172                          * underflowed... This requires a clearing of
1173                          * the FIFO...
1174                          */
1175                         if (readb(sport->port.membase + UARTSFIFO) &
1176                             UARTSFIFO_RXUF) {
1177                                 writeb(UARTSFIFO_RXUF,
1178                                        sport->port.membase + UARTSFIFO);
1179                                 writeb(UARTCFIFO_RXFLUSH,
1180                                        sport->port.membase + UARTCFIFO);
1181                         }
1182
1183                         cr2 |= UARTCR2_RE;
1184                         writeb(cr2, sport->port.membase + UARTCR2);
1185                 }
1186         }
1187
1188         async_tx_ack(sport->dma_rx_desc);
1189
1190         spin_lock_irqsave(&sport->port.lock, flags);
1191
1192         dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1193         if (dmastat == DMA_ERROR) {
1194                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1195                 spin_unlock_irqrestore(&sport->port.lock, flags);
1196                 return;
1197         }
1198
1199         /* CPU claims ownership of RX DMA buffer */
1200         dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1201                             DMA_FROM_DEVICE);
1202
1203         /*
1204          * ring->head points to the end of data already written by the DMA.
1205          * ring->tail points to the beginning of data to be read by the
1206          * framework.
1207          * The current transfer size should not be larger than the dma buffer
1208          * length.
1209          */
1210         ring->head = sport->rx_sgl.length - state.residue;
1211         BUG_ON(ring->head > sport->rx_sgl.length);
1212
1213         /*
1214          * Silent handling of keys pressed in the sysrq timeframe
1215          */
1216         if (sport->port.sysrq) {
1217                 lpuart_handle_sysrq(sport);
1218                 goto exit;
1219         }
1220
1221         /*
1222          * At this point ring->head may point to the first byte right after the
1223          * last byte of the dma buffer:
1224          * 0 <= ring->head <= sport->rx_sgl.length
1225          *
1226          * However ring->tail must always points inside the dma buffer:
1227          * 0 <= ring->tail <= sport->rx_sgl.length - 1
1228          *
1229          * Since we use a ring buffer, we have to handle the case
1230          * where head is lower than tail. In such a case, we first read from
1231          * tail to the end of the buffer then reset tail.
1232          */
1233         if (ring->head < ring->tail) {
1234                 count = sport->rx_sgl.length - ring->tail;
1235
1236                 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1237                                         count, sport->is_cs7);
1238                 if (copied != count)
1239                         sport->port.icount.buf_overrun++;
1240                 ring->tail = 0;
1241                 sport->port.icount.rx += copied;
1242         }
1243
1244         /* Finally we read data from tail to head */
1245         if (ring->tail < ring->head) {
1246                 count = ring->head - ring->tail;
1247                 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1248                                         count, sport->is_cs7);
1249                 if (copied != count)
1250                         sport->port.icount.buf_overrun++;
1251                 /* Wrap ring->head if needed */
1252                 if (ring->head >= sport->rx_sgl.length)
1253                         ring->head = 0;
1254                 ring->tail = ring->head;
1255                 sport->port.icount.rx += copied;
1256         }
1257
1258 exit:
1259         dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1260                                DMA_FROM_DEVICE);
1261
1262         spin_unlock_irqrestore(&sport->port.lock, flags);
1263
1264         tty_flip_buffer_push(port);
1265         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1266 }
1267
1268 static void lpuart_dma_rx_complete(void *arg)
1269 {
1270         struct lpuart_port *sport = arg;
1271
1272         lpuart_copy_rx_to_tty(sport);
1273 }
1274
1275 static void lpuart_timer_func(struct timer_list *t)
1276 {
1277         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1278
1279         lpuart_copy_rx_to_tty(sport);
1280 }
1281
1282 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1283 {
1284         struct dma_slave_config dma_rx_sconfig = {};
1285         struct circ_buf *ring = &sport->rx_ring;
1286         int ret, nent;
1287         struct tty_port *port = &sport->port.state->port;
1288         struct tty_struct *tty = port->tty;
1289         struct ktermios *termios = &tty->termios;
1290         struct dma_chan *chan = sport->dma_rx_chan;
1291         unsigned int bits = tty_get_frame_size(termios->c_cflag);
1292         unsigned int baud = tty_get_baud_rate(tty);
1293
1294         /*
1295          * Calculate length of one DMA buffer size to keep latency below
1296          * 10ms at any baud rate.
1297          */
1298         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1299         sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1300         if (sport->rx_dma_rng_buf_len < 16)
1301                 sport->rx_dma_rng_buf_len = 16;
1302
1303         ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1304         if (!ring->buf)
1305                 return -ENOMEM;
1306
1307         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1308         nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1309                           DMA_FROM_DEVICE);
1310
1311         if (!nent) {
1312                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1313                 return -EINVAL;
1314         }
1315
1316         dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1317         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1318         dma_rx_sconfig.src_maxburst = 1;
1319         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1320         ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1321
1322         if (ret < 0) {
1323                 dev_err(sport->port.dev,
1324                                 "DMA Rx slave config failed, err = %d\n", ret);
1325                 return ret;
1326         }
1327
1328         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1329                                  sg_dma_address(&sport->rx_sgl),
1330                                  sport->rx_sgl.length,
1331                                  sport->rx_sgl.length / 2,
1332                                  DMA_DEV_TO_MEM,
1333                                  DMA_PREP_INTERRUPT);
1334         if (!sport->dma_rx_desc) {
1335                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1336                 return -EFAULT;
1337         }
1338
1339         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1340         sport->dma_rx_desc->callback_param = sport;
1341         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1342         dma_async_issue_pending(chan);
1343
1344         if (lpuart_is_32(sport)) {
1345                 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1346
1347                 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1348         } else {
1349                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1350                        sport->port.membase + UARTCR5);
1351         }
1352
1353         return 0;
1354 }
1355
1356 static void lpuart_dma_rx_free(struct uart_port *port)
1357 {
1358         struct lpuart_port *sport = container_of(port,
1359                                         struct lpuart_port, port);
1360         struct dma_chan *chan = sport->dma_rx_chan;
1361
1362         dmaengine_terminate_sync(chan);
1363         del_timer_sync(&sport->lpuart_timer);
1364         dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1365         kfree(sport->rx_ring.buf);
1366         sport->rx_ring.tail = 0;
1367         sport->rx_ring.head = 0;
1368         sport->dma_rx_desc = NULL;
1369         sport->dma_rx_cookie = -EINVAL;
1370 }
1371
1372 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
1373                         struct serial_rs485 *rs485)
1374 {
1375         struct lpuart_port *sport = container_of(port,
1376                         struct lpuart_port, port);
1377
1378         u8 modem = readb(sport->port.membase + UARTMODEM) &
1379                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1380         writeb(modem, sport->port.membase + UARTMODEM);
1381
1382         if (rs485->flags & SER_RS485_ENABLED) {
1383                 /* Enable auto RS-485 RTS mode */
1384                 modem |= UARTMODEM_TXRTSE;
1385
1386                 /*
1387                  * The hardware defaults to RTS logic HIGH while transfer.
1388                  * Switch polarity in case RTS shall be logic HIGH
1389                  * after transfer.
1390                  * Note: UART is assumed to be active high.
1391                  */
1392                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1393                         modem |= UARTMODEM_TXRTSPOL;
1394                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1395                         modem &= ~UARTMODEM_TXRTSPOL;
1396         }
1397
1398         writeb(modem, sport->port.membase + UARTMODEM);
1399         return 0;
1400 }
1401
1402 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
1403                         struct serial_rs485 *rs485)
1404 {
1405         struct lpuart_port *sport = container_of(port,
1406                         struct lpuart_port, port);
1407
1408         unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1409                                 & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE);
1410         lpuart32_write(&sport->port, modem, UARTMODIR);
1411
1412         if (rs485->flags & SER_RS485_ENABLED) {
1413                 /* Enable auto RS-485 RTS mode */
1414                 modem |= UARTMODIR_TXRTSE;
1415
1416                 /*
1417                  * The hardware defaults to RTS logic HIGH while transfer.
1418                  * Switch polarity in case RTS shall be logic HIGH
1419                  * after transfer.
1420                  * Note: UART is assumed to be active high.
1421                  */
1422                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1423                         modem |= UARTMODIR_TXRTSPOL;
1424                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1425                         modem &= ~UARTMODIR_TXRTSPOL;
1426         }
1427
1428         lpuart32_write(&sport->port, modem, UARTMODIR);
1429         return 0;
1430 }
1431
1432 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1433 {
1434         unsigned int mctrl = 0;
1435         u8 reg;
1436
1437         reg = readb(port->membase + UARTCR1);
1438         if (reg & UARTCR1_LOOPS)
1439                 mctrl |= TIOCM_LOOP;
1440
1441         return mctrl;
1442 }
1443
1444 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1445 {
1446         unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1447         u32 reg;
1448
1449         reg = lpuart32_read(port, UARTCTRL);
1450         if (reg & UARTCTRL_LOOPS)
1451                 mctrl |= TIOCM_LOOP;
1452
1453         return mctrl;
1454 }
1455
1456 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1457 {
1458         u8 reg;
1459
1460         reg = readb(port->membase + UARTCR1);
1461
1462         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1463         reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1464         if (mctrl & TIOCM_LOOP)
1465                 reg |= UARTCR1_LOOPS;
1466
1467         writeb(reg, port->membase + UARTCR1);
1468 }
1469
1470 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1471 {
1472         u32 reg;
1473
1474         reg = lpuart32_read(port, UARTCTRL);
1475
1476         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1477         reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1478         if (mctrl & TIOCM_LOOP)
1479                 reg |= UARTCTRL_LOOPS;
1480
1481         lpuart32_write(port, reg, UARTCTRL);
1482 }
1483
1484 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1485 {
1486         unsigned char temp;
1487
1488         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1489
1490         if (break_state != 0)
1491                 temp |= UARTCR2_SBK;
1492
1493         writeb(temp, port->membase + UARTCR2);
1494 }
1495
1496 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1497 {
1498         unsigned long temp, modem;
1499         struct tty_struct *tty;
1500         unsigned int cflag = 0;
1501
1502         tty = tty_port_tty_get(&port->state->port);
1503         if (tty) {
1504                 cflag = tty->termios.c_cflag;
1505                 tty_kref_put(tty);
1506         }
1507
1508         temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1509         modem = lpuart32_read(port, UARTMODIR);
1510
1511         if (break_state != 0) {
1512                 temp |= UARTCTRL_SBK;
1513                 /*
1514                  * LPUART CTS has higher priority than SBK, need to disable CTS before
1515                  * asserting SBK to avoid any interference if flow control is enabled.
1516                  */
1517                 if (cflag & CRTSCTS && modem & UARTMODIR_TXCTSE)
1518                         lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
1519         } else {
1520                 /* Re-enable the CTS when break off. */
1521                 if (cflag & CRTSCTS && !(modem & UARTMODIR_TXCTSE))
1522                         lpuart32_write(port, modem | UARTMODIR_TXCTSE, UARTMODIR);
1523         }
1524
1525         lpuart32_write(port, temp, UARTCTRL);
1526 }
1527
1528 static void lpuart_setup_watermark(struct lpuart_port *sport)
1529 {
1530         unsigned char val, cr2;
1531         unsigned char cr2_saved;
1532
1533         cr2 = readb(sport->port.membase + UARTCR2);
1534         cr2_saved = cr2;
1535         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1536                         UARTCR2_RIE | UARTCR2_RE);
1537         writeb(cr2, sport->port.membase + UARTCR2);
1538
1539         val = readb(sport->port.membase + UARTPFIFO);
1540         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1541                         sport->port.membase + UARTPFIFO);
1542
1543         /* flush Tx and Rx FIFO */
1544         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1545                         sport->port.membase + UARTCFIFO);
1546
1547         /* explicitly clear RDRF */
1548         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1549                 readb(sport->port.membase + UARTDR);
1550                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1551         }
1552
1553         if (uart_console(&sport->port))
1554                 sport->rx_watermark = 1;
1555         writeb(0, sport->port.membase + UARTTWFIFO);
1556         writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
1557
1558         /* Restore cr2 */
1559         writeb(cr2_saved, sport->port.membase + UARTCR2);
1560 }
1561
1562 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1563 {
1564         unsigned char cr2;
1565
1566         lpuart_setup_watermark(sport);
1567
1568         cr2 = readb(sport->port.membase + UARTCR2);
1569         cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1570         writeb(cr2, sport->port.membase + UARTCR2);
1571 }
1572
1573 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1574 {
1575         unsigned long val, ctrl;
1576         unsigned long ctrl_saved;
1577
1578         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1579         ctrl_saved = ctrl;
1580         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1581                         UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE);
1582         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1583
1584         /* enable FIFO mode */
1585         val = lpuart32_read(&sport->port, UARTFIFO);
1586         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1587         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1588         val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3);
1589         lpuart32_write(&sport->port, val, UARTFIFO);
1590
1591         /* set the watermark */
1592         if (uart_console(&sport->port))
1593                 sport->rx_watermark = 1;
1594         val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
1595               (0x0 << UARTWATER_TXWATER_OFF);
1596         lpuart32_write(&sport->port, val, UARTWATER);
1597
1598         /* set RTS watermark */
1599         if (!uart_console(&sport->port)) {
1600                 val = lpuart32_read(&sport->port, UARTMODIR);
1601                 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1);
1602                 lpuart32_write(&sport->port, val, UARTMODIR);
1603         }
1604
1605         /* Restore cr2 */
1606         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1607 }
1608
1609 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1610 {
1611         u32 temp;
1612
1613         lpuart32_setup_watermark(sport);
1614
1615         temp = lpuart32_read(&sport->port, UARTCTRL);
1616         temp |= UARTCTRL_RE | UARTCTRL_TE;
1617         temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
1618         lpuart32_write(&sport->port, temp, UARTCTRL);
1619 }
1620
1621 static void rx_dma_timer_init(struct lpuart_port *sport)
1622 {
1623         timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1624         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1625         add_timer(&sport->lpuart_timer);
1626 }
1627
1628 static void lpuart_request_dma(struct lpuart_port *sport)
1629 {
1630         sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1631         if (IS_ERR(sport->dma_tx_chan)) {
1632                 dev_dbg_once(sport->port.dev,
1633                              "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1634                              PTR_ERR(sport->dma_tx_chan));
1635                 sport->dma_tx_chan = NULL;
1636         }
1637
1638         sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1639         if (IS_ERR(sport->dma_rx_chan)) {
1640                 dev_dbg_once(sport->port.dev,
1641                              "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1642                              PTR_ERR(sport->dma_rx_chan));
1643                 sport->dma_rx_chan = NULL;
1644         }
1645 }
1646
1647 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1648 {
1649         u32 uartbaud;
1650         int ret;
1651
1652         if (uart_console(&sport->port))
1653                 goto err;
1654
1655         if (!sport->dma_tx_chan)
1656                 goto err;
1657
1658         ret = lpuart_dma_tx_request(&sport->port);
1659         if (ret)
1660                 goto err;
1661
1662         init_waitqueue_head(&sport->dma_wait);
1663         sport->lpuart_dma_tx_use = true;
1664         if (lpuart_is_32(sport)) {
1665                 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1666                 lpuart32_write(&sport->port,
1667                                uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1668         } else {
1669                 writeb(readb(sport->port.membase + UARTCR5) |
1670                        UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1671         }
1672
1673         return;
1674
1675 err:
1676         sport->lpuart_dma_tx_use = false;
1677 }
1678
1679 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1680 {
1681         int ret;
1682         unsigned char cr3;
1683
1684         if (uart_console(&sport->port))
1685                 goto err;
1686
1687         if (!sport->dma_rx_chan)
1688                 goto err;
1689
1690         ret = lpuart_start_rx_dma(sport);
1691         if (ret)
1692                 goto err;
1693
1694         /* set Rx DMA timeout */
1695         sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1696         if (!sport->dma_rx_timeout)
1697                 sport->dma_rx_timeout = 1;
1698
1699         sport->lpuart_dma_rx_use = true;
1700         rx_dma_timer_init(sport);
1701
1702         if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1703                 cr3 = readb(sport->port.membase + UARTCR3);
1704                 cr3 |= UARTCR3_FEIE;
1705                 writeb(cr3, sport->port.membase + UARTCR3);
1706         }
1707
1708         return;
1709
1710 err:
1711         sport->lpuart_dma_rx_use = false;
1712 }
1713
1714 static void lpuart_hw_setup(struct lpuart_port *sport)
1715 {
1716         unsigned long flags;
1717
1718         spin_lock_irqsave(&sport->port.lock, flags);
1719
1720         lpuart_setup_watermark_enable(sport);
1721
1722         lpuart_rx_dma_startup(sport);
1723         lpuart_tx_dma_startup(sport);
1724
1725         spin_unlock_irqrestore(&sport->port.lock, flags);
1726 }
1727
1728 static int lpuart_startup(struct uart_port *port)
1729 {
1730         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1731         unsigned char temp;
1732
1733         /* determine FIFO size and enable FIFO mode */
1734         temp = readb(sport->port.membase + UARTPFIFO);
1735
1736         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1737                                             UARTPFIFO_FIFOSIZE_MASK);
1738         sport->port.fifosize = sport->txfifo_size;
1739
1740         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1741                                             UARTPFIFO_FIFOSIZE_MASK);
1742
1743         lpuart_request_dma(sport);
1744         lpuart_hw_setup(sport);
1745
1746         return 0;
1747 }
1748
1749 static void lpuart32_hw_disable(struct lpuart_port *sport)
1750 {
1751         unsigned long temp;
1752
1753         temp = lpuart32_read(&sport->port, UARTCTRL);
1754         temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
1755                   UARTCTRL_TIE | UARTCTRL_TE);
1756         lpuart32_write(&sport->port, temp, UARTCTRL);
1757 }
1758
1759 static void lpuart32_configure(struct lpuart_port *sport)
1760 {
1761         unsigned long temp;
1762
1763         temp = lpuart32_read(&sport->port, UARTCTRL);
1764         if (!sport->lpuart_dma_rx_use)
1765                 temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
1766         if (!sport->lpuart_dma_tx_use)
1767                 temp |= UARTCTRL_TIE;
1768         lpuart32_write(&sport->port, temp, UARTCTRL);
1769 }
1770
1771 static void lpuart32_hw_setup(struct lpuart_port *sport)
1772 {
1773         unsigned long flags;
1774
1775         spin_lock_irqsave(&sport->port.lock, flags);
1776
1777         lpuart32_hw_disable(sport);
1778
1779         lpuart_rx_dma_startup(sport);
1780         lpuart_tx_dma_startup(sport);
1781
1782         lpuart32_setup_watermark_enable(sport);
1783         lpuart32_configure(sport);
1784
1785         spin_unlock_irqrestore(&sport->port.lock, flags);
1786 }
1787
1788 static int lpuart32_startup(struct uart_port *port)
1789 {
1790         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1791         unsigned long temp;
1792
1793         /* determine FIFO size */
1794         temp = lpuart32_read(&sport->port, UARTFIFO);
1795
1796         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1797                                             UARTFIFO_FIFOSIZE_MASK);
1798         sport->port.fifosize = sport->txfifo_size;
1799
1800         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1801                                             UARTFIFO_FIFOSIZE_MASK);
1802
1803         /*
1804          * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1805          * Although they support the RX/TXSIZE fields, their encoding is
1806          * different. Eg the reference manual states 0b101 is 16 words.
1807          */
1808         if (is_layerscape_lpuart(sport)) {
1809                 sport->rxfifo_size = 16;
1810                 sport->txfifo_size = 16;
1811                 sport->port.fifosize = sport->txfifo_size;
1812         }
1813
1814         lpuart_request_dma(sport);
1815         lpuart32_hw_setup(sport);
1816
1817         return 0;
1818 }
1819
1820 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1821 {
1822         if (sport->lpuart_dma_rx_use) {
1823                 lpuart_dma_rx_free(&sport->port);
1824                 sport->lpuart_dma_rx_use = false;
1825         }
1826
1827         if (sport->lpuart_dma_tx_use) {
1828                 if (wait_event_interruptible_timeout(sport->dma_wait,
1829                         !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
1830                         sport->dma_tx_in_progress = false;
1831                         dmaengine_terminate_sync(sport->dma_tx_chan);
1832                 }
1833                 sport->lpuart_dma_tx_use = false;
1834         }
1835
1836         if (sport->dma_tx_chan)
1837                 dma_release_channel(sport->dma_tx_chan);
1838         if (sport->dma_rx_chan)
1839                 dma_release_channel(sport->dma_rx_chan);
1840 }
1841
1842 static void lpuart_shutdown(struct uart_port *port)
1843 {
1844         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1845         unsigned char temp;
1846         unsigned long flags;
1847
1848         spin_lock_irqsave(&port->lock, flags);
1849
1850         /* disable Rx/Tx and interrupts */
1851         temp = readb(port->membase + UARTCR2);
1852         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1853                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1854         writeb(temp, port->membase + UARTCR2);
1855
1856         spin_unlock_irqrestore(&port->lock, flags);
1857
1858         lpuart_dma_shutdown(sport);
1859 }
1860
1861 static void lpuart32_shutdown(struct uart_port *port)
1862 {
1863         struct lpuart_port *sport =
1864                 container_of(port, struct lpuart_port, port);
1865         unsigned long temp;
1866         unsigned long flags;
1867
1868         spin_lock_irqsave(&port->lock, flags);
1869
1870         /* clear status */
1871         temp = lpuart32_read(&sport->port, UARTSTAT);
1872         lpuart32_write(&sport->port, temp, UARTSTAT);
1873
1874         /* disable Rx/Tx DMA */
1875         temp = lpuart32_read(port, UARTBAUD);
1876         temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1877         lpuart32_write(port, temp, UARTBAUD);
1878
1879         /* disable Rx/Tx and interrupts and break condition */
1880         temp = lpuart32_read(port, UARTCTRL);
1881         temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE |
1882                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK);
1883         lpuart32_write(port, temp, UARTCTRL);
1884
1885         spin_unlock_irqrestore(&port->lock, flags);
1886
1887         lpuart_dma_shutdown(sport);
1888 }
1889
1890 static void
1891 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1892                    const struct ktermios *old)
1893 {
1894         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1895         unsigned long flags;
1896         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1897         unsigned int  baud;
1898         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1899         unsigned int sbr, brfa;
1900
1901         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1902         old_cr2 = readb(sport->port.membase + UARTCR2);
1903         cr3 = readb(sport->port.membase + UARTCR3);
1904         cr4 = readb(sport->port.membase + UARTCR4);
1905         bdh = readb(sport->port.membase + UARTBDH);
1906         modem = readb(sport->port.membase + UARTMODEM);
1907         /*
1908          * only support CS8 and CS7, and for CS7 must enable PE.
1909          * supported mode:
1910          *  - (7,e/o,1)
1911          *  - (8,n,1)
1912          *  - (8,m/s,1)
1913          *  - (8,e/o,1)
1914          */
1915         while ((termios->c_cflag & CSIZE) != CS8 &&
1916                 (termios->c_cflag & CSIZE) != CS7) {
1917                 termios->c_cflag &= ~CSIZE;
1918                 termios->c_cflag |= old_csize;
1919                 old_csize = CS8;
1920         }
1921
1922         if ((termios->c_cflag & CSIZE) == CS8 ||
1923                 (termios->c_cflag & CSIZE) == CS7)
1924                 cr1 = old_cr1 & ~UARTCR1_M;
1925
1926         if (termios->c_cflag & CMSPAR) {
1927                 if ((termios->c_cflag & CSIZE) != CS8) {
1928                         termios->c_cflag &= ~CSIZE;
1929                         termios->c_cflag |= CS8;
1930                 }
1931                 cr1 |= UARTCR1_M;
1932         }
1933
1934         /*
1935          * When auto RS-485 RTS mode is enabled,
1936          * hardware flow control need to be disabled.
1937          */
1938         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1939                 termios->c_cflag &= ~CRTSCTS;
1940
1941         if (termios->c_cflag & CRTSCTS)
1942                 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1943         else
1944                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1945
1946         termios->c_cflag &= ~CSTOPB;
1947
1948         /* parity must be enabled when CS7 to match 8-bits format */
1949         if ((termios->c_cflag & CSIZE) == CS7)
1950                 termios->c_cflag |= PARENB;
1951
1952         if (termios->c_cflag & PARENB) {
1953                 if (termios->c_cflag & CMSPAR) {
1954                         cr1 &= ~UARTCR1_PE;
1955                         if (termios->c_cflag & PARODD)
1956                                 cr3 |= UARTCR3_T8;
1957                         else
1958                                 cr3 &= ~UARTCR3_T8;
1959                 } else {
1960                         cr1 |= UARTCR1_PE;
1961                         if ((termios->c_cflag & CSIZE) == CS8)
1962                                 cr1 |= UARTCR1_M;
1963                         if (termios->c_cflag & PARODD)
1964                                 cr1 |= UARTCR1_PT;
1965                         else
1966                                 cr1 &= ~UARTCR1_PT;
1967                 }
1968         } else {
1969                 cr1 &= ~UARTCR1_PE;
1970         }
1971
1972         /* ask the core to calculate the divisor */
1973         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1974
1975         /*
1976          * Need to update the Ring buffer length according to the selected
1977          * baud rate and restart Rx DMA path.
1978          *
1979          * Since timer function acqures sport->port.lock, need to stop before
1980          * acquring same lock because otherwise del_timer_sync() can deadlock.
1981          */
1982         if (old && sport->lpuart_dma_rx_use)
1983                 lpuart_dma_rx_free(&sport->port);
1984
1985         spin_lock_irqsave(&sport->port.lock, flags);
1986
1987         sport->port.read_status_mask = 0;
1988         if (termios->c_iflag & INPCK)
1989                 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1990         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1991                 sport->port.read_status_mask |= UARTSR1_FE;
1992
1993         /* characters to ignore */
1994         sport->port.ignore_status_mask = 0;
1995         if (termios->c_iflag & IGNPAR)
1996                 sport->port.ignore_status_mask |= UARTSR1_PE;
1997         if (termios->c_iflag & IGNBRK) {
1998                 sport->port.ignore_status_mask |= UARTSR1_FE;
1999                 /*
2000                  * if we're ignoring parity and break indicators,
2001                  * ignore overruns too (for real raw support).
2002                  */
2003                 if (termios->c_iflag & IGNPAR)
2004                         sport->port.ignore_status_mask |= UARTSR1_OR;
2005         }
2006
2007         /* update the per-port timeout */
2008         uart_update_timeout(port, termios->c_cflag, baud);
2009
2010         /* wait transmit engin complete */
2011         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2012
2013         /* disable transmit and receive */
2014         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
2015                         sport->port.membase + UARTCR2);
2016
2017         sbr = sport->port.uartclk / (16 * baud);
2018         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
2019         bdh &= ~UARTBDH_SBR_MASK;
2020         bdh |= (sbr >> 8) & 0x1F;
2021         cr4 &= ~UARTCR4_BRFA_MASK;
2022         brfa &= UARTCR4_BRFA_MASK;
2023         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
2024         writeb(bdh, sport->port.membase + UARTBDH);
2025         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
2026         writeb(cr3, sport->port.membase + UARTCR3);
2027         writeb(cr1, sport->port.membase + UARTCR1);
2028         writeb(modem, sport->port.membase + UARTMODEM);
2029
2030         /* restore control register */
2031         writeb(old_cr2, sport->port.membase + UARTCR2);
2032
2033         if (old && sport->lpuart_dma_rx_use) {
2034                 if (!lpuart_start_rx_dma(sport))
2035                         rx_dma_timer_init(sport);
2036                 else
2037                         sport->lpuart_dma_rx_use = false;
2038         }
2039
2040         spin_unlock_irqrestore(&sport->port.lock, flags);
2041 }
2042
2043 static void __lpuart32_serial_setbrg(struct uart_port *port,
2044                                      unsigned int baudrate, bool use_rx_dma,
2045                                      bool use_tx_dma)
2046 {
2047         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
2048         u32 clk = port->uartclk;
2049
2050         /*
2051          * The idea is to use the best OSR (over-sampling rate) possible.
2052          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
2053          * Loop to find the best OSR value possible, one that generates minimum
2054          * baud_diff iterate through the rest of the supported values of OSR.
2055          *
2056          * Calculation Formula:
2057          *  Baud Rate = baud clock / ((OSR+1) × SBR)
2058          */
2059         baud_diff = baudrate;
2060         osr = 0;
2061         sbr = 0;
2062
2063         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
2064                 /* calculate the temporary sbr value  */
2065                 tmp_sbr = (clk / (baudrate * tmp_osr));
2066                 if (tmp_sbr == 0)
2067                         tmp_sbr = 1;
2068
2069                 /*
2070                  * calculate the baud rate difference based on the temporary
2071                  * osr and sbr values
2072                  */
2073                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
2074
2075                 /* select best values between sbr and sbr+1 */
2076                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
2077                 if (tmp_diff > (baudrate - tmp)) {
2078                         tmp_diff = baudrate - tmp;
2079                         tmp_sbr++;
2080                 }
2081
2082                 if (tmp_sbr > UARTBAUD_SBR_MASK)
2083                         continue;
2084
2085                 if (tmp_diff <= baud_diff) {
2086                         baud_diff = tmp_diff;
2087                         osr = tmp_osr;
2088                         sbr = tmp_sbr;
2089
2090                         if (!baud_diff)
2091                                 break;
2092                 }
2093         }
2094
2095         /* handle buadrate outside acceptable rate */
2096         if (baud_diff > ((baudrate / 100) * 3))
2097                 dev_warn(port->dev,
2098                          "unacceptable baud rate difference of more than 3%%\n");
2099
2100         tmp = lpuart32_read(port, UARTBAUD);
2101
2102         if ((osr > 3) && (osr < 8))
2103                 tmp |= UARTBAUD_BOTHEDGE;
2104
2105         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2106         tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2107
2108         tmp &= ~UARTBAUD_SBR_MASK;
2109         tmp |= sbr & UARTBAUD_SBR_MASK;
2110
2111         if (!use_rx_dma)
2112                 tmp &= ~UARTBAUD_RDMAE;
2113         if (!use_tx_dma)
2114                 tmp &= ~UARTBAUD_TDMAE;
2115
2116         lpuart32_write(port, tmp, UARTBAUD);
2117 }
2118
2119 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2120                                    unsigned int baudrate)
2121 {
2122         __lpuart32_serial_setbrg(&sport->port, baudrate,
2123                                  sport->lpuart_dma_rx_use,
2124                                  sport->lpuart_dma_tx_use);
2125 }
2126
2127
2128 static void
2129 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2130                      const struct ktermios *old)
2131 {
2132         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2133         unsigned long flags;
2134         unsigned long ctrl, old_ctrl, bd, modem;
2135         unsigned int  baud;
2136         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2137
2138         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2139         bd = lpuart32_read(&sport->port, UARTBAUD);
2140         modem = lpuart32_read(&sport->port, UARTMODIR);
2141         sport->is_cs7 = false;
2142         /*
2143          * only support CS8 and CS7, and for CS7 must enable PE.
2144          * supported mode:
2145          *  - (7,e/o,1)
2146          *  - (8,n,1)
2147          *  - (8,m/s,1)
2148          *  - (8,e/o,1)
2149          */
2150         while ((termios->c_cflag & CSIZE) != CS8 &&
2151                 (termios->c_cflag & CSIZE) != CS7) {
2152                 termios->c_cflag &= ~CSIZE;
2153                 termios->c_cflag |= old_csize;
2154                 old_csize = CS8;
2155         }
2156
2157         if ((termios->c_cflag & CSIZE) == CS8 ||
2158                 (termios->c_cflag & CSIZE) == CS7)
2159                 ctrl = old_ctrl & ~UARTCTRL_M;
2160
2161         if (termios->c_cflag & CMSPAR) {
2162                 if ((termios->c_cflag & CSIZE) != CS8) {
2163                         termios->c_cflag &= ~CSIZE;
2164                         termios->c_cflag |= CS8;
2165                 }
2166                 ctrl |= UARTCTRL_M;
2167         }
2168
2169         /*
2170          * When auto RS-485 RTS mode is enabled,
2171          * hardware flow control need to be disabled.
2172          */
2173         if (sport->port.rs485.flags & SER_RS485_ENABLED)
2174                 termios->c_cflag &= ~CRTSCTS;
2175
2176         if (termios->c_cflag & CRTSCTS)
2177                 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
2178         else
2179                 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2180
2181         if (termios->c_cflag & CSTOPB)
2182                 bd |= UARTBAUD_SBNS;
2183         else
2184                 bd &= ~UARTBAUD_SBNS;
2185
2186         /* parity must be enabled when CS7 to match 8-bits format */
2187         if ((termios->c_cflag & CSIZE) == CS7)
2188                 termios->c_cflag |= PARENB;
2189
2190         if ((termios->c_cflag & PARENB)) {
2191                 if (termios->c_cflag & CMSPAR) {
2192                         ctrl &= ~UARTCTRL_PE;
2193                         ctrl |= UARTCTRL_M;
2194                 } else {
2195                         ctrl |= UARTCTRL_PE;
2196                         if ((termios->c_cflag & CSIZE) == CS8)
2197                                 ctrl |= UARTCTRL_M;
2198                         if (termios->c_cflag & PARODD)
2199                                 ctrl |= UARTCTRL_PT;
2200                         else
2201                                 ctrl &= ~UARTCTRL_PT;
2202                 }
2203         } else {
2204                 ctrl &= ~UARTCTRL_PE;
2205         }
2206
2207         /* ask the core to calculate the divisor */
2208         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2209
2210         /*
2211          * Need to update the Ring buffer length according to the selected
2212          * baud rate and restart Rx DMA path.
2213          *
2214          * Since timer function acqures sport->port.lock, need to stop before
2215          * acquring same lock because otherwise del_timer_sync() can deadlock.
2216          */
2217         if (old && sport->lpuart_dma_rx_use)
2218                 lpuart_dma_rx_free(&sport->port);
2219
2220         spin_lock_irqsave(&sport->port.lock, flags);
2221
2222         sport->port.read_status_mask = 0;
2223         if (termios->c_iflag & INPCK)
2224                 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2225         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2226                 sport->port.read_status_mask |= UARTSTAT_FE;
2227
2228         /* characters to ignore */
2229         sport->port.ignore_status_mask = 0;
2230         if (termios->c_iflag & IGNPAR)
2231                 sport->port.ignore_status_mask |= UARTSTAT_PE;
2232         if (termios->c_iflag & IGNBRK) {
2233                 sport->port.ignore_status_mask |= UARTSTAT_FE;
2234                 /*
2235                  * if we're ignoring parity and break indicators,
2236                  * ignore overruns too (for real raw support).
2237                  */
2238                 if (termios->c_iflag & IGNPAR)
2239                         sport->port.ignore_status_mask |= UARTSTAT_OR;
2240         }
2241
2242         /* update the per-port timeout */
2243         uart_update_timeout(port, termios->c_cflag, baud);
2244
2245         /*
2246          * LPUART Transmission Complete Flag may never be set while queuing a break
2247          * character, so skip waiting for transmission complete when UARTCTRL_SBK is
2248          * asserted.
2249          */
2250         if (!(old_ctrl & UARTCTRL_SBK)) {
2251                 lpuart32_write(&sport->port, 0, UARTMODIR);
2252                 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2253         }
2254
2255         /* disable transmit and receive */
2256         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2257                        UARTCTRL);
2258
2259         lpuart32_write(&sport->port, bd, UARTBAUD);
2260         lpuart32_serial_setbrg(sport, baud);
2261         lpuart32_write(&sport->port, modem, UARTMODIR);
2262         lpuart32_write(&sport->port, ctrl, UARTCTRL);
2263         /* restore control register */
2264
2265         if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
2266                 sport->is_cs7 = true;
2267
2268         if (old && sport->lpuart_dma_rx_use) {
2269                 if (!lpuart_start_rx_dma(sport))
2270                         rx_dma_timer_init(sport);
2271                 else
2272                         sport->lpuart_dma_rx_use = false;
2273         }
2274
2275         spin_unlock_irqrestore(&sport->port.lock, flags);
2276 }
2277
2278 static const char *lpuart_type(struct uart_port *port)
2279 {
2280         return "FSL_LPUART";
2281 }
2282
2283 static void lpuart_release_port(struct uart_port *port)
2284 {
2285         /* nothing to do */
2286 }
2287
2288 static int lpuart_request_port(struct uart_port *port)
2289 {
2290         return  0;
2291 }
2292
2293 /* configure/autoconfigure the port */
2294 static void lpuart_config_port(struct uart_port *port, int flags)
2295 {
2296         if (flags & UART_CONFIG_TYPE)
2297                 port->type = PORT_LPUART;
2298 }
2299
2300 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2301 {
2302         int ret = 0;
2303
2304         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2305                 ret = -EINVAL;
2306         if (port->irq != ser->irq)
2307                 ret = -EINVAL;
2308         if (ser->io_type != UPIO_MEM)
2309                 ret = -EINVAL;
2310         if (port->uartclk / 16 != ser->baud_base)
2311                 ret = -EINVAL;
2312         if (port->iobase != ser->port)
2313                 ret = -EINVAL;
2314         if (ser->hub6 != 0)
2315                 ret = -EINVAL;
2316         return ret;
2317 }
2318
2319 static const struct uart_ops lpuart_pops = {
2320         .tx_empty       = lpuart_tx_empty,
2321         .set_mctrl      = lpuart_set_mctrl,
2322         .get_mctrl      = lpuart_get_mctrl,
2323         .stop_tx        = lpuart_stop_tx,
2324         .start_tx       = lpuart_start_tx,
2325         .stop_rx        = lpuart_stop_rx,
2326         .break_ctl      = lpuart_break_ctl,
2327         .startup        = lpuart_startup,
2328         .shutdown       = lpuart_shutdown,
2329         .set_termios    = lpuart_set_termios,
2330         .pm             = lpuart_uart_pm,
2331         .type           = lpuart_type,
2332         .request_port   = lpuart_request_port,
2333         .release_port   = lpuart_release_port,
2334         .config_port    = lpuart_config_port,
2335         .verify_port    = lpuart_verify_port,
2336         .flush_buffer   = lpuart_flush_buffer,
2337 #if defined(CONFIG_CONSOLE_POLL)
2338         .poll_init      = lpuart_poll_init,
2339         .poll_get_char  = lpuart_poll_get_char,
2340         .poll_put_char  = lpuart_poll_put_char,
2341 #endif
2342 };
2343
2344 static const struct uart_ops lpuart32_pops = {
2345         .tx_empty       = lpuart32_tx_empty,
2346         .set_mctrl      = lpuart32_set_mctrl,
2347         .get_mctrl      = lpuart32_get_mctrl,
2348         .stop_tx        = lpuart32_stop_tx,
2349         .start_tx       = lpuart32_start_tx,
2350         .stop_rx        = lpuart32_stop_rx,
2351         .break_ctl      = lpuart32_break_ctl,
2352         .startup        = lpuart32_startup,
2353         .shutdown       = lpuart32_shutdown,
2354         .set_termios    = lpuart32_set_termios,
2355         .pm             = lpuart_uart_pm,
2356         .type           = lpuart_type,
2357         .request_port   = lpuart_request_port,
2358         .release_port   = lpuart_release_port,
2359         .config_port    = lpuart_config_port,
2360         .verify_port    = lpuart_verify_port,
2361         .flush_buffer   = lpuart_flush_buffer,
2362 #if defined(CONFIG_CONSOLE_POLL)
2363         .poll_init      = lpuart32_poll_init,
2364         .poll_get_char  = lpuart32_poll_get_char,
2365         .poll_put_char  = lpuart32_poll_put_char,
2366 #endif
2367 };
2368
2369 static struct lpuart_port *lpuart_ports[UART_NR];
2370
2371 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2372 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
2373 {
2374         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2375         writeb(ch, port->membase + UARTDR);
2376 }
2377
2378 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
2379 {
2380         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2381         lpuart32_write(port, ch, UARTDATA);
2382 }
2383
2384 static void
2385 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2386 {
2387         struct lpuart_port *sport = lpuart_ports[co->index];
2388         unsigned char  old_cr2, cr2;
2389         unsigned long flags;
2390         int locked = 1;
2391
2392         if (oops_in_progress)
2393                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2394         else
2395                 spin_lock_irqsave(&sport->port.lock, flags);
2396
2397         /* first save CR2 and then disable interrupts */
2398         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2399         cr2 |= UARTCR2_TE | UARTCR2_RE;
2400         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2401         writeb(cr2, sport->port.membase + UARTCR2);
2402
2403         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2404
2405         /* wait for transmitter finish complete and restore CR2 */
2406         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2407
2408         writeb(old_cr2, sport->port.membase + UARTCR2);
2409
2410         if (locked)
2411                 spin_unlock_irqrestore(&sport->port.lock, flags);
2412 }
2413
2414 static void
2415 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2416 {
2417         struct lpuart_port *sport = lpuart_ports[co->index];
2418         unsigned long  old_cr, cr;
2419         unsigned long flags;
2420         int locked = 1;
2421
2422         if (oops_in_progress)
2423                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2424         else
2425                 spin_lock_irqsave(&sport->port.lock, flags);
2426
2427         /* first save CR2 and then disable interrupts */
2428         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2429         cr |= UARTCTRL_TE | UARTCTRL_RE;
2430         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2431         lpuart32_write(&sport->port, cr, UARTCTRL);
2432
2433         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2434
2435         /* wait for transmitter finish complete and restore CR2 */
2436         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2437
2438         lpuart32_write(&sport->port, old_cr, UARTCTRL);
2439
2440         if (locked)
2441                 spin_unlock_irqrestore(&sport->port.lock, flags);
2442 }
2443
2444 /*
2445  * if the port was already initialised (eg, by a boot loader),
2446  * try to determine the current setup.
2447  */
2448 static void __init
2449 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2450                            int *parity, int *bits)
2451 {
2452         unsigned char cr, bdh, bdl, brfa;
2453         unsigned int sbr, uartclk, baud_raw;
2454
2455         cr = readb(sport->port.membase + UARTCR2);
2456         cr &= UARTCR2_TE | UARTCR2_RE;
2457         if (!cr)
2458                 return;
2459
2460         /* ok, the port was enabled */
2461
2462         cr = readb(sport->port.membase + UARTCR1);
2463
2464         *parity = 'n';
2465         if (cr & UARTCR1_PE) {
2466                 if (cr & UARTCR1_PT)
2467                         *parity = 'o';
2468                 else
2469                         *parity = 'e';
2470         }
2471
2472         if (cr & UARTCR1_M)
2473                 *bits = 9;
2474         else
2475                 *bits = 8;
2476
2477         bdh = readb(sport->port.membase + UARTBDH);
2478         bdh &= UARTBDH_SBR_MASK;
2479         bdl = readb(sport->port.membase + UARTBDL);
2480         sbr = bdh;
2481         sbr <<= 8;
2482         sbr |= bdl;
2483         brfa = readb(sport->port.membase + UARTCR4);
2484         brfa &= UARTCR4_BRFA_MASK;
2485
2486         uartclk = lpuart_get_baud_clk_rate(sport);
2487         /*
2488          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2489          */
2490         baud_raw = uartclk / (16 * (sbr + brfa / 32));
2491
2492         if (*baud != baud_raw)
2493                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2494                                 "from %d to %d\n", baud_raw, *baud);
2495 }
2496
2497 static void __init
2498 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2499                            int *parity, int *bits)
2500 {
2501         unsigned long cr, bd;
2502         unsigned int sbr, uartclk, baud_raw;
2503
2504         cr = lpuart32_read(&sport->port, UARTCTRL);
2505         cr &= UARTCTRL_TE | UARTCTRL_RE;
2506         if (!cr)
2507                 return;
2508
2509         /* ok, the port was enabled */
2510
2511         cr = lpuart32_read(&sport->port, UARTCTRL);
2512
2513         *parity = 'n';
2514         if (cr & UARTCTRL_PE) {
2515                 if (cr & UARTCTRL_PT)
2516                         *parity = 'o';
2517                 else
2518                         *parity = 'e';
2519         }
2520
2521         if (cr & UARTCTRL_M)
2522                 *bits = 9;
2523         else
2524                 *bits = 8;
2525
2526         bd = lpuart32_read(&sport->port, UARTBAUD);
2527         bd &= UARTBAUD_SBR_MASK;
2528         if (!bd)
2529                 return;
2530
2531         sbr = bd;
2532         uartclk = lpuart_get_baud_clk_rate(sport);
2533         /*
2534          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2535          */
2536         baud_raw = uartclk / (16 * sbr);
2537
2538         if (*baud != baud_raw)
2539                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2540                                 "from %d to %d\n", baud_raw, *baud);
2541 }
2542
2543 static int __init lpuart_console_setup(struct console *co, char *options)
2544 {
2545         struct lpuart_port *sport;
2546         int baud = 115200;
2547         int bits = 8;
2548         int parity = 'n';
2549         int flow = 'n';
2550
2551         /*
2552          * check whether an invalid uart number has been specified, and
2553          * if so, search for the first available port that does have
2554          * console support.
2555          */
2556         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2557                 co->index = 0;
2558
2559         sport = lpuart_ports[co->index];
2560         if (sport == NULL)
2561                 return -ENODEV;
2562
2563         if (options)
2564                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2565         else
2566                 if (lpuart_is_32(sport))
2567                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2568                 else
2569                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2570
2571         if (lpuart_is_32(sport))
2572                 lpuart32_setup_watermark(sport);
2573         else
2574                 lpuart_setup_watermark(sport);
2575
2576         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2577 }
2578
2579 static struct uart_driver lpuart_reg;
2580 static struct console lpuart_console = {
2581         .name           = DEV_NAME,
2582         .write          = lpuart_console_write,
2583         .device         = uart_console_device,
2584         .setup          = lpuart_console_setup,
2585         .flags          = CON_PRINTBUFFER,
2586         .index          = -1,
2587         .data           = &lpuart_reg,
2588 };
2589
2590 static struct console lpuart32_console = {
2591         .name           = DEV_NAME,
2592         .write          = lpuart32_console_write,
2593         .device         = uart_console_device,
2594         .setup          = lpuart_console_setup,
2595         .flags          = CON_PRINTBUFFER,
2596         .index          = -1,
2597         .data           = &lpuart_reg,
2598 };
2599
2600 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2601 {
2602         struct earlycon_device *dev = con->data;
2603
2604         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2605 }
2606
2607 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2608 {
2609         struct earlycon_device *dev = con->data;
2610
2611         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2612 }
2613
2614 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2615                                           const char *opt)
2616 {
2617         if (!device->port.membase)
2618                 return -ENODEV;
2619
2620         device->con->write = lpuart_early_write;
2621         return 0;
2622 }
2623
2624 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2625                                           const char *opt)
2626 {
2627         if (!device->port.membase)
2628                 return -ENODEV;
2629
2630         if (device->port.iotype != UPIO_MEM32)
2631                 device->port.iotype = UPIO_MEM32BE;
2632
2633         device->con->write = lpuart32_early_write;
2634         return 0;
2635 }
2636
2637 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2638                                               const char *opt)
2639 {
2640         u32 cr;
2641
2642         if (!device->port.membase)
2643                 return -ENODEV;
2644
2645         device->port.iotype = UPIO_MEM32;
2646         device->con->write = lpuart32_early_write;
2647
2648         /* set the baudrate */
2649         if (device->port.uartclk && device->baud)
2650                 __lpuart32_serial_setbrg(&device->port, device->baud,
2651                                          false, false);
2652
2653         /* enable transmitter */
2654         cr = lpuart32_read(&device->port, UARTCTRL);
2655         cr |= UARTCTRL_TE;
2656         lpuart32_write(&device->port, cr, UARTCTRL);
2657
2658         return 0;
2659 }
2660
2661 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2662                                                    const char *opt)
2663 {
2664         if (!device->port.membase)
2665                 return -ENODEV;
2666
2667         device->port.iotype = UPIO_MEM32;
2668         device->port.membase += IMX_REG_OFF;
2669         device->con->write = lpuart32_early_write;
2670
2671         return 0;
2672 }
2673 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2674 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2675 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2676 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2677 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2678 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2679 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2680 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2681
2682 #define LPUART_CONSOLE  (&lpuart_console)
2683 #define LPUART32_CONSOLE        (&lpuart32_console)
2684 #else
2685 #define LPUART_CONSOLE  NULL
2686 #define LPUART32_CONSOLE        NULL
2687 #endif
2688
2689 static struct uart_driver lpuart_reg = {
2690         .owner          = THIS_MODULE,
2691         .driver_name    = DRIVER_NAME,
2692         .dev_name       = DEV_NAME,
2693         .nr             = ARRAY_SIZE(lpuart_ports),
2694         .cons           = LPUART_CONSOLE,
2695 };
2696
2697 static const struct serial_rs485 lpuart_rs485_supported = {
2698         .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
2699         /* delay_rts_* and RX_DURING_TX are not supported */
2700 };
2701
2702 static int lpuart_global_reset(struct lpuart_port *sport)
2703 {
2704         struct uart_port *port = &sport->port;
2705         void __iomem *global_addr;
2706         unsigned long ctrl, bd;
2707         unsigned int val = 0;
2708         int ret;
2709
2710         ret = clk_prepare_enable(sport->ipg_clk);
2711         if (ret) {
2712                 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
2713                 return ret;
2714         }
2715
2716         if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
2717                 /*
2718                  * If the transmitter is used by earlycon, wait for transmit engine to
2719                  * complete and then reset.
2720                  */
2721                 ctrl = lpuart32_read(port, UARTCTRL);
2722                 if (ctrl & UARTCTRL_TE) {
2723                         bd = lpuart32_read(&sport->port, UARTBAUD);
2724                         if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,
2725                                               port)) {
2726                                 dev_warn(sport->port.dev,
2727                                          "timeout waiting for transmit engine to complete\n");
2728                                 clk_disable_unprepare(sport->ipg_clk);
2729                                 return 0;
2730                         }
2731                 }
2732
2733                 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
2734                 writel(UART_GLOBAL_RST, global_addr);
2735                 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2736                 writel(0, global_addr);
2737                 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2738
2739                 /* Recover the transmitter for earlycon. */
2740                 if (ctrl & UARTCTRL_TE) {
2741                         lpuart32_write(port, bd, UARTBAUD);
2742                         lpuart32_write(port, ctrl, UARTCTRL);
2743                 }
2744         }
2745
2746         clk_disable_unprepare(sport->ipg_clk);
2747         return 0;
2748 }
2749
2750 static int lpuart_probe(struct platform_device *pdev)
2751 {
2752         const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2753         struct device_node *np = pdev->dev.of_node;
2754         struct lpuart_port *sport;
2755         struct resource *res;
2756         irq_handler_t handler;
2757         int ret;
2758
2759         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2760         if (!sport)
2761                 return -ENOMEM;
2762
2763         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2764         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2765         if (IS_ERR(sport->port.membase))
2766                 return PTR_ERR(sport->port.membase);
2767
2768         sport->port.membase += sdata->reg_off;
2769         sport->port.mapbase = res->start + sdata->reg_off;
2770         sport->port.dev = &pdev->dev;
2771         sport->port.type = PORT_LPUART;
2772         sport->devtype = sdata->devtype;
2773         sport->rx_watermark = sdata->rx_watermark;
2774         ret = platform_get_irq(pdev, 0);
2775         if (ret < 0)
2776                 return ret;
2777         sport->port.irq = ret;
2778         sport->port.iotype = sdata->iotype;
2779         if (lpuart_is_32(sport))
2780                 sport->port.ops = &lpuart32_pops;
2781         else
2782                 sport->port.ops = &lpuart_pops;
2783         sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2784         sport->port.flags = UPF_BOOT_AUTOCONF;
2785
2786         if (lpuart_is_32(sport))
2787                 sport->port.rs485_config = lpuart32_config_rs485;
2788         else
2789                 sport->port.rs485_config = lpuart_config_rs485;
2790         sport->port.rs485_supported = lpuart_rs485_supported;
2791
2792         sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2793         if (IS_ERR(sport->ipg_clk)) {
2794                 ret = PTR_ERR(sport->ipg_clk);
2795                 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2796                 return ret;
2797         }
2798
2799         sport->baud_clk = NULL;
2800         if (is_imx8qxp_lpuart(sport)) {
2801                 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2802                 if (IS_ERR(sport->baud_clk)) {
2803                         ret = PTR_ERR(sport->baud_clk);
2804                         dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2805                         return ret;
2806                 }
2807         }
2808
2809         ret = of_alias_get_id(np, "serial");
2810         if (ret < 0) {
2811                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2812                 return ret;
2813         }
2814         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2815                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2816                 return -EINVAL;
2817         }
2818         sport->port.line = ret;
2819
2820         ret = lpuart_enable_clks(sport);
2821         if (ret)
2822                 return ret;
2823         sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2824
2825         lpuart_ports[sport->port.line] = sport;
2826
2827         platform_set_drvdata(pdev, &sport->port);
2828
2829         if (lpuart_is_32(sport)) {
2830                 lpuart_reg.cons = LPUART32_CONSOLE;
2831                 handler = lpuart32_int;
2832         } else {
2833                 lpuart_reg.cons = LPUART_CONSOLE;
2834                 handler = lpuart_int;
2835         }
2836
2837         pm_runtime_use_autosuspend(&pdev->dev);
2838         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
2839         pm_runtime_set_active(&pdev->dev);
2840         pm_runtime_enable(&pdev->dev);
2841
2842         ret = lpuart_global_reset(sport);
2843         if (ret)
2844                 goto failed_reset;
2845
2846         ret = uart_get_rs485_mode(&sport->port);
2847         if (ret)
2848                 goto failed_get_rs485;
2849
2850         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2851         if (ret)
2852                 goto failed_attach_port;
2853
2854         ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2855                                 DRIVER_NAME, sport);
2856         if (ret)
2857                 goto failed_irq_request;
2858
2859         return 0;
2860
2861 failed_irq_request:
2862         uart_remove_one_port(&lpuart_reg, &sport->port);
2863 failed_attach_port:
2864 failed_get_rs485:
2865 failed_reset:
2866         pm_runtime_disable(&pdev->dev);
2867         pm_runtime_set_suspended(&pdev->dev);
2868         pm_runtime_dont_use_autosuspend(&pdev->dev);
2869         lpuart_disable_clks(sport);
2870         return ret;
2871 }
2872
2873 static int lpuart_remove(struct platform_device *pdev)
2874 {
2875         struct lpuart_port *sport = platform_get_drvdata(pdev);
2876
2877         uart_remove_one_port(&lpuart_reg, &sport->port);
2878
2879         lpuart_disable_clks(sport);
2880
2881         if (sport->dma_tx_chan)
2882                 dma_release_channel(sport->dma_tx_chan);
2883
2884         if (sport->dma_rx_chan)
2885                 dma_release_channel(sport->dma_rx_chan);
2886
2887         pm_runtime_disable(&pdev->dev);
2888         pm_runtime_set_suspended(&pdev->dev);
2889         pm_runtime_dont_use_autosuspend(&pdev->dev);
2890         return 0;
2891 }
2892
2893 static int lpuart_runtime_suspend(struct device *dev)
2894 {
2895         struct platform_device *pdev = to_platform_device(dev);
2896         struct lpuart_port *sport = platform_get_drvdata(pdev);
2897
2898         lpuart_disable_clks(sport);
2899
2900         return 0;
2901 };
2902
2903 static int lpuart_runtime_resume(struct device *dev)
2904 {
2905         struct platform_device *pdev = to_platform_device(dev);
2906         struct lpuart_port *sport = platform_get_drvdata(pdev);
2907
2908         return lpuart_enable_clks(sport);
2909 };
2910
2911 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
2912 {
2913         unsigned int val, baud;
2914
2915         if (lpuart_is_32(sport)) {
2916                 val = lpuart32_read(&sport->port, UARTCTRL);
2917                 baud = lpuart32_read(&sport->port, UARTBAUD);
2918                 if (on) {
2919                         /* set rx_watermark to 0 in wakeup source mode */
2920                         lpuart32_write(&sport->port, 0, UARTWATER);
2921                         val |= UARTCTRL_RIE;
2922                         /* clear RXEDGIF flag before enable RXEDGIE interrupt */
2923                         lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
2924                         baud |= UARTBAUD_RXEDGIE;
2925                 } else {
2926                         val &= ~UARTCTRL_RIE;
2927                         baud &= ~UARTBAUD_RXEDGIE;
2928                 }
2929                 lpuart32_write(&sport->port, val, UARTCTRL);
2930                 lpuart32_write(&sport->port, baud, UARTBAUD);
2931         } else {
2932                 val = readb(sport->port.membase + UARTCR2);
2933                 if (on)
2934                         val |= UARTCR2_RIE;
2935                 else
2936                         val &= ~UARTCR2_RIE;
2937                 writeb(val, sport->port.membase + UARTCR2);
2938         }
2939 }
2940
2941 static bool lpuart_uport_is_active(struct lpuart_port *sport)
2942 {
2943         struct tty_port *port = &sport->port.state->port;
2944         struct tty_struct *tty;
2945         struct device *tty_dev;
2946         int may_wake = 0;
2947
2948         tty = tty_port_tty_get(port);
2949         if (tty) {
2950                 tty_dev = tty->dev;
2951                 may_wake = tty_dev && device_may_wakeup(tty_dev);
2952                 tty_kref_put(tty);
2953         }
2954
2955         if ((tty_port_initialized(port) && may_wake) ||
2956             (!console_suspend_enabled && uart_console(&sport->port)))
2957                 return true;
2958
2959         return false;
2960 }
2961
2962 static int lpuart_suspend_noirq(struct device *dev)
2963 {
2964         struct lpuart_port *sport = dev_get_drvdata(dev);
2965         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2966
2967         if (lpuart_uport_is_active(sport))
2968                 serial_lpuart_enable_wakeup(sport, !!irq_wake);
2969
2970         pinctrl_pm_select_sleep_state(dev);
2971
2972         return 0;
2973 }
2974
2975 static int lpuart_resume_noirq(struct device *dev)
2976 {
2977         struct lpuart_port *sport = dev_get_drvdata(dev);
2978         unsigned int val;
2979
2980         pinctrl_pm_select_default_state(dev);
2981
2982         if (lpuart_uport_is_active(sport)) {
2983                 serial_lpuart_enable_wakeup(sport, false);
2984
2985                 /* clear the wakeup flags */
2986                 if (lpuart_is_32(sport)) {
2987                         val = lpuart32_read(&sport->port, UARTSTAT);
2988                         lpuart32_write(&sport->port, val, UARTSTAT);
2989                 }
2990         }
2991
2992         return 0;
2993 }
2994
2995 static int lpuart_suspend(struct device *dev)
2996 {
2997         struct lpuart_port *sport = dev_get_drvdata(dev);
2998         unsigned long temp, flags;
2999
3000         uart_suspend_port(&lpuart_reg, &sport->port);
3001
3002         if (lpuart_uport_is_active(sport)) {
3003                 spin_lock_irqsave(&sport->port.lock, flags);
3004                 if (lpuart_is_32(sport)) {
3005                         /* disable Rx/Tx and interrupts */
3006                         temp = lpuart32_read(&sport->port, UARTCTRL);
3007                         temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
3008                         lpuart32_write(&sport->port, temp, UARTCTRL);
3009                 } else {
3010                         /* disable Rx/Tx and interrupts */
3011                         temp = readb(sport->port.membase + UARTCR2);
3012                         temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
3013                         writeb(temp, sport->port.membase + UARTCR2);
3014                 }
3015                 spin_unlock_irqrestore(&sport->port.lock, flags);
3016
3017                 if (sport->lpuart_dma_rx_use) {
3018                         /*
3019                          * EDMA driver during suspend will forcefully release any
3020                          * non-idle DMA channels. If port wakeup is enabled or if port
3021                          * is console port or 'no_console_suspend' is set the Rx DMA
3022                          * cannot resume as expected, hence gracefully release the
3023                          * Rx DMA path before suspend and start Rx DMA path on resume.
3024                          */
3025                         lpuart_dma_rx_free(&sport->port);
3026
3027                         /* Disable Rx DMA to use UART port as wakeup source */
3028                         spin_lock_irqsave(&sport->port.lock, flags);
3029                         if (lpuart_is_32(sport)) {
3030                                 temp = lpuart32_read(&sport->port, UARTBAUD);
3031                                 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
3032                                                UARTBAUD);
3033                         } else {
3034                                 writeb(readb(sport->port.membase + UARTCR5) &
3035                                        ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
3036                         }
3037                         spin_unlock_irqrestore(&sport->port.lock, flags);
3038                 }
3039
3040                 if (sport->lpuart_dma_tx_use) {
3041                         spin_lock_irqsave(&sport->port.lock, flags);
3042                         if (lpuart_is_32(sport)) {
3043                                 temp = lpuart32_read(&sport->port, UARTBAUD);
3044                                 temp &= ~UARTBAUD_TDMAE;
3045                                 lpuart32_write(&sport->port, temp, UARTBAUD);
3046                         } else {
3047                                 temp = readb(sport->port.membase + UARTCR5);
3048                                 temp &= ~UARTCR5_TDMAS;
3049                                 writeb(temp, sport->port.membase + UARTCR5);
3050                         }
3051                         spin_unlock_irqrestore(&sport->port.lock, flags);
3052                         sport->dma_tx_in_progress = false;
3053                         dmaengine_terminate_sync(sport->dma_tx_chan);
3054                 }
3055         } else if (pm_runtime_active(sport->port.dev)) {
3056                 lpuart_disable_clks(sport);
3057                 pm_runtime_disable(sport->port.dev);
3058                 pm_runtime_set_suspended(sport->port.dev);
3059         }
3060
3061         return 0;
3062 }
3063
3064 static void lpuart_console_fixup(struct lpuart_port *sport)
3065 {
3066         struct tty_port *port = &sport->port.state->port;
3067         struct uart_port *uport = &sport->port;
3068         struct ktermios termios;
3069
3070         /* i.MX7ULP enter VLLS mode that lpuart module power off and registers
3071          * all lost no matter the port is wakeup source.
3072          * For console port, console baud rate setting lost and print messy
3073          * log when enable the console port as wakeup source. To avoid the
3074          * issue happen, user should not enable uart port as wakeup source
3075          * in VLLS mode, or restore console setting here.
3076          */
3077         if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
3078             console_suspend_enabled && uart_console(&sport->port)) {
3079
3080                 mutex_lock(&port->mutex);
3081                 memset(&termios, 0, sizeof(struct ktermios));
3082                 termios.c_cflag = uport->cons->cflag;
3083                 if (port->tty && termios.c_cflag == 0)
3084                         termios = port->tty->termios;
3085                 uport->ops->set_termios(uport, &termios, NULL);
3086                 mutex_unlock(&port->mutex);
3087         }
3088 }
3089
3090 static int lpuart_resume(struct device *dev)
3091 {
3092         struct lpuart_port *sport = dev_get_drvdata(dev);
3093         int ret;
3094
3095         if (lpuart_uport_is_active(sport)) {
3096                 if (lpuart_is_32(sport))
3097                         lpuart32_hw_setup(sport);
3098                 else
3099                         lpuart_hw_setup(sport);
3100         } else if (pm_runtime_active(sport->port.dev)) {
3101                 ret = lpuart_enable_clks(sport);
3102                 if (ret)
3103                         return ret;
3104                 pm_runtime_set_active(sport->port.dev);
3105                 pm_runtime_enable(sport->port.dev);
3106         }
3107
3108         lpuart_console_fixup(sport);
3109         uart_resume_port(&lpuart_reg, &sport->port);
3110
3111         return 0;
3112 }
3113
3114 static const struct dev_pm_ops lpuart_pm_ops = {
3115         RUNTIME_PM_OPS(lpuart_runtime_suspend,
3116                            lpuart_runtime_resume, NULL)
3117         NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,
3118                                       lpuart_resume_noirq)
3119         SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)
3120 };
3121
3122 static struct platform_driver lpuart_driver = {
3123         .probe          = lpuart_probe,
3124         .remove         = lpuart_remove,
3125         .driver         = {
3126                 .name   = "fsl-lpuart",
3127                 .of_match_table = lpuart_dt_ids,
3128                 .pm     = pm_ptr(&lpuart_pm_ops),
3129         },
3130 };
3131
3132 static int __init lpuart_serial_init(void)
3133 {
3134         int ret = uart_register_driver(&lpuart_reg);
3135
3136         if (ret)
3137                 return ret;
3138
3139         ret = platform_driver_register(&lpuart_driver);
3140         if (ret)
3141                 uart_unregister_driver(&lpuart_reg);
3142
3143         return ret;
3144 }
3145
3146 static void __exit lpuart_serial_exit(void)
3147 {
3148         platform_driver_unregister(&lpuart_driver);
3149         uart_unregister_driver(&lpuart_reg);
3150 }
3151
3152 module_init(lpuart_serial_init);
3153 module_exit(lpuart_serial_exit);
3154
3155 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
3156 MODULE_LICENSE("GPL v2");