1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
6 * Purpose: Implement functions to access baseband
13 * bb_get_frame_time - Calculate data frame transmitting time
14 * bb_read_embedded - Embedded read baseband register via MAC
15 * bb_write_embedded - Embedded write baseband register via MAC
16 * bb_vt3253_init - VIA VT3253 baseband chip init code
19 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
20 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
21 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and
22 * BBvCalculateParameter().
23 * cancel the setting of MAC_REG_SOFTPWRCTL on
26 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
27 * Modified BBvLoopbackOn & BBvLoopbackOff().
37 /*--------------------- Static Classes ----------------------------*/
39 /*--------------------- Static Variables --------------------------*/
41 /*--------------------- Static Functions --------------------------*/
43 /*--------------------- Export Variables --------------------------*/
45 /*--------------------- Static Definitions -------------------------*/
47 /*--------------------- Static Classes ----------------------------*/
49 /*--------------------- Static Variables --------------------------*/
51 #define CB_VT3253_INIT_FOR_RFMD 446
52 static const unsigned char by_vt3253_init_tab_rfmd[CB_VT3253_INIT_FOR_RFMD][2] = {
501 #define CB_VT3253B0_INIT_FOR_RFMD 256
502 static const unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
761 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
764 unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
962 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
965 unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1074 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1224 #define CB_VT3253B0_INIT_FOR_UW2451 256
1226 static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1335 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1485 #define CB_VT3253B0_AGC 193
1487 static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1683 static const unsigned short awc_frame_time[MAX_RATE] = {
1684 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216
1687 /*--------------------- Export Variables --------------------------*/
1689 * Description: Calculate data frame transmitting time
1693 * preamble_type - Preamble Type
1694 * by_pkt_type - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1695 * cb_frame_length - Baseband Type
1699 * Return Value: FrameTime
1702 unsigned int bb_get_frame_time(unsigned char preamble_type,
1703 unsigned char by_pkt_type,
1704 unsigned int cb_frame_length,
1705 unsigned short tx_rate)
1707 unsigned int frame_time;
1708 unsigned int preamble;
1710 unsigned int rate_idx = (unsigned int)tx_rate;
1711 unsigned int rate = 0;
1713 if (rate_idx > RATE_54M)
1716 rate = (unsigned int)awc_frame_time[rate_idx];
1718 if (rate_idx <= 3) { /* CCK mode */
1719 if (preamble_type == PREAMBLE_SHORT)
1723 frame_time = (cb_frame_length * 80) / rate; /* ????? */
1724 tmp = (frame_time * rate) / 80;
1725 if (cb_frame_length != tmp)
1728 return preamble + frame_time;
1730 frame_time = (cb_frame_length * 8 + 22) / rate; /* ???????? */
1731 tmp = ((frame_time * rate) - 22) / 8;
1732 if (cb_frame_length != tmp)
1735 frame_time = frame_time * 4; /* ??????? */
1736 if (by_pkt_type != PK_TYPE_11A)
1737 frame_time += 6; /* ?????? */
1739 return 20 + frame_time; /* ?????? */
1743 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1747 * priv - Device Structure
1748 * frame_length - Tx Frame Length
1751 * struct vnt_phy_field *phy
1752 * - pointer to Phy Length field
1753 * - pointer to Phy Service field
1754 * - pointer to Phy Signal field
1756 * Return Value: none
1759 void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length,
1760 u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy)
1766 u8 preamble_type = priv->preamble_type;
1768 bit_count = frame_length * 8;
1779 count = bit_count / 2;
1781 if (preamble_type == PREAMBLE_SHORT)
1788 count = (bit_count * 10) / 55;
1789 tmp = (count * 55) / 10;
1791 if (tmp != bit_count)
1794 if (preamble_type == PREAMBLE_SHORT)
1801 count = bit_count / 11;
1804 if (tmp != bit_count) {
1807 if ((bit_count - tmp) <= 3)
1811 if (preamble_type == PREAMBLE_SHORT)
1818 if (pkt_type == PK_TYPE_11A)
1825 if (pkt_type == PK_TYPE_11A)
1832 if (pkt_type == PK_TYPE_11A)
1839 if (pkt_type == PK_TYPE_11A)
1846 if (pkt_type == PK_TYPE_11A)
1853 if (pkt_type == PK_TYPE_11A)
1860 if (pkt_type == PK_TYPE_11A)
1867 if (pkt_type == PK_TYPE_11A)
1873 if (pkt_type == PK_TYPE_11A)
1880 if (pkt_type == PK_TYPE_11B) {
1881 phy->service = 0x00;
1883 phy->service |= 0x80;
1884 phy->len = cpu_to_le16((u16)count);
1886 phy->service = 0x00;
1887 phy->len = cpu_to_le16((u16)frame_length);
1892 * Description: Read a byte from BASEBAND, by embedded programming
1896 * iobase - I/O base address
1897 * by_bb_addr - address of register in Baseband
1899 * pby_data - data read
1901 * Return Value: true if succeeded; false if failed.
1904 bool bb_read_embedded(struct vnt_private *priv, unsigned char by_bb_addr,
1905 unsigned char *pby_data)
1907 void __iomem *iobase = priv->port_offset;
1909 unsigned char by_value;
1912 iowrite8(by_bb_addr, iobase + MAC_REG_BBREGADR);
1915 vt6655_mac_reg_bits_on(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
1916 /* W_MAX_TIMEOUT is the timeout period */
1917 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1918 by_value = ioread8(iobase + MAC_REG_BBREGCTL);
1919 if (by_value & BBREGCTL_DONE)
1924 *pby_data = ioread8(iobase + MAC_REG_BBREGDATA);
1926 if (ww == W_MAX_TIMEOUT) {
1927 pr_debug(" DBG_PORT80(0x30)\n");
1934 * Description: Write a Byte to BASEBAND, by embedded programming
1938 * iobase - I/O base address
1939 * by_bb_addr - address of register in Baseband
1940 * by_data - data to write
1944 * Return Value: true if succeeded; false if failed.
1947 bool bb_write_embedded(struct vnt_private *priv, unsigned char by_bb_addr,
1948 unsigned char by_data)
1950 void __iomem *iobase = priv->port_offset;
1952 unsigned char by_value;
1955 iowrite8(by_bb_addr, iobase + MAC_REG_BBREGADR);
1957 iowrite8(by_data, iobase + MAC_REG_BBREGDATA);
1959 /* turn on BBREGCTL_REGW */
1960 vt6655_mac_reg_bits_on(iobase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
1961 /* W_MAX_TIMEOUT is the timeout period */
1962 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1963 by_value = ioread8(iobase + MAC_REG_BBREGCTL);
1964 if (by_value & BBREGCTL_DONE)
1968 if (ww == W_MAX_TIMEOUT) {
1969 pr_debug(" DBG_PORT80(0x31)\n");
1976 * Description: VIA VT3253 Baseband chip init function
1980 * iobase - I/O base address
1981 * byRevId - Revision ID
1982 * byRFType - RF type
1986 * Return Value: true if succeeded; false if failed.
1990 bool bb_vt3253_init(struct vnt_private *priv)
1994 void __iomem *iobase = priv->port_offset;
1995 unsigned char by_rf_type = priv->byRFType;
1996 unsigned char by_local_id = priv->local_id;
1998 if (by_rf_type == RF_RFMD2959) {
1999 if (by_local_id <= REV_ID_VT3253_A1) {
2000 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
2001 result &= bb_write_embedded(priv,
2002 by_vt3253_init_tab_rfmd[ii][0],
2003 by_vt3253_init_tab_rfmd[ii][1]);
2006 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++)
2007 result &= bb_write_embedded(priv,
2008 byVT3253B0_RFMD[ii][0],
2009 byVT3253B0_RFMD[ii][1]);
2011 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
2012 result &= bb_write_embedded(priv,
2013 byVT3253B0_AGC4_RFMD2959[ii][0],
2014 byVT3253B0_AGC4_RFMD2959[ii][1]);
2016 iowrite32(0x23, iobase + MAC_REG_ITRTMSET);
2017 vt6655_mac_reg_bits_on(iobase, MAC_REG_PAPEDELAY, BIT(0));
2019 priv->abyBBVGA[0] = 0x18;
2020 priv->abyBBVGA[1] = 0x0A;
2021 priv->abyBBVGA[2] = 0x0;
2022 priv->abyBBVGA[3] = 0x0;
2023 priv->dbm_threshold[0] = -70;
2024 priv->dbm_threshold[1] = -50;
2025 priv->dbm_threshold[2] = 0;
2026 priv->dbm_threshold[3] = 0;
2027 } else if ((by_rf_type == RF_AIROHA) || (by_rf_type == RF_AL2230S)) {
2028 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2029 result &= bb_write_embedded(priv,
2030 byVT3253B0_AIROHA2230[ii][0],
2031 byVT3253B0_AIROHA2230[ii][1]);
2033 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2034 result &= bb_write_embedded(priv,
2035 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2037 priv->abyBBVGA[0] = 0x1C;
2038 priv->abyBBVGA[1] = 0x10;
2039 priv->abyBBVGA[2] = 0x0;
2040 priv->abyBBVGA[3] = 0x0;
2041 priv->dbm_threshold[0] = -70;
2042 priv->dbm_threshold[1] = -48;
2043 priv->dbm_threshold[2] = 0;
2044 priv->dbm_threshold[3] = 0;
2045 } else if (by_rf_type == RF_UW2451) {
2046 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2047 result &= bb_write_embedded(priv,
2048 byVT3253B0_UW2451[ii][0],
2049 byVT3253B0_UW2451[ii][1]);
2051 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2052 result &= bb_write_embedded(priv,
2053 byVT3253B0_AGC[ii][0],
2054 byVT3253B0_AGC[ii][1]);
2056 iowrite8(0x23, iobase + MAC_REG_ITRTMSET);
2057 vt6655_mac_reg_bits_on(iobase, MAC_REG_PAPEDELAY, BIT(0));
2059 priv->abyBBVGA[0] = 0x14;
2060 priv->abyBBVGA[1] = 0x0A;
2061 priv->abyBBVGA[2] = 0x0;
2062 priv->abyBBVGA[3] = 0x0;
2063 priv->dbm_threshold[0] = -60;
2064 priv->dbm_threshold[1] = -50;
2065 priv->dbm_threshold[2] = 0;
2066 priv->dbm_threshold[3] = 0;
2067 } else if (by_rf_type == RF_VT3226) {
2068 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2069 result &= bb_write_embedded(priv,
2070 byVT3253B0_AIROHA2230[ii][0],
2071 byVT3253B0_AIROHA2230[ii][1]);
2073 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2074 result &= bb_write_embedded(priv,
2075 byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2077 priv->abyBBVGA[0] = 0x1C;
2078 priv->abyBBVGA[1] = 0x10;
2079 priv->abyBBVGA[2] = 0x0;
2080 priv->abyBBVGA[3] = 0x0;
2081 priv->dbm_threshold[0] = -70;
2082 priv->dbm_threshold[1] = -48;
2083 priv->dbm_threshold[2] = 0;
2084 priv->dbm_threshold[3] = 0;
2085 /* Fix VT3226 DFC system timing issue */
2086 vt6655_mac_word_reg_bits_on(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT);
2087 /* {{ RobertYu: 20050104 */
2089 /* No VGA Table now */
2090 priv->bUpdateBBVGA = false;
2091 priv->abyBBVGA[0] = 0x1C;
2094 if (by_local_id > REV_ID_VT3253_A1) {
2095 bb_write_embedded(priv, 0x04, 0x7F);
2096 bb_write_embedded(priv, 0x0D, 0x01);
2103 * Description: Set ShortSlotTime mode
2107 * priv - Device Structure
2111 * Return Value: none
2115 bb_set_short_slot_time(struct vnt_private *priv)
2117 unsigned char by_bb_rx_conf = 0;
2118 unsigned char by_bb_vga = 0;
2120 bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */
2122 if (priv->short_slot_time)
2123 by_bb_rx_conf &= 0xDF; /* 1101 1111 */
2125 by_bb_rx_conf |= 0x20; /* 0010 0000 */
2127 /* patch for 3253B0 Baseband with Cardbus module */
2128 bb_read_embedded(priv, 0xE7, &by_bb_vga);
2129 if (by_bb_vga == priv->abyBBVGA[0])
2130 by_bb_rx_conf |= 0x20; /* 0010 0000 */
2132 bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */
2135 void bb_set_vga_gain_offset(struct vnt_private *priv, unsigned char by_data)
2137 unsigned char by_bb_rx_conf = 0;
2139 bb_write_embedded(priv, 0xE7, by_data);
2141 bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */
2142 /* patch for 3253B0 Baseband with Cardbus module */
2143 if (by_data == priv->abyBBVGA[0])
2144 by_bb_rx_conf |= 0x20; /* 0010 0000 */
2145 else if (priv->short_slot_time)
2146 by_bb_rx_conf &= 0xDF; /* 1101 1111 */
2148 by_bb_rx_conf |= 0x20; /* 0010 0000 */
2149 priv->byBBVGACurrent = by_data;
2150 bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */
2154 * Description: Baseband SoftwareReset
2158 * iobase - I/O base address
2162 * Return Value: none
2166 bb_software_reset(struct vnt_private *priv)
2168 bb_write_embedded(priv, 0x50, 0x40);
2169 bb_write_embedded(priv, 0x50, 0);
2170 bb_write_embedded(priv, 0x9C, 0x01);
2171 bb_write_embedded(priv, 0x9C, 0);
2175 * Description: Set Tx Antenna mode
2179 * priv - Device Structure
2180 * by_antenna_mode - Antenna Mode
2184 * Return Value: none
2189 bb_set_tx_antenna_mode(struct vnt_private *priv, unsigned char by_antenna_mode)
2191 unsigned char by_bb_tx_conf;
2193 bb_read_embedded(priv, 0x09, &by_bb_tx_conf); /* CR09 */
2194 if (by_antenna_mode == ANT_DIVERSITY) {
2195 /* bit 1 is diversity */
2196 by_bb_tx_conf |= 0x02;
2197 } else if (by_antenna_mode == ANT_A) {
2198 /* bit 2 is ANTSEL */
2199 by_bb_tx_conf &= 0xF9; /* 1111 1001 */
2200 } else if (by_antenna_mode == ANT_B) {
2201 by_bb_tx_conf &= 0xFD; /* 1111 1101 */
2202 by_bb_tx_conf |= 0x04;
2204 bb_write_embedded(priv, 0x09, by_bb_tx_conf); /* CR09 */
2208 * Description: Set Rx Antenna mode
2212 * priv - Device Structure
2213 * by_antenna_mode - Antenna Mode
2217 * Return Value: none
2222 bb_set_rx_antenna_mode(struct vnt_private *priv, unsigned char by_antenna_mode)
2224 unsigned char by_bb_rx_conf;
2226 bb_read_embedded(priv, 0x0A, &by_bb_rx_conf); /* CR10 */
2227 if (by_antenna_mode == ANT_DIVERSITY) {
2228 by_bb_rx_conf |= 0x01;
2230 } else if (by_antenna_mode == ANT_A) {
2231 by_bb_rx_conf &= 0xFC; /* 1111 1100 */
2232 } else if (by_antenna_mode == ANT_B) {
2233 by_bb_rx_conf &= 0xFE; /* 1111 1110 */
2234 by_bb_rx_conf |= 0x02;
2236 bb_write_embedded(priv, 0x0A, by_bb_rx_conf); /* CR10 */
2240 * Description: bb_set_deep_sleep
2244 * priv - Device Structure
2248 * Return Value: none
2252 bb_set_deep_sleep(struct vnt_private *priv, unsigned char by_local_id)
2254 bb_write_embedded(priv, 0x0C, 0x17); /* CR12 */
2255 bb_write_embedded(priv, 0x0D, 0xB9); /* CR13 */