drivers/staging/rts5208/rtsx_chip.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for Realtek PCI-Express card reader
   4  *
   5  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   6  *
   7  * Author:
   8  *   Wei WANG ([email protected])
   9  *   Micky Ching ([email protected])
  10  */
  11
  12 #include <linux/blkdev.h>
  13 #include <linux/kthread.h>
  14 #include <linux/sched.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/vmalloc.h>
  17
  18 #include "rtsx.h"
  19 #include "sd.h"
  20 #include "xd.h"
  21 #include "ms.h"
  22
  23 static void rtsx_calibration(struct rtsx_chip *chip)
  24 {
  25         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  26         wait_timeout(10);
  27         rtsx_write_phy_register(chip, 0x00, 0x0280);
  28         rtsx_write_phy_register(chip, 0x01, 0x7112);
  29         rtsx_write_phy_register(chip, 0x01, 0x7110);
  30         rtsx_write_phy_register(chip, 0x01, 0x7112);
  31         rtsx_write_phy_register(chip, 0x01, 0x7113);
  32         rtsx_write_phy_register(chip, 0x00, 0x0288);
  33 }
  34
  35 void rtsx_enable_card_int(struct rtsx_chip *chip)
  36 {
  37         u32 reg = rtsx_readl(chip, RTSX_BIER);
  38         int i;
  39
  40         for (i = 0; i <= chip->max_lun; i++) {
  41                 if (chip->lun2card[i] & XD_CARD)
  42                         reg |= XD_INT_EN;
  43                 if (chip->lun2card[i] & SD_CARD)
  44                         reg |= SD_INT_EN;
  45                 if (chip->lun2card[i] & MS_CARD)
  46                         reg |= MS_INT_EN;
  47         }
  48         if (chip->hw_bypass_sd)
  49                 reg &= ~((u32)SD_INT_EN);
  50
  51         rtsx_writel(chip, RTSX_BIER, reg);
  52 }
  53
  54 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  55 {
  56         u32 reg = 0;
  57 #ifndef DISABLE_CARD_INT
  58         int i;
  59 #endif
  60
  61         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  62
  63 #ifndef DISABLE_CARD_INT
  64         for (i = 0; i <= chip->max_lun; i++) {
  65                 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
  66                         i, chip->lun2card[i]);
  67
  68                 if (chip->lun2card[i] & XD_CARD)
  69                         reg |= XD_INT_EN;
  70                 if (chip->lun2card[i] & SD_CARD)
  71                         reg |= SD_INT_EN;
  72                 if (chip->lun2card[i] & MS_CARD)
  73                         reg |= MS_INT_EN;
  74         }
  75         if (chip->hw_bypass_sd)
  76                 reg &= ~((u32)SD_INT_EN);
  77 #endif
  78
  79         if (chip->ic_version >= IC_VER_C)
  80                 reg |= DELINK_INT_EN;
  81 #ifdef SUPPORT_OCP
  82         reg |= OC_INT_EN;
  83 #endif
  84         if (!chip->adma_mode)
  85                 reg |= DATA_DONE_INT_EN;
  86
  87         /* Enable Bus Interrupt */
  88         rtsx_writel(chip, RTSX_BIER, reg);
  89
  90         dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
  91 }
  92
  93 void rtsx_disable_bus_int(struct rtsx_chip *chip)
  94 {
  95         rtsx_writel(chip, RTSX_BIER, 0);
  96 }
  97
  98 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
  99 {
 100         int retval;
 101
 102         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 103                 if (chip->asic_code) {
 104                         retval = rtsx_write_register(chip, CARD_PULL_CTL5,
 105                                                      0xFF,
 106                                                      MS_INS_PU | SD_WP_PU |
 107                                                      SD_CD_PU | SD_CMD_PU);
 108                         if (retval)
 109                                 return retval;
 110                 } else {
 111                         retval = rtsx_write_register(chip, FPGA_PULL_CTL,
 112                                                      0xFF,
 113                                                      FPGA_SD_PULL_CTL_EN);
 114                         if (retval)
 115                                 return retval;
 116                 }
 117                 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
 118                                              CARD_SHARE_48_SD);
 119                 if (retval)
 120                         return retval;
 121
 122                 /* Enable SDIO internal clock */
 123                 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
 124                 if (retval)
 125                         return retval;
 126
 127                 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
 128                                              SDIO_BUS_CTRL | SDIO_CD_CTRL);
 129                 if (retval)
 130                         return retval;
 131
 132                 chip->sd_int = 1;
 133                 chip->sd_io = 1;
 134         } else {
 135                 chip->need_reset |= SD_CARD;
 136         }
 137
 138         return STATUS_SUCCESS;
 139 }
 140
 141 #ifdef HW_AUTO_SWITCH_SD_BUS
 142 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 143 {
 144         u8 tmp;
 145         bool sw_bypass_sd = false;
 146         int retval;
 147
 148         if (chip->driver_first_load) {
 149                 if (CHECK_PID(chip, 0x5288)) {
 150                         retval = rtsx_read_register(chip, 0xFE5A, &tmp);
 151                         if (retval)
 152                                 return retval;
 153                         if (tmp & 0x08)
 154                                 sw_bypass_sd = true;
 155                 } else if (CHECK_PID(chip, 0x5208)) {
 156                         retval = rtsx_read_register(chip, 0xFE70, &tmp);
 157                         if (retval)
 158                                 return retval;
 159                         if (tmp & 0x80)
 160                                 sw_bypass_sd = true;
 161                 }
 162         } else {
 163                 if (chip->sdio_in_charge)
 164                         sw_bypass_sd = true;
 165         }
 166         dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
 167                 chip->sdio_in_charge);
 168         dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
 169                 chip->driver_first_load);
 170         dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
 171                 sw_bypass_sd);
 172
 173         if (sw_bypass_sd) {
 174                 u8 cd_toggle_mask = 0;
 175
 176                 retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
 177                 if (retval)
 178                         return retval;
 179                 cd_toggle_mask = 0x08;
 180
 181                 if (tmp & cd_toggle_mask) {
 182                         /* Disable sdio_bus_auto_switch */
 183                         if (CHECK_PID(chip, 0x5288)) {
 184                                 retval = rtsx_write_register(chip, 0xFE5A,
 185                                                              0x08, 0x00);
 186                                 if (retval)
 187                                         return retval;
 188                         } else if (CHECK_PID(chip, 0x5208)) {
 189                                 retval = rtsx_write_register(chip, 0xFE70,
 190                                                              0x80, 0x00);
 191                                 if (retval)
 192                                         return retval;
 193                         }
 194
 195                         retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
 196                                                      tmp);
 197                         if (retval)
 198                                 return retval;
 199
 200                         chip->need_reset |= SD_CARD;
 201                 } else {
 202                         dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
 203
 204                         if (chip->asic_code) {
 205                                 retval = sd_pull_ctl_enable(chip);
 206                                 if (retval != STATUS_SUCCESS)
 207                                         return STATUS_FAIL;
 208                         } else {
 209                                 retval = rtsx_write_register
 210                                                 (chip, FPGA_PULL_CTL,
 211                                                  FPGA_SD_PULL_CTL_BIT | 0x20,
 212                                                  0);
 213                                 if (retval)
 214                                         return retval;
 215                         }
 216                         retval = card_share_mode(chip, SD_CARD);
 217                         if (retval != STATUS_SUCCESS)
 218                                 return STATUS_FAIL;
 219
 220                         /* Enable sdio_bus_auto_switch */
 221                         if (CHECK_PID(chip, 0x5288)) {
 222                                 retval = rtsx_write_register(chip, 0xFE5A,
 223                                                              0x08, 0x08);
 224                                 if (retval)
 225                                         return retval;
 226                         } else if (CHECK_PID(chip, 0x5208)) {
 227                                 retval = rtsx_write_register(chip, 0xFE70,
 228                                                              0x80, 0x80);
 229                                 if (retval)
 230                                         return retval;
 231                         }
 232
 233                         chip->chip_insert_with_sdio = 1;
 234                         chip->sd_io = 1;
 235                 }
 236         } else {
 237                 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
 238                 if (retval)
 239                         return retval;
 240
 241                 chip->need_reset |= SD_CARD;
 242         }
 243
 244         return STATUS_SUCCESS;
 245 }
 246 #endif
 247
 248 static int rtsx_reset_aspm(struct rtsx_chip *chip)
 249 {
 250         int ret;
 251
 252         if (chip->dynamic_aspm) {
 253                 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
 254                         return STATUS_SUCCESS;
 255
 256                 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
 257                                         chip->aspm_l0s_l1_en);
 258                 if (ret != STATUS_SUCCESS)
 259                         return STATUS_FAIL;
 260
 261                 return STATUS_SUCCESS;
 262         }
 263
 264         if (CHECK_PID(chip, 0x5208)) {
 265                 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
 266                 if (ret)
 267                         return ret;
 268         }
 269         ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 270         if (ret != STATUS_SUCCESS)
 271                 return STATUS_FAIL;
 272
 273         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 274         if (CHK_SDIO_EXIST(chip)) {
 275                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 276                 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
 277                                         0xC0, 0xFF, chip->aspm_l0s_l1_en);
 278                 if (ret != STATUS_SUCCESS)
 279                         return STATUS_FAIL;
 280         }
 281
 282         chip->aspm_enabled = 1;
 283
 284         return STATUS_SUCCESS;
 285 }
 286
 287 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
 288 {
 289         int ret;
 290
 291         if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
 292                 rtsx_enable_bus_int(chip);
 293                 return STATUS_SUCCESS;
 294         }
 295
 296         if (chip->phy_debug_mode) {
 297                 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
 298                 if (ret)
 299                         return ret;
 300                 rtsx_disable_bus_int(chip);
 301         } else {
 302                 rtsx_enable_bus_int(chip);
 303         }
 304
 305         if (chip->ic_version >= IC_VER_D) {
 306                 u16 reg;
 307
 308                 ret = rtsx_read_phy_register(chip, 0x00, &reg);
 309                 if (ret != STATUS_SUCCESS)
 310                         return STATUS_FAIL;
 311
 312                 reg &= 0xFE7F;
 313                 reg |= 0x80;
 314                 ret = rtsx_write_phy_register(chip, 0x00, reg);
 315                 if (ret != STATUS_SUCCESS)
 316                         return STATUS_FAIL;
 317
 318                 ret = rtsx_read_phy_register(chip, 0x1C, &reg);
 319                 if (ret != STATUS_SUCCESS)
 320                         return STATUS_FAIL;
 321
 322                 reg &= 0xFFF7;
 323                 ret = rtsx_write_phy_register(chip, 0x1C, reg);
 324                 if (ret != STATUS_SUCCESS)
 325                         return STATUS_FAIL;
 326         }
 327
 328         if (chip->driver_first_load && chip->ic_version < IC_VER_C)
 329                 rtsx_calibration(chip);
 330
 331         return STATUS_SUCCESS;
 332 }
 333
 334 int rtsx_reset_chip(struct rtsx_chip *chip)
 335 {
 336         int retval;
 337
 338         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 339
 340         rtsx_disable_aspm(chip);
 341
 342         retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 343         if (retval)
 344                 return retval;
 345
 346         /* Disable card clock */
 347         retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
 348         if (retval)
 349                 return retval;
 350
 351 #ifdef SUPPORT_OCP
 352         /* SSC power on, OCD power on */
 353         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 354                 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
 355                 if (retval)
 356                         return retval;
 357         } else {
 358                 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
 359                                              MS_OC_POWER_DOWN);
 360                 if (retval)
 361                         return retval;
 362         }
 363
 364         retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
 365                                      OCP_TIME_800);
 366         if (retval)
 367                 return retval;
 368         retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
 369                                      OCP_THD_244_946);
 370         if (retval)
 371                 return retval;
 372         retval = rtsx_write_register(chip, OCPCTL, 0xFF,
 373                                      CARD_OC_INT_EN | CARD_DETECT_EN);
 374         if (retval)
 375                 return retval;
 376 #else
 377         /* OC power down */
 378         retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
 379                                      OC_POWER_DOWN);
 380         if (retval)
 381                 return retval;
 382 #endif
 383
 384         if (!CHECK_PID(chip, 0x5288)) {
 385                 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 386                 if (retval)
 387                         return retval;
 388         }
 389
 390         /* Turn off LED */
 391         retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
 392         if (retval)
 393                 return retval;
 394
 395         /* Reset delink mode */
 396         retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
 397         if (retval)
 398                 return retval;
 399
 400         /* Card driving select */
 401         retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
 402                                      chip->card_drive_sel);
 403         if (retval)
 404                 return retval;
 405
 406 #ifdef LED_AUTO_BLINK
 407         retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
 408                                      LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 409         if (retval)
 410                 return retval;
 411 #endif
 412
 413         if (chip->asic_code) {
 414                 /* Enable SSC Clock */
 415                 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
 416                                              SSC_8X_EN | SSC_SEL_4M);
 417                 if (retval)
 418                         return retval;
 419                 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
 420                 if (retval)
 421                         return retval;
 422         }
 423
 424         /*
 425          * Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 426          *    0xFE5B
 427          *    bit[1]    u_cd_rst_core_en        rst_value = 0
 428          *    bit[2]    u_force_rst_core_en     rst_value = 0
 429          *    bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 430          *    bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 431          */
 432         retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 433         if (retval)
 434                 return retval;
 435
 436         /* Enable ASPM */
 437         if (chip->aspm_l0s_l1_en) {
 438                 retval = rtsx_reset_aspm(chip);
 439                 if (retval != STATUS_SUCCESS)
 440                         return STATUS_FAIL;
 441         } else {
 442                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 443                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 444                         if (retval != STATUS_SUCCESS)
 445                                 return STATUS_FAIL;
 446                 }
 447                 retval = rtsx_write_config_byte(chip, LCTLR,
 448                                                 chip->aspm_l0s_l1_en);
 449                 if (retval != STATUS_SUCCESS)
 450                         return STATUS_FAIL;
 451         }
 452
 453         retval = rtsx_write_config_byte(chip, 0x81, 1);
 454         if (retval != STATUS_SUCCESS)
 455                 return STATUS_FAIL;
 456
 457         if (CHK_SDIO_EXIST(chip)) {
 458                 retval = rtsx_write_cfg_dw(chip,
 459                                            CHECK_PID(chip, 0x5288) ? 2 : 1,
 460                                            0xC0, 0xFF00, 0x0100);
 461
 462                 if (retval != STATUS_SUCCESS)
 463                         return STATUS_FAIL;
 464         }
 465
 466         if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
 467                 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
 468                 if (retval != STATUS_SUCCESS)
 469                         return STATUS_FAIL;
 470
 471                 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 472                 if (retval != STATUS_SUCCESS)
 473                         return STATUS_FAIL;
 474         }
 475
 476         retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
 477                                      LINK_RDY_INT);
 478         if (retval)
 479                 return retval;
 480
 481         retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 482         if (retval)
 483                 return retval;
 484
 485         retval = rtsx_enable_pcie_intr(chip);
 486         if (retval != STATUS_SUCCESS)
 487                 return STATUS_FAIL;
 488
 489         chip->need_reset = 0;
 490
 491         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 492
 493         if (chip->hw_bypass_sd)
 494                 goto nextcard;
 495         dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
 496                 chip->int_reg);
 497         if (chip->int_reg & SD_EXIST) {
 498 #ifdef HW_AUTO_SWITCH_SD_BUS
 499                 if (CHECK_PID(chip, 0x5208) && chip->ic_version < IC_VER_C)
 500                         retval = rtsx_pre_handle_sdio_old(chip);
 501                 else
 502                         retval = rtsx_pre_handle_sdio_new(chip);
 503
 504                 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (%s)\n",
 505                         (unsigned int)(chip->need_reset), __func__);
 506 #else  /* HW_AUTO_SWITCH_SD_BUS */
 507                 retval = rtsx_pre_handle_sdio_old(chip);
 508 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 509                 if (retval != STATUS_SUCCESS)
 510                         return STATUS_FAIL;
 511
 512         } else {
 513                 chip->sd_io = 0;
 514                 retval = rtsx_write_register(chip, SDIO_CTRL,
 515                                              SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
 516                 if (retval)
 517                         return retval;
 518         }
 519
 520 nextcard:
 521         if (chip->int_reg & XD_EXIST)
 522                 chip->need_reset |= XD_CARD;
 523         if (chip->int_reg & MS_EXIST)
 524                 chip->need_reset |= MS_CARD;
 525         if (chip->int_reg & CARD_EXIST) {
 526                 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
 527                                              SSC_RSTB);
 528                 if (retval)
 529                         return retval;
 530         }
 531
 532         dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
 533                 (unsigned int)(chip->need_reset));
 534
 535         retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
 536         if (retval)
 537                 return retval;
 538
 539         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 540                 /* Turn off main power when entering S3/S4 state */
 541                 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
 542                                              0x03);
 543                 if (retval)
 544                         return retval;
 545         }
 546
 547         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 548                 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
 549                 if (retval)
 550                         return retval;
 551                 if (chip->aux_pwr_exist) {
 552                         retval = rtsx_write_register(chip, PME_FORCE_CTL,
 553                                                      0xFF, 0x33);
 554                         if (retval)
 555                                 return retval;
 556                 }
 557         } else {
 558                 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
 559                 if (retval)
 560                         return retval;
 561                 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
 562                 if (retval)
 563                         return retval;
 564         }
 565
 566         if (CHECK_PID(chip, 0x5208) && chip->ic_version >= IC_VER_D) {
 567                 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
 568                 if (retval)
 569                         return retval;
 570         }
 571
 572         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 573                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 574                 if (retval != STATUS_SUCCESS)
 575                         return STATUS_FAIL;
 576         }
 577
 578         if (chip->ft2_fast_mode) {
 579                 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
 580                                              MS_PARTIAL_POWER_ON |
 581                                              SD_PARTIAL_POWER_ON);
 582                 if (retval)
 583                         return retval;
 584                 udelay(chip->pmos_pwr_on_interval);
 585                 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
 586                                              MS_POWER_ON | SD_POWER_ON);
 587                 if (retval)
 588                         return retval;
 589
 590                 wait_timeout(200);
 591         }
 592
 593         /* Reset card */
 594         rtsx_reset_detected_cards(chip, 0);
 595
 596         chip->driver_first_load = 0;
 597
 598         return STATUS_SUCCESS;
 599 }
 600
 601 static inline int valid_sd_speed_prior(u32 sd_speed_prior)
 602 {
 603         bool valid_para = true;
 604         int i;
 605
 606         for (i = 0; i < 4; i++) {
 607                 u8 tmp = (u8)(sd_speed_prior >> (i * 8));
 608
 609                 if (tmp < 0x01 || tmp > 0x04) {
 610                         valid_para = false;
 611                         break;
 612                 }
 613         }
 614
 615         return valid_para;
 616 }
 617
 618 static inline int valid_sd_current_prior(u32 sd_current_prior)
 619 {
 620         bool valid_para = true;
 621         int i;
 622
 623         for (i = 0; i < 4; i++) {
 624                 u8 tmp = (u8)(sd_current_prior >> (i * 8));
 625
 626                 if (tmp > 0x03) {
 627                         valid_para = false;
 628                         break;
 629                 }
 630         }
 631
 632         return valid_para;
 633 }
 634
 635 static int rts5208_init(struct rtsx_chip *chip)
 636 {
 637         int retval;
 638         u16 reg = 0;
 639         u8 val = 0;
 640
 641         retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
 642         if (retval)
 643                 return retval;
 644         retval = rtsx_read_register(chip, CLK_SEL, &val);
 645         if (retval)
 646                 return retval;
 647         chip->asic_code = val == 0 ? 1 : 0;
 648
 649         if (chip->asic_code) {
 650                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 651                 if (retval != STATUS_SUCCESS)
 652                         return STATUS_FAIL;
 653
 654                 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
 655                         reg);
 656                 chip->ic_version = (reg >> 4) & 0x07;
 657                 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
 658
 659         } else {
 660                 retval = rtsx_read_register(chip, 0xFE80, &val);
 661                 if (retval)
 662                         return retval;
 663                 chip->ic_version = val;
 664                 chip->phy_debug_mode = 0;
 665         }
 666
 667         retval = rtsx_read_register(chip, PDINFO, &val);
 668         if (retval)
 669                 return retval;
 670         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 671         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 672
 673         retval = rtsx_read_register(chip, 0xFE50, &val);
 674         if (retval)
 675                 return retval;
 676         chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
 677
 678         rtsx_read_config_byte(chip, 0x0E, &val);
 679         if (val & 0x80)
 680                 SET_SDIO_EXIST(chip);
 681         else
 682                 CLR_SDIO_EXIST(chip);
 683
 684         if (chip->use_hw_setting) {
 685                 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
 686                 if (retval)
 687                         return retval;
 688                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 689         }
 690
 691         return STATUS_SUCCESS;
 692 }
 693
 694 static int rts5288_init(struct rtsx_chip *chip)
 695 {
 696         int retval;
 697         u8 val = 0, max_func;
 698         u32 lval = 0;
 699
 700         retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
 701         if (retval)
 702                 return retval;
 703         retval = rtsx_read_register(chip, CLK_SEL, &val);
 704         if (retval)
 705                 return retval;
 706         chip->asic_code = val == 0 ? 1 : 0;
 707
 708         chip->ic_version = 0;
 709         chip->phy_debug_mode = 0;
 710
 711         retval = rtsx_read_register(chip, PDINFO, &val);
 712         if (retval)
 713                 return retval;
 714         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 715         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 716
 717         retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
 718         if (retval)
 719                 return retval;
 720         dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
 721         chip->baro_pkg = val & 0x04 ? QFN : LQFP;
 722
 723         retval = rtsx_read_register(chip, 0xFE5A, &val);
 724         if (retval)
 725                 return retval;
 726         chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
 727
 728         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 729         if (retval != STATUS_SUCCESS)
 730                 return STATUS_FAIL;
 731
 732         max_func = (u8)((lval >> 29) & 0x07);
 733         dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
 734         if (max_func == 0x02)
 735                 SET_SDIO_EXIST(chip);
 736         else
 737                 CLR_SDIO_EXIST(chip);
 738
 739         if (chip->use_hw_setting) {
 740                 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
 741                 if (retval)
 742                         return retval;
 743                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 744
 745                 if (CHECK_BARO_PKG(chip, LQFP))
 746                         chip->lun_mode = SD_MS_1LUN;
 747                 else
 748                         chip->lun_mode = DEFAULT_SINGLE;
 749         }
 750
 751         return STATUS_SUCCESS;
 752 }
 753
 754 int rtsx_init_chip(struct rtsx_chip *chip)
 755 {
 756         struct sd_info *sd_card = &chip->sd_card;
 757         struct xd_info *xd_card = &chip->xd_card;
 758         struct ms_info *ms_card = &chip->ms_card;
 759         int retval;
 760         unsigned int i;
 761
 762         dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 763                 chip->vendor_id, chip->product_id);
 764
 765         chip->ic_version = 0;
 766
 767         memset(xd_card, 0, sizeof(struct xd_info));
 768         memset(sd_card, 0, sizeof(struct sd_info));
 769         memset(ms_card, 0, sizeof(struct ms_info));
 770
 771         chip->xd_reset_counter = 0;
 772         chip->sd_reset_counter = 0;
 773         chip->ms_reset_counter = 0;
 774
 775         chip->xd_show_cnt = MAX_SHOW_CNT;
 776         chip->sd_show_cnt = MAX_SHOW_CNT;
 777         chip->ms_show_cnt = MAX_SHOW_CNT;
 778
 779         chip->sd_io = 0;
 780         chip->auto_delink_cnt = 0;
 781         chip->auto_delink_allowed = 1;
 782         rtsx_set_stat(chip, RTSX_STAT_INIT);
 783
 784         chip->aspm_enabled = 0;
 785         chip->chip_insert_with_sdio = 0;
 786         chip->sdio_aspm = 0;
 787         chip->sdio_idle = 0;
 788         chip->sdio_counter = 0;
 789         chip->cur_card = 0;
 790         chip->phy_debug_mode = 0;
 791         chip->sdio_func_exist = 0;
 792         memset(chip->sdio_raw_data, 0, 12);
 793
 794         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 795                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 796                 chip->rw_fail_cnt[i] = 0;
 797         }
 798
 799         if (!valid_sd_speed_prior(chip->sd_speed_prior))
 800                 chip->sd_speed_prior = 0x01040203;
 801
 802         dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
 803                 chip->sd_speed_prior);
 804
 805         if (!valid_sd_current_prior(chip->sd_current_prior))
 806                 chip->sd_current_prior = 0x00010203;
 807
 808         dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
 809                 chip->sd_current_prior);
 810
 811         if (chip->sd_ddr_tx_phase > 31 || chip->sd_ddr_tx_phase < 0)
 812                 chip->sd_ddr_tx_phase = 0;
 813
 814         if (chip->mmc_ddr_tx_phase > 31 || chip->mmc_ddr_tx_phase < 0)
 815                 chip->mmc_ddr_tx_phase = 0;
 816
 817         retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
 818         if (retval)
 819                 return retval;
 820         wait_timeout(200);
 821         retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
 822         if (retval)
 823                 return retval;
 824         dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
 825                 chip->use_hw_setting);
 826
 827         if (CHECK_PID(chip, 0x5208)) {
 828                 retval = rts5208_init(chip);
 829                 if (retval != STATUS_SUCCESS)
 830                         return STATUS_FAIL;
 831
 832         } else if (CHECK_PID(chip, 0x5288)) {
 833                 retval = rts5288_init(chip);
 834                 if (retval != STATUS_SUCCESS)
 835                         return STATUS_FAIL;
 836         }
 837
 838         if (chip->ss_en == 2)
 839                 chip->ss_en = 0;
 840
 841         dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
 842         dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
 843         dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
 844                 chip->phy_debug_mode);
 845         dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
 846                 chip->aux_pwr_exist);
 847         dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
 848                 chip->sdio_func_exist);
 849         dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
 850                 chip->hw_bypass_sd);
 851         dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
 852                 chip->aspm_l0s_l1_en);
 853         dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
 854         dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
 855                 chip->auto_delink_en);
 856         dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
 857         dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
 858
 859         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 860                 chip->card2lun[SD_CARD] = 0;
 861                 chip->card2lun[MS_CARD] = 1;
 862                 chip->card2lun[XD_CARD] = 0xFF;
 863                 chip->lun2card[0] = SD_CARD;
 864                 chip->lun2card[1] = MS_CARD;
 865                 chip->max_lun = 1;
 866                 SET_SDIO_IGNORED(chip);
 867         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
 868                 chip->card2lun[SD_CARD] = 0;
 869                 chip->card2lun[MS_CARD] = 0;
 870                 chip->card2lun[XD_CARD] = 0xFF;
 871                 chip->lun2card[0] = SD_CARD | MS_CARD;
 872                 chip->max_lun = 0;
 873         } else {
 874                 chip->card2lun[XD_CARD] = 0;
 875                 chip->card2lun[SD_CARD] = 0;
 876                 chip->card2lun[MS_CARD] = 0;
 877                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
 878                 chip->max_lun = 0;
 879         }
 880
 881         retval = rtsx_reset_chip(chip);
 882         if (retval != STATUS_SUCCESS)
 883                 return STATUS_FAIL;
 884
 885         return STATUS_SUCCESS;
 886 }
 887
 888 void rtsx_release_chip(struct rtsx_chip *chip)
 889 {
 890         xd_free_l2p_tbl(chip);
 891         ms_free_l2p_tbl(chip);
 892         chip->card_exist = 0;
 893         chip->card_ready = 0;
 894 }
 895
 896 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 897 static inline void rtsx_blink_led(struct rtsx_chip *chip)
 898 {
 899         if (chip->card_exist && chip->blink_led) {
 900                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
 901                         chip->led_toggle_counter++;
 902                 } else {
 903                         chip->led_toggle_counter = 0;
 904                         toggle_gpio(chip, LED_GPIO);
 905                 }
 906         }
 907 }
 908 #endif
 909
 910 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
 911 {
 912         bool reg_changed, maybe_support_aspm;
 913         u32 tmp = 0;
 914         u8 reg0 = 0, reg1 = 0;
 915
 916         maybe_support_aspm = false;
 917         reg_changed = false;
 918         rtsx_read_config_byte(chip, LCTLR, &reg0);
 919         if (chip->aspm_level[0] != reg0) {
 920                 reg_changed = true;
 921                 chip->aspm_level[0] = reg0;
 922         }
 923         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
 924                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
 925                 reg1 = (u8)tmp;
 926                 if (chip->aspm_level[1] != reg1) {
 927                         reg_changed = true;
 928                         chip->aspm_level[1] = reg1;
 929                 }
 930
 931                 if ((reg0 & 0x03) && (reg1 & 0x03))
 932                         maybe_support_aspm = true;
 933
 934         } else {
 935                 if (reg0 & 0x03)
 936                         maybe_support_aspm = true;
 937         }
 938
 939         if (reg_changed) {
 940                 if (maybe_support_aspm)
 941                         chip->aspm_l0s_l1_en = 0x03;
 942
 943                 dev_dbg(rtsx_dev(chip),
 944                         "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
 945                         chip->aspm_level[0], chip->aspm_level[1]);
 946
 947                 if (chip->aspm_l0s_l1_en) {
 948                         chip->aspm_enabled = 1;
 949                 } else {
 950                         chip->aspm_enabled = 0;
 951                         chip->sdio_aspm = 0;
 952                 }
 953                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
 954                                     0x30 | chip->aspm_level[0] |
 955                                     (chip->aspm_level[1] << 2));
 956         }
 957 }
 958
 959 static void rtsx_manage_ocp(struct rtsx_chip *chip)
 960 {
 961 #ifdef SUPPORT_OCP
 962         if (!chip->ocp_int)
 963                 return;
 964
 965         rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
 966
 967         if (chip->card_exist & SD_CARD)
 968                 sd_power_off_card3v3(chip);
 969         else if (chip->card_exist & MS_CARD)
 970                 ms_power_off_card3v3(chip);
 971         else if (chip->card_exist & XD_CARD)
 972                 xd_power_off_card3v3(chip);
 973
 974         chip->ocp_int = 0;
 975 #endif
 976 }
 977
 978 static void rtsx_manage_sd_lock(struct rtsx_chip *chip)
 979 {
 980 #ifdef SUPPORT_SD_LOCK
 981         struct sd_info *sd_card = &chip->sd_card;
 982         u8 val;
 983
 984         if (!sd_card->sd_erase_status)
 985                 return;
 986
 987         if (chip->card_exist & SD_CARD) {
 988                 rtsx_read_register(chip, 0xFD30, &val);
 989                 if (val & 0x02) {
 990                         sd_card->sd_erase_status = SD_NOT_ERASE;
 991                         sd_card->sd_lock_notify = 1;
 992                         chip->need_reinit |= SD_CARD;
 993                 }
 994         } else {
 995                 sd_card->sd_erase_status = SD_NOT_ERASE;
 996         }
 997 #endif
 998 }
 999
1000 static bool rtsx_is_ss_allowed(struct rtsx_chip *chip)
1001 {
1002         u32 val;
1003
1004         if (!chip->ss_en || CHECK_PID(chip, 0x5288))
1005                 return false;
1006
1007         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1008                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1009                 if (val & 0x07)
1010                         return false;
1011         }
1012
1013         return true;
1014 }
1015
1016 static void rtsx_manage_ss(struct rtsx_chip *chip)
1017 {
1018         if (!rtsx_is_ss_allowed(chip) || chip->sd_io)
1019                 return;
1020
1021         if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1022                 chip->ss_counter = 0;
1023                 return;
1024         }
1025
1026         if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL))
1027                 chip->ss_counter++;
1028         else
1029                 rtsx_exclusive_enter_ss(chip);
1030 }
1031
1032 static void rtsx_manage_aspm(struct rtsx_chip *chip)
1033 {
1034         u8 data;
1035
1036         if (!CHECK_PID(chip, 0x5208))
1037                 return;
1038
1039         rtsx_monitor_aspm_config(chip);
1040
1041 #ifdef SUPPORT_SDIO_ASPM
1042         if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) ||
1043             !chip->aspm_l0s_l1_en || !chip->dynamic_aspm)
1044                 return;
1045
1046         if (chip->sd_io) {
1047                 dynamic_configure_sdio_aspm(chip);
1048                 return;
1049         }
1050
1051         if (chip->sdio_aspm)
1052                 return;
1053
1054         dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
1055         data = 0x30 | (chip->aspm_level[1] << 2);
1056         rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data);
1057         chip->sdio_aspm = 1;
1058 #endif
1059 }
1060
1061 static void rtsx_manage_idle(struct rtsx_chip *chip)
1062 {
1063         if (chip->idle_counter < IDLE_MAX_COUNT) {
1064                 chip->idle_counter++;
1065                 return;
1066         }
1067
1068         if (rtsx_get_stat(chip) == RTSX_STAT_IDLE)
1069                 return;
1070
1071         dev_dbg(rtsx_dev(chip), "Idle state!\n");
1072         rtsx_set_stat(chip, RTSX_STAT_IDLE);
1073
1074 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1075         chip->led_toggle_counter = 0;
1076 #endif
1077         rtsx_force_power_on(chip, SSC_PDCTL);
1078
1079         turn_off_led(chip, LED_GPIO);
1080
1081         if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1082                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1083 }
1084
1085 static void rtsx_manage_2lun_mode(struct rtsx_chip *chip)
1086 {
1087 #ifdef SUPPORT_OCP
1088         u8 sd_oc, ms_oc;
1089
1090         sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER);
1091         ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER);
1092
1093         if (sd_oc || ms_oc)
1094                 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1095                         chip->ocp_stat);
1096
1097         if (sd_oc && (chip->card_exist & SD_CARD)) {
1098                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1099                 card_power_off(chip, SD_CARD);
1100                 chip->card_fail |= SD_CARD;
1101         }
1102
1103         if (ms_oc && (chip->card_exist & MS_CARD)) {
1104                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1105                 card_power_off(chip, MS_CARD);
1106                 chip->card_fail |= MS_CARD;
1107         }
1108 #endif
1109 }
1110
1111 static void rtsx_manage_1lun_mode(struct rtsx_chip *chip)
1112 {
1113 #ifdef SUPPORT_OCP
1114         if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)))
1115                 return;
1116
1117         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1118                 chip->ocp_stat);
1119
1120         if (chip->card_exist & SD_CARD) {
1121                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1122                 chip->card_fail |= SD_CARD;
1123         } else if (chip->card_exist & MS_CARD) {
1124                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1125                 chip->card_fail |= MS_CARD;
1126         } else if (chip->card_exist & XD_CARD) {
1127                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1128                 chip->card_fail |= XD_CARD;
1129         }
1130         card_power_off(chip, SD_CARD);
1131 #endif
1132 }
1133
1134 static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1,
1135                                int stage3_cnt)
1136 {
1137         u8 val;
1138
1139         rtsx_set_stat(chip, RTSX_STAT_DELINK);
1140
1141         if (chip->asic_code && CHECK_PID(chip, 0x5208))
1142                 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1143
1144         if (chip->card_exist)
1145                 dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1146         else
1147                 dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1148
1149         if (enter_L1)
1150                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1151
1152         if (chip->card_exist)
1153                 val = 0x02;
1154         else
1155                 val = 0x0A;
1156
1157         rtsx_write_register(chip, CHANGE_LINK_STATE, val, val);
1158
1159         if (enter_L1)
1160                 rtsx_enter_L1(chip);
1161
1162         if (chip->card_exist)
1163                 chip->auto_delink_cnt = stage3_cnt + 1;
1164 }
1165
1166 static void rtsx_delink_stage(struct rtsx_chip *chip)
1167 {
1168         int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt;
1169         int enter_L1;
1170
1171         if (!chip->auto_delink_en || !chip->auto_delink_allowed ||
1172             chip->card_ready || chip->card_ejected || chip->sd_io) {
1173                 chip->auto_delink_cnt = 0;
1174                 return;
1175         }
1176
1177         enter_L1 = chip->auto_delink_in_L1 &&
1178                 (chip->aspm_l0s_l1_en || chip->ss_en);
1179
1180         delink_stage1_cnt = chip->delink_stage1_step;
1181         delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1182         delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1183
1184         if (chip->auto_delink_cnt > delink_stage3_cnt)
1185                 return;
1186
1187         if (chip->auto_delink_cnt == delink_stage1_cnt)
1188                 rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt);
1189
1190         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1191                 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1192
1193                 if (enter_L1)
1194                         rtsx_exit_L1(chip);
1195
1196                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1197                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1198
1199                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1200         }
1201
1202         chip->auto_delink_cnt++;
1203 }
1204
1205 void rtsx_polling_func(struct rtsx_chip *chip)
1206 {
1207         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1208                 return;
1209
1210         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1211                 goto delink_stage;
1212
1213         if (chip->polling_config) {
1214                 u8 val;
1215
1216                 rtsx_read_config_byte(chip, 0, &val);
1217         }
1218
1219         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1220                 return;
1221
1222         rtsx_manage_ocp(chip);
1223
1224         rtsx_manage_sd_lock(chip);
1225
1226         rtsx_init_cards(chip);
1227
1228         rtsx_manage_ss(chip);
1229
1230         rtsx_manage_aspm(chip);
1231
1232         rtsx_manage_idle(chip);
1233
1234         switch (rtsx_get_stat(chip)) {
1235         case RTSX_STAT_RUN:
1236 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1237                 rtsx_blink_led(chip);
1238 #endif
1239                 do_remaining_work(chip);
1240                 break;
1241
1242         case RTSX_STAT_IDLE:
1243                 if (chip->sd_io && !chip->sd_int)
1244                         try_to_switch_sdio_ctrl(chip);
1245
1246                 rtsx_enable_aspm(chip);
1247                 break;
1248
1249         default:
1250                 break;
1251         }
1252
1253         if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1254                 rtsx_manage_2lun_mode(chip);
1255         else
1256                 rtsx_manage_1lun_mode(chip);
1257
1258 delink_stage:
1259         rtsx_delink_stage(chip);
1260 }
1261
1262 /**
1263  * rtsx_stop_cmd - stop command transfer and DMA transfer
1264  * @chip: Realtek's card reader chip
1265  * @card: flash card type
1266  *
1267  * Stop command transfer and DMA transfer.
1268  * This function is called in error handler.
1269  */
1270 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1271 {
1272         int i;
1273
1274         for (i = 0; i <= 8; i++) {
1275                 int addr = RTSX_HCBAR + i * 4;
1276                 u32 reg;
1277
1278                 reg = rtsx_readl(chip, addr);
1279                 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1280         }
1281         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1282         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1283
1284         for (i = 0; i < 16; i++) {
1285                 u16 addr = 0xFE20 + (u16)i;
1286                 u8 val;
1287
1288                 rtsx_read_register(chip, addr, &val);
1289                 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1290         }
1291
1292         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1293         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1294 }
1295
1296 #define MAX_RW_REG_CNT          1024
1297
1298 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1299 {
1300         int i;
1301         u32 val = 3 << 30;
1302
1303         val |= (u32)(addr & 0x3FFF) << 16;
1304         val |= (u32)mask << 8;
1305         val |= (u32)data;
1306
1307         rtsx_writel(chip, RTSX_HAIMR, val);
1308
1309         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1310                 val = rtsx_readl(chip, RTSX_HAIMR);
1311                 if ((val & BIT(31)) == 0) {
1312                         if (data != (u8)val)
1313                                 return STATUS_FAIL;
1314
1315                         return STATUS_SUCCESS;
1316                 }
1317         }
1318
1319         return STATUS_TIMEDOUT;
1320 }
1321
1322 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1323 {
1324         u32 val = 2 << 30;
1325         int i;
1326
1327         if (data)
1328                 *data = 0;
1329
1330         val |= (u32)(addr & 0x3FFF) << 16;
1331
1332         rtsx_writel(chip, RTSX_HAIMR, val);
1333
1334         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1335                 val = rtsx_readl(chip, RTSX_HAIMR);
1336                 if ((val & BIT(31)) == 0)
1337                         break;
1338         }
1339
1340         if (i >= MAX_RW_REG_CNT)
1341                 return STATUS_TIMEDOUT;
1342
1343         if (data)
1344                 *data = (u8)(val & 0xFF);
1345
1346         return STATUS_SUCCESS;
1347 }
1348
1349 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1350                       u32 val)
1351 {
1352         int retval;
1353         u8 mode = 0, tmp;
1354         int i;
1355
1356         for (i = 0; i < 4; i++) {
1357                 if (mask & 0xFF) {
1358                         retval = rtsx_write_register(chip, CFGDATA0 + i,
1359                                                      0xFF,
1360                                                      (u8)(val & mask & 0xFF));
1361                         if (retval)
1362                                 return retval;
1363                         mode |= (1 << i);
1364                 }
1365                 mask >>= 8;
1366                 val >>= 8;
1367         }
1368
1369         if (mode) {
1370                 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1371                 if (retval)
1372                         return retval;
1373                 retval = rtsx_write_register(chip, CFGADDR1, 0xFF,
1374                                              (u8)(addr >> 8));
1375                 if (retval)
1376                         return retval;
1377
1378                 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1379                                              0x80 | mode |
1380                                              ((func_no & 0x03) << 4));
1381                 if (retval)
1382                         return retval;
1383
1384                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1385                         retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1386                         if (retval)
1387                                 return retval;
1388                         if ((tmp & 0x80) == 0)
1389                                 break;
1390                 }
1391         }
1392
1393         return STATUS_SUCCESS;
1394 }
1395
1396 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1397 {
1398         int retval;
1399         int i;
1400         u8 tmp;
1401         u32 data = 0;
1402
1403         retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1404         if (retval)
1405                 return retval;
1406         retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1407         if (retval)
1408                 return retval;
1409         retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1410                                      0x80 | ((func_no & 0x03) << 4));
1411         if (retval)
1412                 return retval;
1413
1414         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1415                 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1416                 if (retval)
1417                         return retval;
1418                 if ((tmp & 0x80) == 0)
1419                         break;
1420         }
1421
1422         for (i = 0; i < 4; i++) {
1423                 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp);
1424                 if (retval)
1425                         return retval;
1426                 data |= (u32)tmp << (i * 8);
1427         }
1428
1429         if (val)
1430                 *val = data;
1431
1432         return STATUS_SUCCESS;
1433 }
1434
1435 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1436                        int len)
1437 {
1438         u32 *data, *mask;
1439         u16 offset = addr % 4;
1440         u16 aligned_addr = addr - offset;
1441         int dw_len, i, j;
1442         int retval;
1443         size_t size;
1444
1445         if (!buf)
1446                 return STATUS_NOMEM;
1447
1448         if ((len + offset) % 4)
1449                 dw_len = (len + offset) / 4 + 1;
1450         else
1451                 dw_len = (len + offset) / 4;
1452
1453         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1454
1455         size = array_size(dw_len, 4);
1456         data = vzalloc(size);
1457         if (!data)
1458                 return STATUS_NOMEM;
1459
1460         mask = vzalloc(size);
1461         if (!mask) {
1462                 vfree(data);
1463                 return STATUS_NOMEM;
1464         }
1465
1466         j = 0;
1467         for (i = 0; i < len; i++) {
1468                 mask[j] |= 0xFF << (offset * 8);
1469                 data[j] |= buf[i] << (offset * 8);
1470                 if (++offset == 4) {
1471                         j++;
1472                         offset = 0;
1473                 }
1474         }
1475
1476         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask, size);
1477         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data, size);
1478
1479         for (i = 0; i < dw_len; i++) {
1480                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1481                                            mask[i], data[i]);
1482                 if (retval != STATUS_SUCCESS) {
1483                         vfree(data);
1484                         vfree(mask);
1485                         return STATUS_FAIL;
1486                 }
1487         }
1488
1489         vfree(data);
1490         vfree(mask);
1491
1492         return STATUS_SUCCESS;
1493 }
1494
1495 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1496                       int len)
1497 {
1498         u32 *data;
1499         u16 offset = addr % 4;
1500         u16 aligned_addr = addr - offset;
1501         int dw_len, i, j;
1502         int retval;
1503
1504         if ((len + offset) % 4)
1505                 dw_len = (len + offset) / 4 + 1;
1506         else
1507                 dw_len = (len + offset) / 4;
1508
1509         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1510
1511         data = vmalloc(array_size(dw_len, 4));
1512         if (!data)
1513                 return STATUS_NOMEM;
1514
1515         for (i = 0; i < dw_len; i++) {
1516                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1517                                           data + i);
1518                 if (retval != STATUS_SUCCESS) {
1519                         vfree(data);
1520                         return STATUS_FAIL;
1521                 }
1522         }
1523
1524         if (buf) {
1525                 j = 0;
1526
1527                 for (i = 0; i < len; i++) {
1528                         buf[i] = (u8)(data[j] >> (offset * 8));
1529                         if (++offset == 4) {
1530                                 j++;
1531                                 offset = 0;
1532                         }
1533                 }
1534         }
1535
1536         vfree(data);
1537
1538         return STATUS_SUCCESS;
1539 }
1540
1541 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1542 {
1543         int retval;
1544         bool finished = false;
1545         int i;
1546         u8 tmp;
1547
1548         retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val);
1549         if (retval)
1550                 return retval;
1551         retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1552         if (retval)
1553                 return retval;
1554         retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1555         if (retval)
1556                 return retval;
1557         retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81);
1558         if (retval)
1559                 return retval;
1560
1561         for (i = 0; i < 100000; i++) {
1562                 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1563                 if (retval)
1564                         return retval;
1565                 if (!(tmp & 0x80)) {
1566                         finished = true;
1567                         break;
1568                 }
1569         }
1570
1571         if (!finished)
1572                 return STATUS_FAIL;
1573
1574         return STATUS_SUCCESS;
1575 }
1576
1577 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1578 {
1579         int retval;
1580         bool finished = false;
1581         int i;
1582         u16 data = 0;
1583         u8 tmp;
1584
1585         retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1586         if (retval)
1587                 return retval;
1588         retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80);
1589         if (retval)
1590                 return retval;
1591
1592         for (i = 0; i < 100000; i++) {
1593                 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1594                 if (retval)
1595                         return retval;
1596                 if (!(tmp & 0x80)) {
1597                         finished = true;
1598                         break;
1599                 }
1600         }
1601
1602         if (!finished)
1603                 return STATUS_FAIL;
1604
1605         retval = rtsx_read_register(chip, PHYDATA0, &tmp);
1606         if (retval)
1607                 return retval;
1608         data = tmp;
1609         retval = rtsx_read_register(chip, PHYDATA1, &tmp);
1610         if (retval)
1611                 return retval;
1612         data |= (u16)tmp << 8;
1613
1614         if (val)
1615                 *val = data;
1616
1617         return STATUS_SUCCESS;
1618 }
1619
1620 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1621 {
1622         int retval;
1623         int i;
1624         u8 data = 0;
1625
1626         retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr);
1627         if (retval)
1628                 return retval;
1629
1630         for (i = 0; i < 100; i++) {
1631                 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1632                 if (retval)
1633                         return retval;
1634                 if (!(data & 0x80))
1635                         break;
1636                 udelay(1);
1637         }
1638
1639         if (data & 0x80)
1640                 return STATUS_TIMEDOUT;
1641
1642         retval = rtsx_read_register(chip, EFUSE_DATA, &data);
1643         if (retval)
1644                 return retval;
1645         if (val)
1646                 *val = data;
1647
1648         return STATUS_SUCCESS;
1649 }
1650
1651 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1652 {
1653         int retval;
1654         int i, j;
1655         u8 data = 0, tmp = 0xFF;
1656
1657         for (i = 0; i < 8; i++) {
1658                 if (val & (u8)(1 << i))
1659                         continue;
1660
1661                 tmp &= (~(u8)(1 << i));
1662                 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1663
1664                 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp);
1665                 if (retval)
1666                         return retval;
1667                 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF,
1668                                              0xA0 | addr);
1669                 if (retval)
1670                         return retval;
1671
1672                 for (j = 0; j < 100; j++) {
1673                         retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1674                         if (retval)
1675                                 return retval;
1676                         if (!(data & 0x80))
1677                                 break;
1678                         wait_timeout(3);
1679                 }
1680
1681                 if (data & 0x80)
1682                         return STATUS_TIMEDOUT;
1683
1684                 wait_timeout(5);
1685         }
1686
1687         return STATUS_SUCCESS;
1688 }
1689
1690 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1691 {
1692         int retval;
1693         u16 value;
1694
1695         retval = rtsx_read_phy_register(chip, reg, &value);
1696         if (retval != STATUS_SUCCESS)
1697                 return STATUS_FAIL;
1698
1699         if (value & (1 << bit)) {
1700                 value &= ~(1 << bit);
1701                 retval = rtsx_write_phy_register(chip, reg, value);
1702                 if (retval != STATUS_SUCCESS)
1703                         return STATUS_FAIL;
1704         }
1705
1706         return STATUS_SUCCESS;
1707 }
1708
1709 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1710 {
1711         int retval;
1712         u16 value;
1713
1714         retval = rtsx_read_phy_register(chip, reg, &value);
1715         if (retval != STATUS_SUCCESS)
1716                 return STATUS_FAIL;
1717
1718         if ((value & (1 << bit)) == 0) {
1719                 value |= (1 << bit);
1720                 retval = rtsx_write_phy_register(chip, reg, value);
1721                 if (retval != STATUS_SUCCESS)
1722                         return STATUS_FAIL;
1723         }
1724
1725         return STATUS_SUCCESS;
1726 }
1727
1728 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1729 {
1730         u32 ultmp;
1731
1732         dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1733                 chip->product_id, dstate);
1734
1735         if (CHK_SDIO_EXIST(chip)) {
1736                 u8 func_no;
1737
1738                 if (CHECK_PID(chip, 0x5288))
1739                         func_no = 2;
1740                 else
1741                         func_no = 1;
1742
1743                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
1744                 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
1745                         (int)func_no, ultmp);
1746                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
1747         }
1748
1749         rtsx_write_config_byte(chip, 0x44, dstate);
1750         rtsx_write_config_byte(chip, 0x45, 0);
1751 }
1752
1753 void rtsx_enter_L1(struct rtsx_chip *chip)
1754 {
1755         rtsx_handle_pm_dstate(chip, 2);
1756 }
1757
1758 void rtsx_exit_L1(struct rtsx_chip *chip)
1759 {
1760         rtsx_write_config_byte(chip, 0x44, 0);
1761         rtsx_write_config_byte(chip, 0x45, 0);
1762 }
1763
1764 void rtsx_enter_ss(struct rtsx_chip *chip)
1765 {
1766         dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
1767
1768         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1769
1770         if (chip->power_down_in_ss) {
1771                 rtsx_power_off_card(chip);
1772                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1773         }
1774
1775         if (CHK_SDIO_EXIST(chip))
1776                 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
1777                                   0xC0, 0xFF00, 0x0100);
1778
1779         if (chip->auto_delink_en) {
1780                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
1781         } else {
1782                 if (!chip->phy_debug_mode) {
1783                         u32 tmp;
1784
1785                         tmp = rtsx_readl(chip, RTSX_BIER);
1786                         tmp |= CARD_INT;
1787                         rtsx_writel(chip, RTSX_BIER, tmp);
1788                 }
1789
1790                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
1791         }
1792
1793         rtsx_enter_L1(chip);
1794
1795         RTSX_CLR_DELINK(chip);
1796         rtsx_set_stat(chip, RTSX_STAT_SS);
1797 }
1798
1799 void rtsx_exit_ss(struct rtsx_chip *chip)
1800 {
1801         dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
1802
1803         rtsx_exit_L1(chip);
1804
1805         if (chip->power_down_in_ss) {
1806                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
1807                 udelay(1000);
1808         }
1809
1810         if (RTSX_TST_DELINK(chip)) {
1811                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1812                 rtsx_reinit_cards(chip, 1);
1813                 RTSX_CLR_DELINK(chip);
1814         } else if (chip->power_down_in_ss) {
1815                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1816                 rtsx_reinit_cards(chip, 0);
1817         }
1818 }
1819
1820 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
1821 {
1822         u32 status, int_enable;
1823         bool exit_ss = false;
1824 #ifdef SUPPORT_OCP
1825         u32 ocp_int = 0;
1826
1827         ocp_int = OC_INT;
1828 #endif
1829
1830         if (chip->ss_en) {
1831                 chip->ss_counter = 0;
1832                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
1833                         exit_ss = true;
1834                         rtsx_exit_L1(chip);
1835                         rtsx_set_stat(chip, RTSX_STAT_RUN);
1836                 }
1837         }
1838
1839         int_enable = rtsx_readl(chip, RTSX_BIER);
1840         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
1841
1842         if (((chip->int_reg & int_enable) == 0) ||
1843             chip->int_reg == 0xFFFFFFFF)
1844                 return STATUS_FAIL;
1845
1846         status = chip->int_reg &= (int_enable | 0x7FFFFF);
1847
1848         if (status & CARD_INT) {
1849                 chip->auto_delink_cnt = 0;
1850
1851                 if (status & SD_INT) {
1852                         if (status & SD_EXIST) {
1853                                 set_bit(SD_NR, &chip->need_reset);
1854                         } else {
1855                                 set_bit(SD_NR, &chip->need_release);
1856                                 chip->sd_reset_counter = 0;
1857                                 chip->sd_show_cnt = 0;
1858                                 clear_bit(SD_NR, &chip->need_reset);
1859                         }
1860                 } else {
1861                         /*
1862                          * If multi-luns, it's possible that
1863                          * when plugging/unplugging one card
1864                          * there is another card which still
1865                          * exists in the slot. In this case,
1866                          * all existed cards should be reset.
1867                          */
1868                         if (exit_ss && (status & SD_EXIST))
1869                                 set_bit(SD_NR, &chip->need_reinit);
1870                 }
1871                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
1872                         if (status & XD_INT) {
1873                                 if (status & XD_EXIST) {
1874                                         set_bit(XD_NR, &chip->need_reset);
1875                                 } else {
1876                                         set_bit(XD_NR, &chip->need_release);
1877                                         chip->xd_reset_counter = 0;
1878                                         chip->xd_show_cnt = 0;
1879                                         clear_bit(XD_NR, &chip->need_reset);
1880                                 }
1881                         } else {
1882                                 if (exit_ss && (status & XD_EXIST))
1883                                         set_bit(XD_NR, &chip->need_reinit);
1884                         }
1885                 }
1886                 if (status & MS_INT) {
1887                         if (status & MS_EXIST) {
1888                                 set_bit(MS_NR, &chip->need_reset);
1889                         } else {
1890                                 set_bit(MS_NR, &chip->need_release);
1891                                 chip->ms_reset_counter = 0;
1892                                 chip->ms_show_cnt = 0;
1893                                 clear_bit(MS_NR, &chip->need_reset);
1894                         }
1895                 } else {
1896                         if (exit_ss && (status & MS_EXIST))
1897                                 set_bit(MS_NR, &chip->need_reinit);
1898                 }
1899         }
1900
1901 #ifdef SUPPORT_OCP
1902         chip->ocp_int = ocp_int & status;
1903 #endif
1904
1905         if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
1906                 chip->int_reg &= ~(u32)DATA_DONE_INT;
1907
1908         return STATUS_SUCCESS;
1909 }
1910
1911 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
1912 {
1913         int retval;
1914
1915         dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
1916
1917         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
1918
1919         retval = rtsx_force_power_on(chip, SSC_PDCTL);
1920         if (retval != STATUS_SUCCESS)
1921                 return;
1922
1923         rtsx_release_cards(chip);
1924         rtsx_disable_bus_int(chip);
1925         turn_off_led(chip, LED_GPIO);
1926
1927 #ifdef HW_AUTO_SWITCH_SD_BUS
1928         if (chip->sd_io) {
1929                 chip->sdio_in_charge = 1;
1930                 if (CHECK_PID(chip, 0x5208)) {
1931                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
1932                         /* Enable sdio_bus_auto_switch */
1933                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
1934                 } else if (CHECK_PID(chip, 0x5288)) {
1935                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
1936                         /* Enable sdio_bus_auto_switch */
1937                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
1938                 }
1939         }
1940 #endif
1941
1942         if (CHECK_PID(chip, 0x5208) && chip->ic_version >= IC_VER_D) {
1943                 /* u_force_clkreq_0 */
1944                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
1945         }
1946
1947         if (pm_stat == PM_S1) {
1948                 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
1949                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
1950                                     HOST_ENTER_S1);
1951         } else if (pm_stat == PM_S3) {
1952                 if (chip->s3_pwr_off_delay > 0)
1953                         wait_timeout(chip->s3_pwr_off_delay);
1954
1955                 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
1956                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
1957                                     HOST_ENTER_S3);
1958         }
1959
1960         if (chip->do_delink_before_power_down && chip->auto_delink_en)
1961                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
1962
1963         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1964
1965         chip->cur_clk = 0;
1966         chip->cur_card = 0;
1967         chip->card_exist = 0;
1968 }
1969
1970 void rtsx_enable_aspm(struct rtsx_chip *chip)
1971 {
1972         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
1973                 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
1974                 chip->aspm_enabled = 1;
1975
1976                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1977                         rtsx_write_phy_register(chip, 0x07, 0);
1978                 if (CHECK_PID(chip, 0x5208)) {
1979                         rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
1980                                             0x30 | chip->aspm_level[0]);
1981                 } else {
1982                         rtsx_write_config_byte(chip, LCTLR,
1983                                                chip->aspm_l0s_l1_en);
1984                 }
1985
1986                 if (CHK_SDIO_EXIST(chip)) {
1987                         u16 val = chip->aspm_l0s_l1_en | 0x0100;
1988
1989                         rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
1990                                           0xC0, 0xFFF, val);
1991                 }
1992         }
1993 }
1994
1995 void rtsx_disable_aspm(struct rtsx_chip *chip)
1996 {
1997         if (CHECK_PID(chip, 0x5208))
1998                 rtsx_monitor_aspm_config(chip);
1999
2000         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
2001                 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
2002                 chip->aspm_enabled = 0;
2003
2004                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2005                         rtsx_write_phy_register(chip, 0x07, 0x0129);
2006                 if (CHECK_PID(chip, 0x5208))
2007                         rtsx_write_register(chip, ASPM_FORCE_CTL,
2008                                             0xF3, 0x30);
2009                 else
2010                         rtsx_write_config_byte(chip, LCTLR, 0x00);
2011
2012                 wait_timeout(1);
2013         }
2014 }
2015
2016 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2017 {
2018         int retval;
2019         int i, j;
2020         u16 reg_addr;
2021         u8 *ptr;
2022
2023         if (!buf)
2024                 return STATUS_ERROR;
2025
2026         ptr = buf;
2027         reg_addr = PPBUF_BASE2;
2028         for (i = 0; i < buf_len / 256; i++) {
2029                 rtsx_init_cmd(chip);
2030
2031                 for (j = 0; j < 256; j++)
2032                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2033
2034                 retval = rtsx_send_cmd(chip, 0, 250);
2035                 if (retval < 0)
2036                         return STATUS_FAIL;
2037
2038                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2039                 ptr += 256;
2040         }
2041
2042         if (buf_len % 256) {
2043                 rtsx_init_cmd(chip);
2044
2045                 for (j = 0; j < buf_len % 256; j++)
2046                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2047
2048                 retval = rtsx_send_cmd(chip, 0, 250);
2049                 if (retval < 0)
2050                         return STATUS_FAIL;
2051         }
2052
2053         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len % 256);
2054
2055         return STATUS_SUCCESS;
2056 }
2057
2058 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2059 {
2060         int retval;
2061         int i, j;
2062         u16 reg_addr;
2063         u8 *ptr;
2064
2065         if (!buf)
2066                 return STATUS_ERROR;
2067
2068         ptr = buf;
2069         reg_addr = PPBUF_BASE2;
2070         for (i = 0; i < buf_len / 256; i++) {
2071                 rtsx_init_cmd(chip);
2072
2073                 for (j = 0; j < 256; j++) {
2074                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2075                                      *ptr);
2076                         ptr++;
2077                 }
2078
2079                 retval = rtsx_send_cmd(chip, 0, 250);
2080                 if (retval < 0)
2081                         return STATUS_FAIL;
2082         }
2083
2084         if (buf_len % 256) {
2085                 rtsx_init_cmd(chip);
2086
2087                 for (j = 0; j < buf_len % 256; j++) {
2088                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2089                                      *ptr);
2090                         ptr++;
2091                 }
2092
2093                 retval = rtsx_send_cmd(chip, 0, 250);
2094                 if (retval < 0)
2095                         return STATUS_FAIL;
2096         }
2097
2098         return STATUS_SUCCESS;
2099 }
2100
2101 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2102 {
2103         if (rtsx_readl(chip, 0) == 0xFFFFFFFF)
2104                 return STATUS_FAIL;
2105
2106         return STATUS_SUCCESS;
2107 }
2108
2109 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2110 {
2111         int retval;
2112         u8 mask = 0;
2113
2114         if (ctl & SSC_PDCTL)
2115                 mask |= SSC_POWER_DOWN;
2116
2117 #ifdef SUPPORT_OCP
2118         if (ctl & OC_PDCTL) {
2119                 mask |= SD_OC_POWER_DOWN;
2120                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2121                         mask |= MS_OC_POWER_DOWN;
2122         }
2123 #endif
2124
2125         if (mask) {
2126                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2127                 if (retval != STATUS_SUCCESS)
2128                         return STATUS_FAIL;
2129
2130                 if (CHECK_PID(chip, 0x5288))
2131                         wait_timeout(200);
2132         }
2133
2134         return STATUS_SUCCESS;
2135 }
2136
2137 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2138 {
2139         int retval;
2140         u8 mask = 0, val = 0;
2141
2142         if (ctl & SSC_PDCTL)
2143                 mask |= SSC_POWER_DOWN;
2144
2145 #ifdef SUPPORT_OCP
2146         if (ctl & OC_PDCTL) {
2147                 mask |= SD_OC_POWER_DOWN;
2148                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2149                         mask |= MS_OC_POWER_DOWN;
2150         }
2151 #endif
2152
2153         if (mask) {
2154                 val = mask;
2155                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2156                 if (retval != STATUS_SUCCESS)
2157                         return STATUS_FAIL;
2158         }
2159
2160         return STATUS_SUCCESS;
2161 }