drivers/staging/rtl8192u/r8192U_dm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*++
   3  * Copyright-c Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * Module Name:
   6  *      r8192U_dm.c
   7  *
   8  * Abstract:
   9  *      HW dynamic mechanism.
  10  *--
  11  */
  12 #include "r8192U.h"
  13 #include "r8192U_dm.h"
  14 #include "r8192U_hw.h"
  15 #include "r819xU_phy.h"
  16 #include "r819xU_phyreg.h"
  17 #include "r8190_rtl8256.h"
  18 #include "r819xU_cmdpkt.h"
  19 /*---------------------------Define Local Constant---------------------------*/
  20 /* Indicate different AP vendor for IOT issue. */
  21 static u32 edca_setting_DL[HT_IOT_PEER_MAX] = {
  22         0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0x00a44f, 0x5ea44f
  23 };
  24
  25 static u32 edca_setting_UL[HT_IOT_PEER_MAX] = {
  26         0x5e4322, 0x00a44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f
  27 };
  28
  29 #define RTK_UL_EDCA 0xa44f
  30 #define RTK_DL_EDCA 0x5e4322
  31 /*---------------------------Define Local Constant---------------------------*/
  32
  33
  34 /*------------------------Define global variable-----------------------------*/
  35 /* Debug variable ? */
  36 struct dig dm_digtable;
  37 /* Store current software write register content for MAC PHY. */
  38 u8              dm_shadow[16][256] = { {0} };
  39 /* For Dynamic Rx Path Selection by Signal Strength */
  40 static struct dynamic_rx_path_sel DM_RxPathSelTable;
  41
  42 extern  void dm_check_fsync(struct net_device *dev);
  43
  44 /* DM --> Rate Adaptive */
  45 static  void    dm_check_rate_adaptive(struct net_device *dev);
  46
  47 /* DM --> Bandwidth switch */
  48 static  void    dm_init_bandwidth_autoswitch(struct net_device *dev);
  49 static  void    dm_bandwidth_autoswitch(struct net_device *dev);
  50
  51 /* DM --> TX power control */
  52 static  void    dm_check_txpower_tracking(struct net_device *dev);
  53
  54 /* DM --> Dynamic Init Gain by RSSI */
  55 static  void    dm_dig_init(struct net_device *dev);
  56 static  void    dm_ctrl_initgain_byrssi(struct net_device *dev);
  57 static  void    dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
  58 static  void    dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device *dev);
  59 static  void    dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
  60 static  void    dm_initial_gain(struct net_device *dev);
  61 static  void    dm_pd_th(struct net_device *dev);
  62 static  void    dm_cs_ratio(struct net_device *dev);
  63
  64 static  void dm_init_ctstoself(struct net_device *dev);
  65 /* DM --> EDCA turbo mode control */
  66 static  void    dm_check_edca_turbo(struct net_device *dev);
  67
  68 /* DM --> Check PBC */
  69 static  void dm_check_pbc_gpio(struct net_device *dev);
  70
  71 /* DM --> Check current RX RF path state */
  72 static  void    dm_check_rx_path_selection(struct net_device *dev);
  73 static  void dm_init_rxpath_selection(struct net_device *dev);
  74 static  void dm_rxpath_sel_byrssi(struct net_device *dev);
  75
  76 /* DM --> Fsync for broadcom ap */
  77 static void dm_init_fsync(struct net_device *dev);
  78 static void dm_deInit_fsync(struct net_device *dev);
  79
  80 /* Added by vivi, 20080522 */
  81 static  void    dm_check_txrateandretrycount(struct net_device *dev);
  82
  83 /*---------------------Define local function prototype-----------------------*/
  84
  85 /*---------------------Define of Tx Power Control For Near/Far Range --------*/   /*Add by Jacken 2008/02/18 */
  86 static  void    dm_init_dynamic_txpower(struct net_device *dev);
  87 static  void    dm_dynamic_txpower(struct net_device *dev);
  88
  89 /* DM --> For rate adaptive and DIG, we must send RSSI to firmware */
  90 static  void dm_send_rssi_tofw(struct net_device *dev);
  91 static  void    dm_ctstoself(struct net_device *dev);
  92 /*---------------------------Define function prototype------------------------*/
  93 /* ================================================================================
  94  *      HW Dynamic mechanism interface.
  95  * ================================================================================
  96  *
  97  *
  98  *      Description:
  99  *              Prepare SW resource for HW dynamic mechanism.
 100  *
 101  *      Assumption:
 102  *              This function is only invoked at driver initialization once.
 103  */
 104 void init_hal_dm(struct net_device *dev)
 105 {
 106         struct r8192_priv *priv = ieee80211_priv(dev);
 107
 108         /* Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism. */
 109         priv->undecorated_smoothed_pwdb = -1;
 110
 111         /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
 112         dm_init_dynamic_txpower(dev);
 113         init_rate_adaptive(dev);
 114         dm_dig_init(dev);
 115         dm_init_edca_turbo(dev);
 116         dm_init_bandwidth_autoswitch(dev);
 117         dm_init_fsync(dev);
 118         dm_init_rxpath_selection(dev);
 119         dm_init_ctstoself(dev);
 120
 121 }       /* InitHalDm */
 122
 123 void deinit_hal_dm(struct net_device *dev)
 124 {
 125         dm_deInit_fsync(dev);
 126 }
 127
 128 #ifdef USB_RX_AGGREGATION_SUPPORT
 129 void dm_CheckRxAggregation(struct net_device *dev)
 130 {
 131         struct r8192_priv *priv = ieee80211_priv(dev);
 132         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
 133         static unsigned long    lastTxOkCnt;
 134         static unsigned long    lastRxOkCnt;
 135         unsigned long           curTxOkCnt = 0;
 136         unsigned long           curRxOkCnt = 0;
 137
 138         curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
 139         curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
 140
 141         if ((curTxOkCnt + curRxOkCnt) < 15000000)
 142                 return;
 143
 144         if (curTxOkCnt > 4*curRxOkCnt) {
 145                 if (priv->bCurrentRxAggrEnable) {
 146                         write_nic_dword(dev, 0x1a8, 0);
 147                         priv->bCurrentRxAggrEnable = false;
 148                 }
 149         } else {
 150                 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
 151                         u32 ulValue;
 152
 153                         ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
 154                                 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
 155                         /* If usb rx firmware aggregation is enabled,
 156                          * when anyone of three threshold conditions above is reached,
 157                          * firmware will send aggregated packet to driver.
 158                          */
 159                         write_nic_dword(dev, 0x1a8, ulValue);
 160                         priv->bCurrentRxAggrEnable = true;
 161                 }
 162         }
 163
 164         lastTxOkCnt = priv->stats.txbytesunicast;
 165         lastRxOkCnt = priv->stats.rxbytesunicast;
 166 }       /* dm_CheckEdcaTurbo */
 167 #endif
 168
 169 void hal_dm_watchdog(struct net_device *dev)
 170 {
 171         /*Add by amy 2008/05/15 ,porting from windows code.*/
 172         dm_check_rate_adaptive(dev);
 173         dm_dynamic_txpower(dev);
 174         dm_check_txrateandretrycount(dev);
 175         dm_check_txpower_tracking(dev);
 176         dm_ctrl_initgain_byrssi(dev);
 177         dm_check_edca_turbo(dev);
 178         dm_bandwidth_autoswitch(dev);
 179         dm_check_rx_path_selection(dev);
 180         dm_check_fsync(dev);
 181
 182         /* Add by amy 2008-05-15 porting from windows code. */
 183         dm_check_pbc_gpio(dev);
 184         dm_send_rssi_tofw(dev);
 185         dm_ctstoself(dev);
 186 #ifdef USB_RX_AGGREGATION_SUPPORT
 187         dm_CheckRxAggregation(dev);
 188 #endif
 189 }       /* HalDmWatchDog */
 190
 191 /* Decide Rate Adaptive Set according to distance (signal strength)
 192  *      01/11/2008      MHC             Modify input arguments and RATR table level.
 193  *      01/16/2008      MHC             RF_Type is assigned in ReadAdapterInfo(). We must call
 194  *                                              the function after making sure RF_Type.
 195  */
 196 void init_rate_adaptive(struct net_device *dev)
 197 {
 198         struct r8192_priv *priv = ieee80211_priv(dev);
 199         prate_adaptive  pra = (prate_adaptive)&priv->rate_adaptive;
 200
 201         pra->ratr_state = DM_RATR_STA_MAX;
 202         pra->high2low_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH;
 203         pra->low2high_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M + 5;
 204         pra->low2high_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M + 5;
 205
 206         pra->high_rssi_thresh_for_ra = RATE_ADAPTIVE_TH_HIGH + 5;
 207         pra->low_rssi_thresh_for_ra20M = RATE_ADAPTIVE_TH_LOW_20M;
 208         pra->low_rssi_thresh_for_ra40M = RATE_ADAPTIVE_TH_LOW_40M;
 209
 210         if (priv->CustomerID == RT_CID_819x_Netcore)
 211                 pra->ping_rssi_enable = 1;
 212         else
 213                 pra->ping_rssi_enable = 0;
 214         pra->ping_rssi_thresh_for_ra = 15;
 215
 216         if (priv->rf_type == RF_2T4R) {
 217                 /* 07/10/08 MH Modify for RA smooth scheme.
 218                  * 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.
 219                  */
 220                 pra->upper_rssi_threshold_ratr          =       0x8f0f0000;
 221                 pra->middle_rssi_threshold_ratr         =       0x8f0ff000;
 222                 pra->low_rssi_threshold_ratr            =       0x8f0ff001;
 223                 pra->low_rssi_threshold_ratr_40M        =       0x8f0ff005;
 224                 pra->low_rssi_threshold_ratr_20M        =       0x8f0ff001;
 225                 pra->ping_rssi_ratr     =       0x0000000d;/* cosa add for test */
 226         } else if (priv->rf_type == RF_1T2R) {
 227                 pra->upper_rssi_threshold_ratr          =       0x000f0000;
 228                 pra->middle_rssi_threshold_ratr         =       0x000ff000;
 229                 pra->low_rssi_threshold_ratr            =       0x000ff001;
 230                 pra->low_rssi_threshold_ratr_40M        =       0x000ff005;
 231                 pra->low_rssi_threshold_ratr_20M        =       0x000ff001;
 232                 pra->ping_rssi_ratr     =       0x0000000d;/* cosa add for test */
 233         }
 234
 235 }       /* InitRateAdaptive */
 236
 237 /*-----------------------------------------------------------------------------
 238  * Function:    dm_check_rate_adaptive()
 239  *
 240  * Overview:
 241  *
 242  * Input:               NONE
 243  *
 244  * Output:              NONE
 245  *
 246  * Return:              NONE
 247  *---------------------------------------------------------------------------
 248  */
 249 static void dm_check_rate_adaptive(struct net_device *dev)
 250 {
 251         struct r8192_priv *priv = ieee80211_priv(dev);
 252         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
 253         prate_adaptive                  pra = (prate_adaptive)&priv->rate_adaptive;
 254         u32                                             currentRATR, targetRATR = 0;
 255         u32                                             LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
 256         bool                                            bshort_gi_enabled = false;
 257         static u8                                       ping_rssi_state;
 258
 259         if (!priv->up) {
 260                 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
 261                 return;
 262         }
 263
 264         if (pra->rate_adaptive_disabled) /* this variable is set by ioctl. */
 265                 return;
 266
 267         /* TODO: Only 11n mode is implemented currently, */
 268         if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
 269               priv->ieee80211->mode == WIRELESS_MODE_N_5G))
 270                 return;
 271
 272         if (priv->ieee80211->state == IEEE80211_LINKED) {
 273
 274                 /* Check whether Short GI is enabled */
 275                 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
 276                         (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
 277
 278                 pra->upper_rssi_threshold_ratr =
 279                                 (pra->upper_rssi_threshold_ratr & (~BIT(31))) |
 280                                 ((bshort_gi_enabled) ? BIT(31) : 0);
 281
 282                 pra->middle_rssi_threshold_ratr =
 283                                 (pra->middle_rssi_threshold_ratr & (~BIT(31))) |
 284                                 ((bshort_gi_enabled) ? BIT(31) : 0);
 285
 286                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
 287                         pra->low_rssi_threshold_ratr =
 288                               (pra->low_rssi_threshold_ratr_40M & (~BIT(31))) |
 289                               ((bshort_gi_enabled) ? BIT(31) : 0);
 290                 } else {
 291                         pra->low_rssi_threshold_ratr =
 292                         (pra->low_rssi_threshold_ratr_20M & (~BIT(31))) |
 293                         ((bshort_gi_enabled) ? BIT(31) : 0);
 294                 }
 295                 /* cosa add for test */
 296                 pra->ping_rssi_ratr =
 297                                 (pra->ping_rssi_ratr & (~BIT(31))) |
 298                                 ((bshort_gi_enabled) ? BIT(31) : 0);
 299
 300                 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
 301                  * time to link with AP. We will not change upper/lower threshold. If
 302                  * STA stay in high or low level, we must change two different threshold
 303                  * to prevent jumping frequently.
 304                  */
 305                 if (pra->ratr_state == DM_RATR_STA_HIGH) {
 306                         HighRSSIThreshForRA     = pra->high2low_rssi_thresh_for_ra;
 307                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 308                                         (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
 309                 } else if (pra->ratr_state == DM_RATR_STA_LOW) {
 310                         HighRSSIThreshForRA     = pra->high_rssi_thresh_for_ra;
 311                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 312                                         (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
 313                 } else {
 314                         HighRSSIThreshForRA     = pra->high_rssi_thresh_for_ra;
 315                         LowRSSIThreshForRA      = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) ?
 316                                         (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
 317                 }
 318
 319                 if (priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA) {
 320                         pra->ratr_state = DM_RATR_STA_HIGH;
 321                         targetRATR = pra->upper_rssi_threshold_ratr;
 322                 } else if (priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA) {
 323                         pra->ratr_state = DM_RATR_STA_MIDDLE;
 324                         targetRATR = pra->middle_rssi_threshold_ratr;
 325                 } else {
 326                         pra->ratr_state = DM_RATR_STA_LOW;
 327                         targetRATR = pra->low_rssi_threshold_ratr;
 328                 }
 329
 330                 /* cosa add for test */
 331                 if (pra->ping_rssi_enable) {
 332                         if (priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5)) {
 333                                 if ((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
 334                                         ping_rssi_state) {
 335                                         pra->ratr_state = DM_RATR_STA_LOW;
 336                                         targetRATR = pra->ping_rssi_ratr;
 337                                         ping_rssi_state = 1;
 338                                 }
 339                         } else {
 340                                 ping_rssi_state = 0;
 341                         }
 342                 }
 343
 344                 /* 2008.04.01
 345                  * For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
 346                  */
 347                 if (priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
 348                         targetRATR &= 0xf00fffff;
 349
 350                 /* Check whether updating of RATR0 is required */
 351                 read_nic_dword(dev, RATR0, &currentRATR);
 352                 if (targetRATR !=  currentRATR) {
 353                         u32 ratr_value;
 354
 355                         ratr_value = targetRATR;
 356                         RT_TRACE(COMP_RATE, "currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
 357                         if (priv->rf_type == RF_1T2R)
 358                                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
 359                         write_nic_dword(dev, RATR0, ratr_value);
 360                         write_nic_byte(dev, UFWP, 1);
 361
 362                         pra->last_ratr = targetRATR;
 363                 }
 364
 365         } else {
 366                 pra->ratr_state = DM_RATR_STA_MAX;
 367         }
 368
 369 }       /* dm_CheckRateAdaptive */
 370
 371 static void dm_init_bandwidth_autoswitch(struct net_device *dev)
 372 {
 373         struct r8192_priv *priv = ieee80211_priv(dev);
 374
 375         priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
 376         priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
 377         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
 378         priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
 379
 380 }       /* dm_init_bandwidth_autoswitch */
 381
 382 static void dm_bandwidth_autoswitch(struct net_device *dev)
 383 {
 384         struct r8192_priv *priv = ieee80211_priv(dev);
 385
 386         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 || !priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable)
 387                 return;
 388         if (!priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz) { /* If send packets in 40 Mhz in 20/40 */
 389                 if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
 390                         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
 391         } else { /* in force send packets in 20 Mhz in 20/40 */
 392                 if (priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
 393                         priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
 394         }
 395 }       /* dm_BandwidthAutoSwitch */
 396
 397 /* OFDM default at 0db, index=6. */
 398 static u32 OFDMSwingTable[OFDM_Table_Length] = {
 399         0x7f8001fe,     /* 0, +6db */
 400         0x71c001c7,     /* 1, +5db */
 401         0x65400195,     /* 2, +4db */
 402         0x5a400169,     /* 3, +3db */
 403         0x50800142,     /* 4, +2db */
 404         0x47c0011f,     /* 5, +1db */
 405         0x40000100,     /* 6, +0db ===> default, upper for higher temperature, lower for low temperature */
 406         0x390000e4,     /* 7, -1db */
 407         0x32c000cb,     /* 8, -2db */
 408         0x2d4000b5,     /* 9, -3db */
 409         0x288000a2,     /* 10, -4db */
 410         0x24000090,     /* 11, -5db */
 411         0x20000080,     /* 12, -6db */
 412         0x1c800072,     /* 13, -7db */
 413         0x19800066,     /* 14, -8db */
 414         0x26c0005b,     /* 15, -9db */
 415         0x24400051,     /* 16, -10db */
 416         0x12000048,     /* 17, -11db */
 417         0x10000040      /* 18, -12db */
 418 };
 419
 420 static u8       CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
 421         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       /* 0, +0db ===> CCK40M default */
 422         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       /* 1, -1db */
 423         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       /* 2, -2db */
 424         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       /* 3, -3db */
 425         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       /* 4, -4db */
 426         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       /* 5, -5db */
 427         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       /* 6, -6db ===> CCK20M default */
 428         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       /* 7, -7db */
 429         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       /* 8, -8db */
 430         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       /* 9, -9db */
 431         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       /* 10, -10db */
 432         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}        /* 11, -11db */
 433 };
 434
 435 static u8       CCKSwingTable_Ch14[CCK_Table_length][8] = {
 436         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       /* 0, +0db  ===> CCK40M default */
 437         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       /* 1, -1db */
 438         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       /* 2, -2db */
 439         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       /* 3, -3db */
 440         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       /* 4, -4db */
 441         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       /* 5, -5db */
 442         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       /* 6, -6db  ===> CCK20M default */
 443         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       /* 7, -7db */
 444         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       /* 8, -8db */
 445         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       /* 9, -9db */
 446         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       /* 10, -10db */
 447         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}        /* 11, -11db */
 448 };
 449
 450 static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
 451 {
 452         struct r8192_priv *priv = ieee80211_priv(dev);
 453         bool                                            viviflag = false;
 454         struct tx_config_cmd                            tx_cmd;
 455         u8                                              powerlevelOFDM24G;
 456         int                                             i = 0, j = 0, k = 0;
 457         u8                                              RF_Type, tmp_report[5] = {0, 0, 0, 0, 0};
 458         u32                                             Value;
 459         u8                                              Pwr_Flag;
 460         u16                                             Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver = 0;
 461         bool rtStatus = true;
 462         u32                                             delta = 0;
 463
 464         write_nic_byte(dev, 0x1ba, 0);
 465
 466         priv->ieee80211->bdynamic_txpower_enable = false;
 467
 468         powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
 469         RF_Type = priv->rf_type;
 470         Value = (RF_Type<<8) | powerlevelOFDM24G;
 471
 472         RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
 473
 474         for (j = 0; j <= 30; j++) { /* fill tx_cmd */
 475                 tx_cmd.cmd_op = TXCMD_SET_TX_PWR_TRACKING;
 476                 tx_cmd.cmd_length = sizeof(tx_cmd.cmd_op);
 477                 tx_cmd.cmd_value = Value;
 478                 rtStatus = SendTxCommandPacket(dev, &tx_cmd, sizeof(struct tx_config_cmd));
 479                 if (rtStatus == RT_STATUS_FAILURE)
 480                         RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
 481                 usleep_range(1000, 2000);
 482                 for (i = 0; i <= 30; i++) {
 483                         read_nic_byte(dev, 0x1ba, &Pwr_Flag);
 484
 485                         if (Pwr_Flag == 0) {
 486                                 usleep_range(1000, 2000);
 487                                 continue;
 488                         }
 489                         read_nic_word(dev, 0x13c, &Avg_TSSI_Meas);
 490                         if (Avg_TSSI_Meas == 0) {
 491                                 write_nic_byte(dev, 0x1ba, 0);
 492                                 break;
 493                         }
 494
 495                         for (k = 0; k < 5; k++) {
 496                                 if (k != 4)
 497                                         read_nic_byte(dev, 0x134+k, &tmp_report[k]);
 498                                 else
 499                                         read_nic_byte(dev, 0x13e, &tmp_report[k]);
 500                                 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
 501                         }
 502
 503                         /* check if the report value is right */
 504                         for (k = 0; k < 5; k++) {
 505                                 if (tmp_report[k] <= 20) {
 506                                         viviflag = true;
 507                                         break;
 508                                 }
 509                         }
 510                         if (viviflag) {
 511                                 write_nic_byte(dev, 0x1ba, 0);
 512                                 viviflag = false;
 513                                 RT_TRACE(COMP_POWER_TRACKING, "we filtered the data\n");
 514                                 for (k = 0; k < 5; k++)
 515                                         tmp_report[k] = 0;
 516                                 break;
 517                         }
 518
 519                         for (k = 0; k < 5; k++)
 520                                 Avg_TSSI_Meas_from_driver += tmp_report[k];
 521
 522                         Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
 523                         RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
 524                         TSSI_13dBm = priv->TSSI_13dBm;
 525                         RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
 526
 527                         if (Avg_TSSI_Meas_from_driver > TSSI_13dBm)
 528                                 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
 529                         else
 530                                 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
 531
 532                         if (delta <= E_FOR_TX_POWER_TRACK) {
 533                                 priv->ieee80211->bdynamic_txpower_enable = true;
 534                                 write_nic_byte(dev, 0x1ba, 0);
 535                                 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
 536                                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
 537                                 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
 538                                 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation_difference = %d\n", priv->cck_present_attenuation_difference);
 539                                 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation = %d\n", priv->cck_present_attenuation);
 540                                 return;
 541                         }
 542                         if (Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK) {
 543                                 if (priv->rfa_txpowertrackingindex > 0) {
 544                                         priv->rfa_txpowertrackingindex--;
 545                                         if (priv->rfa_txpowertrackingindex_real > 4) {
 546                                                 priv->rfa_txpowertrackingindex_real--;
 547                                                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
 548                                         }
 549                                 }
 550                         } else {
 551                                 if (priv->rfa_txpowertrackingindex < 36) {
 552                                         priv->rfa_txpowertrackingindex++;
 553                                         priv->rfa_txpowertrackingindex_real++;
 554                                         rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
 555                                 }
 556                         }
 557                         priv->cck_present_attenuation_difference
 558                                 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
 559
 560                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 561                                 priv->cck_present_attenuation
 562                                         = priv->cck_present_attenuation_20Mdefault + priv->cck_present_attenuation_difference;
 563                         else
 564                                 priv->cck_present_attenuation
 565                                         = priv->cck_present_attenuation_40Mdefault + priv->cck_present_attenuation_difference;
 566
 567                         if (priv->cck_present_attenuation > -1 && priv->cck_present_attenuation < 23) {
 568                                 if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) {
 569                                         priv->bcck_in_ch14 = true;
 570                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 571                                 } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) {
 572                                         priv->bcck_in_ch14 = false;
 573                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 574                                 } else
 575                                         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 576                         }
 577                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
 578                         RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
 579                         RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation_difference = %d\n", priv->cck_present_attenuation_difference);
 580                         RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attenuation = %d\n", priv->cck_present_attenuation);
 581
 582                         if (priv->cck_present_attenuation_difference <= -12 || priv->cck_present_attenuation_difference >= 24) {
 583                                 priv->ieee80211->bdynamic_txpower_enable = true;
 584                                 write_nic_byte(dev, 0x1ba, 0);
 585                                 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
 586                                 return;
 587                         }
 588
 589                         write_nic_byte(dev, 0x1ba, 0);
 590                         Avg_TSSI_Meas_from_driver = 0;
 591                         for (k = 0; k < 5; k++)
 592                                 tmp_report[k] = 0;
 593                         break;
 594                 }
 595         }
 596         priv->ieee80211->bdynamic_txpower_enable = true;
 597         write_nic_byte(dev, 0x1ba, 0);
 598 }
 599
 600 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
 601 {
 602 #define ThermalMeterVal 9
 603         struct r8192_priv *priv = ieee80211_priv(dev);
 604         u32 tmpRegA, TempCCk;
 605         u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
 606         int i = 0, CCKSwingNeedUpdate = 0;
 607
 608         if (!priv->btxpower_trackingInit) {
 609                 /* Query OFDM default setting */
 610                 tmpRegA = rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
 611                 for (i = 0; i < OFDM_Table_Length; i++) { /* find the index */
 612                         if (tmpRegA == OFDMSwingTable[i]) {
 613                                 priv->OFDM_index = (u8)i;
 614                                 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
 615                                         rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
 616                         }
 617                 }
 618
 619                 /* Query CCK default setting From 0xa22 */
 620                 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
 621                 for (i = 0; i < CCK_Table_length; i++) {
 622                         if (TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0]) {
 623                                 priv->CCK_index = (u8) i;
 624                                 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
 625                                         rCCK0_TxFilter1, TempCCk, priv->CCK_index);
 626                                 break;
 627                         }
 628                 }
 629                 priv->btxpower_trackingInit = true;
 630                 return;
 631         }
 632
 633         /* ==========================
 634          * this is only for test, should be masked
 635          * ==========================
 636          */
 637
 638         /* read and filter out unreasonable value */
 639         tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078);        /* 0x12: RF Reg[10:7] */
 640         RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d\n", tmpRegA);
 641         if (tmpRegA < 3 || tmpRegA > 13)
 642                 return;
 643         if (tmpRegA >= 12)      /* if over 12, TP will be bad when high temperature */
 644                 tmpRegA = 12;
 645         RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d\n", tmpRegA);
 646         priv->ThermalMeter[0] = ThermalMeterVal;        /* We use fixed value by Bryant's suggestion */
 647         priv->ThermalMeter[1] = ThermalMeterVal;        /* We use fixed value by Bryant's suggestion */
 648
 649         /* Get current RF-A temperature index */
 650         if (priv->ThermalMeter[0] >= (u8)tmpRegA) {     /* lower temperature */
 651                 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
 652                 tmpCCK40Mindex = tmpCCK20Mindex - 6;
 653                 if (tmpOFDMindex >= OFDM_Table_Length)
 654                         tmpOFDMindex = OFDM_Table_Length-1;
 655                 if (tmpCCK20Mindex >= CCK_Table_length)
 656                         tmpCCK20Mindex = CCK_Table_length-1;
 657                 if (tmpCCK40Mindex >= CCK_Table_length)
 658                         tmpCCK40Mindex = CCK_Table_length-1;
 659         } else {
 660                 tmpval = (u8)tmpRegA - priv->ThermalMeter[0];
 661
 662                 if (tmpval >= 6) {
 663                         /* higher temperature */
 664                         tmpOFDMindex = 0;
 665                         tmpCCK20Mindex = 0;
 666                 } else {
 667                         /* max to +6dB */
 668                         tmpOFDMindex = 6 - tmpval;
 669                         tmpCCK20Mindex = 6 - tmpval;
 670                 }
 671                 tmpCCK40Mindex = 0;
 672         }
 673         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)      /* 40M */
 674                 tmpCCKindex = tmpCCK40Mindex;
 675         else
 676                 tmpCCKindex = tmpCCK20Mindex;
 677
 678         if (priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14) {
 679                 priv->bcck_in_ch14 = true;
 680                 CCKSwingNeedUpdate = 1;
 681         } else if (priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14) {
 682                 priv->bcck_in_ch14 = false;
 683                 CCKSwingNeedUpdate = 1;
 684         }
 685
 686         if (priv->CCK_index != tmpCCKindex) {
 687                 priv->CCK_index = tmpCCKindex;
 688                 CCKSwingNeedUpdate = 1;
 689         }
 690
 691         if (CCKSwingNeedUpdate) {
 692                 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
 693         }
 694         if (priv->OFDM_index != tmpOFDMindex) {
 695                 priv->OFDM_index = tmpOFDMindex;
 696                 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
 697                 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
 698                         priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
 699         }
 700         priv->txpower_count = 0;
 701 }
 702
 703 void dm_txpower_trackingcallback(struct work_struct *work)
 704 {
 705         struct delayed_work *dwork = to_delayed_work(work);
 706         struct r8192_priv *priv = container_of(dwork, struct r8192_priv, txpower_tracking_wq);
 707         struct net_device *dev = priv->ieee80211->dev;
 708
 709         if (priv->bDcut)
 710                 dm_TXPowerTrackingCallback_TSSI(dev);
 711         else
 712                 dm_TXPowerTrackingCallback_ThermalMeter(dev);
 713 }
 714
 715 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
 716 {
 717         struct r8192_priv *priv = ieee80211_priv(dev);
 718
 719         /* Initial the Tx BB index and mapping value */
 720         priv->txbbgain_table[0].txbb_iq_amplifygain =                   12;
 721         priv->txbbgain_table[0].txbbgain_value = 0x7f8001fe;
 722         priv->txbbgain_table[1].txbb_iq_amplifygain =                   11;
 723         priv->txbbgain_table[1].txbbgain_value = 0x788001e2;
 724         priv->txbbgain_table[2].txbb_iq_amplifygain =                   10;
 725         priv->txbbgain_table[2].txbbgain_value = 0x71c001c7;
 726         priv->txbbgain_table[3].txbb_iq_amplifygain =                   9;
 727         priv->txbbgain_table[3].txbbgain_value = 0x6b8001ae;
 728         priv->txbbgain_table[4].txbb_iq_amplifygain =                  8;
 729         priv->txbbgain_table[4].txbbgain_value = 0x65400195;
 730         priv->txbbgain_table[5].txbb_iq_amplifygain =                  7;
 731         priv->txbbgain_table[5].txbbgain_value = 0x5fc0017f;
 732         priv->txbbgain_table[6].txbb_iq_amplifygain =                  6;
 733         priv->txbbgain_table[6].txbbgain_value = 0x5a400169;
 734         priv->txbbgain_table[7].txbb_iq_amplifygain =                  5;
 735         priv->txbbgain_table[7].txbbgain_value = 0x55400155;
 736         priv->txbbgain_table[8].txbb_iq_amplifygain =                  4;
 737         priv->txbbgain_table[8].txbbgain_value = 0x50800142;
 738         priv->txbbgain_table[9].txbb_iq_amplifygain =                  3;
 739         priv->txbbgain_table[9].txbbgain_value = 0x4c000130;
 740         priv->txbbgain_table[10].txbb_iq_amplifygain =                 2;
 741         priv->txbbgain_table[10].txbbgain_value = 0x47c0011f;
 742         priv->txbbgain_table[11].txbb_iq_amplifygain =                 1;
 743         priv->txbbgain_table[11].txbbgain_value = 0x43c0010f;
 744         priv->txbbgain_table[12].txbb_iq_amplifygain =                 0;
 745         priv->txbbgain_table[12].txbbgain_value = 0x40000100;
 746         priv->txbbgain_table[13].txbb_iq_amplifygain =                 -1;
 747         priv->txbbgain_table[13].txbbgain_value = 0x3c8000f2;
 748         priv->txbbgain_table[14].txbb_iq_amplifygain =               -2;
 749         priv->txbbgain_table[14].txbbgain_value = 0x390000e4;
 750         priv->txbbgain_table[15].txbb_iq_amplifygain =               -3;
 751         priv->txbbgain_table[15].txbbgain_value = 0x35c000d7;
 752         priv->txbbgain_table[16].txbb_iq_amplifygain =               -4;
 753         priv->txbbgain_table[16].txbbgain_value = 0x32c000cb;
 754         priv->txbbgain_table[17].txbb_iq_amplifygain =               -5;
 755         priv->txbbgain_table[17].txbbgain_value = 0x300000c0;
 756         priv->txbbgain_table[18].txbb_iq_amplifygain =                      -6;
 757         priv->txbbgain_table[18].txbbgain_value = 0x2d4000b5;
 758         priv->txbbgain_table[19].txbb_iq_amplifygain =               -7;
 759         priv->txbbgain_table[19].txbbgain_value = 0x2ac000ab;
 760         priv->txbbgain_table[20].txbb_iq_amplifygain =               -8;
 761         priv->txbbgain_table[20].txbbgain_value = 0x288000a2;
 762         priv->txbbgain_table[21].txbb_iq_amplifygain =               -9;
 763         priv->txbbgain_table[21].txbbgain_value = 0x26000098;
 764         priv->txbbgain_table[22].txbb_iq_amplifygain =               -10;
 765         priv->txbbgain_table[22].txbbgain_value = 0x24000090;
 766         priv->txbbgain_table[23].txbb_iq_amplifygain =               -11;
 767         priv->txbbgain_table[23].txbbgain_value = 0x22000088;
 768         priv->txbbgain_table[24].txbb_iq_amplifygain =               -12;
 769         priv->txbbgain_table[24].txbbgain_value = 0x20000080;
 770         priv->txbbgain_table[25].txbb_iq_amplifygain =               -13;
 771         priv->txbbgain_table[25].txbbgain_value = 0x1a00006c;
 772         priv->txbbgain_table[26].txbb_iq_amplifygain =               -14;
 773         priv->txbbgain_table[26].txbbgain_value = 0x1c800072;
 774         priv->txbbgain_table[27].txbb_iq_amplifygain =               -15;
 775         priv->txbbgain_table[27].txbbgain_value = 0x18000060;
 776         priv->txbbgain_table[28].txbb_iq_amplifygain =               -16;
 777         priv->txbbgain_table[28].txbbgain_value = 0x19800066;
 778         priv->txbbgain_table[29].txbb_iq_amplifygain =               -17;
 779         priv->txbbgain_table[29].txbbgain_value = 0x15800056;
 780         priv->txbbgain_table[30].txbb_iq_amplifygain =               -18;
 781         priv->txbbgain_table[30].txbbgain_value = 0x26c0005b;
 782         priv->txbbgain_table[31].txbb_iq_amplifygain =               -19;
 783         priv->txbbgain_table[31].txbbgain_value = 0x14400051;
 784         priv->txbbgain_table[32].txbb_iq_amplifygain =               -20;
 785         priv->txbbgain_table[32].txbbgain_value = 0x24400051;
 786         priv->txbbgain_table[33].txbb_iq_amplifygain =               -21;
 787         priv->txbbgain_table[33].txbbgain_value = 0x1300004c;
 788         priv->txbbgain_table[34].txbb_iq_amplifygain =               -22;
 789         priv->txbbgain_table[34].txbbgain_value = 0x12000048;
 790         priv->txbbgain_table[35].txbb_iq_amplifygain =               -23;
 791         priv->txbbgain_table[35].txbbgain_value = 0x11000044;
 792         priv->txbbgain_table[36].txbb_iq_amplifygain =               -24;
 793         priv->txbbgain_table[36].txbbgain_value = 0x10000040;
 794
 795         /* ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
 796          * This Table is for CH1~CH13
 797          */
 798         priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
 799         priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
 800         priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
 801         priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
 802         priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
 803         priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
 804         priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
 805         priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
 806
 807         priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
 808         priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
 809         priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
 810         priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
 811         priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
 812         priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
 813         priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
 814         priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
 815
 816         priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
 817         priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
 818         priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
 819         priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
 820         priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
 821         priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
 822         priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
 823         priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
 824
 825         priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
 826         priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
 827         priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
 828         priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
 829         priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
 830         priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
 831         priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
 832         priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
 833
 834         priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
 835         priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
 836         priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
 837         priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
 838         priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
 839         priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
 840         priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
 841         priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
 842
 843         priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
 844         priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
 845         priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
 846         priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
 847         priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
 848         priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
 849         priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
 850         priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
 851
 852         priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
 853         priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
 854         priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
 855         priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
 856         priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
 857         priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
 858         priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
 859         priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
 860
 861         priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
 862         priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
 863         priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
 864         priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
 865         priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
 866         priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
 867         priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
 868         priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
 869
 870         priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
 871         priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
 872         priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
 873         priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
 874         priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
 875         priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
 876         priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
 877         priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
 878
 879         priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
 880         priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
 881         priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
 882         priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
 883         priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
 884         priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
 885         priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
 886         priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
 887
 888         priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
 889         priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
 890         priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
 891         priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
 892         priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
 893         priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
 894         priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
 895         priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
 896
 897         priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
 898         priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
 899         priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
 900         priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
 901         priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
 902         priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
 903         priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
 904         priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
 905
 906         priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
 907         priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
 908         priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
 909         priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
 910         priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
 911         priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
 912         priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
 913         priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
 914
 915         priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
 916         priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
 917         priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
 918         priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
 919         priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
 920         priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
 921         priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
 922         priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
 923
 924         priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
 925         priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
 926         priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
 927         priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
 928         priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
 929         priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
 930         priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
 931         priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
 932
 933         priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
 934         priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
 935         priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
 936         priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
 937         priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
 938         priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
 939         priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
 940         priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
 941
 942         priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
 943         priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
 944         priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
 945         priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
 946         priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
 947         priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
 948         priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
 949         priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
 950
 951         priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
 952         priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
 953         priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
 954         priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
 955         priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
 956         priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
 957         priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
 958         priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
 959
 960         priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
 961         priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
 962         priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
 963         priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
 964         priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
 965         priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
 966         priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
 967         priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
 968
 969         priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
 970         priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
 971         priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
 972         priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
 973         priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
 974         priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
 975         priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
 976         priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
 977
 978         priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
 979         priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
 980         priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
 981         priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
 982         priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
 983         priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
 984         priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
 985         priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
 986
 987         priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
 988         priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
 989         priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
 990         priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
 991         priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
 992         priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
 993         priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
 994         priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
 995
 996         priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
 997         priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
 998         priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
 999         priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1000         priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1001         priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1002         priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1003         priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1004
1005         /* ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1006          * This Table is for CH14
1007          */
1008         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1009         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1010         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1011         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1012         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1013         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1014         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1015         priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1016
1017         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1018         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1019         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1020         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1021         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1022         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1023         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1024         priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1025
1026         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1027         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1028         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1029         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1030         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1031         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1032         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1033         priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1034
1035         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1036         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1037         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1038         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1039         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1040         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1041         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1042         priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1043
1044         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1045         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1046         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1047         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1048         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1049         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1050         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1051         priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1052
1053         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1054         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1055         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1056         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1057         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1058         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1059         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1060         priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1061
1062         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1063         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1064         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1065         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1066         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1067         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1068         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1069         priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1070
1071         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1072         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1073         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1074         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1075         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1076         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1077         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1078         priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1079
1080         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1081         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1082         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1083         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1084         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1085         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1086         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1087         priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1088
1089         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1090         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1091         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1092         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1093         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1094         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1095         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1096         priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1097
1098         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1099         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1100         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1101         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1102         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1103         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1104         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1105         priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1106
1107         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1108         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1109         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1110         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1111         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1112         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1113         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1114         priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1115
1116         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1117         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1118         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1119         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1120         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1121         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1122         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1123         priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1124
1125         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1126         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1127         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1128         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1129         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1130         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1131         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1132         priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1133
1134         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1135         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1136         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1137         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1138         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1139         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1140         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1141         priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1142
1143         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1144         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1145         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1146         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1147         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1148         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1149         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1150         priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1151
1152         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1153         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1154         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1155         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1156         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1157         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1158         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1159         priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1160
1161         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1162         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1163         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1164         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1165         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1166         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1167         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1168         priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1169
1170         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1171         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1172         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1173         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1174         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1175         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1176         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1177         priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1178
1179         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1180         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1181         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1182         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1183         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1184         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1185         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1186         priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1187
1188         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1189         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1190         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1191         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1192         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1193         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1194         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1195         priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1196
1197         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1198         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1199         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1200         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1201         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1202         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1203         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1204         priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1205
1206         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1207         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1208         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1209         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1210         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1211         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1212         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1213         priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1214
1215         priv->btxpower_tracking = true;
1216         priv->txpower_count       = 0;
1217         priv->btxpower_trackingInit = false;
1218 }
1219
1220 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1221 {
1222         struct r8192_priv *priv = ieee80211_priv(dev);
1223
1224         /* Tx Power tracking by Thermal Meter requires Firmware R/W 3-wire. This mechanism
1225          * can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1226          * 3-wire by driver causes RF to go into a wrong state.
1227          */
1228         if (priv->ieee80211->FwRWRF)
1229                 priv->btxpower_tracking = true;
1230         else
1231                 priv->btxpower_tracking = false;
1232         priv->txpower_count       = 0;
1233         priv->btxpower_trackingInit = false;
1234 }
1235
1236 void dm_initialize_txpower_tracking(struct net_device *dev)
1237 {
1238         struct r8192_priv *priv = ieee80211_priv(dev);
1239
1240         if (priv->bDcut)
1241                 dm_InitializeTXPowerTracking_TSSI(dev);
1242         else
1243                 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1244 } /* dm_InitializeTXPowerTracking */
1245
1246 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1247 {
1248         struct r8192_priv *priv = ieee80211_priv(dev);
1249         static u32 tx_power_track_counter;
1250
1251         if (!priv->btxpower_tracking)
1252                 return;
1253         if ((tx_power_track_counter % 30 == 0) && (tx_power_track_counter != 0))
1254                 queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
1255         tx_power_track_counter++;
1256 }
1257
1258 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1259 {
1260         struct r8192_priv *priv = ieee80211_priv(dev);
1261         static u8       TM_Trigger;
1262         if (!priv->btxpower_tracking)
1263                 return;
1264         if (priv->txpower_count  <= 2) {
1265                 priv->txpower_count++;
1266                 return;
1267         }
1268
1269         if (!TM_Trigger) {
1270                 /* Attention!! You have to write all 12bits of data to RF, or it may cause RF to crash
1271                  * actually write reg0x02 bit1=0, then bit1=1.
1272                  * DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1273                  */
1274                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1275                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1276                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1277                 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1278                 TM_Trigger = 1;
1279                 return;
1280         }
1281         queue_delayed_work(priv->priv_wq, &priv->txpower_tracking_wq, 0);
1282         TM_Trigger = 0;
1283 }
1284
1285 static void dm_check_txpower_tracking(struct net_device *dev)
1286 {
1287         struct r8192_priv *priv = ieee80211_priv(dev);
1288
1289 #ifdef RTL8190P
1290         dm_CheckTXPowerTracking_TSSI(dev);
1291 #else
1292         if (priv->bDcut)
1293                 dm_CheckTXPowerTracking_TSSI(dev);
1294         else
1295                 dm_CheckTXPowerTracking_ThermalMeter(dev);
1296 #endif
1297
1298 }       /* dm_CheckTXPowerTracking */
1299
1300 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool  bInCH14)
1301 {
1302         u32 TempVal;
1303         struct r8192_priv *priv = ieee80211_priv(dev);
1304
1305         /* Write 0xa22 0xa23 */
1306         TempVal = 0;
1307         if (!bInCH14) {
1308                 /* Write 0xa22 0xa23 */
1309                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[0] +
1310                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[1]<<8);
1311
1312                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1313                 /* Write 0xa24 ~ 0xa27 */
1314                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[2] +
1315                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[3]<<8) +
1316                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[4]<<16)+
1317                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[5]<<24);
1318                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1319                 /* Write 0xa28  0xa29 */
1320                 TempVal =       priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[6] +
1321                                         (priv->cck_txbbgain_table[priv->cck_present_attenuation].ccktxbb_valuearray[7]<<8);
1322
1323                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1324         } else {
1325                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[0] +
1326                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[1]<<8);
1327
1328                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1329                 /* Write 0xa24 ~ 0xa27 */
1330                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[2] +
1331                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[3]<<8) +
1332                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[4]<<16)+
1333                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[5]<<24);
1334                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1335                 /* Write 0xa28  0xa29 */
1336                 TempVal =       priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[6] +
1337                                         (priv->cck_txbbgain_ch14_table[priv->cck_present_attenuation].ccktxbb_valuearray[7]<<8);
1338
1339                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1340         }
1341 }
1342
1343 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool  bInCH14)
1344 {
1345         u32 TempVal;
1346         struct r8192_priv *priv = ieee80211_priv(dev);
1347
1348         TempVal = 0;
1349         if (!bInCH14) {
1350                 /* Write 0xa22 0xa23 */
1351                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1352                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8);
1353                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1354                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1355                         rCCK0_TxFilter1, TempVal);
1356                 /* Write 0xa24 ~ 0xa27 */
1357                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1358                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1359                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16)+
1360                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1361                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1362                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1363                         rCCK0_TxFilter2, TempVal);
1364                 /* Write 0xa28  0xa29 */
1365                 TempVal =       CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1366                                         (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8);
1367
1368                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1369                 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1370                         rCCK0_DebugPort, TempVal);
1371         } else {
1372                 /* Write 0xa22 0xa23 */
1373                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][0] +
1374                                         (CCKSwingTable_Ch14[priv->CCK_index][1]<<8);
1375
1376                 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1377                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1378                          rCCK0_TxFilter1, TempVal);
1379                 /* Write 0xa24 ~ 0xa27 */
1380                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][2] +
1381                                         (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1382                                         (CCKSwingTable_Ch14[priv->CCK_index][4]<<16)+
1383                                         (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1384                 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1385                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1386                          rCCK0_TxFilter2, TempVal);
1387                 /* Write 0xa28  0xa29 */
1388                 TempVal =       CCKSwingTable_Ch14[priv->CCK_index][6] +
1389                                         (CCKSwingTable_Ch14[priv->CCK_index][7]<<8);
1390
1391                 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1392                 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1393                          rCCK0_DebugPort, TempVal);
1394         }
1395 }
1396
1397 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1398 {       /*  dm_CCKTxPowerAdjust */
1399         struct r8192_priv *priv = ieee80211_priv(dev);
1400
1401         if (priv->bDcut)
1402                 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1403         else
1404                 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1405 }
1406
1407 #ifndef RTL8192U
1408 static void dm_txpower_reset_recovery(
1409         struct net_device *dev
1410 )
1411 {
1412         struct r8192_priv *priv = ieee80211_priv(dev);
1413
1414         RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1415         rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1416         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1417         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n", priv->rfa_txpowertrackingindex);
1418         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1419         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n", priv->cck_present_attenuation);
1420         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1421
1422         rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1423         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1424         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n", priv->rfc_txpowertrackingindex);
1425         RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n", priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1426
1427 }       /* dm_TXPowerResetRecovery */
1428
1429 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1430 {
1431         struct r8192_priv *priv = ieee80211_priv(dev);
1432         u32     reg_ratr = priv->rate_adaptive.last_ratr;
1433
1434         if (!priv->up) {
1435                 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1436                 return;
1437         }
1438
1439         /* Restore previous state for rate adaptive */
1440         if (priv->rate_adaptive.rate_adaptive_disabled)
1441                 return;
1442         /* TODO: Only 11n mode is implemented currently, */
1443         if (!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
1444               priv->ieee80211->mode == WIRELESS_MODE_N_5G))
1445                 return;
1446
1447         {
1448                         /* 2007/11/15 MH Copy from 8190PCI. */
1449                         u32 ratr_value;
1450
1451                         ratr_value = reg_ratr;
1452                         if (priv->rf_type == RF_1T2R) { /* 1T2R, Spatial Stream 2 should be disabled */
1453                                 ratr_value &= ~(RATE_ALL_OFDM_2SS);
1454                         }
1455                         write_nic_dword(dev, RATR0, ratr_value);
1456                         write_nic_byte(dev, UFWP, 1);
1457         }
1458         /* Restore TX Power Tracking Index */
1459         if (priv->btxpower_trackingInit && priv->btxpower_tracking)
1460                 dm_txpower_reset_recovery(dev);
1461
1462         /* Restore BB Initial Gain */
1463         dm_bb_initialgain_restore(dev);
1464
1465 }       /* DM_RestoreDynamicMechanismState */
1466
1467 static void dm_bb_initialgain_restore(struct net_device *dev)
1468 {
1469         struct r8192_priv *priv = ieee80211_priv(dev);
1470         u32 bit_mask = 0x7f; /* Bit0~ Bit6 */
1471
1472         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1473                 return;
1474
1475         /* Disable Initial Gain */
1476         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1477         rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1478         rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1479         rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1480         rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1481         bit_mask  = bMaskByte2;
1482         rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1483
1484         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n", priv->initgain_backup.xaagccore1);
1485         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n", priv->initgain_backup.xbagccore1);
1486         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n", priv->initgain_backup.xcagccore1);
1487         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
1488         RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n", priv->initgain_backup.cca);
1489         /* Enable Initial Gain */
1490         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /* Only clear byte 1 and rewrite. */
1491
1492 }       /* dm_BBInitialGainRestore */
1493
1494 static void dm_bb_initialgain_backup(struct net_device *dev)
1495 {
1496         struct r8192_priv *priv = ieee80211_priv(dev);
1497         u32 bit_mask = bMaskByte0; /* Bit0~ Bit6 */
1498
1499         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1500                 return;
1501
1502         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1503         priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1504         priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1505         priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1506         priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1507         bit_mask  = bMaskByte2;
1508         priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1509
1510         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n", priv->initgain_backup.xaagccore1);
1511         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n", priv->initgain_backup.xbagccore1);
1512         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n", priv->initgain_backup.xcagccore1);
1513         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n", priv->initgain_backup.xdagccore1);
1514         RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n", priv->initgain_backup.cca);
1515
1516 }   /* dm_BBInitialGainBakcup */
1517
1518 #endif
1519 /*-----------------------------------------------------------------------------
1520  * Function:    dm_dig_init()
1521  *
1522  * Overview:    Set DIG scheme init value.
1523  *
1524  * Input:               NONE
1525  *
1526  * Output:              NONE
1527  *
1528  * Return:              NONE
1529  *---------------------------------------------------------------------------
1530  */
1531 static void dm_dig_init(struct net_device *dev)
1532 {
1533         struct r8192_priv *priv = ieee80211_priv(dev);
1534         /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
1535         dm_digtable.dig_enable_flag     = true;
1536         dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
1537         dm_digtable.dig_algorithm_switch = 0;
1538
1539         /* 2007/10/04 MH Define init gain threshold. */
1540         dm_digtable.dig_state           = DM_STA_DIG_MAX;
1541         dm_digtable.dig_highpwr_state   = DM_STA_DIG_MAX;
1542
1543         dm_digtable.rssi_low_thresh     = DM_DIG_THRESH_LOW;
1544         dm_digtable.rssi_high_thresh    = DM_DIG_THRESH_HIGH;
1545
1546         dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
1547         dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
1548
1549         dm_digtable.rssi_val = 50;      /* for new dig debug rssi value */
1550         dm_digtable.backoff_val = DM_DIG_BACKOFF;
1551         if (priv->CustomerID == RT_CID_819x_Netcore)
1552                 dm_digtable.rx_gain_range_min = DM_DIG_MIN_NETCORE;
1553         else
1554                 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
1555
1556 }       /* dm_dig_init */
1557
1558 /*-----------------------------------------------------------------------------
1559  * Function:    dm_ctrl_initgain_byrssi()
1560  *
1561  * Overview:    Driver must monitor RSSI and notify firmware to change initial
1562  *                              gain according to different threshold. BB team provide the
1563  *                              suggested solution.
1564  *
1565  * Input:                       struct net_device *dev
1566  *
1567  * Output:              NONE
1568  *
1569  * Return:              NONE
1570  *---------------------------------------------------------------------------
1571  */
1572 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
1573 {
1574         if (!dm_digtable.dig_enable_flag)
1575                 return;
1576
1577         if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1578                 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
1579         else if (dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1580                 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
1581         /* ; */
1582         else
1583                 return;
1584 }
1585
1586 static void dm_ctrl_initgain_byrssi_by_driverrssi(
1587         struct net_device *dev)
1588 {
1589         struct r8192_priv *priv = ieee80211_priv(dev);
1590         u8 i;
1591         static u8       fw_dig;
1592
1593         if (!dm_digtable.dig_enable_flag)
1594                 return;
1595
1596         if (dm_digtable.dig_algorithm_switch)   /* if switched algorithm, we have to disable FW Dig. */
1597                 fw_dig = 0;
1598
1599         if (fw_dig <= 3) { /* execute several times to make sure the FW Dig is disabled */
1600                 /* FW DIG Off */
1601                 for (i = 0; i < 3; i++)
1602                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /* Only clear byte 1 and rewrite. */
1603                 fw_dig++;
1604                 dm_digtable.dig_state = DM_STA_DIG_OFF; /* fw dig off. */
1605         }
1606
1607         if (priv->ieee80211->state == IEEE80211_LINKED)
1608                 dm_digtable.cur_connect_state = DIG_CONNECT;
1609         else
1610                 dm_digtable.cur_connect_state = DIG_DISCONNECT;
1611
1612         dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
1613         dm_initial_gain(dev);
1614         dm_pd_th(dev);
1615         dm_cs_ratio(dev);
1616         if (dm_digtable.dig_algorithm_switch)
1617                 dm_digtable.dig_algorithm_switch = 0;
1618         dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
1619
1620 }       /* dm_CtrlInitGainByRssi */
1621
1622 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1623         struct net_device *dev)
1624 {
1625         struct r8192_priv *priv = ieee80211_priv(dev);
1626         static u32 reset_cnt;
1627         u8 i;
1628
1629         if (!dm_digtable.dig_enable_flag)
1630                 return;
1631
1632         if (dm_digtable.dig_algorithm_switch) {
1633                 dm_digtable.dig_state = DM_STA_DIG_MAX;
1634                 /* Fw DIG On. */
1635                 for (i = 0; i < 3; i++)
1636                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /* Only clear byte 1 and rewrite.*/
1637                 dm_digtable.dig_algorithm_switch = 0;
1638         }
1639
1640         if (priv->ieee80211->state != IEEE80211_LINKED)
1641                 return;
1642
1643         /* For smooth, we can not change DIG state. */
1644         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
1645             (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
1646                 return;
1647
1648         /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
1649          * and then execute the step below.
1650          */
1651         if (priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh) {
1652                 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
1653                  * will be reset to init value. We must prevent the condition.
1654                  */
1655                 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
1656                     (priv->reset_count == reset_cnt)) {
1657                         return;
1658                 }
1659                 reset_cnt = priv->reset_count;
1660
1661                 /* If DIG is off, DIG high power state must reset. */
1662                 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1663                 dm_digtable.dig_state = DM_STA_DIG_OFF;
1664
1665                 /*  1.1 DIG Off. */
1666                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   /*  Only clear byte 1 and rewrite. */
1667
1668                 /*  1.2 Set initial gain. */
1669                 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
1670                 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
1671                 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
1672                 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
1673
1674                 /*  1.3 Lower PD_TH for OFDM. */
1675                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1676                         /* 2008/01/11 MH 40MHZ 90/92 register are not the same.
1677                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1678                          */
1679                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1680                 } else
1681                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1682
1683                 /* 1.4 Lower CS ratio for CCK. */
1684                 write_nic_byte(dev, 0xa0a, 0x08);
1685
1686                 /* 1.5 Higher EDCCA. */
1687                 return;
1688         }
1689
1690         /* 2. When RSSI increase, We have to judge if it is larger than a threshold
1691          * and then execute the step below.
1692          */
1693         if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1694                 u8 reset_flag = 0;
1695
1696                 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
1697                     (priv->reset_count == reset_cnt)) {
1698                         dm_ctrl_initgain_byrssi_highpwr(dev);
1699                         return;
1700                 }
1701                 if (priv->reset_count != reset_cnt)
1702                         reset_flag = 1;
1703
1704                 reset_cnt = priv->reset_count;
1705
1706                 dm_digtable.dig_state = DM_STA_DIG_ON;
1707
1708                 /* 2.1 Set initial gain.
1709                  * 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
1710                  */
1711                 if (reset_flag == 1) {
1712                         write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
1713                         write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
1714                         write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
1715                         write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
1716                 } else {
1717                         write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
1718                         write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
1719                         write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
1720                         write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
1721                 }
1722
1723                 /* 2.2 Higher PD_TH for OFDM. */
1724                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1725                         /* 2008/01/11 MH 40MHZ 90/92 register are not the same.
1726                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1727                          */
1728                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1729                 } else
1730                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1731
1732                 /* 2.3 Higher CS ratio for CCK. */
1733                 write_nic_byte(dev, 0xa0a, 0xcd);
1734
1735                 /* 2.4 Lower EDCCA.
1736                  * 2008/01/11 MH 90/92 series are the same.
1737                  */
1738
1739                 /* 2.5 DIG On. */
1740                 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   /*  Only clear byte 1 and rewrite. */
1741         }
1742
1743         dm_ctrl_initgain_byrssi_highpwr(dev);
1744
1745 }       /* dm_CtrlInitGainByRssi */
1746
1747 /*-----------------------------------------------------------------------------
1748  * Function:    dm_ctrl_initgain_byrssi_highpwr()
1749  *
1750  * Overview:
1751  *
1752  * Input:               NONE
1753  *
1754  * Output:              NONE
1755  *
1756  * Return:              NONE
1757  *---------------------------------------------------------------------------
1758  */
1759 static void dm_ctrl_initgain_byrssi_highpwr(
1760         struct net_device *dev)
1761 {
1762         struct r8192_priv *priv = ieee80211_priv(dev);
1763         static u32 reset_cnt_highpwr;
1764
1765         /*  For smooth, we can not change high power DIG state in the range. */
1766         if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
1767                 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
1768                 return;
1769
1770         /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
1771          *    it is larger than a threshold and then execute the step below.
1772          *
1773          * 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
1774          */
1775         if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh) {
1776                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
1777                     (priv->reset_count == reset_cnt_highpwr))
1778                         return;
1779                 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
1780
1781                 /* 3.1 Higher PD_TH for OFDM for high power state. */
1782                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1783                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
1784                 } else
1785                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
1786         } else {
1787                 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF &&
1788                     (priv->reset_count == reset_cnt_highpwr))
1789                         return;
1790                 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
1791
1792                 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
1793                          priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) {
1794                         /*  3.2 Recover PD_TH for OFDM for normal power region. */
1795                         if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1796                                 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1797                         } else
1798                                 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1799                 }
1800         }
1801
1802         reset_cnt_highpwr = priv->reset_count;
1803
1804 }       /* dm_CtrlInitGainByRssiHighPwr */
1805
1806 static void dm_initial_gain(
1807         struct net_device *dev)
1808 {
1809         struct r8192_priv *priv = ieee80211_priv(dev);
1810         u8                                      initial_gain = 0;
1811         static u8                               initialized, force_write;
1812         static u32                      reset_cnt;
1813         u8                              tmp;
1814
1815         if (dm_digtable.dig_algorithm_switch) {
1816                 initialized = 0;
1817                 reset_cnt = 0;
1818         }
1819
1820         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
1821                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
1822                         if ((dm_digtable.rssi_val + 10 - dm_digtable.backoff_val) > DM_DIG_MAX)
1823                                 dm_digtable.cur_ig_value = DM_DIG_MAX;
1824                         else if ((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
1825                                 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
1826                         else
1827                                 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
1828                 } else {        /* current state is disconnected */
1829                         if (dm_digtable.cur_ig_value == 0)
1830                                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1831                         else
1832                                 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
1833                 }
1834         } else { /*  disconnected -> connected or connected -> disconnected */
1835                 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1836                 dm_digtable.pre_ig_value = 0;
1837         }
1838
1839         /* if silent reset happened, we should rewrite the values back */
1840         if (priv->reset_count != reset_cnt) {
1841                 force_write = 1;
1842                 reset_cnt = priv->reset_count;
1843         }
1844
1845         read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp);
1846         if (dm_digtable.pre_ig_value != tmp)
1847                 force_write = 1;
1848
1849         {
1850                 if ((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
1851                         || !initialized || force_write) {
1852                         initial_gain = (u8)dm_digtable.cur_ig_value;
1853                         /*  Set initial gain. */
1854                         write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1855                         write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1856                         write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1857                         write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1858                         dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
1859                         initialized = 1;
1860                         force_write = 0;
1861                 }
1862         }
1863 }
1864
1865 static void dm_pd_th(
1866         struct net_device *dev)
1867 {
1868         struct r8192_priv *priv = ieee80211_priv(dev);
1869         static u8                               initialized, force_write;
1870         static u32                      reset_cnt;
1871
1872         if (dm_digtable.dig_algorithm_switch) {
1873                 initialized = 0;
1874                 reset_cnt = 0;
1875         }
1876
1877         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
1878                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
1879                         if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
1880                                 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
1881                         else if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
1882                                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1883                         else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
1884                                         (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
1885                                 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
1886                         else
1887                                 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
1888                 } else {
1889                         dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1890                 }
1891         } else { /* disconnected -> connected or connected -> disconnected */
1892                 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1893         }
1894
1895         /*  if silent reset happened, we should rewrite the values back */
1896         if (priv->reset_count != reset_cnt) {
1897                 force_write = 1;
1898                 reset_cnt = priv->reset_count;
1899         }
1900
1901         {
1902                 if ((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
1903                     (initialized <= 3) || force_write) {
1904                         if (dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER) {
1905                                 /*  Lower PD_TH for OFDM. */
1906                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1907                                         /* 2008/01/11 MH 40MHZ 90/92 register are not the same.
1908                                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1909                                          */
1910                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1911                                 } else
1912                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1913                         } else if (dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER) {
1914                                 /* Higher PD_TH for OFDM. */
1915                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1916                                         /* 2008/01/11 MH 40MHZ 90/92 register are not the same.
1917                                          * 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1918                                          */
1919                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1920                                 } else
1921                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1922                         } else if (dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER) {
1923                                 /* Higher PD_TH for OFDM for high power state. */
1924                                 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) {
1925                                         write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
1926                                 } else
1927                                         write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
1928                         }
1929                         dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
1930                         if (initialized <= 3)
1931                                 initialized++;
1932                         force_write = 0;
1933                 }
1934         }
1935 }
1936
1937 static  void dm_cs_ratio(
1938         struct net_device *dev)
1939 {
1940         struct r8192_priv *priv = ieee80211_priv(dev);
1941         static u8                               initialized, force_write;
1942         static u32                      reset_cnt;
1943
1944         if (dm_digtable.dig_algorithm_switch) {
1945                 initialized = 0;
1946                 reset_cnt = 0;
1947         }
1948
1949         if (dm_digtable.pre_connect_state == dm_digtable.cur_connect_state) {
1950                 if (dm_digtable.cur_connect_state == DIG_CONNECT) {
1951                         if (dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh)
1952                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
1953                         else if (dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh)
1954                                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
1955                         else
1956                                 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
1957                 } else {
1958                         dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
1959                 }
1960         } else  /* disconnected -> connected or connected -> disconnected */
1961                 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
1962
1963         /* if silent reset happened, we should rewrite the values back */
1964         if (priv->reset_count != reset_cnt) {
1965                 force_write = 1;
1966                 reset_cnt = priv->reset_count;
1967         }
1968
1969         {
1970                 if ((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
1971                     !initialized || force_write) {
1972                         if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER) {
1973                                 /*  Lower CS ratio for CCK. */
1974                                 write_nic_byte(dev, 0xa0a, 0x08);
1975                         } else if (dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER) {
1976                                 /*  Higher CS ratio for CCK. */
1977                                 write_nic_byte(dev, 0xa0a, 0xcd);
1978                         }
1979                         dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
1980                         initialized = 1;
1981                         force_write = 0;
1982                 }
1983         }
1984 }
1985
1986 void dm_init_edca_turbo(struct net_device *dev)
1987 {
1988         struct r8192_priv *priv = ieee80211_priv(dev);
1989
1990         priv->bcurrent_turbo_EDCA = false;
1991         priv->ieee80211->bis_any_nonbepkts = false;
1992         priv->bis_cur_rdlstate = false;
1993 }       /* dm_init_edca_turbo */
1994
1995 static void dm_check_edca_turbo(
1996         struct net_device *dev)
1997 {
1998         struct r8192_priv *priv = ieee80211_priv(dev);
1999         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
2000
2001         /* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */
2002         static unsigned long                    lastTxOkCnt;
2003         static unsigned long                    lastRxOkCnt;
2004         unsigned long                           curTxOkCnt = 0;
2005         unsigned long                           curRxOkCnt = 0;
2006
2007         /* Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2008          * should follow the settings from QAP. By Bruce, 2007-12-07.
2009          */
2010         if (priv->ieee80211->state != IEEE80211_LINKED)
2011                 goto dm_CheckEdcaTurbo_EXIT;
2012         /* We do not turn on EDCA turbo mode for some AP that has IOT issue */
2013         if (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2014                 goto dm_CheckEdcaTurbo_EXIT;
2015
2016         if (!priv->ieee80211->bis_any_nonbepkts) {
2017                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2018                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2019                 /* For RT-AP, we needs to turn it on when Rx>Tx */
2020                 if (curRxOkCnt > 4*curTxOkCnt) {
2021                         if (!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
2022                                 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2023                                 priv->bis_cur_rdlstate = true;
2024                         }
2025                 } else {
2026                         if (priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA) {
2027                                 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2028                                 priv->bis_cur_rdlstate = false;
2029                         }
2030                 }
2031
2032                 priv->bcurrent_turbo_EDCA = true;
2033         } else {
2034                 /* Turn Off EDCA turbo here.
2035                  * Restore original EDCA according to the declaration of AP.
2036                  */
2037                 if (priv->bcurrent_turbo_EDCA) {
2038                         u8      u1bAIFS;
2039                         u32     u4bAcParam, op_limit, cw_max, cw_min;
2040
2041                         struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2042                         u8 mode = priv->ieee80211->mode;
2043
2044                         /*  For Each time updating EDCA parameter, reset EDCA turbo mode status. */
2045                         dm_init_edca_turbo(dev);
2046
2047                         u1bAIFS = qos_parameters->aifs[0] * ((mode & (IEEE_G | IEEE_N_24G)) ? 9 : 20) + aSifsTime;
2048
2049                         op_limit = (u32)le16_to_cpu(qos_parameters->tx_op_limit[0]);
2050                         cw_max   = (u32)le16_to_cpu(qos_parameters->cw_max[0]);
2051                         cw_min   = (u32)le16_to_cpu(qos_parameters->cw_min[0]);
2052
2053                         op_limit <<= AC_PARAM_TXOP_LIMIT_OFFSET;
2054                         cw_max   <<= AC_PARAM_ECW_MAX_OFFSET;
2055                         cw_min   <<= AC_PARAM_ECW_MIN_OFFSET;
2056                         u1bAIFS  <<= AC_PARAM_AIFS_OFFSET;
2057
2058                         u4bAcParam = op_limit | cw_max | cw_min | u1bAIFS;
2059                         cpu_to_le32s(&u4bAcParam);
2060
2061                         write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
2062
2063                         /* Check ACM bit.
2064                          * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2065                          */
2066                         {
2067                                 /*  TODO:  Modified this part and try to set acm control in only 1 IO processing!! */
2068
2069                                 struct aci_aifsn *pAciAifsn = (struct aci_aifsn *)&(qos_parameters->aifs[0]);
2070                                 u8              AcmCtrl;
2071
2072                                 read_nic_byte(dev, AcmHwCtrl, &AcmCtrl);
2073
2074                                 if (pAciAifsn->acm) { /*  acm bit is 1. */
2075                                         AcmCtrl |= AcmHw_BeqEn;
2076                                 } else {        /* ACM bit is 0. */
2077                                         AcmCtrl &= (~AcmHw_BeqEn);
2078                                 }
2079
2080                                 RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
2081                                 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
2082                         }
2083                         priv->bcurrent_turbo_EDCA = false;
2084                 }
2085         }
2086
2087 dm_CheckEdcaTurbo_EXIT:
2088         /* Set variables for next time. */
2089         priv->ieee80211->bis_any_nonbepkts = false;
2090         lastTxOkCnt = priv->stats.txbytesunicast;
2091         lastRxOkCnt = priv->stats.rxbytesunicast;
2092 }       /* dm_CheckEdcaTurbo */
2093
2094 static void dm_init_ctstoself(struct net_device *dev)
2095 {
2096         struct r8192_priv *priv = ieee80211_priv(dev);
2097
2098         priv->ieee80211->bCTSToSelfEnable = true;
2099         priv->ieee80211->CTSToSelfTH = CTS_TO_SELF_TH_VAL;
2100 }
2101
2102 static void dm_ctstoself(struct net_device *dev)
2103 {
2104         struct r8192_priv *priv = ieee80211_priv(dev);
2105         PRT_HIGH_THROUGHPUT     pHTInfo = priv->ieee80211->pHTInfo;
2106         static unsigned long                            lastTxOkCnt;
2107         static unsigned long                            lastRxOkCnt;
2108         unsigned long                                           curTxOkCnt = 0;
2109         unsigned long                                           curRxOkCnt = 0;
2110
2111         if (!priv->ieee80211->bCTSToSelfEnable) {
2112                 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2113                 return;
2114         }
2115         /* 1. Uplink
2116          * 2. Linksys350/Linksys300N
2117          * 3. <50 disable, >55 enable
2118          */
2119
2120         if (pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM) {
2121                 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2122                 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2123                 if (curRxOkCnt > 4*curTxOkCnt) { /* downlink, disable CTS to self */
2124                         pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2125                 } else { /* uplink */
2126                         pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2127                 }
2128
2129                 lastTxOkCnt = priv->stats.txbytesunicast;
2130                 lastRxOkCnt = priv->stats.rxbytesunicast;
2131         }
2132 }
2133
2134 /*-----------------------------------------------------------------------------
2135  * Function:    dm_check_pbc_gpio()
2136  *
2137  * Overview:    Check if PBC button is pressed.
2138  *
2139  * Input:               NONE
2140  *
2141  * Output:              NONE
2142  *
2143  * Return:              NONE
2144  *---------------------------------------------------------------------------
2145  */
2146 static  void    dm_check_pbc_gpio(struct net_device *dev)
2147 {
2148         struct r8192_priv *priv = ieee80211_priv(dev);
2149         u8 tmp1byte;
2150
2151         read_nic_byte(dev, GPI, &tmp1byte);
2152         if (tmp1byte == 0xff)
2153                 return;
2154
2155         if (tmp1byte & BIT(6) || tmp1byte & BIT(0)) {
2156                 /* Here we only set bPbcPressed to TRUE
2157                  * After trigger PBC, the variable will be set to FALSE
2158                  */
2159                 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2160                 priv->bpbc_pressed = true;
2161         }
2162 }
2163
2164 /*-----------------------------------------------------------------------------
2165  * Function:    DM_RFPathCheckWorkItemCallBack()
2166  *
2167  * Overview:    Check if Current RF RX path is enabled
2168  *
2169  * Input:               NONE
2170  *
2171  * Output:              NONE
2172  *
2173  * Return:              NONE
2174  *---------------------------------------------------------------------------
2175  */
2176 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2177 {
2178         struct delayed_work *dwork = to_delayed_work(work);
2179         struct r8192_priv *priv = container_of(dwork, struct r8192_priv, rfpath_check_wq);
2180         struct net_device *dev = priv->ieee80211->dev;
2181         u8 rfpath = 0, i;
2182
2183         /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2184          * always be the same. We only read 0xc04 now.
2185          */
2186         read_nic_byte(dev, 0xc04, &rfpath);
2187
2188         /* Check Bit 0-3, it means if RF A-D is enabled. */
2189         for (i = 0; i < RF90_PATH_MAX; i++) {
2190                 if (rfpath & (0x01<<i))
2191                         priv->brfpath_rxenable[i] = true;
2192                 else
2193                         priv->brfpath_rxenable[i] = false;
2194         }
2195
2196         dm_rxpath_sel_byrssi(dev);
2197 }       /* DM_RFPathCheckWorkItemCallBack */
2198
2199 static void dm_init_rxpath_selection(struct net_device *dev)
2200 {
2201         u8 i;
2202         struct r8192_priv *priv = ieee80211_priv(dev);
2203
2204         if (priv->CustomerID == RT_CID_819x_Netcore)
2205                 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2;
2206         else
2207                 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_1;
2208         DM_RxPathSelTable.disabled_rf = 0;
2209         for (i = 0; i < 4; i++) {
2210                 DM_RxPathSelTable.rf_rssi[i] = 50;
2211                 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
2212                 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2213         }
2214 }
2215
2216 static void dm_rxpath_sel_byrssi(struct net_device *dev)
2217 {
2218         struct r8192_priv *priv = ieee80211_priv(dev);
2219         u8                              i, max_rssi_index = 0, min_rssi_index = 0, sec_rssi_index = 0, rf_num = 0;
2220         u8                              tmp_max_rssi = 0, tmp_min_rssi = 0, tmp_sec_rssi = 0;
2221         u8                              cck_default_Rx = 0x2;  /* RF-C */
2222         u8                              cck_optional_Rx = 0x3; /* RF-D */
2223         long                            tmp_cck_max_pwdb = 0, tmp_cck_min_pwdb = 0, tmp_cck_sec_pwdb = 0;
2224         u8                              cck_rx_ver2_max_index = 0, cck_rx_ver2_min_index = 0, cck_rx_ver2_sec_index = 0;
2225         u8                              cur_rf_rssi;
2226         long                            cur_cck_pwdb;
2227         static u8                       disabled_rf_cnt, cck_Rx_Path_initialized;
2228         u8                              update_cck_rx_path;
2229
2230         if (priv->rf_type != RF_2T4R)
2231                 return;
2232
2233         if (!cck_Rx_Path_initialized) {
2234                 read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_rx_path);
2235                 DM_RxPathSelTable.cck_rx_path &= 0xf;
2236                 cck_Rx_Path_initialized = 1;
2237         }
2238
2239         read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabled_rf);
2240         DM_RxPathSelTable.disabled_rf = ~DM_RxPathSelTable.disabled_rf & 0xf;
2241
2242         if (priv->ieee80211->mode == WIRELESS_MODE_B) {
2243                 DM_RxPathSelTable.cck_method = CCK_RX_VERSION_2;        /* pure B mode, fixed cck version2 */
2244         }
2245
2246         /* decide max/sec/min rssi index */
2247         for (i = 0; i < RF90_PATH_MAX; i++) {
2248                 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
2249
2250                 if (priv->brfpath_rxenable[i]) {
2251                         rf_num++;
2252                         cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
2253
2254                         if (rf_num == 1) { /* find first enabled rf path and the rssi values */
2255                                 /* initialize, set all rssi index to the same one */
2256                                 max_rssi_index = min_rssi_index = sec_rssi_index = i;
2257                                 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
2258                         } else if (rf_num == 2) { /* we pick up the max index first, and let sec and min to be the same one */
2259                                 if (cur_rf_rssi >= tmp_max_rssi) {
2260                                         tmp_max_rssi = cur_rf_rssi;
2261                                         max_rssi_index = i;
2262                                 } else {
2263                                         tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
2264                                         sec_rssi_index = min_rssi_index = i;
2265                                 }
2266                         } else {
2267                                 if (cur_rf_rssi > tmp_max_rssi) {
2268                                         tmp_sec_rssi = tmp_max_rssi;
2269                                         sec_rssi_index = max_rssi_index;
2270                                         tmp_max_rssi = cur_rf_rssi;
2271                                         max_rssi_index = i;
2272                                 } else if (cur_rf_rssi == tmp_max_rssi) {       /* let sec and min point to the different index */
2273                                         tmp_sec_rssi = cur_rf_rssi;
2274                                         sec_rssi_index = i;
2275                                 } else if ((cur_rf_rssi < tmp_max_rssi) && (cur_rf_rssi > tmp_sec_rssi)) {
2276                                         tmp_sec_rssi = cur_rf_rssi;
2277                                         sec_rssi_index = i;
2278                                 } else if (cur_rf_rssi == tmp_sec_rssi) {
2279                                         if (tmp_sec_rssi == tmp_min_rssi) {
2280                                                 /* let sec and min point to the different index */
2281                                                 tmp_sec_rssi = cur_rf_rssi;
2282                                                 sec_rssi_index = i;
2283                                         } else {
2284                                                 /* This case we don't need to set any index */
2285                                         }
2286                                 } else if ((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi)) {
2287                                         /* This case we don't need to set any index */
2288                                 } else if (cur_rf_rssi == tmp_min_rssi) {
2289                                         if (tmp_sec_rssi == tmp_min_rssi) {
2290                                                 /* let sec and min point to the different index */
2291                                                 tmp_min_rssi = cur_rf_rssi;
2292                                                 min_rssi_index = i;
2293                                         } else {
2294                                                 /* This case we don't need to set any index */
2295                                         }
2296                                 } else if (cur_rf_rssi < tmp_min_rssi) {
2297                                         tmp_min_rssi = cur_rf_rssi;
2298                                         min_rssi_index = i;
2299                                 }
2300                         }
2301                 }
2302         }
2303
2304         rf_num = 0;
2305         /* decide max/sec/min cck pwdb index */
2306         if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_2) {
2307                 for (i = 0; i < RF90_PATH_MAX; i++) {
2308                         if (priv->brfpath_rxenable[i]) {
2309                                 rf_num++;
2310                                 cur_cck_pwdb =  DM_RxPathSelTable.cck_pwdb_sta[i];
2311
2312                                 if (rf_num == 1) {      /* find first enabled rf path and the rssi values */
2313                                         /* initialize, set all rssi index to the same one */
2314                                         cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
2315                                         tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
2316                                 } else if (rf_num == 2) {       /* we pick up the max index first, and let sec and min to be the same one */
2317                                         if (cur_cck_pwdb >= tmp_cck_max_pwdb) {
2318                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
2319                                                 cck_rx_ver2_max_index = i;
2320                                         } else {
2321                                                 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
2322                                                 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
2323                                         }
2324                                 } else {
2325                                         if (cur_cck_pwdb > tmp_cck_max_pwdb) {
2326                                                 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
2327                                                 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
2328                                                 tmp_cck_max_pwdb = cur_cck_pwdb;
2329                                                 cck_rx_ver2_max_index = i;
2330                                         } else if (cur_cck_pwdb == tmp_cck_max_pwdb) {
2331                                                 /* let sec and min point to the different index */
2332                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
2333                                                 cck_rx_ver2_sec_index = i;
2334                                         } else if ((cur_cck_pwdb < tmp_cck_max_pwdb) && (cur_cck_pwdb > tmp_cck_sec_pwdb)) {
2335                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
2336                                                 cck_rx_ver2_sec_index = i;
2337                                         } else if (cur_cck_pwdb == tmp_cck_sec_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) {
2338                                                 /* let sec and min point to the different index */
2339                                                 tmp_cck_sec_pwdb = cur_cck_pwdb;
2340                                                 cck_rx_ver2_sec_index = i;
2341                                                 /* otherwise we don't need to set any index */
2342                                         } else if ((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb)) {
2343                                                 /*  This case we don't need to set any index */
2344                                         } else if (cur_cck_pwdb == tmp_cck_min_pwdb && tmp_cck_sec_pwdb == tmp_cck_min_pwdb) {
2345                                                 /*  let sec and min point to the different index */
2346                                                 tmp_cck_min_pwdb = cur_cck_pwdb;
2347                                                 cck_rx_ver2_min_index = i;
2348                                                 /* otherwise we don't need to set any index */
2349                                         } else if (cur_cck_pwdb < tmp_cck_min_pwdb) {
2350                                                 tmp_cck_min_pwdb = cur_cck_pwdb;
2351                                                 cck_rx_ver2_min_index = i;
2352                                         }
2353                                 }
2354                         }
2355                 }
2356         }
2357
2358         /* Set CCK Rx path
2359          * reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
2360          */
2361         update_cck_rx_path = 0;
2362         if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_2) {
2363                 cck_default_Rx = cck_rx_ver2_max_index;
2364                 cck_optional_Rx = cck_rx_ver2_sec_index;
2365                 if (tmp_cck_max_pwdb != -64)
2366                         update_cck_rx_path = 1;
2367         }
2368
2369         if (tmp_min_rssi < RX_PATH_SELECTION_SS_TH_LOW && disabled_rf_cnt < 2) {
2370                 if ((tmp_max_rssi - tmp_min_rssi) >= RX_PATH_SELECTION_DIFF_TH) {
2371                         /* record the enabled rssi threshold */
2372                         DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
2373                         /* disable the BB Rx path, OFDM */
2374                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0);  /* 0xc04[3:0] */
2375                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0);  /* 0xd04[3:0] */
2376                         disabled_rf_cnt++;
2377                 }
2378                 if (DM_RxPathSelTable.cck_method == CCK_RX_VERSION_1) {
2379                         cck_default_Rx = max_rssi_index;
2380                         cck_optional_Rx = sec_rssi_index;
2381                         if (tmp_max_rssi)
2382                                 update_cck_rx_path = 1;
2383                 }
2384         }
2385
2386         if (update_cck_rx_path) {
2387                 DM_RxPathSelTable.cck_rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
2388                 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_rx_path);
2389         }
2390
2391         if (DM_RxPathSelTable.disabled_rf) {
2392                 for (i = 0; i < 4; i++) {
2393                         if ((DM_RxPathSelTable.disabled_rf >> i) & 0x1) {       /* disabled rf */
2394                                 if (tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i]) {
2395                                         /* enable the BB Rx path */
2396                                         rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1);       /* 0xc04[3:0] */
2397                                         rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1);       /* 0xd04[3:0] */
2398                                         DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2399                                         disabled_rf_cnt--;
2400                                 }
2401                         }
2402                 }
2403         }
2404 }
2405
2406 /*-----------------------------------------------------------------------------
2407  * Function:    dm_check_rx_path_selection()
2408  *
2409  * Overview:    Call a workitem to check current RXRF path and Rx Path selection by RSSI.
2410  *
2411  * Input:               NONE
2412  *
2413  * Output:              NONE
2414  *
2415  * Return:              NONE
2416  *---------------------------------------------------------------------------
2417  */
2418 static void dm_check_rx_path_selection(struct net_device *dev)
2419 {
2420         struct r8192_priv *priv = ieee80211_priv(dev);
2421
2422         queue_delayed_work(priv->priv_wq, &priv->rfpath_check_wq, 0);
2423 }       /* dm_CheckRxRFPath */
2424
2425 static void dm_init_fsync(struct net_device *dev)
2426 {
2427         struct r8192_priv *priv = ieee80211_priv(dev);
2428
2429         priv->ieee80211->fsync_time_interval = 500;
2430         priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
2431         priv->ieee80211->fsync_rssi_threshold = 30;
2432         priv->ieee80211->bfsync_enable = false;
2433         priv->ieee80211->fsync_multiple_timeinterval = 3;
2434         priv->ieee80211->fsync_firstdiff_ratethreshold = 100;
2435         priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2436         priv->ieee80211->fsync_state = Default_Fsync;
2437         priv->framesyncMonitor = 1;     /* current default 0xc38 monitor on */
2438         INIT_DELAYED_WORK(&priv->fsync_work, dm_fsync_work_callback);
2439 }
2440
2441 static void dm_deInit_fsync(struct net_device *dev)
2442 {
2443         struct r8192_priv *priv = ieee80211_priv(dev);
2444
2445         cancel_delayed_work_sync(&priv->fsync_work);
2446 }
2447
2448 void dm_fsync_work_callback(struct work_struct *work)
2449 {
2450         struct r8192_priv *priv =
2451             container_of(work, struct r8192_priv, fsync_work.work);
2452         struct net_device *dev = priv->ieee80211->dev;
2453         u32 rate_index, rate_count = 0, rate_count_diff = 0;
2454         bool            bSwitchFromCountDiff = false;
2455         bool            bDoubleTimeInterval = false;
2456
2457         if (priv->ieee80211->state == IEEE80211_LINKED &&
2458             priv->ieee80211->bfsync_enable &&
2459                 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2460                 /* Count rate 54, MCS [7], [12, 13, 14, 15] */
2461                 u32 rate_bitmap;
2462
2463                 for (rate_index = 0; rate_index <= 27; rate_index++) {
2464                         rate_bitmap  = 1 << rate_index;
2465                         if (priv->ieee80211->fsync_rate_bitmap &  rate_bitmap)
2466                                 rate_count += priv->stats.received_rate_histogram[1][rate_index];
2467                 }
2468
2469                 if (rate_count < priv->rate_record)
2470                         rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
2471                 else
2472                         rate_count_diff = rate_count - priv->rate_record;
2473                 if (rate_count_diff < priv->rateCountDiffRecord) {
2474                         u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
2475                         /* Continue count */
2476                         if (DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
2477                                 priv->ContinueDiffCount++;
2478                         else
2479                                 priv->ContinueDiffCount = 0;
2480
2481                         /* Continue count over */
2482                         if (priv->ContinueDiffCount >= 2) {
2483                                 bSwitchFromCountDiff = true;
2484                                 priv->ContinueDiffCount = 0;
2485                         }
2486                 } else {
2487                         /* Stop the continued count */
2488                         priv->ContinueDiffCount = 0;
2489                 }
2490
2491                 /* If Count diff <= FsyncRateCountThreshold */
2492                 if (rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold) {
2493                         bSwitchFromCountDiff = true;
2494                         priv->ContinueDiffCount = 0;
2495                 }
2496                 priv->rate_record = rate_count;
2497                 priv->rateCountDiffRecord = rate_count_diff;
2498                 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync);
2499                 /* if we never receive those mcs rate and rssi > 30 % then switch fsyn */
2500                 if (priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff) {
2501                         bDoubleTimeInterval = true;
2502                         priv->bswitch_fsync = !priv->bswitch_fsync;
2503                         if (priv->bswitch_fsync) {
2504                                 write_nic_byte(dev, 0xC36, 0x1c);
2505                                 write_nic_byte(dev, 0xC3e, 0x90);
2506                         } else {
2507                                 write_nic_byte(dev, 0xC36, 0x5c);
2508                                 write_nic_byte(dev, 0xC3e, 0x96);
2509                         }
2510                 } else if (priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold) {
2511                         if (priv->bswitch_fsync) {
2512                                 priv->bswitch_fsync  = false;
2513                                 write_nic_byte(dev, 0xC36, 0x5c);
2514                                 write_nic_byte(dev, 0xC3e, 0x96);
2515                         }
2516                 }
2517                 if (bDoubleTimeInterval) {
2518                         cancel_delayed_work_sync(&priv->fsync_work);
2519                         schedule_delayed_work(&priv->fsync_work,
2520                                               msecs_to_jiffies(priv
2521                                               ->ieee80211->fsync_time_interval *
2522                                               priv->ieee80211->fsync_multiple_timeinterval));
2523                 } else {
2524                         cancel_delayed_work_sync(&priv->fsync_work);
2525                         schedule_delayed_work(&priv->fsync_work,
2526                                               msecs_to_jiffies(priv
2527                                               ->ieee80211->fsync_time_interval));
2528                 }
2529         } else {
2530                 /* Let Register return to default value; */
2531                 if (priv->bswitch_fsync) {
2532                         priv->bswitch_fsync  = false;
2533                         write_nic_byte(dev, 0xC36, 0x5c);
2534                         write_nic_byte(dev, 0xC3e, 0x96);
2535                 }
2536                 priv->ContinueDiffCount = 0;
2537                 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2538         }
2539         RT_TRACE(COMP_HALDM, "ContinueDiffCount %d\n", priv->ContinueDiffCount);
2540         RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff, priv->bswitch_fsync);
2541 }
2542
2543 static void dm_StartHWFsync(struct net_device *dev)
2544 {
2545         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2546         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
2547         write_nic_byte(dev, 0xc3b, 0x41);
2548 }
2549
2550 static void dm_EndSWFsync(struct net_device *dev)
2551 {
2552         struct r8192_priv *priv = ieee80211_priv(dev);
2553
2554         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2555         cancel_delayed_work_sync(&priv->fsync_work);
2556
2557         /* Let Register return to default value; */
2558         if (priv->bswitch_fsync) {
2559                 priv->bswitch_fsync  = false;
2560
2561                 write_nic_byte(dev, 0xC36, 0x5c);
2562
2563                 write_nic_byte(dev, 0xC3e, 0x96);
2564         }
2565
2566         priv->ContinueDiffCount = 0;
2567         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2568 }
2569
2570 static void dm_StartSWFsync(struct net_device *dev)
2571 {
2572         struct r8192_priv *priv = ieee80211_priv(dev);
2573         u32                     rateIndex;
2574         u32                     rateBitmap;
2575
2576         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2577         /* Initial rate record to zero, start to record. */
2578         priv->rate_record = 0;
2579         /* Initialize continue diff count to zero, start to record. */
2580         priv->ContinueDiffCount = 0;
2581         priv->rateCountDiffRecord = 0;
2582         priv->bswitch_fsync  = false;
2583
2584         if (priv->ieee80211->mode == WIRELESS_MODE_N_24G) {
2585                 priv->ieee80211->fsync_firstdiff_ratethreshold = 600;
2586                 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
2587         } else {
2588                 priv->ieee80211->fsync_firstdiff_ratethreshold = 200;
2589                 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2590         }
2591         for (rateIndex = 0; rateIndex <= 27; rateIndex++) {
2592                 rateBitmap = 1 << rateIndex;
2593                 if (priv->ieee80211->fsync_rate_bitmap &  rateBitmap)
2594                         priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
2595         }
2596         cancel_delayed_work_sync(&priv->fsync_work);
2597         schedule_delayed_work(&priv->fsync_work,
2598                               msecs_to_jiffies(priv->ieee80211->fsync_time_interval));
2599
2600         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
2601 }
2602
2603 static void dm_EndHWFsync(struct net_device *dev)
2604 {
2605         RT_TRACE(COMP_HALDM, "%s\n", __func__);
2606         write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2607         write_nic_byte(dev, 0xc3b, 0x49);
2608 }
2609
2610 void dm_check_fsync(struct net_device *dev)
2611 {
2612 #define RegC38_Default                          0
2613 #define RegC38_NonFsync_Other_AP                1
2614 #define RegC38_Fsync_AP_BCM                     2
2615         struct r8192_priv *priv = ieee80211_priv(dev);
2616         static u8               reg_c38_State = RegC38_Default;
2617         static u32      reset_cnt;
2618
2619         RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
2620         RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
2621
2622         if (priv->ieee80211->state == IEEE80211_LINKED &&
2623                 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC)) {
2624                 if (priv->ieee80211->bfsync_enable == 0) {
2625                         switch (priv->ieee80211->fsync_state) {
2626                         case Default_Fsync:
2627                                 dm_StartHWFsync(dev);
2628                                 priv->ieee80211->fsync_state = HW_Fsync;
2629                                 break;
2630                         case SW_Fsync:
2631                                 dm_EndSWFsync(dev);
2632                                 dm_StartHWFsync(dev);
2633                                 priv->ieee80211->fsync_state = HW_Fsync;
2634                                 break;
2635                         case HW_Fsync:
2636                         default:
2637                                 break;
2638                         }
2639                 } else {
2640                         switch (priv->ieee80211->fsync_state) {
2641                         case Default_Fsync:
2642                                 dm_StartSWFsync(dev);
2643                                 priv->ieee80211->fsync_state = SW_Fsync;
2644                                 break;
2645                         case HW_Fsync:
2646                                 dm_EndHWFsync(dev);
2647                                 dm_StartSWFsync(dev);
2648                                 priv->ieee80211->fsync_state = SW_Fsync;
2649                                 break;
2650                         case SW_Fsync:
2651                         default:
2652                                 break;
2653                         }
2654                 }
2655                 if (priv->framesyncMonitor) {
2656                         if (reg_c38_State != RegC38_Fsync_AP_BCM) {
2657                                 /* For broadcom AP we write different default value */
2658                                 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
2659
2660                                 reg_c38_State = RegC38_Fsync_AP_BCM;
2661                         }
2662                 }
2663         } else {
2664                 switch (priv->ieee80211->fsync_state) {
2665                 case HW_Fsync:
2666                         dm_EndHWFsync(dev);
2667                         priv->ieee80211->fsync_state = Default_Fsync;
2668                         break;
2669                 case SW_Fsync:
2670                         dm_EndSWFsync(dev);
2671                         priv->ieee80211->fsync_state = Default_Fsync;
2672                         break;
2673                 case Default_Fsync:
2674                 default:
2675                         break;
2676                 }
2677
2678                 if (priv->framesyncMonitor) {
2679                         if (priv->ieee80211->state == IEEE80211_LINKED) {
2680                                 if (priv->undecorated_smoothed_pwdb <= REG_C38_TH) {
2681                                         if (reg_c38_State != RegC38_NonFsync_Other_AP) {
2682                                                 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
2683
2684                                                 reg_c38_State = RegC38_NonFsync_Other_AP;
2685                                         }
2686                                 } else if (priv->undecorated_smoothed_pwdb >= (REG_C38_TH + 5)) {
2687                                         if (reg_c38_State) {
2688                                                 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2689                                                 reg_c38_State = RegC38_Default;
2690                                         }
2691                                 }
2692                         } else {
2693                                 if (reg_c38_State) {
2694                                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2695                                         reg_c38_State = RegC38_Default;
2696                                 }
2697                         }
2698                 }
2699         }
2700         if (priv->framesyncMonitor) {
2701                 if (priv->reset_count != reset_cnt) { /* After silent reset, the reg_c38_State will be returned to default value */
2702                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2703                         reg_c38_State = RegC38_Default;
2704                         reset_cnt = priv->reset_count;
2705                 }
2706         } else {
2707                 if (reg_c38_State) {
2708                         write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
2709                         reg_c38_State = RegC38_Default;
2710                 }
2711         }
2712 }
2713
2714 /*---------------------------Define function prototype------------------------*/
2715 /*-----------------------------------------------------------------------------
2716  * Function:    DM_DynamicTxPower()
2717  *
2718  * Overview:    Detect Signal strength to control TX Registry
2719                         Tx Power Control For Near/Far Range
2720  *
2721  * Input:               NONE
2722  *
2723  * Output:              NONE
2724  *
2725  * Return:              NONE
2726  *---------------------------------------------------------------------------
2727  */
2728 static void dm_init_dynamic_txpower(struct net_device *dev)
2729 {
2730         struct r8192_priv *priv = ieee80211_priv(dev);
2731
2732         /* Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code. */
2733         priv->ieee80211->bdynamic_txpower_enable = true;    /* Default to enable Tx Power Control */
2734         priv->bLastDTPFlag_High = false;
2735         priv->bLastDTPFlag_Low = false;
2736         priv->bDynamicTxHighPower = false;
2737         priv->bDynamicTxLowPower = false;
2738 }
2739
2740 static void dm_dynamic_txpower(struct net_device *dev)
2741 {
2742         struct r8192_priv *priv = ieee80211_priv(dev);
2743         unsigned int txhipower_threshold = 0;
2744         unsigned int txlowpower_threshold = 0;
2745
2746         if (!priv->ieee80211->bdynamic_txpower_enable) {
2747                 priv->bDynamicTxHighPower = false;
2748                 priv->bDynamicTxLowPower = false;
2749                 return;
2750         }
2751         if ((priv->ieee80211->current_network.atheros_cap_exist) && (priv->ieee80211->mode == IEEE_G)) {
2752                 txhipower_threshold = TX_POWER_ATHEROAP_THRESH_HIGH;
2753                 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
2754         } else {
2755                 txhipower_threshold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
2756                 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
2757         }
2758
2759         RT_TRACE(COMP_TXAGC, "priv->undecorated_smoothed_pwdb = %ld\n", priv->undecorated_smoothed_pwdb);
2760
2761         if (priv->ieee80211->state == IEEE80211_LINKED) {
2762                 if (priv->undecorated_smoothed_pwdb >= txhipower_threshold) {
2763                         priv->bDynamicTxHighPower = true;
2764                         priv->bDynamicTxLowPower = false;
2765                 } else {
2766                         /* high power state check */
2767                         if (priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower)
2768                                 priv->bDynamicTxHighPower = false;
2769
2770                         /* low power state check */
2771                         if (priv->undecorated_smoothed_pwdb < 35)
2772                                 priv->bDynamicTxLowPower = true;
2773                         else if (priv->undecorated_smoothed_pwdb >= 40)
2774                                 priv->bDynamicTxLowPower = false;
2775                 }
2776         } else {
2777                 priv->bDynamicTxHighPower = false;
2778                 priv->bDynamicTxLowPower = false;
2779         }
2780
2781         if ((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) ||
2782                 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low)) {
2783                 RT_TRACE(COMP_TXAGC, "SetTxPowerLevel8190()  channel = %d\n", priv->ieee80211->current_network.channel);
2784
2785 #if  defined(RTL8190P) || defined(RTL8192E)
2786                 SetTxPowerLevel8190(Adapter, pHalData->CurrentChannel);
2787 #endif
2788
2789                 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
2790                 /*pHalData->bStartTxCtrlByTPCNFR = FALSE;    Clear th flag of Set TX Power from Sitesurvey*/
2791         }
2792         priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
2793         priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
2794
2795 }       /* dm_dynamic_txpower */
2796
2797 /* added by vivi, for read tx rate and retrycount */
2798 static void dm_check_txrateandretrycount(struct net_device *dev)
2799 {
2800         struct r8192_priv *priv = ieee80211_priv(dev);
2801         struct ieee80211_device *ieee = priv->ieee80211;
2802         /* for 11n tx rate */
2803         read_nic_byte(dev, CURRENT_TX_RATE_REG, &ieee->softmac_stats.CurrentShowTxate);
2804         /* for initial tx rate */
2805         read_nic_byte(dev, INITIAL_TX_RATE_REG, &ieee->softmac_stats.last_packet_rate);
2806         /* for tx retry count */
2807         read_nic_dword(dev, TX_RETRY_COUNT_REG, &ieee->softmac_stats.txretrycount);
2808 }
2809
2810 static void dm_send_rssi_tofw(struct net_device *dev)
2811 {
2812         struct r8192_priv *priv = ieee80211_priv(dev);
2813
2814         /* If we test chariot, we should stop the TX command ?
2815          * Because 92E will always silent reset when we send tx command. We use register
2816          * 0x1e0(byte) to notify driver.
2817          */
2818         write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
2819 }
2820
2821 /*---------------------------Define function prototype------------------------*/