drivers/phy/qualcomm/phy-qcom-snps-eusb2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2023, Linaro Limited
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/iopoll.h>
  10 #include <linux/phy/phy.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/regulator/consumer.h>
  13 #include <linux/reset.h>
  14
  15 #define USB_PHY_UTMI_CTRL0              (0x3c)
  16 #define SLEEPM                          BIT(0)
  17 #define OPMODE_MASK                     GENMASK(4, 3)
  18 #define OPMODE_NONDRIVING               BIT(3)
  19
  20 #define USB_PHY_UTMI_CTRL5              (0x50)
  21 #define POR                             BIT(1)
  22
  23 #define USB_PHY_HS_PHY_CTRL_COMMON0     (0x54)
  24 #define PHY_ENABLE                      BIT(0)
  25 #define SIDDQ_SEL                       BIT(1)
  26 #define SIDDQ                           BIT(2)
  27 #define RETENABLEN                      BIT(3)
  28 #define FSEL_MASK                       GENMASK(6, 4)
  29 #define FSEL_19_2_MHZ_VAL               (0x0)
  30 #define FSEL_38_4_MHZ_VAL               (0x4)
  31
  32 #define USB_PHY_CFG_CTRL_1              (0x58)
  33 #define PHY_CFG_PLL_CPBIAS_CNTRL_MASK   GENMASK(7, 1)
  34
  35 #define USB_PHY_CFG_CTRL_2              (0x5c)
  36 #define PHY_CFG_PLL_FB_DIV_7_0_MASK     GENMASK(7, 0)
  37 #define DIV_7_0_19_2_MHZ_VAL            (0x90)
  38 #define DIV_7_0_38_4_MHZ_VAL            (0xc8)
  39
  40 #define USB_PHY_CFG_CTRL_3              (0x60)
  41 #define PHY_CFG_PLL_FB_DIV_11_8_MASK    GENMASK(3, 0)
  42 #define DIV_11_8_19_2_MHZ_VAL           (0x1)
  43 #define DIV_11_8_38_4_MHZ_VAL           (0x0)
  44
  45 #define PHY_CFG_PLL_REF_DIV             GENMASK(7, 4)
  46 #define PLL_REF_DIV_VAL                 (0x0)
  47
  48 #define USB_PHY_HS_PHY_CTRL2            (0x64)
  49 #define VBUSVLDEXT0                     BIT(0)
  50 #define USB2_SUSPEND_N                  BIT(2)
  51 #define USB2_SUSPEND_N_SEL              BIT(3)
  52 #define VBUS_DET_EXT_SEL                BIT(4)
  53
  54 #define USB_PHY_CFG_CTRL_4              (0x68)
  55 #define PHY_CFG_PLL_GMP_CNTRL_MASK      GENMASK(1, 0)
  56 #define PHY_CFG_PLL_INT_CNTRL_MASK      GENMASK(7, 2)
  57
  58 #define USB_PHY_CFG_CTRL_5              (0x6c)
  59 #define PHY_CFG_PLL_PROP_CNTRL_MASK     GENMASK(4, 0)
  60 #define PHY_CFG_PLL_VREF_TUNE_MASK      GENMASK(7, 6)
  61
  62 #define USB_PHY_CFG_CTRL_6              (0x70)
  63 #define PHY_CFG_PLL_VCO_CNTRL_MASK      GENMASK(2, 0)
  64
  65 #define USB_PHY_CFG_CTRL_7              (0x74)
  66
  67 #define USB_PHY_CFG_CTRL_8              (0x78)
  68 #define PHY_CFG_TX_FSLS_VREF_TUNE_MASK  GENMASK(1, 0)
  69 #define PHY_CFG_TX_FSLS_VREG_BYPASS     BIT(2)
  70 #define PHY_CFG_TX_HS_VREF_TUNE_MASK    GENMASK(5, 3)
  71 #define PHY_CFG_TX_HS_XV_TUNE_MASK      GENMASK(7, 6)
  72
  73 #define USB_PHY_CFG_CTRL_9              (0x7c)
  74 #define PHY_CFG_TX_PREEMP_TUNE_MASK     GENMASK(2, 0)
  75 #define PHY_CFG_TX_RES_TUNE_MASK        GENMASK(4, 3)
  76 #define PHY_CFG_TX_RISE_TUNE_MASK       GENMASK(6, 5)
  77 #define PHY_CFG_RCAL_BYPASS             BIT(7)
  78
  79 #define USB_PHY_CFG_CTRL_10             (0x80)
  80
  81 #define USB_PHY_CFG0                    (0x94)
  82 #define DATAPATH_CTRL_OVERRIDE_EN       BIT(0)
  83 #define CMN_CTRL_OVERRIDE_EN            BIT(1)
  84
  85 #define UTMI_PHY_CMN_CTRL0              (0x98)
  86 #define TESTBURNIN                      BIT(6)
  87
  88 #define USB_PHY_FSEL_SEL                (0xb8)
  89 #define FSEL_SEL                        BIT(0)
  90
  91 #define USB_PHY_APB_ACCESS_CMD          (0x130)
  92 #define RW_ACCESS                       BIT(0)
  93 #define APB_START_CMD                   BIT(1)
  94 #define APB_LOGIC_RESET                 BIT(2)
  95
  96 #define USB_PHY_APB_ACCESS_STATUS       (0x134)
  97 #define ACCESS_DONE                     BIT(0)
  98 #define TIMED_OUT                       BIT(1)
  99 #define ACCESS_ERROR                    BIT(2)
 100 #define ACCESS_IN_PROGRESS              BIT(3)
 101
 102 #define USB_PHY_APB_ADDRESS             (0x138)
 103 #define APB_REG_ADDR_MASK               GENMASK(7, 0)
 104
 105 #define USB_PHY_APB_WRDATA_LSB          (0x13c)
 106 #define APB_REG_WRDATA_7_0_MASK         GENMASK(3, 0)
 107
 108 #define USB_PHY_APB_WRDATA_MSB          (0x140)
 109 #define APB_REG_WRDATA_15_8_MASK        GENMASK(7, 4)
 110
 111 #define USB_PHY_APB_RDDATA_LSB          (0x144)
 112 #define APB_REG_RDDATA_7_0_MASK         GENMASK(3, 0)
 113
 114 #define USB_PHY_APB_RDDATA_MSB          (0x148)
 115 #define APB_REG_RDDATA_15_8_MASK        GENMASK(7, 4)
 116
 117 static const char * const eusb2_hsphy_vreg_names[] = {
 118         "vdd", "vdda12",
 119 };
 120
 121 #define EUSB2_NUM_VREGS         ARRAY_SIZE(eusb2_hsphy_vreg_names)
 122
 123 struct qcom_snps_eusb2_hsphy {
 124         struct phy *phy;
 125         void __iomem *base;
 126
 127         struct clk *ref_clk;
 128         struct reset_control *phy_reset;
 129
 130         struct regulator_bulk_data vregs[EUSB2_NUM_VREGS];
 131
 132         enum phy_mode mode;
 133
 134         struct phy *repeater;
 135 };
 136
 137 static int qcom_snps_eusb2_hsphy_set_mode(struct phy *p, enum phy_mode mode, int submode)
 138 {
 139         struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
 140
 141         phy->mode = mode;
 142
 143         return phy_set_mode_ext(phy->repeater, mode, submode);
 144 }
 145
 146 static void qcom_snps_eusb2_hsphy_write_mask(void __iomem *base, u32 offset,
 147                                              u32 mask, u32 val)
 148 {
 149         u32 reg;
 150
 151         reg = readl_relaxed(base + offset);
 152         reg &= ~mask;
 153         reg |= val & mask;
 154         writel_relaxed(reg, base + offset);
 155
 156         /* Ensure above write is completed */
 157         readl_relaxed(base + offset);
 158 }
 159
 160 static void qcom_eusb2_default_parameters(struct qcom_snps_eusb2_hsphy *phy)
 161 {
 162         /* default parameters: tx pre-emphasis */
 163         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
 164                                          PHY_CFG_TX_PREEMP_TUNE_MASK,
 165                                          FIELD_PREP(PHY_CFG_TX_PREEMP_TUNE_MASK, 0));
 166
 167         /* tx rise/fall time */
 168         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
 169                                          PHY_CFG_TX_RISE_TUNE_MASK,
 170                                          FIELD_PREP(PHY_CFG_TX_RISE_TUNE_MASK, 0x2));
 171
 172         /* source impedance adjustment */
 173         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_9,
 174                                          PHY_CFG_TX_RES_TUNE_MASK,
 175                                          FIELD_PREP(PHY_CFG_TX_RES_TUNE_MASK, 0x1));
 176
 177         /* dc voltage level adjustement */
 178         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
 179                                          PHY_CFG_TX_HS_VREF_TUNE_MASK,
 180                                          FIELD_PREP(PHY_CFG_TX_HS_VREF_TUNE_MASK, 0x3));
 181
 182         /* transmitter HS crossover adjustement */
 183         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_8,
 184                                          PHY_CFG_TX_HS_XV_TUNE_MASK,
 185                                          FIELD_PREP(PHY_CFG_TX_HS_XV_TUNE_MASK, 0x0));
 186 }
 187
 188 static int qcom_eusb2_ref_clk_init(struct qcom_snps_eusb2_hsphy *phy)
 189 {
 190         unsigned long ref_clk_freq = clk_get_rate(phy->ref_clk);
 191
 192         switch (ref_clk_freq) {
 193         case 19200000:
 194                 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
 195                                                  FSEL_MASK,
 196                                                  FIELD_PREP(FSEL_MASK, FSEL_19_2_MHZ_VAL));
 197
 198                 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
 199                                                  PHY_CFG_PLL_FB_DIV_7_0_MASK,
 200                                                  DIV_7_0_19_2_MHZ_VAL);
 201
 202                 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
 203                                                  PHY_CFG_PLL_FB_DIV_11_8_MASK,
 204                                                  DIV_11_8_19_2_MHZ_VAL);
 205                 break;
 206
 207         case 38400000:
 208                 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
 209                                                  FSEL_MASK,
 210                                                  FIELD_PREP(FSEL_MASK, FSEL_38_4_MHZ_VAL));
 211
 212                 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_2,
 213                                                  PHY_CFG_PLL_FB_DIV_7_0_MASK,
 214                                                  DIV_7_0_38_4_MHZ_VAL);
 215
 216                 qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
 217                                                  PHY_CFG_PLL_FB_DIV_11_8_MASK,
 218                                                  DIV_11_8_38_4_MHZ_VAL);
 219                 break;
 220
 221         default:
 222                 dev_err(&phy->phy->dev, "unsupported ref_clk_freq:%lu\n", ref_clk_freq);
 223                 return -EINVAL;
 224         }
 225
 226         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_3,
 227                                          PHY_CFG_PLL_REF_DIV, PLL_REF_DIV_VAL);
 228
 229         return 0;
 230 }
 231
 232 static int qcom_snps_eusb2_hsphy_init(struct phy *p)
 233 {
 234         struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
 235         int ret;
 236
 237         ret = regulator_bulk_enable(ARRAY_SIZE(phy->vregs), phy->vregs);
 238         if (ret)
 239                 return ret;
 240
 241         ret = phy_init(phy->repeater);
 242         if (ret) {
 243                 dev_err(&p->dev, "repeater init failed. %d\n", ret);
 244                 goto disable_vreg;
 245         }
 246
 247         ret = clk_prepare_enable(phy->ref_clk);
 248         if (ret) {
 249                 dev_err(&p->dev, "failed to enable ref clock, %d\n", ret);
 250                 goto disable_vreg;
 251         }
 252
 253         ret = reset_control_assert(phy->phy_reset);
 254         if (ret) {
 255                 dev_err(&p->dev, "failed to assert phy_reset, %d\n", ret);
 256                 goto disable_ref_clk;
 257         }
 258
 259         usleep_range(100, 150);
 260
 261         ret = reset_control_deassert(phy->phy_reset);
 262         if (ret) {
 263                 dev_err(&p->dev, "failed to de-assert phy_reset, %d\n", ret);
 264                 goto disable_ref_clk;
 265         }
 266
 267         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG0,
 268                                          CMN_CTRL_OVERRIDE_EN, CMN_CTRL_OVERRIDE_EN);
 269
 270         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, POR);
 271
 272         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
 273                                          PHY_ENABLE | RETENABLEN, PHY_ENABLE | RETENABLEN);
 274
 275         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_APB_ACCESS_CMD,
 276                                          APB_LOGIC_RESET, APB_LOGIC_RESET);
 277
 278         qcom_snps_eusb2_hsphy_write_mask(phy->base, UTMI_PHY_CMN_CTRL0, TESTBURNIN, 0);
 279
 280         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_FSEL_SEL,
 281                                          FSEL_SEL, FSEL_SEL);
 282
 283         /* update ref_clk related registers */
 284         ret = qcom_eusb2_ref_clk_init(phy);
 285         if (ret)
 286                 goto disable_ref_clk;
 287
 288         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_1,
 289                                          PHY_CFG_PLL_CPBIAS_CNTRL_MASK,
 290                                          FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_MASK, 0x1));
 291
 292         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
 293                                          PHY_CFG_PLL_INT_CNTRL_MASK,
 294                                          FIELD_PREP(PHY_CFG_PLL_INT_CNTRL_MASK, 0x8));
 295
 296         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_4,
 297                                          PHY_CFG_PLL_GMP_CNTRL_MASK,
 298                                          FIELD_PREP(PHY_CFG_PLL_GMP_CNTRL_MASK, 0x1));
 299
 300         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
 301                                          PHY_CFG_PLL_PROP_CNTRL_MASK,
 302                                          FIELD_PREP(PHY_CFG_PLL_PROP_CNTRL_MASK, 0x10));
 303
 304         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_6,
 305                                          PHY_CFG_PLL_VCO_CNTRL_MASK,
 306                                          FIELD_PREP(PHY_CFG_PLL_VCO_CNTRL_MASK, 0x0));
 307
 308         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_CFG_CTRL_5,
 309                                          PHY_CFG_PLL_VREF_TUNE_MASK,
 310                                          FIELD_PREP(PHY_CFG_PLL_VREF_TUNE_MASK, 0x1));
 311
 312         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
 313                                          VBUS_DET_EXT_SEL, VBUS_DET_EXT_SEL);
 314
 315         /* set default parameters */
 316         qcom_eusb2_default_parameters(phy);
 317
 318         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
 319                                          USB2_SUSPEND_N_SEL | USB2_SUSPEND_N,
 320                                          USB2_SUSPEND_N_SEL | USB2_SUSPEND_N);
 321
 322         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL0, SLEEPM, SLEEPM);
 323
 324         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
 325                                          SIDDQ_SEL, SIDDQ_SEL);
 326
 327         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL_COMMON0,
 328                                          SIDDQ, 0);
 329
 330         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_UTMI_CTRL5, POR, 0);
 331
 332         qcom_snps_eusb2_hsphy_write_mask(phy->base, USB_PHY_HS_PHY_CTRL2,
 333                                          USB2_SUSPEND_N_SEL, 0);
 334
 335         return 0;
 336
 337 disable_ref_clk:
 338         clk_disable_unprepare(phy->ref_clk);
 339
 340 disable_vreg:
 341         regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
 342
 343         return ret;
 344 }
 345
 346 static int qcom_snps_eusb2_hsphy_exit(struct phy *p)
 347 {
 348         struct qcom_snps_eusb2_hsphy *phy = phy_get_drvdata(p);
 349
 350         clk_disable_unprepare(phy->ref_clk);
 351
 352         regulator_bulk_disable(ARRAY_SIZE(phy->vregs), phy->vregs);
 353
 354         phy_exit(phy->repeater);
 355
 356         return 0;
 357 }
 358
 359 static const struct phy_ops qcom_snps_eusb2_hsphy_ops = {
 360         .init           = qcom_snps_eusb2_hsphy_init,
 361         .exit           = qcom_snps_eusb2_hsphy_exit,
 362         .set_mode       = qcom_snps_eusb2_hsphy_set_mode,
 363         .owner          = THIS_MODULE,
 364 };
 365
 366 static int qcom_snps_eusb2_hsphy_probe(struct platform_device *pdev)
 367 {
 368         struct device *dev = &pdev->dev;
 369         struct device_node *np = dev->of_node;
 370         struct qcom_snps_eusb2_hsphy *phy;
 371         struct phy_provider *phy_provider;
 372         struct phy *generic_phy;
 373         int ret, i;
 374         int num;
 375
 376         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 377         if (!phy)
 378                 return -ENOMEM;
 379
 380         phy->base = devm_platform_ioremap_resource(pdev, 0);
 381         if (IS_ERR(phy->base))
 382                 return PTR_ERR(phy->base);
 383
 384         phy->phy_reset = devm_reset_control_get_exclusive(dev, NULL);
 385         if (IS_ERR(phy->phy_reset))
 386                 return PTR_ERR(phy->phy_reset);
 387
 388         phy->ref_clk = devm_clk_get(dev, "ref");
 389         if (IS_ERR(phy->ref_clk))
 390                 return dev_err_probe(dev, PTR_ERR(phy->ref_clk),
 391                                      "failed to get ref clk\n");
 392
 393         num = ARRAY_SIZE(phy->vregs);
 394         for (i = 0; i < num; i++)
 395                 phy->vregs[i].supply = eusb2_hsphy_vreg_names[i];
 396
 397         ret = devm_regulator_bulk_get(dev, num, phy->vregs);
 398         if (ret)
 399                 return dev_err_probe(dev, ret,
 400                                      "failed to get regulator supplies\n");
 401
 402         phy->repeater = devm_of_phy_get_by_index(dev, np, 0);
 403         if (IS_ERR(phy->repeater))
 404                 return dev_err_probe(dev, PTR_ERR(phy->repeater),
 405                                      "failed to get repeater\n");
 406
 407         generic_phy = devm_phy_create(dev, NULL, &qcom_snps_eusb2_hsphy_ops);
 408         if (IS_ERR(generic_phy)) {
 409                 dev_err(dev, "failed to create phy %d\n", ret);
 410                 return PTR_ERR(generic_phy);
 411         }
 412
 413         dev_set_drvdata(dev, phy);
 414         phy_set_drvdata(generic_phy, phy);
 415
 416         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 417         if (IS_ERR(phy_provider))
 418                 return PTR_ERR(phy_provider);
 419
 420         dev_info(dev, "Registered Qcom-eUSB2 phy\n");
 421
 422         return 0;
 423 }
 424
 425 static const struct of_device_id qcom_snps_eusb2_hsphy_of_match_table[] = {
 426         { .compatible = "qcom,sm8550-snps-eusb2-phy", },
 427         { },
 428 };
 429 MODULE_DEVICE_TABLE(of, qcom_snps_eusb2_hsphy_of_match_table);
 430
 431 static struct platform_driver qcom_snps_eusb2_hsphy_driver = {
 432         .probe          = qcom_snps_eusb2_hsphy_probe,
 433         .driver = {
 434                 .name   = "qcom-snps-eusb2-hsphy",
 435                 .of_match_table = qcom_snps_eusb2_hsphy_of_match_table,
 436         },
 437 };
 438
 439 module_platform_driver(qcom_snps_eusb2_hsphy_driver);
 440 MODULE_DESCRIPTION("Qualcomm SNPS eUSB2 HS PHY driver");
 441 MODULE_LICENSE("GPL");