1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/delay.h>
8 #include <linux/device.h>
11 #include <linux/pci.h>
15 #define PT3_I2C_BASE 2048
16 #define PT3_CMD_ADDR_NORMAL 0
17 #define PT3_CMD_ADDR_INIT_DEMOD 4096
18 #define PT3_CMD_ADDR_INIT_TUNER (4096 + 2042)
20 /* masks for I2C status register */
21 #define STAT_SEQ_RUNNING 0x1
22 #define STAT_SEQ_ERROR 0x6
23 #define STAT_NO_SEQ 0x8
25 #define PT3_I2C_RUN (1 << 16)
26 #define PT3_I2C_RESET (1 << 17)
45 static void cmdbuf_add(struct pt3_i2cbuf *cbuf, enum ctl_cmd cmd)
49 if ((cbuf->num_cmds % 2) == 0)
52 cbuf->tmp |= cmd << 4;
53 buf_idx = cbuf->num_cmds / 2;
54 if (buf_idx < ARRAY_SIZE(cbuf->data))
55 cbuf->data[buf_idx] = cbuf->tmp;
60 static void put_end(struct pt3_i2cbuf *cbuf)
62 cmdbuf_add(cbuf, I_END);
63 if (cbuf->num_cmds % 2)
64 cmdbuf_add(cbuf, I_END);
67 static void put_start(struct pt3_i2cbuf *cbuf)
69 cmdbuf_add(cbuf, I_DATA_H);
70 cmdbuf_add(cbuf, I_CLOCK_H);
71 cmdbuf_add(cbuf, I_DATA_L);
72 cmdbuf_add(cbuf, I_CLOCK_L);
75 static void put_byte_write(struct pt3_i2cbuf *cbuf, u8 val)
79 for (mask = 0x80; mask > 0; mask >>= 1)
80 cmdbuf_add(cbuf, (val & mask) ? I_DATA_H_NOP : I_DATA_L_NOP);
81 cmdbuf_add(cbuf, I_DATA_H_ACK0);
84 static void put_byte_read(struct pt3_i2cbuf *cbuf, u32 size)
88 for (i = 0; i < size; i++) {
89 for (j = 0; j < 8; j++)
90 cmdbuf_add(cbuf, I_DATA_H_READ);
91 cmdbuf_add(cbuf, (i == size - 1) ? I_DATA_H_NOP : I_DATA_L_NOP);
95 static void put_stop(struct pt3_i2cbuf *cbuf)
97 cmdbuf_add(cbuf, I_DATA_L);
98 cmdbuf_add(cbuf, I_CLOCK_H);
99 cmdbuf_add(cbuf, I_DATA_H);
103 /* translates msgs to internal commands for bit-banging */
104 static void translate(struct pt3_i2cbuf *cbuf, struct i2c_msg *msgs, int num)
110 for (i = 0; i < num; i++) {
111 rd = !!(msgs[i].flags & I2C_M_RD);
113 put_byte_write(cbuf, msgs[i].addr << 1 | rd);
115 put_byte_read(cbuf, msgs[i].len);
117 for (j = 0; j < msgs[i].len; j++)
118 put_byte_write(cbuf, msgs[i].buf[j]);
126 static int wait_i2c_result(struct pt3_board *pt3, u32 *result, int max_wait)
131 for (i = 0; i < max_wait; i++) {
132 v = ioread32(pt3->regs[0] + REG_I2C_R);
133 if (!(v & STAT_SEQ_RUNNING))
135 usleep_range(500, 750);
144 /* send [pre-]translated i2c msgs stored at addr */
145 static int send_i2c_cmd(struct pt3_board *pt3, u32 addr)
149 /* make sure that previous transactions had finished */
150 if (wait_i2c_result(pt3, NULL, 50)) {
151 dev_warn(&pt3->pdev->dev, "(%s) prev. transaction stalled\n",
156 iowrite32(PT3_I2C_RUN | addr, pt3->regs[0] + REG_I2C_W);
157 usleep_range(200, 300);
158 /* wait for the current transaction to finish */
159 if (wait_i2c_result(pt3, &ret, 500) || (ret & STAT_SEQ_ERROR)) {
160 dev_warn(&pt3->pdev->dev, "(%s) failed.\n", __func__);
167 /* init commands for each demod are combined into one transaction
168 * and hidden in ROM with the address PT3_CMD_ADDR_INIT_DEMOD.
170 int pt3_init_all_demods(struct pt3_board *pt3)
172 ioread32(pt3->regs[0] + REG_I2C_R);
173 return send_i2c_cmd(pt3, PT3_CMD_ADDR_INIT_DEMOD);
176 /* init commands for two ISDB-T tuners are hidden in ROM. */
177 int pt3_init_all_mxl301rf(struct pt3_board *pt3)
179 usleep_range(1000, 2000);
180 return send_i2c_cmd(pt3, PT3_CMD_ADDR_INIT_TUNER);
183 void pt3_i2c_reset(struct pt3_board *pt3)
185 iowrite32(PT3_I2C_RESET, pt3->regs[0] + REG_I2C_W);
192 pt3_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
194 struct pt3_board *pt3;
195 struct pt3_i2cbuf *cbuf;
199 pt3 = i2c_get_adapdata(adap);
202 for (i = 0; i < num; i++)
203 if (msgs[i].flags & I2C_M_RECV_LEN) {
204 dev_warn(&pt3->pdev->dev,
205 "(%s) I2C_M_RECV_LEN not supported.\n",
210 translate(cbuf, msgs, num);
211 memcpy_toio(pt3->regs[1] + PT3_I2C_BASE + PT3_CMD_ADDR_NORMAL / 2,
212 cbuf->data, cbuf->num_cmds);
214 if (send_i2c_cmd(pt3, PT3_CMD_ADDR_NORMAL) < 0)
217 p = pt3->regs[1] + PT3_I2C_BASE;
218 for (i = 0; i < num; i++)
219 if ((msgs[i].flags & I2C_M_RD) && msgs[i].len > 0) {
220 memcpy_fromio(msgs[i].buf, p, msgs[i].len);
227 u32 pt3_i2c_functionality(struct i2c_adapter *adap)