drivers/media/i2c/imx415.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Driver for the Sony IMX415 CMOS Image Sensor.
   4  *
   5  * Copyright (C) 2023 WolfVision GmbH.
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/gpio/consumer.h>
  10 #include <linux/i2c.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/pm_runtime.h>
  14 #include <linux/regmap.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/slab.h>
  17 #include <linux/videodev2.h>
  18
  19 #include <media/v4l2-ctrls.h>
  20 #include <media/v4l2-fwnode.h>
  21 #include <media/v4l2-subdev.h>
  22
  23 #define IMX415_PIXEL_ARRAY_TOP    0
  24 #define IMX415_PIXEL_ARRAY_LEFT   0
  25 #define IMX415_PIXEL_ARRAY_WIDTH  3864
  26 #define IMX415_PIXEL_ARRAY_HEIGHT 2192
  27 #define IMX415_PIXEL_ARRAY_VBLANK 58
  28
  29 #define IMX415_NUM_CLK_PARAM_REGS 11
  30
  31 #define IMX415_REG_8BIT(n)        ((1 << 16) | (n))
  32 #define IMX415_REG_16BIT(n)       ((2 << 16) | (n))
  33 #define IMX415_REG_24BIT(n)       ((3 << 16) | (n))
  34 #define IMX415_REG_SIZE_SHIFT     16
  35 #define IMX415_REG_ADDR_MASK      0xffff
  36
  37 #define IMX415_MODE               IMX415_REG_8BIT(0x3000)
  38 #define IMX415_MODE_OPERATING     (0)
  39 #define IMX415_MODE_STANDBY       BIT(0)
  40 #define IMX415_REGHOLD            IMX415_REG_8BIT(0x3001)
  41 #define IMX415_REGHOLD_INVALID    (0)
  42 #define IMX415_REGHOLD_VALID      BIT(0)
  43 #define IMX415_XMSTA              IMX415_REG_8BIT(0x3002)
  44 #define IMX415_XMSTA_START        (0)
  45 #define IMX415_XMSTA_STOP         BIT(0)
  46 #define IMX415_BCWAIT_TIME        IMX415_REG_16BIT(0x3008)
  47 #define IMX415_CPWAIT_TIME        IMX415_REG_16BIT(0x300A)
  48 #define IMX415_WINMODE            IMX415_REG_8BIT(0x301C)
  49 #define IMX415_ADDMODE            IMX415_REG_8BIT(0x3022)
  50 #define IMX415_REVERSE            IMX415_REG_8BIT(0x3030)
  51 #define IMX415_HREVERSE_SHIFT     (0)
  52 #define IMX415_VREVERSE_SHIFT     BIT(0)
  53 #define IMX415_ADBIT              IMX415_REG_8BIT(0x3031)
  54 #define IMX415_MDBIT              IMX415_REG_8BIT(0x3032)
  55 #define IMX415_SYS_MODE           IMX415_REG_8BIT(0x3033)
  56 #define IMX415_OUTSEL             IMX415_REG_8BIT(0x30C0)
  57 #define IMX415_DRV                IMX415_REG_8BIT(0x30C1)
  58 #define IMX415_VMAX               IMX415_REG_24BIT(0x3024)
  59 #define IMX415_HMAX               IMX415_REG_16BIT(0x3028)
  60 #define IMX415_SHR0               IMX415_REG_24BIT(0x3050)
  61 #define IMX415_GAIN_PCG_0         IMX415_REG_16BIT(0x3090)
  62 #define IMX415_AGAIN_MIN          0
  63 #define IMX415_AGAIN_MAX          100
  64 #define IMX415_AGAIN_STEP         1
  65 #define IMX415_BLKLEVEL           IMX415_REG_16BIT(0x30E2)
  66 #define IMX415_BLKLEVEL_DEFAULT   50
  67 #define IMX415_TPG_EN_DUOUT       IMX415_REG_8BIT(0x30E4)
  68 #define IMX415_TPG_PATSEL_DUOUT   IMX415_REG_8BIT(0x30E6)
  69 #define IMX415_TPG_COLORWIDTH     IMX415_REG_8BIT(0x30E8)
  70 #define IMX415_TESTCLKEN_MIPI     IMX415_REG_8BIT(0x3110)
  71 #define IMX415_INCKSEL1           IMX415_REG_8BIT(0x3115)
  72 #define IMX415_INCKSEL2           IMX415_REG_8BIT(0x3116)
  73 #define IMX415_INCKSEL3           IMX415_REG_16BIT(0x3118)
  74 #define IMX415_INCKSEL4           IMX415_REG_16BIT(0x311A)
  75 #define IMX415_INCKSEL5           IMX415_REG_8BIT(0x311E)
  76 #define IMX415_DIG_CLP_MODE       IMX415_REG_8BIT(0x32C8)
  77 #define IMX415_WRJ_OPEN           IMX415_REG_8BIT(0x3390)
  78 #define IMX415_SENSOR_INFO        IMX415_REG_16BIT(0x3F12)
  79 #define IMX415_SENSOR_INFO_MASK   0xFFF
  80 #define IMX415_CHIP_ID            0x514
  81 #define IMX415_LANEMODE           IMX415_REG_16BIT(0x4001)
  82 #define IMX415_LANEMODE_2         1
  83 #define IMX415_LANEMODE_4         3
  84 #define IMX415_TXCLKESC_FREQ      IMX415_REG_16BIT(0x4004)
  85 #define IMX415_INCKSEL6           IMX415_REG_8BIT(0x400C)
  86 #define IMX415_TCLKPOST           IMX415_REG_16BIT(0x4018)
  87 #define IMX415_TCLKPREPARE        IMX415_REG_16BIT(0x401A)
  88 #define IMX415_TCLKTRAIL          IMX415_REG_16BIT(0x401C)
  89 #define IMX415_TCLKZERO           IMX415_REG_16BIT(0x401E)
  90 #define IMX415_THSPREPARE         IMX415_REG_16BIT(0x4020)
  91 #define IMX415_THSZERO            IMX415_REG_16BIT(0x4022)
  92 #define IMX415_THSTRAIL           IMX415_REG_16BIT(0x4024)
  93 #define IMX415_THSEXIT            IMX415_REG_16BIT(0x4026)
  94 #define IMX415_TLPX               IMX415_REG_16BIT(0x4028)
  95 #define IMX415_INCKSEL7           IMX415_REG_8BIT(0x4074)
  96
  97 struct imx415_reg {
  98         u32 address;
  99         u32 val;
 100 };
 101
 102 static const char *const imx415_supply_names[] = {
 103         "dvdd",
 104         "ovdd",
 105         "avdd",
 106 };
 107
 108 /*
 109  * The IMX415 data sheet uses lane rates but v4l2 uses link frequency to
 110  * describe MIPI CSI-2 speed. This driver uses lane rates wherever possible
 111  * and converts them to link frequencies by a factor of two when needed.
 112  */
 113 static const s64 link_freq_menu_items[] = {
 114         594000000 / 2,  720000000 / 2,  891000000 / 2,
 115         1440000000 / 2, 1485000000 / 2,
 116 };
 117
 118 struct imx415_clk_params {
 119         u64 lane_rate;
 120         u64 inck;
 121         struct imx415_reg regs[IMX415_NUM_CLK_PARAM_REGS];
 122 };
 123
 124 /* INCK Settings - includes all lane rate and INCK dependent registers */
 125 static const struct imx415_clk_params imx415_clk_params[] = {
 126         {
 127                 .lane_rate = 594000000,
 128                 .inck = 27000000,
 129                 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
 130                 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
 131                 .regs[2] = { IMX415_SYS_MODE, 0x7 },
 132                 .regs[3] = { IMX415_INCKSEL1, 0x00 },
 133                 .regs[4] = { IMX415_INCKSEL2, 0x23 },
 134                 .regs[5] = { IMX415_INCKSEL3, 0x084 },
 135                 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
 136                 .regs[7] = { IMX415_INCKSEL5, 0x23 },
 137                 .regs[8] = { IMX415_INCKSEL6, 0x0 },
 138                 .regs[9] = { IMX415_INCKSEL7, 0x1 },
 139                 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
 140         },
 141         {
 142                 .lane_rate = 720000000,
 143                 .inck = 24000000,
 144                 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
 145                 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
 146                 .regs[2] = { IMX415_SYS_MODE, 0x9 },
 147                 .regs[3] = { IMX415_INCKSEL1, 0x00 },
 148                 .regs[4] = { IMX415_INCKSEL2, 0x23 },
 149                 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },
 150                 .regs[6] = { IMX415_INCKSEL4, 0x0FC },
 151                 .regs[7] = { IMX415_INCKSEL5, 0x23 },
 152                 .regs[8] = { IMX415_INCKSEL6, 0x0 },
 153                 .regs[9] = { IMX415_INCKSEL7, 0x1 },
 154                 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
 155         },
 156         {
 157                 .lane_rate = 891000000,
 158                 .inck = 27000000,
 159                 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
 160                 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
 161                 .regs[2] = { IMX415_SYS_MODE, 0x5 },
 162                 .regs[3] = { IMX415_INCKSEL1, 0x00 },
 163                 .regs[4] = { IMX415_INCKSEL2, 0x23 },
 164                 .regs[5] = { IMX415_INCKSEL3, 0x0C6 },
 165                 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
 166                 .regs[7] = { IMX415_INCKSEL5, 0x23 },
 167                 .regs[8] = { IMX415_INCKSEL6, 0x0 },
 168                 .regs[9] = { IMX415_INCKSEL7, 0x1 },
 169                 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
 170         },
 171         {
 172                 .lane_rate = 1440000000,
 173                 .inck = 24000000,
 174                 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
 175                 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
 176                 .regs[2] = { IMX415_SYS_MODE, 0x8 },
 177                 .regs[3] = { IMX415_INCKSEL1, 0x00 },
 178                 .regs[4] = { IMX415_INCKSEL2, 0x23 },
 179                 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },
 180                 .regs[6] = { IMX415_INCKSEL4, 0x0FC },
 181                 .regs[7] = { IMX415_INCKSEL5, 0x23 },
 182                 .regs[8] = { IMX415_INCKSEL6, 0x1 },
 183                 .regs[9] = { IMX415_INCKSEL7, 0x0 },
 184                 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
 185         },
 186         {
 187                 .lane_rate = 1485000000,
 188                 .inck = 27000000,
 189                 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
 190                 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
 191                 .regs[2] = { IMX415_SYS_MODE, 0x8 },
 192                 .regs[3] = { IMX415_INCKSEL1, 0x00 },
 193                 .regs[4] = { IMX415_INCKSEL2, 0x23 },
 194                 .regs[5] = { IMX415_INCKSEL3, 0x0A5 },
 195                 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },
 196                 .regs[7] = { IMX415_INCKSEL5, 0x23 },
 197                 .regs[8] = { IMX415_INCKSEL6, 0x1 },
 198                 .regs[9] = { IMX415_INCKSEL7, 0x0 },
 199                 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
 200         },
 201 };
 202
 203 /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
 204 static const struct imx415_reg imx415_mode_2_720[] = {
 205         { IMX415_VMAX, 0x08CA },
 206         { IMX415_HMAX, 0x07F0 },
 207         { IMX415_LANEMODE, IMX415_LANEMODE_2 },
 208         { IMX415_TCLKPOST, 0x006F },
 209         { IMX415_TCLKPREPARE, 0x002F },
 210         { IMX415_TCLKTRAIL, 0x002F },
 211         { IMX415_TCLKZERO, 0x00BF },
 212         { IMX415_THSPREPARE, 0x002F },
 213         { IMX415_THSZERO, 0x0057 },
 214         { IMX415_THSTRAIL, 0x002F },
 215         { IMX415_THSEXIT, 0x004F },
 216         { IMX415_TLPX, 0x0027 },
 217 };
 218
 219 /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
 220 static const struct imx415_reg imx415_mode_2_1440[] = {
 221         { IMX415_VMAX, 0x08CA },
 222         { IMX415_HMAX, 0x042A },
 223         { IMX415_LANEMODE, IMX415_LANEMODE_2 },
 224         { IMX415_TCLKPOST, 0x009F },
 225         { IMX415_TCLKPREPARE, 0x0057 },
 226         { IMX415_TCLKTRAIL, 0x0057 },
 227         { IMX415_TCLKZERO, 0x0187 },
 228         { IMX415_THSPREPARE, 0x005F },
 229         { IMX415_THSZERO, 0x00A7 },
 230         { IMX415_THSTRAIL, 0x005F },
 231         { IMX415_THSEXIT, 0x0097 },
 232         { IMX415_TLPX, 0x004F },
 233 };
 234
 235 /* all-pixel 4-lane 891 Mbps 30 Hz mode */
 236 static const struct imx415_reg imx415_mode_4_891[] = {
 237         { IMX415_VMAX, 0x08CA },
 238         { IMX415_HMAX, 0x044C },
 239         { IMX415_LANEMODE, IMX415_LANEMODE_4 },
 240         { IMX415_TCLKPOST, 0x007F },
 241         { IMX415_TCLKPREPARE, 0x0037 },
 242         { IMX415_TCLKTRAIL, 0x0037 },
 243         { IMX415_TCLKZERO, 0x00F7 },
 244         { IMX415_THSPREPARE, 0x003F },
 245         { IMX415_THSZERO, 0x006F },
 246         { IMX415_THSTRAIL, 0x003F },
 247         { IMX415_THSEXIT, 0x005F },
 248         { IMX415_TLPX, 0x002F },
 249 };
 250
 251 struct imx415_mode_reg_list {
 252         u32 num_of_regs;
 253         const struct imx415_reg *regs;
 254 };
 255
 256 /*
 257  * Mode : number of lanes, lane rate and frame rate dependent settings
 258  *
 259  * pixel_rate and hmax_pix are needed to calculate hblank for the v4l2 ctrl
 260  * interface. These values can not be found in the data sheet and should be
 261  * treated as virtual values. Use following table when adding new modes.
 262  *
 263  * lane_rate  lanes    fps     hmax_pix   pixel_rate
 264  *
 265  *     594      2     10.000     4400       99000000
 266  *     891      2     15.000     4400      148500000
 267  *     720      2     15.748     4064      144000000
 268  *    1782      2     30.000     4400      297000000
 269  *    2079      2     30.000     4400      297000000
 270  *    1440      2     30.019     4510      304615385
 271  *
 272  *     594      4     20.000     5500      247500000
 273  *     594      4     25.000     4400      247500000
 274  *     720      4     25.000     4400      247500000
 275  *     720      4     30.019     4510      304615385
 276  *     891      4     30.000     4400      297000000
 277  *    1440      4     30.019     4510      304615385
 278  *    1440      4     60.038     4510      609230769
 279  *    1485      4     60.000     4400      594000000
 280  *    1782      4     60.000     4400      594000000
 281  *    2079      4     60.000     4400      594000000
 282  *    2376      4     90.164     4392      891000000
 283  */
 284 struct imx415_mode {
 285         u64 lane_rate;
 286         u32 lanes;
 287         u32 hmax_pix;
 288         u64 pixel_rate;
 289         struct imx415_mode_reg_list reg_list;
 290 };
 291
 292 /* mode configs */
 293 static const struct imx415_mode supported_modes[] = {
 294         {
 295                 .lane_rate = 720000000,
 296                 .lanes = 2,
 297                 .hmax_pix = 4064,
 298                 .pixel_rate = 144000000,
 299                 .reg_list = {
 300                         .num_of_regs = ARRAY_SIZE(imx415_mode_2_720),
 301                         .regs = imx415_mode_2_720,
 302                 },
 303         },
 304         {
 305                 .lane_rate = 1440000000,
 306                 .lanes = 2,
 307                 .hmax_pix = 4510,
 308                 .pixel_rate = 304615385,
 309                 .reg_list = {
 310                         .num_of_regs = ARRAY_SIZE(imx415_mode_2_1440),
 311                         .regs = imx415_mode_2_1440,
 312                 },
 313         },
 314         {
 315                 .lane_rate = 891000000,
 316                 .lanes = 4,
 317                 .hmax_pix = 4400,
 318                 .pixel_rate = 297000000,
 319                 .reg_list = {
 320                         .num_of_regs = ARRAY_SIZE(imx415_mode_4_891),
 321                         .regs = imx415_mode_4_891,
 322                 },
 323         },
 324 };
 325
 326 static const struct regmap_config imx415_regmap_config = {
 327         .reg_bits = 16,
 328         .val_bits = 8,
 329 };
 330
 331 static const char *const imx415_test_pattern_menu[] = {
 332         "disabled",
 333         "solid black",
 334         "solid white",
 335         "solid dark gray",
 336         "solid light gray",
 337         "stripes light/dark grey",
 338         "stripes dark/light grey",
 339         "stripes black/dark grey",
 340         "stripes dark grey/black",
 341         "stripes black/white",
 342         "stripes white/black",
 343         "horizontal color bar",
 344         "vertical color bar",
 345 };
 346
 347 struct imx415 {
 348         struct device *dev;
 349         struct clk *clk;
 350         struct regulator_bulk_data supplies[ARRAY_SIZE(imx415_supply_names)];
 351         struct gpio_desc *reset;
 352         struct regmap *regmap;
 353
 354         const struct imx415_clk_params *clk_params;
 355
 356         bool streaming;
 357
 358         struct v4l2_subdev subdev;
 359         struct media_pad pad;
 360
 361         struct v4l2_ctrl_handler ctrls;
 362         struct v4l2_ctrl *vblank;
 363         struct v4l2_ctrl *hflip;
 364         struct v4l2_ctrl *vflip;
 365
 366         unsigned int cur_mode;
 367         unsigned int num_data_lanes;
 368 };
 369
 370 /*
 371  * This table includes fixed register settings and a bunch of undocumented
 372  * registers that have to be set to another value than default.
 373  */
 374 static const struct imx415_reg imx415_init_table[] = {
 375         /* use all-pixel readout mode, no flip */
 376         { IMX415_WINMODE, 0x00 },
 377         { IMX415_ADDMODE, 0x00 },
 378         { IMX415_REVERSE, 0x00 },
 379         /* use RAW 10-bit mode */
 380         { IMX415_ADBIT, 0x00 },
 381         { IMX415_MDBIT, 0x00 },
 382         /* output VSYNC on XVS and low on XHS */
 383         { IMX415_OUTSEL, 0x22 },
 384         { IMX415_DRV, 0x00 },
 385
 386         /* SONY magic registers */
 387         { IMX415_REG_8BIT(0x32D4), 0x21 },
 388         { IMX415_REG_8BIT(0x32EC), 0xA1 },
 389         { IMX415_REG_8BIT(0x3452), 0x7F },
 390         { IMX415_REG_8BIT(0x3453), 0x03 },
 391         { IMX415_REG_8BIT(0x358A), 0x04 },
 392         { IMX415_REG_8BIT(0x35A1), 0x02 },
 393         { IMX415_REG_8BIT(0x36BC), 0x0C },
 394         { IMX415_REG_8BIT(0x36CC), 0x53 },
 395         { IMX415_REG_8BIT(0x36CD), 0x00 },
 396         { IMX415_REG_8BIT(0x36CE), 0x3C },
 397         { IMX415_REG_8BIT(0x36D0), 0x8C },
 398         { IMX415_REG_8BIT(0x36D1), 0x00 },
 399         { IMX415_REG_8BIT(0x36D2), 0x71 },
 400         { IMX415_REG_8BIT(0x36D4), 0x3C },
 401         { IMX415_REG_8BIT(0x36D6), 0x53 },
 402         { IMX415_REG_8BIT(0x36D7), 0x00 },
 403         { IMX415_REG_8BIT(0x36D8), 0x71 },
 404         { IMX415_REG_8BIT(0x36DA), 0x8C },
 405         { IMX415_REG_8BIT(0x36DB), 0x00 },
 406         { IMX415_REG_8BIT(0x3724), 0x02 },
 407         { IMX415_REG_8BIT(0x3726), 0x02 },
 408         { IMX415_REG_8BIT(0x3732), 0x02 },
 409         { IMX415_REG_8BIT(0x3734), 0x03 },
 410         { IMX415_REG_8BIT(0x3736), 0x03 },
 411         { IMX415_REG_8BIT(0x3742), 0x03 },
 412         { IMX415_REG_8BIT(0x3862), 0xE0 },
 413         { IMX415_REG_8BIT(0x38CC), 0x30 },
 414         { IMX415_REG_8BIT(0x38CD), 0x2F },
 415         { IMX415_REG_8BIT(0x395C), 0x0C },
 416         { IMX415_REG_8BIT(0x3A42), 0xD1 },
 417         { IMX415_REG_8BIT(0x3A4C), 0x77 },
 418         { IMX415_REG_8BIT(0x3AE0), 0x02 },
 419         { IMX415_REG_8BIT(0x3AEC), 0x0C },
 420         { IMX415_REG_8BIT(0x3B00), 0x2E },
 421         { IMX415_REG_8BIT(0x3B06), 0x29 },
 422         { IMX415_REG_8BIT(0x3B98), 0x25 },
 423         { IMX415_REG_8BIT(0x3B99), 0x21 },
 424         { IMX415_REG_8BIT(0x3B9B), 0x13 },
 425         { IMX415_REG_8BIT(0x3B9C), 0x13 },
 426         { IMX415_REG_8BIT(0x3B9D), 0x13 },
 427         { IMX415_REG_8BIT(0x3B9E), 0x13 },
 428         { IMX415_REG_8BIT(0x3BA1), 0x00 },
 429         { IMX415_REG_8BIT(0x3BA2), 0x06 },
 430         { IMX415_REG_8BIT(0x3BA3), 0x0B },
 431         { IMX415_REG_8BIT(0x3BA4), 0x10 },
 432         { IMX415_REG_8BIT(0x3BA5), 0x14 },
 433         { IMX415_REG_8BIT(0x3BA6), 0x18 },
 434         { IMX415_REG_8BIT(0x3BA7), 0x1A },
 435         { IMX415_REG_8BIT(0x3BA8), 0x1A },
 436         { IMX415_REG_8BIT(0x3BA9), 0x1A },
 437         { IMX415_REG_8BIT(0x3BAC), 0xED },
 438         { IMX415_REG_8BIT(0x3BAD), 0x01 },
 439         { IMX415_REG_8BIT(0x3BAE), 0xF6 },
 440         { IMX415_REG_8BIT(0x3BAF), 0x02 },
 441         { IMX415_REG_8BIT(0x3BB0), 0xA2 },
 442         { IMX415_REG_8BIT(0x3BB1), 0x03 },
 443         { IMX415_REG_8BIT(0x3BB2), 0xE0 },
 444         { IMX415_REG_8BIT(0x3BB3), 0x03 },
 445         { IMX415_REG_8BIT(0x3BB4), 0xE0 },
 446         { IMX415_REG_8BIT(0x3BB5), 0x03 },
 447         { IMX415_REG_8BIT(0x3BB6), 0xE0 },
 448         { IMX415_REG_8BIT(0x3BB7), 0x03 },
 449         { IMX415_REG_8BIT(0x3BB8), 0xE0 },
 450         { IMX415_REG_8BIT(0x3BBA), 0xE0 },
 451         { IMX415_REG_8BIT(0x3BBC), 0xDA },
 452         { IMX415_REG_8BIT(0x3BBE), 0x88 },
 453         { IMX415_REG_8BIT(0x3BC0), 0x44 },
 454         { IMX415_REG_8BIT(0x3BC2), 0x7B },
 455         { IMX415_REG_8BIT(0x3BC4), 0xA2 },
 456         { IMX415_REG_8BIT(0x3BC8), 0xBD },
 457         { IMX415_REG_8BIT(0x3BCA), 0xBD },
 458 };
 459
 460 static inline struct imx415 *to_imx415(struct v4l2_subdev *sd)
 461 {
 462         return container_of(sd, struct imx415, subdev);
 463 }
 464
 465 static int imx415_read(struct imx415 *sensor, u32 addr)
 466 {
 467         u8 data[3] = { 0 };
 468         int ret;
 469
 470         ret = regmap_raw_read(sensor->regmap, addr & IMX415_REG_ADDR_MASK, data,
 471                               (addr >> IMX415_REG_SIZE_SHIFT) & 3);
 472         if (ret < 0)
 473                 return ret;
 474
 475         return (data[2] << 16) | (data[1] << 8) | data[0];
 476 }
 477
 478 static int imx415_write(struct imx415 *sensor, u32 addr, u32 value)
 479 {
 480         u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 };
 481         int ret;
 482
 483         ret = regmap_raw_write(sensor->regmap, addr & IMX415_REG_ADDR_MASK,
 484                                data, (addr >> IMX415_REG_SIZE_SHIFT) & 3);
 485         if (ret < 0)
 486                 dev_err_ratelimited(sensor->dev,
 487                                     "%u-bit write to 0x%04x failed: %d\n",
 488                                     ((addr >> IMX415_REG_SIZE_SHIFT) & 3) * 8,
 489                                     addr & IMX415_REG_ADDR_MASK, ret);
 490
 491         return 0;
 492 }
 493
 494 static int imx415_set_testpattern(struct imx415 *sensor, int val)
 495 {
 496         int ret;
 497
 498         if (val) {
 499                 ret = imx415_write(sensor, IMX415_BLKLEVEL, 0x00);
 500                 if (ret)
 501                         return ret;
 502                 ret = imx415_write(sensor, IMX415_TPG_EN_DUOUT, 0x01);
 503                 if (ret)
 504                         return ret;
 505                 ret = imx415_write(sensor, IMX415_TPG_PATSEL_DUOUT, val - 1);
 506                 if (ret)
 507                         return ret;
 508                 ret = imx415_write(sensor, IMX415_TPG_COLORWIDTH, 0x01);
 509                 if (ret)
 510                         return ret;
 511                 ret = imx415_write(sensor, IMX415_TESTCLKEN_MIPI, 0x20);
 512                 if (ret)
 513                         return ret;
 514                 ret = imx415_write(sensor, IMX415_DIG_CLP_MODE, 0x00);
 515                 if (ret)
 516                         return ret;
 517                 ret = imx415_write(sensor, IMX415_WRJ_OPEN, 0x00);
 518         } else {
 519                 ret = imx415_write(sensor, IMX415_BLKLEVEL,
 520                                    IMX415_BLKLEVEL_DEFAULT);
 521                 if (ret)
 522                         return ret;
 523                 ret = imx415_write(sensor, IMX415_TPG_EN_DUOUT, 0x00);
 524                 if (ret)
 525                         return ret;
 526                 ret = imx415_write(sensor, IMX415_TESTCLKEN_MIPI, 0x00);
 527                 if (ret)
 528                         return ret;
 529                 ret = imx415_write(sensor, IMX415_DIG_CLP_MODE, 0x01);
 530                 if (ret)
 531                         return ret;
 532                 ret = imx415_write(sensor, IMX415_WRJ_OPEN, 0x01);
 533         }
 534         return 0;
 535 }
 536
 537 static int imx415_s_ctrl(struct v4l2_ctrl *ctrl)
 538 {
 539         struct imx415 *sensor = container_of(ctrl->handler, struct imx415,
 540                                              ctrls);
 541         const struct v4l2_mbus_framefmt *format;
 542         struct v4l2_subdev_state *state;
 543         unsigned int vmax;
 544         unsigned int flip;
 545
 546         if (!sensor->streaming)
 547                 return 0;
 548
 549         state = v4l2_subdev_get_locked_active_state(&sensor->subdev);
 550         format = v4l2_subdev_get_pad_format(&sensor->subdev, state, 0);
 551
 552         switch (ctrl->id) {
 553         case V4L2_CID_EXPOSURE:
 554                 /* clamp the exposure value to VMAX. */
 555                 vmax = format->height + sensor->vblank->cur.val;
 556                 ctrl->val = min_t(int, ctrl->val, vmax);
 557                 return imx415_write(sensor, IMX415_SHR0, vmax - ctrl->val);
 558
 559         case V4L2_CID_ANALOGUE_GAIN:
 560                 /* analogue gain in 0.3 dB step size */
 561                 return imx415_write(sensor, IMX415_GAIN_PCG_0, ctrl->val);
 562
 563         case V4L2_CID_HFLIP:
 564         case V4L2_CID_VFLIP:
 565                 flip = (sensor->hflip->val << IMX415_HREVERSE_SHIFT) |
 566                        (sensor->vflip->val << IMX415_VREVERSE_SHIFT);
 567                 return imx415_write(sensor, IMX415_REVERSE, flip);
 568
 569         case V4L2_CID_TEST_PATTERN:
 570                 return imx415_set_testpattern(sensor, ctrl->val);
 571
 572         default:
 573                 return -EINVAL;
 574         }
 575 }
 576
 577 static const struct v4l2_ctrl_ops imx415_ctrl_ops = {
 578         .s_ctrl = imx415_s_ctrl,
 579 };
 580
 581 static int imx415_ctrls_init(struct imx415 *sensor)
 582 {
 583         struct v4l2_fwnode_device_properties props;
 584         struct v4l2_ctrl *ctrl;
 585         u64 pixel_rate = supported_modes[sensor->cur_mode].pixel_rate;
 586         u64 lane_rate = supported_modes[sensor->cur_mode].lane_rate;
 587         u32 exposure_max = IMX415_PIXEL_ARRAY_HEIGHT +
 588                            IMX415_PIXEL_ARRAY_VBLANK - 8;
 589         u32 hblank;
 590         unsigned int i;
 591         int ret;
 592
 593         ret = v4l2_fwnode_device_parse(sensor->dev, &props);
 594         if (ret < 0)
 595                 return ret;
 596
 597         v4l2_ctrl_handler_init(&sensor->ctrls, 10);
 598
 599         for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); ++i) {
 600                 if (lane_rate == link_freq_menu_items[i] * 2)
 601                         break;
 602         }
 603         if (i == ARRAY_SIZE(link_freq_menu_items)) {
 604                 return dev_err_probe(sensor->dev, -EINVAL,
 605                                      "lane rate %llu not supported\n",
 606                                      lane_rate);
 607         }
 608
 609         ctrl = v4l2_ctrl_new_int_menu(&sensor->ctrls, &imx415_ctrl_ops,
 610                                       V4L2_CID_LINK_FREQ,
 611                                       ARRAY_SIZE(link_freq_menu_items) - 1, i,
 612                                       link_freq_menu_items);
 613
 614         if (ctrl)
 615                 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 616
 617         v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, V4L2_CID_EXPOSURE,
 618                           4, exposure_max, 1, exposure_max);
 619
 620         v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
 621                           V4L2_CID_ANALOGUE_GAIN, IMX415_AGAIN_MIN,
 622                           IMX415_AGAIN_MAX, IMX415_AGAIN_STEP,
 623                           IMX415_AGAIN_MIN);
 624
 625         hblank = supported_modes[sensor->cur_mode].hmax_pix -
 626                  IMX415_PIXEL_ARRAY_WIDTH;
 627         ctrl = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
 628                                  V4L2_CID_HBLANK, hblank, hblank, 1, hblank);
 629         if (ctrl)
 630                 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 631
 632         sensor->vblank = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
 633                                            V4L2_CID_VBLANK,
 634                                            IMX415_PIXEL_ARRAY_VBLANK,
 635                                            IMX415_PIXEL_ARRAY_VBLANK, 1,
 636                                            IMX415_PIXEL_ARRAY_VBLANK);
 637         if (sensor->vblank)
 638                 sensor->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 639
 640         /*
 641          * The pixel rate used here is a virtual value and can be used for
 642          * calculating the frame rate together with hblank. It may not
 643          * necessarily be the physically correct pixel clock.
 644          */
 645         v4l2_ctrl_new_std(&sensor->ctrls, NULL, V4L2_CID_PIXEL_RATE, pixel_rate,
 646                           pixel_rate, 1, pixel_rate);
 647
 648         sensor->hflip = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
 649                                           V4L2_CID_HFLIP, 0, 1, 1, 0);
 650         sensor->vflip = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,
 651                                           V4L2_CID_VFLIP, 0, 1, 1, 0);
 652
 653         v4l2_ctrl_new_std_menu_items(&sensor->ctrls, &imx415_ctrl_ops,
 654                                      V4L2_CID_TEST_PATTERN,
 655                                      ARRAY_SIZE(imx415_test_pattern_menu) - 1,
 656                                      0, 0, imx415_test_pattern_menu);
 657
 658         v4l2_ctrl_new_fwnode_properties(&sensor->ctrls, &imx415_ctrl_ops,
 659                                         &props);
 660
 661         if (sensor->ctrls.error) {
 662                 dev_err_probe(sensor->dev, sensor->ctrls.error,
 663                               "failed to add controls\n");
 664                 v4l2_ctrl_handler_free(&sensor->ctrls);
 665                 return sensor->ctrls.error;
 666         }
 667         sensor->subdev.ctrl_handler = &sensor->ctrls;
 668
 669         return 0;
 670 }
 671
 672 static int imx415_set_mode(struct imx415 *sensor, int mode)
 673 {
 674         const struct imx415_reg *reg;
 675         unsigned int i;
 676         int ret = 0;
 677
 678         if (mode >= ARRAY_SIZE(supported_modes)) {
 679                 dev_err(sensor->dev, "Mode %d not supported\n", mode);
 680                 return -EINVAL;
 681         }
 682
 683         for (i = 0; i < supported_modes[mode].reg_list.num_of_regs; ++i) {
 684                 reg = &supported_modes[mode].reg_list.regs[i];
 685                 ret = imx415_write(sensor, reg->address, reg->val);
 686                 if (ret)
 687                         return ret;
 688         }
 689
 690         for (i = 0; i < IMX415_NUM_CLK_PARAM_REGS; ++i) {
 691                 reg = &sensor->clk_params->regs[i];
 692                 ret = imx415_write(sensor, reg->address, reg->val);
 693                 if (ret)
 694                         return ret;
 695         }
 696
 697         return 0;
 698 }
 699
 700 static int imx415_setup(struct imx415 *sensor, struct v4l2_subdev_state *state)
 701 {
 702         unsigned int i;
 703         int ret;
 704
 705         for (i = 0; i < ARRAY_SIZE(imx415_init_table); ++i) {
 706                 ret = imx415_write(sensor, imx415_init_table[i].address,
 707                                    imx415_init_table[i].val);
 708                 if (ret)
 709                         return ret;
 710         }
 711
 712         return imx415_set_mode(sensor, sensor->cur_mode);
 713 }
 714
 715 static int imx415_wakeup(struct imx415 *sensor)
 716 {
 717         int ret;
 718
 719         ret = imx415_write(sensor, IMX415_MODE, IMX415_MODE_OPERATING);
 720         if (ret)
 721                 return ret;
 722
 723         /*
 724          * According to the datasheet we have to wait at least 63 us after
 725          * leaving standby mode. But this doesn't work even after 30 ms.
 726          * So probably this should be 63 ms and therefore we wait for 80 ms.
 727          */
 728         msleep(80);
 729
 730         return 0;
 731 }
 732
 733 static int imx415_stream_on(struct imx415 *sensor)
 734 {
 735         int ret;
 736
 737         ret = imx415_wakeup(sensor);
 738         if (ret)
 739                 return ret;
 740
 741         return imx415_write(sensor, IMX415_XMSTA, IMX415_XMSTA_START);
 742 }
 743
 744 static int imx415_stream_off(struct imx415 *sensor)
 745 {
 746         int ret;
 747
 748         ret = imx415_write(sensor, IMX415_XMSTA, IMX415_XMSTA_STOP);
 749         if (ret)
 750                 return ret;
 751
 752         return imx415_write(sensor, IMX415_MODE, IMX415_MODE_STANDBY);
 753 }
 754
 755 static int imx415_s_stream(struct v4l2_subdev *sd, int enable)
 756 {
 757         struct imx415 *sensor = to_imx415(sd);
 758         struct v4l2_subdev_state *state;
 759         int ret;
 760
 761         state = v4l2_subdev_lock_and_get_active_state(sd);
 762
 763         if (!enable) {
 764                 ret = imx415_stream_off(sensor);
 765
 766                 pm_runtime_mark_last_busy(sensor->dev);
 767                 pm_runtime_put_autosuspend(sensor->dev);
 768
 769                 sensor->streaming = false;
 770
 771                 goto unlock;
 772         }
 773
 774         ret = pm_runtime_resume_and_get(sensor->dev);
 775         if (ret < 0)
 776                 goto unlock;
 777
 778         ret = imx415_setup(sensor, state);
 779         if (ret)
 780                 goto err_pm;
 781
 782         /*
 783          * Set streaming to true to ensure __v4l2_ctrl_handler_setup() will set
 784          * the controls. The flag is reset to false further down if an error
 785          * occurs.
 786          */
 787         sensor->streaming = true;
 788
 789         ret = __v4l2_ctrl_handler_setup(&sensor->ctrls);
 790         if (ret < 0)
 791                 goto err_pm;
 792
 793         ret = imx415_stream_on(sensor);
 794         if (ret)
 795                 goto err_pm;
 796
 797         ret = 0;
 798
 799 unlock:
 800         v4l2_subdev_unlock_state(state);
 801
 802         return ret;
 803
 804 err_pm:
 805         /*
 806          * In case of error, turn the power off synchronously as the device
 807          * likely has no other chance to recover.
 808          */
 809         pm_runtime_put_sync(sensor->dev);
 810         sensor->streaming = false;
 811
 812         goto unlock;
 813 }
 814
 815 static int imx415_enum_mbus_code(struct v4l2_subdev *sd,
 816                                  struct v4l2_subdev_state *state,
 817                                  struct v4l2_subdev_mbus_code_enum *code)
 818 {
 819         if (code->index != 0)
 820                 return -EINVAL;
 821
 822         code->code = MEDIA_BUS_FMT_SGBRG10_1X10;
 823
 824         return 0;
 825 }
 826
 827 static int imx415_enum_frame_size(struct v4l2_subdev *sd,
 828                                   struct v4l2_subdev_state *state,
 829                                   struct v4l2_subdev_frame_size_enum *fse)
 830 {
 831         const struct v4l2_mbus_framefmt *format;
 832
 833         format = v4l2_subdev_get_pad_format(sd, state, fse->pad);
 834
 835         if (fse->index > 0 || fse->code != format->code)
 836                 return -EINVAL;
 837
 838         fse->min_width = IMX415_PIXEL_ARRAY_WIDTH;
 839         fse->max_width = fse->min_width;
 840         fse->min_height = IMX415_PIXEL_ARRAY_HEIGHT;
 841         fse->max_height = fse->min_height;
 842         return 0;
 843 }
 844
 845 static int imx415_get_format(struct v4l2_subdev *sd,
 846                              struct v4l2_subdev_state *state,
 847                              struct v4l2_subdev_format *fmt)
 848 {
 849         fmt->format = *v4l2_subdev_get_pad_format(sd, state, fmt->pad);
 850
 851         return 0;
 852 }
 853
 854 static int imx415_set_format(struct v4l2_subdev *sd,
 855                              struct v4l2_subdev_state *state,
 856                              struct v4l2_subdev_format *fmt)
 857 {
 858         struct v4l2_mbus_framefmt *format;
 859
 860         format = v4l2_subdev_get_pad_format(sd, state, fmt->pad);
 861
 862         format->width = fmt->format.width;
 863         format->height = fmt->format.height;
 864         format->code = MEDIA_BUS_FMT_SGBRG10_1X10;
 865         format->field = V4L2_FIELD_NONE;
 866         format->colorspace = V4L2_COLORSPACE_RAW;
 867         format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
 868         format->quantization = V4L2_QUANTIZATION_DEFAULT;
 869         format->xfer_func = V4L2_XFER_FUNC_NONE;
 870
 871         fmt->format = *format;
 872         return 0;
 873 }
 874
 875 static int imx415_get_selection(struct v4l2_subdev *sd,
 876                                 struct v4l2_subdev_state *sd_state,
 877                                 struct v4l2_subdev_selection *sel)
 878 {
 879         switch (sel->target) {
 880         case V4L2_SEL_TGT_CROP:
 881         case V4L2_SEL_TGT_CROP_DEFAULT:
 882         case V4L2_SEL_TGT_CROP_BOUNDS:
 883                 sel->r.top = IMX415_PIXEL_ARRAY_TOP;
 884                 sel->r.left = IMX415_PIXEL_ARRAY_LEFT;
 885                 sel->r.width = IMX415_PIXEL_ARRAY_WIDTH;
 886                 sel->r.height = IMX415_PIXEL_ARRAY_HEIGHT;
 887
 888                 return 0;
 889         }
 890
 891         return -EINVAL;
 892 }
 893
 894 static int imx415_init_cfg(struct v4l2_subdev *sd,
 895                            struct v4l2_subdev_state *state)
 896 {
 897         struct v4l2_subdev_format format = {
 898                 .format = {
 899                         .width = IMX415_PIXEL_ARRAY_WIDTH,
 900                         .height = IMX415_PIXEL_ARRAY_HEIGHT,
 901                 },
 902         };
 903
 904         imx415_set_format(sd, state, &format);
 905
 906         return 0;
 907 }
 908
 909 static const struct v4l2_subdev_video_ops imx415_subdev_video_ops = {
 910         .s_stream = imx415_s_stream,
 911 };
 912
 913 static const struct v4l2_subdev_pad_ops imx415_subdev_pad_ops = {
 914         .enum_mbus_code = imx415_enum_mbus_code,
 915         .enum_frame_size = imx415_enum_frame_size,
 916         .get_fmt = imx415_get_format,
 917         .set_fmt = imx415_set_format,
 918         .get_selection = imx415_get_selection,
 919         .init_cfg = imx415_init_cfg,
 920 };
 921
 922 static const struct v4l2_subdev_ops imx415_subdev_ops = {
 923         .video = &imx415_subdev_video_ops,
 924         .pad = &imx415_subdev_pad_ops,
 925 };
 926
 927 static int imx415_subdev_init(struct imx415 *sensor)
 928 {
 929         struct i2c_client *client = to_i2c_client(sensor->dev);
 930         int ret;
 931
 932         v4l2_i2c_subdev_init(&sensor->subdev, client, &imx415_subdev_ops);
 933
 934         ret = imx415_ctrls_init(sensor);
 935         if (ret)
 936                 return ret;
 937
 938         sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
 939                                 V4L2_SUBDEV_FL_HAS_EVENTS;
 940         sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
 941         sensor->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
 942         ret = media_entity_pads_init(&sensor->subdev.entity, 1, &sensor->pad);
 943         if (ret < 0) {
 944                 v4l2_ctrl_handler_free(&sensor->ctrls);
 945                 return ret;
 946         }
 947
 948         sensor->subdev.state_lock = sensor->subdev.ctrl_handler->lock;
 949         v4l2_subdev_init_finalize(&sensor->subdev);
 950
 951         return 0;
 952 }
 953
 954 static void imx415_subdev_cleanup(struct imx415 *sensor)
 955 {
 956         media_entity_cleanup(&sensor->subdev.entity);
 957         v4l2_ctrl_handler_free(&sensor->ctrls);
 958 }
 959
 960 static int imx415_power_on(struct imx415 *sensor)
 961 {
 962         int ret;
 963
 964         ret = regulator_bulk_enable(ARRAY_SIZE(sensor->supplies),
 965                                     sensor->supplies);
 966         if (ret < 0)
 967                 return ret;
 968
 969         gpiod_set_value_cansleep(sensor->reset, 0);
 970
 971         udelay(1);
 972
 973         ret = clk_prepare_enable(sensor->clk);
 974         if (ret < 0)
 975                 goto err_reset;
 976
 977         /*
 978          * Data sheet states that 20 us are required before communication start,
 979          * but this doesn't work in all cases. Use 100 us to be on the safe
 980          * side.
 981          */
 982         usleep_range(100, 200);
 983
 984         return 0;
 985
 986 err_reset:
 987         gpiod_set_value_cansleep(sensor->reset, 1);
 988         regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies);
 989         return ret;
 990 }
 991
 992 static void imx415_power_off(struct imx415 *sensor)
 993 {
 994         clk_disable_unprepare(sensor->clk);
 995         gpiod_set_value_cansleep(sensor->reset, 1);
 996         regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies);
 997 }
 998
 999 static int imx415_identify_model(struct imx415 *sensor)
1000 {
1001         int model, ret;
1002
1003         /*
1004          * While most registers can be read when the sensor is in standby, this
1005          * is not the case of the sensor info register :-(
1006          */
1007         ret = imx415_wakeup(sensor);
1008         if (ret)
1009                 return dev_err_probe(sensor->dev, ret,
1010                                      "failed to get sensor out of standby\n");
1011
1012         ret = imx415_read(sensor, IMX415_SENSOR_INFO);
1013         if (ret < 0) {
1014                 dev_err_probe(sensor->dev, ret,
1015                               "failed to read sensor information\n");
1016                 goto done;
1017         }
1018
1019         model = ret & IMX415_SENSOR_INFO_MASK;
1020
1021         switch (model) {
1022         case IMX415_CHIP_ID:
1023                 dev_info(sensor->dev, "Detected IMX415 image sensor\n");
1024                 break;
1025         default:
1026                 ret = dev_err_probe(sensor->dev, -ENODEV,
1027                                     "invalid device model 0x%04x\n", model);
1028                 goto done;
1029         }
1030
1031         ret = 0;
1032
1033 done:
1034         imx415_write(sensor, IMX415_MODE, IMX415_MODE_STANDBY);
1035         return ret;
1036 }
1037
1038 static int imx415_check_inck(unsigned long inck, u64 link_frequency)
1039 {
1040         unsigned int i;
1041
1042         for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {
1043                 if ((imx415_clk_params[i].lane_rate == link_frequency * 2) &&
1044                     imx415_clk_params[i].inck == inck)
1045                         break;
1046         }
1047
1048         if (i == ARRAY_SIZE(imx415_clk_params))
1049                 return -EINVAL;
1050         else
1051                 return 0;
1052 }
1053
1054 static int imx415_parse_hw_config(struct imx415 *sensor)
1055 {
1056         struct v4l2_fwnode_endpoint bus_cfg = {
1057                 .bus_type = V4L2_MBUS_CSI2_DPHY,
1058         };
1059         struct fwnode_handle *ep;
1060         u64 lane_rate;
1061         unsigned long inck;
1062         unsigned int i, j;
1063         int ret;
1064
1065         for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i)
1066                 sensor->supplies[i].supply = imx415_supply_names[i];
1067
1068         ret = devm_regulator_bulk_get(sensor->dev, ARRAY_SIZE(sensor->supplies),
1069                                       sensor->supplies);
1070         if (ret)
1071                 return dev_err_probe(sensor->dev, ret,
1072                                      "failed to get supplies\n");
1073
1074         sensor->reset = devm_gpiod_get_optional(sensor->dev, "reset",
1075                                                 GPIOD_OUT_HIGH);
1076         if (IS_ERR(sensor->reset))
1077                 return dev_err_probe(sensor->dev, PTR_ERR(sensor->reset),
1078                                      "failed to get reset GPIO\n");
1079
1080         sensor->clk = devm_clk_get(sensor->dev, "inck");
1081         if (IS_ERR(sensor->clk))
1082                 return dev_err_probe(sensor->dev, PTR_ERR(sensor->clk),
1083                                      "failed to get clock\n");
1084
1085         ep = fwnode_graph_get_next_endpoint(dev_fwnode(sensor->dev), NULL);
1086         if (!ep)
1087                 return -ENXIO;
1088
1089         ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1090         fwnode_handle_put(ep);
1091         if (ret)
1092                 return ret;
1093
1094         switch (bus_cfg.bus.mipi_csi2.num_data_lanes) {
1095         case 2:
1096         case 4:
1097                 sensor->num_data_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
1098                 break;
1099         default:
1100                 ret = dev_err_probe(sensor->dev, -EINVAL,
1101                                     "invalid number of CSI2 data lanes %d\n",
1102                                     bus_cfg.bus.mipi_csi2.num_data_lanes);
1103                 goto done_endpoint_free;
1104         }
1105
1106         if (!bus_cfg.nr_of_link_frequencies) {
1107                 ret = dev_err_probe(sensor->dev, -EINVAL,
1108                                     "no link frequencies defined");
1109                 goto done_endpoint_free;
1110         }
1111
1112         /*
1113          * Check if there exists a sensor mode defined for current INCK,
1114          * number of lanes and given lane rates.
1115          */
1116         inck = clk_get_rate(sensor->clk);
1117         for (i = 0; i < bus_cfg.nr_of_link_frequencies; ++i) {
1118                 if (imx415_check_inck(inck, bus_cfg.link_frequencies[i])) {
1119                         dev_dbg(sensor->dev,
1120                                 "INCK %lu Hz not supported for this link freq",
1121                                 inck);
1122                         continue;
1123                 }
1124
1125                 for (j = 0; j < ARRAY_SIZE(supported_modes); ++j) {
1126                         if (sensor->num_data_lanes != supported_modes[j].lanes)
1127                                 continue;
1128                         if (bus_cfg.link_frequencies[i] * 2 !=
1129                             supported_modes[j].lane_rate)
1130                                 continue;
1131                         sensor->cur_mode = j;
1132                         break;
1133                 }
1134                 if (j < ARRAY_SIZE(supported_modes))
1135                         break;
1136         }
1137         if (i == bus_cfg.nr_of_link_frequencies) {
1138                 ret = dev_err_probe(sensor->dev, -EINVAL,
1139                                     "no valid sensor mode defined\n");
1140                 goto done_endpoint_free;
1141         }
1142
1143         lane_rate = supported_modes[sensor->cur_mode].lane_rate;
1144         for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {
1145                 if (lane_rate == imx415_clk_params[i].lane_rate &&
1146                     inck == imx415_clk_params[i].inck) {
1147                         sensor->clk_params = &imx415_clk_params[i];
1148                         break;
1149                 }
1150         }
1151         if (i == ARRAY_SIZE(imx415_clk_params)) {
1152                 ret = dev_err_probe(sensor->dev, -EINVAL,
1153                                     "Mode %d not supported\n",
1154                                     sensor->cur_mode);
1155                 goto done_endpoint_free;
1156         }
1157
1158         ret = 0;
1159         dev_dbg(sensor->dev, "clock: %lu Hz, lane_rate: %llu bps, lanes: %d\n",
1160                 inck, lane_rate, sensor->num_data_lanes);
1161
1162 done_endpoint_free:
1163         v4l2_fwnode_endpoint_free(&bus_cfg);
1164
1165         return ret;
1166 }
1167
1168 static int imx415_probe(struct i2c_client *client)
1169 {
1170         struct imx415 *sensor;
1171         int ret;
1172
1173         sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
1174         if (!sensor)
1175                 return -ENOMEM;
1176
1177         sensor->dev = &client->dev;
1178
1179         ret = imx415_parse_hw_config(sensor);
1180         if (ret)
1181                 return ret;
1182
1183         sensor->regmap = devm_regmap_init_i2c(client, &imx415_regmap_config);
1184         if (IS_ERR(sensor->regmap))
1185                 return PTR_ERR(sensor->regmap);
1186
1187         /*
1188          * Enable power management. The driver supports runtime PM, but needs to
1189          * work when runtime PM is disabled in the kernel. To that end, power
1190          * the sensor on manually here, identify it, and fully initialize it.
1191          */
1192         ret = imx415_power_on(sensor);
1193         if (ret)
1194                 return ret;
1195
1196         ret = imx415_identify_model(sensor);
1197         if (ret)
1198                 goto err_power;
1199
1200         ret = imx415_subdev_init(sensor);
1201         if (ret)
1202                 goto err_power;
1203
1204         /*
1205          * Enable runtime PM. As the device has been powered manually, mark it
1206          * as active, and increase the usage count without resuming the device.
1207          */
1208         pm_runtime_set_active(sensor->dev);
1209         pm_runtime_get_noresume(sensor->dev);
1210         pm_runtime_enable(sensor->dev);
1211
1212         ret = v4l2_async_register_subdev_sensor(&sensor->subdev);
1213         if (ret < 0)
1214                 goto err_pm;
1215
1216         /*
1217          * Finally, enable autosuspend and decrease the usage count. The device
1218          * will get suspended after the autosuspend delay, turning the power
1219          * off.
1220          */
1221         pm_runtime_set_autosuspend_delay(sensor->dev, 1000);
1222         pm_runtime_use_autosuspend(sensor->dev);
1223         pm_runtime_put_autosuspend(sensor->dev);
1224
1225         return 0;
1226
1227 err_pm:
1228         pm_runtime_disable(sensor->dev);
1229         pm_runtime_put_noidle(sensor->dev);
1230         imx415_subdev_cleanup(sensor);
1231 err_power:
1232         imx415_power_off(sensor);
1233         return ret;
1234 }
1235
1236 static void imx415_remove(struct i2c_client *client)
1237 {
1238         struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1239         struct imx415 *sensor = to_imx415(subdev);
1240
1241         v4l2_async_unregister_subdev(subdev);
1242
1243         imx415_subdev_cleanup(sensor);
1244
1245         /*
1246          * Disable runtime PM. In case runtime PM is disabled in the kernel,
1247          * make sure to turn power off manually.
1248          */
1249         pm_runtime_disable(sensor->dev);
1250         if (!pm_runtime_status_suspended(sensor->dev))
1251                 imx415_power_off(sensor);
1252         pm_runtime_set_suspended(sensor->dev);
1253 }
1254
1255 static int imx415_runtime_resume(struct device *dev)
1256 {
1257         struct i2c_client *client = to_i2c_client(dev);
1258         struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1259         struct imx415 *sensor = to_imx415(subdev);
1260
1261         return imx415_power_on(sensor);
1262 }
1263
1264 static int imx415_runtime_suspend(struct device *dev)
1265 {
1266         struct i2c_client *client = to_i2c_client(dev);
1267         struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1268         struct imx415 *sensor = to_imx415(subdev);
1269
1270         imx415_power_off(sensor);
1271
1272         return 0;
1273 }
1274
1275 static DEFINE_RUNTIME_DEV_PM_OPS(imx415_pm_ops, imx415_runtime_suspend,
1276                                  imx415_runtime_resume, NULL);
1277
1278 static const struct of_device_id imx415_of_match[] = {
1279         { .compatible = "sony,imx415" },
1280         { /* sentinel */ }
1281 };
1282
1283 MODULE_DEVICE_TABLE(of, imx415_of_match);
1284
1285 static struct i2c_driver imx415_driver = {
1286         .probe_new = imx415_probe,
1287         .remove = imx415_remove,
1288         .driver = {
1289                 .name = "imx415",
1290                 .of_match_table = imx415_of_match,
1291                 .pm = pm_ptr(&imx415_pm_ops),
1292         },
1293 };
1294
1295 module_i2c_driver(imx415_driver);
1296
1297 MODULE_DESCRIPTION("Sony IMX415 image sensor driver");
1298 MODULE_AUTHOR("Gerald Loacker <[email protected]>");
1299 MODULE_AUTHOR("Michael Riesch <[email protected]>");
1300 MODULE_LICENSE("GPL");