drivers/interconnect/qcom/sm6350.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2022 Luca Weiss <[email protected]>
   4  */
   5
   6 #include <linux/device.h>
   7 #include <linux/interconnect.h>
   8 #include <linux/interconnect-provider.h>
   9 #include <linux/module.h>
  10 #include <linux/of_platform.h>
  11 #include <dt-bindings/interconnect/qcom,sm6350.h>
  12
  13 #include "bcm-voter.h"
  14 #include "icc-rpmh.h"
  15 #include "sm6350.h"
  16
  17 DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A1NOC);
  18 DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV);
  19 DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV);
  20 DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SLV);
  21 DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A2NOC);
  22 DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC_SLV);
  23 DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV);
  24 DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_SNOC_SLV);
  25 DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV);
  26 DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_SLV);
  27 DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV);
  28 DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV);
  29 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32, SM6350_SLAVE_CAMNOC_UNCOMP);
  30 DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP);
  31 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP);
  32 DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAVE_QUP_CORE_0);
  33 DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAVE_QUP_CORE_1);
  34 DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC);
  35 DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_GEM_NOC);
  36 DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL);
  37 DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL);
  38 DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAVE_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG);
  39 DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
  40 DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
  41 DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE_MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG);
  42 DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
  43 DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
  44 DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
  45 DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAVE_LLCC);
  46 DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLAVE_LLCC);
  47 DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC);
  48 DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0);
  49 DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_MNOC);
  50 DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC);
  51 DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC);
  52 DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC);
  53 DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC);
  54 DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC);
  55 DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC);
  56 DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_COMPUTE_NOC);
  57 DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM6350_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM);
  58 DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_SNOC);
  59 DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM);
  60 DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM);
  61 DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM);
  62 DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC, SM6350_SLAVE_OCIMEM);
  63 DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC);
  64 DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SNOC_MAS);
  65 DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4);
  66 DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SNOC_MAS);
  67 DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4);
  68 DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32);
  69 DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4);
  70 DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4);
  71 DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MASTER_COMPUTE_NOC);
  72 DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A1NOC_CFG);
  73 DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A2NOC_CFG);
  74 DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4);
  75 DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4);
  76 DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4);
  77 DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4);
  78 DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4);
  79 DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4);
  80 DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4);
  81 DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4);
  82 DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4);
  83 DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4);
  84 DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4);
  85 DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4);
  86 DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_CNOC_DC_NOC);
  87 DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4);
  88 DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4);
  89 DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4);
  90 DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4);
  91 DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8);
  92 DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4);
  93 DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4);
  94 DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER_CNOC_MNOC_CFG);
  95 DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4);
  96 DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NOC_CFG);
  97 DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4);
  98 DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4);
  99 DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4);
 100 DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4);
 101 DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4);
 102 DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4);
 103 DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4);
 104 DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4);
 105 DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4);
 106 DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4);
 107 DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC_CFG);
 108 DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4);
 109 DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4);
 110 DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4);
 111 DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4);
 112 DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4);
 113 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4);
 114 DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4);
 115 DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM_NOC_CFG);
 116 DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4);
 117 DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4);
 118 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4);
 119 DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MASTER_GEM_NOC_SNOC);
 120 DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC);
 121 DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4);
 122 DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4);
 123 DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_HF_MEM_NOC);
 124 DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_SF_MEM_NOC);
 125 DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4);
 126 DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4);
 127 DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4);
 128 DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4);
 129 DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4);
 130 DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4);
 131 DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4);
 132 DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4);
 133 DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32);
 134 DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4);
 135 DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8);
 136 DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS);
 137 DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MASTER_SNOC_GC_MEM_NOC);
 138 DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MASTER_SNOC_SF_MEM_NOC);
 139 DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8);
 140 DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8);
 141 DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4);
 142 DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4);
 143 DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8);
 144
 145 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
 146 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
 147 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc);
 148 DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_sdc2);
 149 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc);
 150 DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu);
 151 DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp);
 152 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
 153 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
 154 DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0);
 155 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
 156 DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf);
 157 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave);
 158 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
 159 DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
 160 DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
 161 DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps);
 162 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
 163 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
 164 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);
 165 DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem);
 166 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm);
 167 DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc);
 168 DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc);
 169 DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc);
 170
 171 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
 172         &bcm_cn1,
 173 };
 174
 175 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
 176         [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
 177         [MASTER_QUP_0] = &qhm_qup_0,
 178         [MASTER_EMMC] = &xm_emmc,
 179         [MASTER_UFS_MEM] = &xm_ufs_mem,
 180         [A1NOC_SNOC_SLV] = &qns_a1noc_snoc,
 181         [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
 182 };
 183
 184 static const struct qcom_icc_desc sm6350_aggre1_noc = {
 185         .nodes = aggre1_noc_nodes,
 186         .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
 187         .bcms = aggre1_noc_bcms,
 188         .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
 189 };
 190
 191 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
 192         &bcm_ce0,
 193         &bcm_cn1,
 194 };
 195
 196 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
 197         [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
 198         [MASTER_QDSS_BAM] = &qhm_qdss_bam,
 199         [MASTER_QUP_1] = &qhm_qup_1,
 200         [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
 201         [MASTER_IPA] = &qxm_ipa,
 202         [MASTER_QDSS_ETR] = &xm_qdss_etr,
 203         [MASTER_SDCC_2] = &xm_sdc2,
 204         [MASTER_USB3] = &xm_usb3_0,
 205         [A2NOC_SNOC_SLV] = &qns_a2noc_snoc,
 206         [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
 207 };
 208
 209 static const struct qcom_icc_desc sm6350_aggre2_noc = {
 210         .nodes = aggre2_noc_nodes,
 211         .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
 212         .bcms = aggre2_noc_bcms,
 213         .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
 214 };
 215
 216 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
 217         &bcm_acv,
 218         &bcm_mc0,
 219         &bcm_mm1,
 220         &bcm_qup0,
 221 };
 222
 223 static struct qcom_icc_node * const clk_virt_nodes[] = {
 224         [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp,
 225         [MASTER_CAMNOC_ICP_UNCOMP] = &qxm_camnoc_icp_uncomp,
 226         [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp,
 227         [MASTER_QUP_CORE_0] = &qup0_core_master,
 228         [MASTER_QUP_CORE_1] = &qup1_core_master,
 229         [MASTER_LLCC] = &llcc_mc,
 230         [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp,
 231         [SLAVE_QUP_CORE_0] = &qup0_core_slave,
 232         [SLAVE_QUP_CORE_1] = &qup1_core_slave,
 233         [SLAVE_EBI_CH0] = &ebi,
 234 };
 235
 236 static const struct qcom_icc_desc sm6350_clk_virt = {
 237         .nodes = clk_virt_nodes,
 238         .num_nodes = ARRAY_SIZE(clk_virt_nodes),
 239         .bcms = clk_virt_bcms,
 240         .num_bcms = ARRAY_SIZE(clk_virt_bcms),
 241 };
 242
 243 static struct qcom_icc_bcm * const compute_noc_bcms[] = {
 244         &bcm_co0,
 245         &bcm_co2,
 246         &bcm_co3,
 247 };
 248
 249 static struct qcom_icc_node * const compute_noc_nodes[] = {
 250         [MASTER_NPU] = &qnm_npu,
 251         [MASTER_NPU_PROC] = &qxm_npu_dsp,
 252         [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc,
 253 };
 254
 255 static const struct qcom_icc_desc sm6350_compute_noc = {
 256         .nodes = compute_noc_nodes,
 257         .num_nodes = ARRAY_SIZE(compute_noc_nodes),
 258         .bcms = compute_noc_bcms,
 259         .num_bcms = ARRAY_SIZE(compute_noc_bcms),
 260 };
 261
 262 static struct qcom_icc_bcm * const config_noc_bcms[] = {
 263         &bcm_cn0,
 264         &bcm_cn1,
 265 };
 266
 267 static struct qcom_icc_node * const config_noc_nodes[] = {
 268         [SNOC_CNOC_MAS] = &qnm_snoc,
 269         [MASTER_QDSS_DAP] = &xm_qdss_dap,
 270         [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg,
 271         [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg,
 272         [SLAVE_AHB2PHY] = &qhs_ahb2phy0,
 273         [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
 274         [SLAVE_AOSS] = &qhs_aoss,
 275         [SLAVE_BOOT_ROM] = &qhs_boot_rom,
 276         [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
 277         [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg,
 278         [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
 279         [SLAVE_CLK_CTL] = &qhs_clk_ctl,
 280         [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
 281         [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
 282         [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
 283         [SLAVE_DCC_CFG] = &qhs_dcc_cfg,
 284         [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
 285         [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
 286         [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg,
 287         [SLAVE_EMMC_CFG] = &qhs_emmc_cfg,
 288         [SLAVE_GLM] = &qhs_glm,
 289         [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg,
 290         [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
 291         [SLAVE_IPA_CFG] = &qhs_ipa,
 292         [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg,
 293         [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
 294         [SLAVE_NPU_CFG] = &qhs_npu_cfg,
 295         [SLAVE_PDM] = &qhs_pdm,
 296         [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
 297         [SLAVE_PRNG] = &qhs_prng,
 298         [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
 299         [SLAVE_QM_CFG] = &qhs_qm_cfg,
 300         [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
 301         [SLAVE_QUP_0] = &qhs_qup0,
 302         [SLAVE_QUP_1] = &qhs_qup1,
 303         [SLAVE_SDCC_2] = &qhs_sdc2,
 304         [SLAVE_SECURITY] = &qhs_security,
 305         [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
 306         [SLAVE_TCSR] = &qhs_tcsr,
 307         [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
 308         [SLAVE_USB3] = &qhs_usb3_0,
 309         [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
 310         [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg,
 311         [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
 312         [SLAVE_SERVICE_CNOC] = &srvc_cnoc,
 313 };
 314
 315 static const struct qcom_icc_desc sm6350_config_noc = {
 316         .nodes = config_noc_nodes,
 317         .num_nodes = ARRAY_SIZE(config_noc_nodes),
 318         .bcms = config_noc_bcms,
 319         .num_bcms = ARRAY_SIZE(config_noc_bcms),
 320 };
 321
 322 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
 323 };
 324
 325 static struct qcom_icc_node * const dc_noc_nodes[] = {
 326         [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc,
 327         [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc,
 328         [SLAVE_LLCC_CFG] = &qhs_llcc,
 329 };
 330
 331 static const struct qcom_icc_desc sm6350_dc_noc = {
 332         .nodes = dc_noc_nodes,
 333         .num_nodes = ARRAY_SIZE(dc_noc_nodes),
 334         .bcms = dc_noc_bcms,
 335         .num_bcms = ARRAY_SIZE(dc_noc_bcms),
 336 };
 337
 338 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
 339         &bcm_sh0,
 340         &bcm_sh2,
 341         &bcm_sh3,
 342         &bcm_sh4,
 343 };
 344
 345 static struct qcom_icc_node * const gem_noc_nodes[] = {
 346         [MASTER_AMPSS_M0] = &acm_apps,
 347         [MASTER_SYS_TCU] = &acm_sys_tcu,
 348         [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg,
 349         [MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
 350         [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
 351         [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
 352         [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
 353         [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
 354         [MASTER_GRAPHICS_3D] = &qxm_gpu,
 355         [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_mcdma_ms_mpu_cfg,
 356         [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
 357         [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc,
 358         [SLAVE_LLCC] = &qns_llcc,
 359         [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,
 360 };
 361
 362 static const struct qcom_icc_desc sm6350_gem_noc = {
 363         .nodes = gem_noc_nodes,
 364         .num_nodes = ARRAY_SIZE(gem_noc_nodes),
 365         .bcms = gem_noc_bcms,
 366         .num_bcms = ARRAY_SIZE(gem_noc_bcms),
 367 };
 368
 369 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
 370         &bcm_mm0,
 371         &bcm_mm1,
 372         &bcm_mm2,
 373         &bcm_mm3,
 374 };
 375
 376 static struct qcom_icc_node * const mmss_noc_nodes[] = {
 377         [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg,
 378         [MASTER_VIDEO_P0] = &qnm_video0,
 379         [MASTER_VIDEO_PROC] = &qnm_video_cvp,
 380         [MASTER_CAMNOC_HF] = &qxm_camnoc_hf,
 381         [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
 382         [MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
 383         [MASTER_MDP_PORT0] = &qxm_mdp0,
 384         [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
 385         [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
 386         [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
 387 };
 388
 389 static const struct qcom_icc_desc sm6350_mmss_noc = {
 390         .nodes = mmss_noc_nodes,
 391         .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
 392         .bcms = mmss_noc_bcms,
 393         .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
 394 };
 395
 396 static struct qcom_icc_bcm * const npu_noc_bcms[] = {
 397 };
 398
 399 static struct qcom_icc_node * const npu_noc_nodes[] = {
 400         [MASTER_NPU_SYS] = &amm_npu_sys,
 401         [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg,
 402         [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0,
 403         [SLAVE_NPU_CP] = &qhs_cp,
 404         [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon,
 405         [SLAVE_NPU_DPM] = &qhs_dpm,
 406         [SLAVE_ISENSE_CFG] = &qhs_isense,
 407         [SLAVE_NPU_LLM_CFG] = &qhs_llm,
 408         [SLAVE_NPU_TCM] = &qhs_tcm,
 409         [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys,
 410         [SLAVE_SERVICE_NPU_NOC] = &srvc_noc,
 411 };
 412
 413 static const struct qcom_icc_desc sm6350_npu_noc = {
 414         .nodes = npu_noc_nodes,
 415         .num_nodes = ARRAY_SIZE(npu_noc_nodes),
 416         .bcms = npu_noc_bcms,
 417         .num_bcms = ARRAY_SIZE(npu_noc_bcms),
 418 };
 419
 420 static struct qcom_icc_bcm * const system_noc_bcms[] = {
 421         &bcm_sn0,
 422         &bcm_sn1,
 423         &bcm_sn10,
 424         &bcm_sn2,
 425         &bcm_sn3,
 426         &bcm_sn4,
 427         &bcm_sn5,
 428         &bcm_sn6,
 429 };
 430
 431 static struct qcom_icc_node * const system_noc_nodes[] = {
 432         [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
 433         [A1NOC_SNOC_MAS] = &qnm_aggre1_noc,
 434         [A2NOC_SNOC_MAS] = &qnm_aggre2_noc,
 435         [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc,
 436         [MASTER_PIMEM] = &qxm_pimem,
 437         [MASTER_GIC] = &xm_gic,
 438         [SLAVE_APPSS] = &qhs_apss,
 439         [SNOC_CNOC_SLV] = &qns_cnoc,
 440         [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
 441         [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
 442         [SLAVE_OCIMEM] = &qxs_imem,
 443         [SLAVE_PIMEM] = &qxs_pimem,
 444         [SLAVE_SERVICE_SNOC] = &srvc_snoc,
 445         [SLAVE_QDSS_STM] = &xs_qdss_stm,
 446         [SLAVE_TCU] = &xs_sys_tcu_cfg,
 447 };
 448
 449 static const struct qcom_icc_desc sm6350_system_noc = {
 450         .nodes = system_noc_nodes,
 451         .num_nodes = ARRAY_SIZE(system_noc_nodes),
 452         .bcms = system_noc_bcms,
 453         .num_bcms = ARRAY_SIZE(system_noc_bcms),
 454 };
 455
 456 static const struct of_device_id qnoc_of_match[] = {
 457         { .compatible = "qcom,sm6350-aggre1-noc",
 458           .data = &sm6350_aggre1_noc},
 459         { .compatible = "qcom,sm6350-aggre2-noc",
 460           .data = &sm6350_aggre2_noc},
 461         { .compatible = "qcom,sm6350-clk-virt",
 462           .data = &sm6350_clk_virt},
 463         { .compatible = "qcom,sm6350-compute-noc",
 464           .data = &sm6350_compute_noc},
 465         { .compatible = "qcom,sm6350-config-noc",
 466           .data = &sm6350_config_noc},
 467         { .compatible = "qcom,sm6350-dc-noc",
 468           .data = &sm6350_dc_noc},
 469         { .compatible = "qcom,sm6350-gem-noc",
 470           .data = &sm6350_gem_noc},
 471         { .compatible = "qcom,sm6350-mmss-noc",
 472           .data = &sm6350_mmss_noc},
 473         { .compatible = "qcom,sm6350-npu-noc",
 474           .data = &sm6350_npu_noc},
 475         { .compatible = "qcom,sm6350-system-noc",
 476           .data = &sm6350_system_noc},
 477         { }
 478 };
 479 MODULE_DEVICE_TABLE(of, qnoc_of_match);
 480
 481 static struct platform_driver qnoc_driver = {
 482         .probe = qcom_icc_rpmh_probe,
 483         .remove = qcom_icc_rpmh_remove,
 484         .driver = {
 485                 .name = "qnoc-sm6350",
 486                 .of_match_table = qnoc_of_match,
 487                 .sync_state = icc_sync_state,
 488         },
 489 };
 490 module_platform_driver(qnoc_driver);
 491
 492 MODULE_DESCRIPTION("Qualcomm SM6350 NoC driver");
 493 MODULE_LICENSE("GPL v2");