drivers/interconnect/qcom/osm-l3.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitfield.h>
   7 #include <linux/clk.h>
   8 #include <linux/interconnect-provider.h>
   9 #include <linux/io.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14
  15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  16
  17 #define LUT_MAX_ENTRIES                 40U
  18 #define LUT_SRC                         GENMASK(31, 30)
  19 #define LUT_L_VAL                       GENMASK(7, 0)
  20 #define CLK_HW_DIV                      2
  21
  22 /* OSM Register offsets */
  23 #define REG_ENABLE                      0x0
  24 #define OSM_LUT_ROW_SIZE                32
  25 #define OSM_REG_FREQ_LUT                0x110
  26 #define OSM_REG_PERF_STATE              0x920
  27
  28 /* EPSS Register offsets */
  29 #define EPSS_LUT_ROW_SIZE               4
  30 #define EPSS_REG_L3_VOTE                0x90
  31 #define EPSS_REG_FREQ_LUT               0x100
  32 #define EPSS_REG_PERF_STATE             0x320
  33
  34 #define OSM_L3_MAX_LINKS                1
  35
  36 #define to_osm_l3_provider(_provider) \
  37         container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
  38
  39 struct qcom_osm_l3_icc_provider {
  40         void __iomem *base;
  41         unsigned int max_state;
  42         unsigned int reg_perf_state;
  43         unsigned long lut_tables[LUT_MAX_ENTRIES];
  44         struct icc_provider provider;
  45 };
  46
  47 /**
  48  * struct qcom_osm_l3_node - Qualcomm specific interconnect nodes
  49  * @name: the node name used in debugfs
  50  * @links: an array of nodes where we can go next while traversing
  51  * @id: a unique node identifier
  52  * @num_links: the total number of @links
  53  * @buswidth: width of the interconnect between a node and the bus
  54  */
  55 struct qcom_osm_l3_node {
  56         const char *name;
  57         u16 links[OSM_L3_MAX_LINKS];
  58         u16 id;
  59         u16 num_links;
  60         u16 buswidth;
  61 };
  62
  63 struct qcom_osm_l3_desc {
  64         const struct qcom_osm_l3_node * const *nodes;
  65         size_t num_nodes;
  66         unsigned int lut_row_size;
  67         unsigned int reg_freq_lut;
  68         unsigned int reg_perf_state;
  69 };
  70
  71 enum {
  72         OSM_L3_MASTER_NODE = 10000,
  73         OSM_L3_SLAVE_NODE,
  74 };
  75
  76 #define DEFINE_QNODE(_name, _id, _buswidth, ...)                        \
  77         static const struct qcom_osm_l3_node _name = {                  \
  78                 .name = #_name,                                         \
  79                 .id = _id,                                              \
  80                 .buswidth = _buswidth,                                  \
  81                 .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })),      \
  82                 .links = { __VA_ARGS__ },                               \
  83         }
  84
  85 DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE);
  86 DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16);
  87
  88 static const struct qcom_osm_l3_node * const osm_l3_nodes[] = {
  89         [MASTER_OSM_L3_APPS] = &osm_l3_master,
  90         [SLAVE_OSM_L3] = &osm_l3_slave,
  91 };
  92
  93 DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE);
  94 DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32);
  95
  96 static const struct qcom_osm_l3_node * const epss_l3_nodes[] = {
  97         [MASTER_EPSS_L3_APPS] = &epss_l3_master,
  98         [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave,
  99 };
 100
 101 static const struct qcom_osm_l3_desc osm_l3 = {
 102         .nodes = osm_l3_nodes,
 103         .num_nodes = ARRAY_SIZE(osm_l3_nodes),
 104         .lut_row_size = OSM_LUT_ROW_SIZE,
 105         .reg_freq_lut = OSM_REG_FREQ_LUT,
 106         .reg_perf_state = OSM_REG_PERF_STATE,
 107 };
 108
 109 static const struct qcom_osm_l3_desc epss_l3_perf_state = {
 110         .nodes = epss_l3_nodes,
 111         .num_nodes = ARRAY_SIZE(epss_l3_nodes),
 112         .lut_row_size = EPSS_LUT_ROW_SIZE,
 113         .reg_freq_lut = EPSS_REG_FREQ_LUT,
 114         .reg_perf_state = EPSS_REG_PERF_STATE,
 115 };
 116
 117 static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
 118         .nodes = epss_l3_nodes,
 119         .num_nodes = ARRAY_SIZE(epss_l3_nodes),
 120         .lut_row_size = EPSS_LUT_ROW_SIZE,
 121         .reg_freq_lut = EPSS_REG_FREQ_LUT,
 122         .reg_perf_state = EPSS_REG_L3_VOTE,
 123 };
 124
 125 static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
 126 {
 127         struct qcom_osm_l3_icc_provider *qp;
 128         struct icc_provider *provider;
 129         const struct qcom_osm_l3_node *qn;
 130         unsigned int index;
 131         u64 rate;
 132
 133         qn = src->data;
 134         provider = src->provider;
 135         qp = to_osm_l3_provider(provider);
 136
 137         rate = icc_units_to_bps(dst->peak_bw);
 138         do_div(rate, qn->buswidth);
 139
 140         for (index = 0; index < qp->max_state - 1; index++) {
 141                 if (qp->lut_tables[index] >= rate)
 142                         break;
 143         }
 144
 145         writel_relaxed(index, qp->base + qp->reg_perf_state);
 146
 147         return 0;
 148 }
 149
 150 static int qcom_osm_l3_remove(struct platform_device *pdev)
 151 {
 152         struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);
 153
 154         icc_provider_deregister(&qp->provider);
 155         icc_nodes_remove(&qp->provider);
 156
 157         return 0;
 158 }
 159
 160 static int qcom_osm_l3_probe(struct platform_device *pdev)
 161 {
 162         u32 info, src, lval, i, prev_freq = 0, freq;
 163         static unsigned long hw_rate, xo_rate;
 164         struct qcom_osm_l3_icc_provider *qp;
 165         const struct qcom_osm_l3_desc *desc;
 166         struct icc_onecell_data *data;
 167         struct icc_provider *provider;
 168         const struct qcom_osm_l3_node * const *qnodes;
 169         struct icc_node *node;
 170         size_t num_nodes;
 171         struct clk *clk;
 172         int ret;
 173
 174         clk = clk_get(&pdev->dev, "xo");
 175         if (IS_ERR(clk))
 176                 return PTR_ERR(clk);
 177
 178         xo_rate = clk_get_rate(clk);
 179         clk_put(clk);
 180
 181         clk = clk_get(&pdev->dev, "alternate");
 182         if (IS_ERR(clk))
 183                 return PTR_ERR(clk);
 184
 185         hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
 186         clk_put(clk);
 187
 188         qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
 189         if (!qp)
 190                 return -ENOMEM;
 191
 192         qp->base = devm_platform_ioremap_resource(pdev, 0);
 193         if (IS_ERR(qp->base))
 194                 return PTR_ERR(qp->base);
 195
 196         /* HW should be in enabled state to proceed */
 197         if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
 198                 dev_err(&pdev->dev, "error hardware not enabled\n");
 199                 return -ENODEV;
 200         }
 201
 202         desc = device_get_match_data(&pdev->dev);
 203         if (!desc)
 204                 return -EINVAL;
 205
 206         qp->reg_perf_state = desc->reg_perf_state;
 207
 208         for (i = 0; i < LUT_MAX_ENTRIES; i++) {
 209                 info = readl_relaxed(qp->base + desc->reg_freq_lut +
 210                                      i * desc->lut_row_size);
 211                 src = FIELD_GET(LUT_SRC, info);
 212                 lval = FIELD_GET(LUT_L_VAL, info);
 213                 if (src)
 214                         freq = xo_rate * lval;
 215                 else
 216                         freq = hw_rate;
 217
 218                 /* Two of the same frequencies signify end of table */
 219                 if (i > 0 && prev_freq == freq)
 220                         break;
 221
 222                 dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq);
 223
 224                 qp->lut_tables[i] = freq;
 225                 prev_freq = freq;
 226         }
 227         qp->max_state = i;
 228
 229         qnodes = desc->nodes;
 230         num_nodes = desc->num_nodes;
 231
 232         data = devm_kzalloc(&pdev->dev, struct_size(data, nodes, num_nodes), GFP_KERNEL);
 233         if (!data)
 234                 return -ENOMEM;
 235
 236         provider = &qp->provider;
 237         provider->dev = &pdev->dev;
 238         provider->set = qcom_osm_l3_set;
 239         provider->aggregate = icc_std_aggregate;
 240         provider->xlate = of_icc_xlate_onecell;
 241         provider->data = data;
 242
 243         icc_provider_init(provider);
 244
 245         for (i = 0; i < num_nodes; i++) {
 246                 size_t j;
 247
 248                 node = icc_node_create(qnodes[i]->id);
 249                 if (IS_ERR(node)) {
 250                         ret = PTR_ERR(node);
 251                         goto err;
 252                 }
 253
 254                 node->name = qnodes[i]->name;
 255                 /* Cast away const and add it back in qcom_osm_l3_set() */
 256                 node->data = (void *)qnodes[i];
 257                 icc_node_add(node, provider);
 258
 259                 for (j = 0; j < qnodes[i]->num_links; j++)
 260                         icc_link_create(node, qnodes[i]->links[j]);
 261
 262                 data->nodes[i] = node;
 263         }
 264         data->num_nodes = num_nodes;
 265
 266         ret = icc_provider_register(provider);
 267         if (ret)
 268                 goto err;
 269
 270         platform_set_drvdata(pdev, qp);
 271
 272         return 0;
 273 err:
 274         icc_nodes_remove(provider);
 275
 276         return ret;
 277 }
 278
 279 static const struct of_device_id osm_l3_of_match[] = {
 280         { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote },
 281         { .compatible = "qcom,osm-l3", .data = &osm_l3 },
 282         { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
 283         { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
 284         { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
 285         { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
 286         { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
 287         { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
 288         { }
 289 };
 290 MODULE_DEVICE_TABLE(of, osm_l3_of_match);
 291
 292 static struct platform_driver osm_l3_driver = {
 293         .probe = qcom_osm_l3_probe,
 294         .remove = qcom_osm_l3_remove,
 295         .driver = {
 296                 .name = "osm-l3",
 297                 .of_match_table = osm_l3_of_match,
 298                 .sync_state = icc_sync_state,
 299         },
 300 };
 301 module_platform_driver(osm_l3_driver);
 302
 303 MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver");
 304 MODULE_LICENSE("GPL v2");