drivers/iio/frequency/adf4377.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ADF4377 driver
   4  *
   5  * Copyright 2022 Analog Devices Inc.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/clkdev.h>
  12 #include <linux/delay.h>
  13 #include <linux/device.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/module.h>
  16 #include <linux/notifier.h>
  17 #include <linux/property.h>
  18 #include <linux/spi/spi.h>
  19 #include <linux/iio/iio.h>
  20 #include <linux/regmap.h>
  21 #include <linux/units.h>
  22
  23 #include <asm/unaligned.h>
  24
  25 /* ADF4377 REG0000 Map */
  26 #define ADF4377_0000_SOFT_RESET_R_MSK           BIT(7)
  27 #define ADF4377_0000_LSB_FIRST_R_MSK            BIT(6)
  28 #define ADF4377_0000_ADDRESS_ASC_R_MSK          BIT(5)
  29 #define ADF4377_0000_SDO_ACTIVE_R_MSK           BIT(4)
  30 #define ADF4377_0000_SDO_ACTIVE_MSK             BIT(3)
  31 #define ADF4377_0000_ADDRESS_ASC_MSK            BIT(2)
  32 #define ADF4377_0000_LSB_FIRST_MSK              BIT(1)
  33 #define ADF4377_0000_SOFT_RESET_MSK             BIT(0)
  34
  35 /* ADF4377 REG0000 Bit Definition */
  36 #define ADF4377_0000_SDO_ACTIVE_SPI_3W          0x0
  37 #define ADF4377_0000_SDO_ACTIVE_SPI_4W          0x1
  38
  39 #define ADF4377_0000_ADDR_ASC_AUTO_DECR         0x0
  40 #define ADF4377_0000_ADDR_ASC_AUTO_INCR         0x1
  41
  42 #define ADF4377_0000_LSB_FIRST_MSB              0x0
  43 #define ADF4377_0000_LSB_FIRST_LSB              0x1
  44
  45 #define ADF4377_0000_SOFT_RESET_N_OP            0x0
  46 #define ADF4377_0000_SOFT_RESET_EN              0x1
  47
  48 /* ADF4377 REG0001 Map */
  49 #define ADF4377_0001_SINGLE_INSTR_MSK           BIT(7)
  50 #define ADF4377_0001_MASTER_RB_CTRL_MSK         BIT(5)
  51
  52 /* ADF4377 REG0003 Bit Definition */
  53 #define ADF4377_0003_CHIP_TYPE                  0x06
  54
  55 /* ADF4377 REG0004 Bit Definition */
  56 #define ADF4377_0004_PRODUCT_ID_LSB             0x0005
  57
  58 /* ADF4377 REG0005 Bit Definition */
  59 #define ADF4377_0005_PRODUCT_ID_MSB             0x0005
  60
  61 /* ADF4377 REG000A Map */
  62 #define ADF4377_000A_SCRATCHPAD_MSK             GENMASK(7, 0)
  63
  64 /* ADF4377 REG000C Bit Definition */
  65 #define ADF4377_000C_VENDOR_ID_LSB              0x56
  66
  67 /* ADF4377 REG000D Bit Definition */
  68 #define ADF4377_000D_VENDOR_ID_MSB              0x04
  69
  70 /* ADF4377 REG000F Bit Definition */
  71 #define ADF4377_000F_R00F_RSV1_MSK              GENMASK(7, 0)
  72
  73 /* ADF4377 REG0010 Map*/
  74 #define ADF4377_0010_N_INT_LSB_MSK              GENMASK(7, 0)
  75
  76 /* ADF4377 REG0011 Map*/
  77 #define ADF4377_0011_EN_AUTOCAL_MSK             BIT(7)
  78 #define ADF4377_0011_EN_RDBLR_MSK               BIT(6)
  79 #define ADF4377_0011_DCLK_DIV2_MSK              GENMASK(5, 4)
  80 #define ADF4377_0011_N_INT_MSB_MSK              GENMASK(3, 0)
  81
  82 /* ADF4377 REG0011 Bit Definition */
  83 #define ADF4377_0011_DCLK_DIV2_1                0x0
  84 #define ADF4377_0011_DCLK_DIV2_2                0x1
  85 #define ADF4377_0011_DCLK_DIV2_4                0x2
  86 #define ADF4377_0011_DCLK_DIV2_8                0x3
  87
  88 /* ADF4377 REG0012 Map*/
  89 #define ADF4377_0012_CLKOUT_DIV_MSK             GENMASK(7, 6)
  90 #define ADF4377_0012_R_DIV_MSK                  GENMASK(5, 0)
  91
  92 /* ADF4377 REG0012 Bit Definition */
  93 #define ADF4377_0012_CLKOUT_DIV_1               0x0
  94 #define ADF4377_0012_CLKOUT_DIV_2               0x1
  95 #define ADF4377_0012_CLKOUT_DIV_4               0x2
  96 #define ADF4377_0012_CLKOUT_DIV_8               0x3
  97
  98 /* ADF4377 REG0013 Map */
  99 #define ADF4377_0013_M_VCO_CORE_MSK             GENMASK(5, 4)
 100 #define ADF4377_0013_VCO_BIAS_MSK               GENMASK(3, 0)
 101
 102 /* ADF4377 REG0013 Bit Definition */
 103 #define ADF4377_0013_M_VCO_0                    0x0
 104 #define ADF4377_0013_M_VCO_1                    0x1
 105 #define ADF4377_0013_M_VCO_2                    0x2
 106 #define ADF4377_0013_M_VCO_3                    0x3
 107
 108 /* ADF4377 REG0014 Map */
 109 #define ADF4377_0014_M_VCO_BAND_MSK             GENMASK(7, 0)
 110
 111 /* ADF4377 REG0015 Map */
 112 #define ADF4377_0015_BLEED_I_LSB_MSK            GENMASK(7, 6)
 113 #define ADF4377_0015_BLEED_POL_MSK              BIT(5)
 114 #define ADF4377_0015_EN_BLEED_MSK               BIT(4)
 115 #define ADF4377_0015_CP_I_MSK                   GENMASK(3, 0)
 116
 117 /* ADF4377 REG0015 Bit Definition */
 118 #define ADF4377_CURRENT_SINK                    0x0
 119 #define ADF4377_CURRENT_SOURCE                  0x1
 120
 121 #define ADF4377_0015_CP_0MA7                    0x0
 122 #define ADF4377_0015_CP_0MA9                    0x1
 123 #define ADF4377_0015_CP_1MA1                    0x2
 124 #define ADF4377_0015_CP_1MA3                    0x3
 125 #define ADF4377_0015_CP_1MA4                    0x4
 126 #define ADF4377_0015_CP_1MA8                    0x5
 127 #define ADF4377_0015_CP_2MA2                    0x6
 128 #define ADF4377_0015_CP_2MA5                    0x7
 129 #define ADF4377_0015_CP_2MA9                    0x8
 130 #define ADF4377_0015_CP_3MA6                    0x9
 131 #define ADF4377_0015_CP_4MA3                    0xA
 132 #define ADF4377_0015_CP_5MA0                    0xB
 133 #define ADF4377_0015_CP_5MA7                    0xC
 134 #define ADF4377_0015_CP_7MA2                    0xD
 135 #define ADF4377_0015_CP_8MA6                    0xE
 136 #define ADF4377_0015_CP_10MA1                   0xF
 137
 138 /* ADF4377 REG0016 Map */
 139 #define ADF4377_0016_BLEED_I_MSB_MSK            GENMASK(7, 0)
 140
 141 /* ADF4377 REG0017 Map */
 142 #define ADF4377_0016_INV_CLKOUT_MSK             BIT(7)
 143 #define ADF4377_0016_N_DEL_MSK                  GENMASK(6, 0)
 144
 145 /* ADF4377 REG0018 Map */
 146 #define ADF4377_0018_CMOS_OV_MSK                BIT(7)
 147 #define ADF4377_0018_R_DEL_MSK                  GENMASK(6, 0)
 148
 149 /* ADF4377 REG0018 Bit Definition */
 150 #define ADF4377_0018_1V8_LOGIC                  0x0
 151 #define ADF4377_0018_3V3_LOGIC                  0x1
 152
 153 /* ADF4377 REG0019 Map */
 154 #define ADF4377_0019_CLKOUT2_OP_MSK             GENMASK(7, 6)
 155 #define ADF4377_0019_CLKOUT1_OP_MSK             GENMASK(5, 4)
 156 #define ADF4377_0019_PD_CLK_MSK                 BIT(3)
 157 #define ADF4377_0019_PD_RDET_MSK                BIT(2)
 158 #define ADF4377_0019_PD_ADC_MSK                 BIT(1)
 159 #define ADF4377_0019_PD_CALADC_MSK              BIT(0)
 160
 161 /* ADF4377 REG0019 Bit Definition */
 162 #define ADF4377_0019_CLKOUT_320MV               0x0
 163 #define ADF4377_0019_CLKOUT_420MV               0x1
 164 #define ADF4377_0019_CLKOUT_530MV               0x2
 165 #define ADF4377_0019_CLKOUT_640MV               0x3
 166
 167 /* ADF4377 REG001A Map */
 168 #define ADF4377_001A_PD_ALL_MSK                 BIT(7)
 169 #define ADF4377_001A_PD_RDIV_MSK                BIT(6)
 170 #define ADF4377_001A_PD_NDIV_MSK                BIT(5)
 171 #define ADF4377_001A_PD_VCO_MSK                 BIT(4)
 172 #define ADF4377_001A_PD_LD_MSK                  BIT(3)
 173 #define ADF4377_001A_PD_PFDCP_MSK               BIT(2)
 174 #define ADF4377_001A_PD_CLKOUT1_MSK             BIT(1)
 175 #define ADF4377_001A_PD_CLKOUT2_MSK             BIT(0)
 176
 177 /* ADF4377 REG001B Map */
 178 #define ADF4377_001B_EN_LOL_MSK                 BIT(7)
 179 #define ADF4377_001B_LDWIN_PW_MSK               BIT(6)
 180 #define ADF4377_001B_EN_LDWIN_MSK               BIT(5)
 181 #define ADF4377_001B_LD_COUNT_MSK               GENMASK(4, 0)
 182
 183 /* ADF4377 REG001B Bit Definition */
 184 #define ADF4377_001B_LDWIN_PW_NARROW            0x0
 185 #define ADF4377_001B_LDWIN_PW_WIDE              0x1
 186
 187 /* ADF4377 REG001C Map */
 188 #define ADF4377_001C_EN_DNCLK_MSK               BIT(7)
 189 #define ADF4377_001C_EN_DRCLK_MSK               BIT(6)
 190 #define ADF4377_001C_RST_LD_MSK                 BIT(2)
 191 #define ADF4377_001C_R01C_RSV1_MSK              BIT(0)
 192
 193 /* ADF4377 REG001C Bit Definition */
 194 #define ADF4377_001C_RST_LD_INACTIVE            0x0
 195 #define ADF4377_001C_RST_LD_ACTIVE              0x1
 196
 197 #define ADF4377_001C_R01C_RSV1                  0x1
 198
 199 /* ADF4377 REG001D Map */
 200 #define ADF4377_001D_MUXOUT_MSK                 GENMASK(7, 4)
 201 #define ADF4377_001D_EN_CPTEST_MSK              BIT(2)
 202 #define ADF4377_001D_CP_DOWN_MSK                BIT(1)
 203 #define ADF4377_001D_CP_UP_MSK                  BIT(0)
 204
 205 #define ADF4377_001D_EN_CPTEST_OFF              0x0
 206 #define ADF4377_001D_EN_CPTEST_ON               0x1
 207
 208 #define ADF4377_001D_CP_DOWN_OFF                0x0
 209 #define ADF4377_001D_CP_DOWN_ON                 0x1
 210
 211 #define ADF4377_001D_CP_UP_OFF                  0x0
 212 #define ADF4377_001D_CP_UP_ON                   0x1
 213
 214 /* ADF4377 REG001F Map */
 215 #define ADF4377_001F_BST_REF_MSK                BIT(7)
 216 #define ADF4377_001F_FILT_REF_MSK               BIT(6)
 217 #define ADF4377_001F_REF_SEL_MSK                BIT(5)
 218 #define ADF4377_001F_R01F_RSV1_MSK              GENMASK(4, 0)
 219
 220 /* ADF4377 REG001F Bit Definition */
 221 #define ADF4377_001F_BST_LARGE_REF_IN           0x0
 222 #define ADF4377_001F_BST_SMALL_REF_IN           0x1
 223
 224 #define ADF4377_001F_FILT_REF_OFF               0x0
 225 #define ADF4377_001F_FILT_REF_ON                0x1
 226
 227 #define ADF4377_001F_REF_SEL_DMA                0x0
 228 #define ADF4377_001F_REF_SEL_LNA                0x1
 229
 230 #define ADF4377_001F_R01F_RSV1                  0x7
 231
 232 /* ADF4377 REG0020 Map */
 233 #define ADF4377_0020_RST_SYS_MSK                BIT(4)
 234 #define ADF4377_0020_EN_ADC_CLK_MSK             BIT(3)
 235 #define ADF4377_0020_R020_RSV1_MSK              BIT(0)
 236
 237 /* ADF4377 REG0021 Bit Definition */
 238 #define ADF4377_0021_R021_RSV1                  0xD3
 239
 240 /* ADF4377 REG0022 Bit Definition */
 241 #define ADF4377_0022_R022_RSV1                  0x32
 242
 243 /* ADF4377 REG0023 Map */
 244 #define ADF4377_0023_CAT_CT_SEL                 BIT(7)
 245 #define ADF4377_0023_R023_RSV1_MSK              GENMASK(6, 0)
 246
 247 /* ADF4377 REG0023 Bit Definition */
 248 #define ADF4377_0023_R023_RSV1                  0x18
 249
 250 /* ADF4377 REG0024 Map */
 251 #define ADF4377_0024_DCLK_MODE_MSK              BIT(2)
 252
 253 /* ADF4377 REG0025 Map */
 254 #define ADF4377_0025_CLKODIV_DB_MSK             BIT(7)
 255 #define ADF4377_0025_DCLK_DB_MSK                BIT(6)
 256 #define ADF4377_0025_R025_RSV1_MSK              GENMASK(5, 0)
 257
 258 /* ADF4377 REG0025 Bit Definition */
 259 #define ADF4377_0025_R025_RSV1                  0x16
 260
 261 /* ADF4377 REG0026 Map */
 262 #define ADF4377_0026_VCO_BAND_DIV_MSK           GENMASK(7, 0)
 263
 264 /* ADF4377 REG0027 Map */
 265 #define ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK      GENMASK(7, 0)
 266
 267 /* ADF4377 REG0028 Map */
 268 #define ADF4377_0028_O_VCO_DB_MSK               BIT(7)
 269 #define ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK      GENMASK(6, 0)
 270
 271 /* ADF4377 REG0029 Map */
 272 #define ADF4377_0029_VCO_ALC_TO_LSB_MSK         GENMASK(7, 0)
 273
 274 /* ADF4377 REG002A Map */
 275 #define ADF4377_002A_DEL_CTRL_DB_MSK            BIT(7)
 276 #define ADF4377_002A_VCO_ALC_TO_MSB_MSK         GENMASK(6, 0)
 277
 278 /* ADF4377 REG002C Map */
 279 #define ADF4377_002C_R02C_RSV1                  0xC0
 280
 281 /* ADF4377 REG002D Map */
 282 #define ADF4377_002D_ADC_CLK_DIV_MSK            GENMASK(7, 0)
 283
 284 /* ADF4377 REG002E Map */
 285 #define ADF4377_002E_EN_ADC_CNV_MSK             BIT(7)
 286 #define ADF4377_002E_EN_ADC_MSK                 BIT(1)
 287 #define ADF4377_002E_ADC_A_CONV_MSK             BIT(0)
 288
 289 /* ADF4377 REG002E Bit Definition */
 290 #define ADF4377_002E_ADC_A_CONV_ADC_ST_CNV      0x0
 291 #define ADF4377_002E_ADC_A_CONV_VCO_CALIB       0x1
 292
 293 /* ADF4377 REG002F Map */
 294 #define ADF4377_002F_DCLK_DIV1_MSK              GENMASK(1, 0)
 295
 296 /* ADF4377 REG002F Bit Definition */
 297 #define ADF4377_002F_DCLK_DIV1_1                0x0
 298 #define ADF4377_002F_DCLK_DIV1_2                0x1
 299 #define ADF4377_002F_DCLK_DIV1_8                0x2
 300 #define ADF4377_002F_DCLK_DIV1_32               0x3
 301
 302 /* ADF4377 REG0031 Bit Definition */
 303 #define ADF4377_0031_R031_RSV1                  0x09
 304
 305 /* ADF4377 REG0032 Map */
 306 #define ADF4377_0032_ADC_CLK_SEL_MSK            BIT(6)
 307 #define ADF4377_0032_R032_RSV1_MSK              GENMASK(5, 0)
 308
 309 /* ADF4377 REG0032 Bit Definition */
 310 #define ADF4377_0032_ADC_CLK_SEL_N_OP           0x0
 311 #define ADF4377_0032_ADC_CLK_SEL_SPI_CLK        0x1
 312
 313 #define ADF4377_0032_R032_RSV1                  0x9
 314
 315 /* ADF4377 REG0033 Bit Definition */
 316 #define ADF4377_0033_R033_RSV1                  0x18
 317
 318 /* ADF4377 REG0034 Bit Definition */
 319 #define ADF4377_0034_R034_RSV1                  0x08
 320
 321 /* ADF4377 REG003A Bit Definition */
 322 #define ADF4377_003A_R03A_RSV1                  0x5D
 323
 324 /* ADF4377 REG003B Bit Definition */
 325 #define ADF4377_003B_R03B_RSV1                  0x2B
 326
 327 /* ADF4377 REG003D Map */
 328 #define ADF4377_003D_O_VCO_BAND_MSK             BIT(3)
 329 #define ADF4377_003D_O_VCO_CORE_MSK             BIT(2)
 330 #define ADF4377_003D_O_VCO_BIAS_MSK             BIT(1)
 331
 332 /* ADF4377 REG003D Bit Definition */
 333 #define ADF4377_003D_O_VCO_BAND_VCO_CALIB       0x0
 334 #define ADF4377_003D_O_VCO_BAND_M_VCO           0x1
 335
 336 #define ADF4377_003D_O_VCO_CORE_VCO_CALIB       0x0
 337 #define ADF4377_003D_O_VCO_CORE_M_VCO           0x1
 338
 339 #define ADF4377_003D_O_VCO_BIAS_VCO_CALIB       0x0
 340 #define ADF4377_003D_O_VCO_BIAS_M_VCO           0x1
 341
 342 /* ADF4377 REG0042 Map */
 343 #define ADF4377_0042_R042_RSV1                  0x05
 344
 345 /* ADF4377 REG0045 Map */
 346 #define ADF4377_0045_ADC_ST_CNV_MSK             BIT(0)
 347
 348 /* ADF4377 REG0049 Map */
 349 #define ADF4377_0049_EN_CLK2_MSK                BIT(7)
 350 #define ADF4377_0049_EN_CLK1_MSK                BIT(6)
 351 #define ADF4377_0049_REF_OK_MSK                 BIT(3)
 352 #define ADF4377_0049_ADC_BUSY_MSK               BIT(2)
 353 #define ADF4377_0049_FSM_BUSY_MSK               BIT(1)
 354 #define ADF4377_0049_LOCKED_MSK                 BIT(0)
 355
 356 /* ADF4377 REG004B Map */
 357 #define ADF4377_004B_VCO_CORE_MSK               GENMASK(1, 0)
 358
 359 /* ADF4377 REG004C Map */
 360 #define ADF4377_004C_CHIP_TEMP_LSB_MSK          GENMASK(7, 0)
 361
 362 /* ADF4377 REG004D Map */
 363 #define ADF4377_004D_CHIP_TEMP_MSB_MSK          BIT(0)
 364
 365 /* ADF4377 REG004F Map */
 366 #define ADF4377_004F_VCO_BAND_MSK               GENMASK(7, 0)
 367
 368 /* ADF4377 REG0051 Map */
 369 #define ADF4377_0051_VCO_BIAS_MSK               GENMASK(3, 0)
 370
 371 /* ADF4377 REG0054 Map */
 372 #define ADF4377_0054_CHIP_VERSION_MSK           GENMASK(7, 0)
 373
 374 /* Specifications */
 375 #define ADF4377_SPI_READ_CMD                    BIT(7)
 376 #define ADF4377_MAX_VCO_FREQ                    (12800ULL * HZ_PER_MHZ)
 377 #define ADF4377_MIN_VCO_FREQ                    (6400ULL * HZ_PER_MHZ)
 378 #define ADF4377_MAX_REFIN_FREQ                  (1000 * HZ_PER_MHZ)
 379 #define ADF4377_MIN_REFIN_FREQ                  (10 * HZ_PER_MHZ)
 380 #define ADF4377_MAX_FREQ_PFD                    (500 * HZ_PER_MHZ)
 381 #define ADF4377_MIN_FREQ_PFD                    (3 * HZ_PER_MHZ)
 382 #define ADF4377_MAX_CLKPN_FREQ                  ADF4377_MAX_VCO_FREQ
 383 #define ADF4377_MIN_CLKPN_FREQ                  (ADF4377_MIN_VCO_FREQ / 8)
 384 #define ADF4377_FREQ_PFD_80MHZ                  (80 * HZ_PER_MHZ)
 385 #define ADF4377_FREQ_PFD_125MHZ                 (125 * HZ_PER_MHZ)
 386 #define ADF4377_FREQ_PFD_160MHZ                 (160 * HZ_PER_MHZ)
 387 #define ADF4377_FREQ_PFD_250MHZ                 (250 * HZ_PER_MHZ)
 388 #define ADF4377_FREQ_PFD_320MHZ                 (320 * HZ_PER_MHZ)
 389
 390 enum {
 391         ADF4377_FREQ,
 392 };
 393
 394 enum muxout_select_mode {
 395         ADF4377_MUXOUT_HIGH_Z = 0x0,
 396         ADF4377_MUXOUT_LKDET = 0x1,
 397         ADF4377_MUXOUT_LOW = 0x2,
 398         ADF4377_MUXOUT_DIV_RCLK_2 = 0x4,
 399         ADF4377_MUXOUT_DIV_NCLK_2 = 0x5,
 400         ADF4377_MUXOUT_HIGH = 0x8,
 401 };
 402
 403 struct adf4377_state {
 404         struct spi_device       *spi;
 405         struct regmap           *regmap;
 406         struct clk              *clkin;
 407         /* Protect against concurrent accesses to the device and data content */
 408         struct mutex            lock;
 409         struct notifier_block   nb;
 410         /* Reference Divider */
 411         unsigned int            ref_div_factor;
 412         /* PFD Frequency */
 413         unsigned int            f_pfd;
 414         /* Input Reference Clock */
 415         unsigned int            clkin_freq;
 416         /* CLKOUT Divider */
 417         u8                      clkout_div_sel;
 418         /* Feedback Divider (N) */
 419         u16                     n_int;
 420         u16                     synth_lock_timeout;
 421         u16                     vco_alc_timeout;
 422         u16                     adc_clk_div;
 423         u16                     vco_band_div;
 424         u8                      dclk_div1;
 425         u8                      dclk_div2;
 426         u8                      dclk_mode;
 427         unsigned int            f_div_rclk;
 428         enum muxout_select_mode muxout_select;
 429         struct gpio_desc        *gpio_ce;
 430         struct gpio_desc        *gpio_enclk1;
 431         struct gpio_desc        *gpio_enclk2;
 432         u8                      buf[2] __aligned(IIO_DMA_MINALIGN);
 433 };
 434
 435 static const char * const adf4377_muxout_modes[] = {
 436         [ADF4377_MUXOUT_HIGH_Z] = "high_z",
 437         [ADF4377_MUXOUT_LKDET] = "lock_detect",
 438         [ADF4377_MUXOUT_LOW] = "muxout_low",
 439         [ADF4377_MUXOUT_DIV_RCLK_2] = "f_div_rclk_2",
 440         [ADF4377_MUXOUT_DIV_NCLK_2] = "f_div_nclk_2",
 441         [ADF4377_MUXOUT_HIGH] = "muxout_high",
 442 };
 443
 444 static const struct reg_sequence adf4377_reg_defaults[] = {
 445         { 0x42,  ADF4377_0042_R042_RSV1 },
 446         { 0x3B,  ADF4377_003B_R03B_RSV1 },
 447         { 0x3A,  ADF4377_003A_R03A_RSV1 },
 448         { 0x34,  ADF4377_0034_R034_RSV1 },
 449         { 0x33,  ADF4377_0033_R033_RSV1 },
 450         { 0x32,  ADF4377_0032_R032_RSV1 },
 451         { 0x31,  ADF4377_0031_R031_RSV1 },
 452         { 0x2C,  ADF4377_002C_R02C_RSV1 },
 453         { 0x25,  ADF4377_0025_R025_RSV1 },
 454         { 0x23,  ADF4377_0023_R023_RSV1 },
 455         { 0x22,  ADF4377_0022_R022_RSV1 },
 456         { 0x21,  ADF4377_0021_R021_RSV1 },
 457         { 0x1f,  ADF4377_001F_R01F_RSV1 },
 458         { 0x1c,  ADF4377_001C_R01C_RSV1 },
 459 };
 460
 461 static const struct regmap_config adf4377_regmap_config = {
 462         .reg_bits = 16,
 463         .val_bits = 8,
 464         .read_flag_mask = BIT(7),
 465         .max_register = 0x54,
 466 };
 467
 468 static int adf4377_reg_access(struct iio_dev *indio_dev,
 469                               unsigned int reg,
 470                               unsigned int write_val,
 471                               unsigned int *read_val)
 472 {
 473         struct adf4377_state *st = iio_priv(indio_dev);
 474
 475         if (read_val)
 476                 return regmap_read(st->regmap, reg, read_val);
 477
 478         return regmap_write(st->regmap, reg, write_val);
 479 }
 480
 481 static const struct iio_info adf4377_info = {
 482         .debugfs_reg_access = &adf4377_reg_access,
 483 };
 484
 485 static int adf4377_soft_reset(struct adf4377_state *st)
 486 {
 487         unsigned int read_val;
 488         int ret;
 489
 490         ret = regmap_update_bits(st->regmap, 0x0, ADF4377_0000_SOFT_RESET_MSK |
 491                                  ADF4377_0000_SOFT_RESET_R_MSK,
 492                                  FIELD_PREP(ADF4377_0000_SOFT_RESET_MSK, 1) |
 493                                  FIELD_PREP(ADF4377_0000_SOFT_RESET_R_MSK, 1));
 494         if (ret)
 495                 return ret;
 496
 497         return regmap_read_poll_timeout(st->regmap, 0x0, read_val,
 498                                         !(read_val & (ADF4377_0000_SOFT_RESET_R_MSK |
 499                                         ADF4377_0000_SOFT_RESET_R_MSK)), 200, 200 * 100);
 500 }
 501
 502 static int adf4377_get_freq(struct adf4377_state *st, u64 *freq)
 503 {
 504         unsigned int ref_div_factor, n_int;
 505         u64 clkin_freq;
 506         int ret;
 507
 508         mutex_lock(&st->lock);
 509         ret = regmap_read(st->regmap, 0x12, &ref_div_factor);
 510         if (ret)
 511                 goto exit;
 512
 513         ret = regmap_bulk_read(st->regmap, 0x10, st->buf, sizeof(st->buf));
 514         if (ret)
 515                 goto exit;
 516
 517         clkin_freq = clk_get_rate(st->clkin);
 518         ref_div_factor = FIELD_GET(ADF4377_0012_R_DIV_MSK, ref_div_factor);
 519         n_int = FIELD_GET(ADF4377_0010_N_INT_LSB_MSK | ADF4377_0011_N_INT_MSB_MSK,
 520                           get_unaligned_le16(&st->buf));
 521
 522         *freq = div_u64(clkin_freq, ref_div_factor) * n_int;
 523 exit:
 524         mutex_unlock(&st->lock);
 525
 526         return ret;
 527 }
 528
 529 static int adf4377_set_freq(struct adf4377_state *st, u64 freq)
 530 {
 531         unsigned int read_val;
 532         u64 f_vco;
 533         int ret;
 534
 535         mutex_lock(&st->lock);
 536
 537         if (freq > ADF4377_MAX_CLKPN_FREQ || freq < ADF4377_MIN_CLKPN_FREQ) {
 538                 ret = -EINVAL;
 539                 goto exit;
 540         }
 541
 542         ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK |
 543                                  ADF4377_001C_EN_DRCLK_MSK,
 544                                  FIELD_PREP(ADF4377_001C_EN_DNCLK_MSK, 1) |
 545                                  FIELD_PREP(ADF4377_001C_EN_DRCLK_MSK, 1));
 546         if (ret)
 547                 goto exit;
 548
 549         ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_AUTOCAL_MSK |
 550                                  ADF4377_0011_DCLK_DIV2_MSK,
 551                                  FIELD_PREP(ADF4377_0011_EN_AUTOCAL_MSK, 1) |
 552                                  FIELD_PREP(ADF4377_0011_DCLK_DIV2_MSK, st->dclk_div2));
 553         if (ret)
 554                 goto exit;
 555
 556         ret = regmap_update_bits(st->regmap, 0x2E, ADF4377_002E_EN_ADC_CNV_MSK |
 557                                  ADF4377_002E_EN_ADC_MSK |
 558                                  ADF4377_002E_ADC_A_CONV_MSK,
 559                                  FIELD_PREP(ADF4377_002E_EN_ADC_CNV_MSK, 1) |
 560                                  FIELD_PREP(ADF4377_002E_EN_ADC_MSK, 1) |
 561                                  FIELD_PREP(ADF4377_002E_ADC_A_CONV_MSK,
 562                                             ADF4377_002E_ADC_A_CONV_VCO_CALIB));
 563         if (ret)
 564                 goto exit;
 565
 566         ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK,
 567                                  FIELD_PREP(ADF4377_0020_EN_ADC_CLK_MSK, 1));
 568         if (ret)
 569                 goto exit;
 570
 571         ret = regmap_update_bits(st->regmap, 0x2F, ADF4377_002F_DCLK_DIV1_MSK,
 572                                  FIELD_PREP(ADF4377_002F_DCLK_DIV1_MSK, st->dclk_div1));
 573         if (ret)
 574                 goto exit;
 575
 576         ret = regmap_update_bits(st->regmap, 0x24, ADF4377_0024_DCLK_MODE_MSK,
 577                                  FIELD_PREP(ADF4377_0024_DCLK_MODE_MSK, st->dclk_mode));
 578         if (ret)
 579                 goto exit;
 580
 581         ret = regmap_write(st->regmap, 0x27,
 582                            FIELD_PREP(ADF4377_0027_SYNTH_LOCK_TO_LSB_MSK,
 583                                       st->synth_lock_timeout));
 584         if (ret)
 585                 goto exit;
 586
 587         ret = regmap_update_bits(st->regmap, 0x28, ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK,
 588                                  FIELD_PREP(ADF4377_0028_SYNTH_LOCK_TO_MSB_MSK,
 589                                             st->synth_lock_timeout >> 8));
 590         if (ret)
 591                 goto exit;
 592
 593         ret = regmap_write(st->regmap, 0x29,
 594                            FIELD_PREP(ADF4377_0029_VCO_ALC_TO_LSB_MSK,
 595                                       st->vco_alc_timeout));
 596         if (ret)
 597                 goto exit;
 598
 599         ret = regmap_update_bits(st->regmap, 0x2A, ADF4377_002A_VCO_ALC_TO_MSB_MSK,
 600                                  FIELD_PREP(ADF4377_002A_VCO_ALC_TO_MSB_MSK,
 601                                             st->vco_alc_timeout >> 8));
 602         if (ret)
 603                 goto exit;
 604
 605         ret = regmap_write(st->regmap, 0x26,
 606                            FIELD_PREP(ADF4377_0026_VCO_BAND_DIV_MSK, st->vco_band_div));
 607         if (ret)
 608                 goto exit;
 609
 610         ret = regmap_write(st->regmap, 0x2D,
 611                            FIELD_PREP(ADF4377_002D_ADC_CLK_DIV_MSK, st->adc_clk_div));
 612         if (ret)
 613                 goto exit;
 614
 615         st->clkout_div_sel = 0;
 616
 617         f_vco = freq;
 618
 619         while (f_vco < ADF4377_MIN_VCO_FREQ) {
 620                 f_vco <<= 1;
 621                 st->clkout_div_sel++;
 622         }
 623
 624         st->n_int = div_u64(freq, st->f_pfd);
 625
 626         ret = regmap_update_bits(st->regmap, 0x11, ADF4377_0011_EN_RDBLR_MSK |
 627                                  ADF4377_0011_N_INT_MSB_MSK,
 628                                  FIELD_PREP(ADF4377_0011_EN_RDBLR_MSK, 0) |
 629                                  FIELD_PREP(ADF4377_0011_N_INT_MSB_MSK, st->n_int >> 8));
 630         if (ret)
 631                 goto exit;
 632
 633         ret = regmap_update_bits(st->regmap, 0x12, ADF4377_0012_R_DIV_MSK |
 634                                  ADF4377_0012_CLKOUT_DIV_MSK,
 635                                  FIELD_PREP(ADF4377_0012_CLKOUT_DIV_MSK, st->clkout_div_sel) |
 636                                  FIELD_PREP(ADF4377_0012_R_DIV_MSK, st->ref_div_factor));
 637         if (ret)
 638                 goto exit;
 639
 640         ret = regmap_write(st->regmap, 0x10,
 641                            FIELD_PREP(ADF4377_0010_N_INT_LSB_MSK, st->n_int));
 642         if (ret)
 643                 goto exit;
 644
 645         ret = regmap_read_poll_timeout(st->regmap, 0x49, read_val,
 646                                        !(read_val & (ADF4377_0049_FSM_BUSY_MSK)), 200, 200 * 100);
 647         if (ret)
 648                 goto exit;
 649
 650         /* Disable EN_DNCLK, EN_DRCLK */
 651         ret = regmap_update_bits(st->regmap, 0x1C, ADF4377_001C_EN_DNCLK_MSK |
 652                                  ADF4377_001C_EN_DRCLK_MSK,
 653                                  FIELD_PREP(ADF4377_001C_EN_DNCLK_MSK, 0) |
 654                                  FIELD_PREP(ADF4377_001C_EN_DRCLK_MSK, 0));
 655         if (ret)
 656                 goto exit;
 657
 658         /* Disable EN_ADC_CLK */
 659         ret = regmap_update_bits(st->regmap, 0x20, ADF4377_0020_EN_ADC_CLK_MSK,
 660                                  FIELD_PREP(ADF4377_0020_EN_ADC_CLK_MSK, 0));
 661         if (ret)
 662                 goto exit;
 663
 664         /* Set output Amplitude */
 665         ret = regmap_update_bits(st->regmap, 0x19, ADF4377_0019_CLKOUT2_OP_MSK |
 666                                  ADF4377_0019_CLKOUT1_OP_MSK,
 667                                  FIELD_PREP(ADF4377_0019_CLKOUT1_OP_MSK,
 668                                             ADF4377_0019_CLKOUT_420MV) |
 669                                  FIELD_PREP(ADF4377_0019_CLKOUT2_OP_MSK,
 670                                             ADF4377_0019_CLKOUT_420MV));
 671
 672 exit:
 673         mutex_unlock(&st->lock);
 674
 675         return ret;
 676 }
 677
 678 static void adf4377_gpio_init(struct adf4377_state *st)
 679 {
 680         if (st->gpio_ce) {
 681                 gpiod_set_value(st->gpio_ce, 1);
 682
 683                 /* Delay for SPI register bits to settle to their power-on reset state */
 684                 fsleep(200);
 685         }
 686
 687         if (st->gpio_enclk1)
 688                 gpiod_set_value(st->gpio_enclk1, 1);
 689
 690         if (st->gpio_enclk2)
 691                 gpiod_set_value(st->gpio_enclk2, 1);
 692 }
 693
 694 static int adf4377_init(struct adf4377_state *st)
 695 {
 696         struct spi_device *spi = st->spi;
 697         int ret;
 698
 699         adf4377_gpio_init(st);
 700
 701         ret = adf4377_soft_reset(st);
 702         if (ret) {
 703                 dev_err(&spi->dev, "Failed to soft reset.\n");
 704                 return ret;
 705         }
 706
 707         ret = regmap_multi_reg_write(st->regmap, adf4377_reg_defaults,
 708                                      ARRAY_SIZE(adf4377_reg_defaults));
 709         if (ret) {
 710                 dev_err(&spi->dev, "Failed to set default registers.\n");
 711                 return ret;
 712         }
 713
 714         ret = regmap_update_bits(st->regmap, 0x00,
 715                                  ADF4377_0000_SDO_ACTIVE_MSK | ADF4377_0000_SDO_ACTIVE_R_MSK,
 716                                  FIELD_PREP(ADF4377_0000_SDO_ACTIVE_MSK,
 717                                             ADF4377_0000_SDO_ACTIVE_SPI_4W) |
 718                                  FIELD_PREP(ADF4377_0000_SDO_ACTIVE_R_MSK,
 719                                             ADF4377_0000_SDO_ACTIVE_SPI_4W));
 720         if (ret) {
 721                 dev_err(&spi->dev, "Failed to set 4-Wire Operation.\n");
 722                 return ret;
 723         }
 724
 725         st->clkin_freq = clk_get_rate(st->clkin);
 726
 727         /* Power Up */
 728         ret = regmap_write(st->regmap, 0x1a,
 729                            FIELD_PREP(ADF4377_001A_PD_ALL_MSK, 0) |
 730                            FIELD_PREP(ADF4377_001A_PD_RDIV_MSK, 0) |
 731                            FIELD_PREP(ADF4377_001A_PD_NDIV_MSK, 0) |
 732                            FIELD_PREP(ADF4377_001A_PD_VCO_MSK, 0) |
 733                            FIELD_PREP(ADF4377_001A_PD_LD_MSK, 0) |
 734                            FIELD_PREP(ADF4377_001A_PD_PFDCP_MSK, 0) |
 735                            FIELD_PREP(ADF4377_001A_PD_CLKOUT1_MSK, 0) |
 736                            FIELD_PREP(ADF4377_001A_PD_CLKOUT2_MSK, 0));
 737         if (ret) {
 738                 dev_err(&spi->dev, "Failed to set power down registers.\n");
 739                 return ret;
 740         }
 741
 742         /* Set Mux Output */
 743         ret = regmap_update_bits(st->regmap, 0x1D,
 744                                  ADF4377_001D_MUXOUT_MSK,
 745                                  FIELD_PREP(ADF4377_001D_MUXOUT_MSK, st->muxout_select));
 746         if (ret)
 747                 return ret;
 748
 749         /* Compute PFD */
 750         st->ref_div_factor = 0;
 751         do {
 752                 st->ref_div_factor++;
 753                 st->f_pfd = st->clkin_freq / st->ref_div_factor;
 754         } while (st->f_pfd > ADF4377_MAX_FREQ_PFD);
 755
 756         if (st->f_pfd > ADF4377_MAX_FREQ_PFD || st->f_pfd < ADF4377_MIN_FREQ_PFD)
 757                 return -EINVAL;
 758
 759         st->f_div_rclk = st->f_pfd;
 760
 761         if (st->f_pfd <= ADF4377_FREQ_PFD_80MHZ) {
 762                 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1;
 763                 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1;
 764                 st->dclk_mode = 0;
 765         } else if (st->f_pfd <= ADF4377_FREQ_PFD_125MHZ) {
 766                 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_1;
 767                 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1;
 768                 st->dclk_mode = 1;
 769         } else if (st->f_pfd <= ADF4377_FREQ_PFD_160MHZ) {
 770                 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2;
 771                 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1;
 772                 st->dclk_mode = 0;
 773                 st->f_div_rclk /= 2;
 774         } else if (st->f_pfd <= ADF4377_FREQ_PFD_250MHZ) {
 775                 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2;
 776                 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_1;
 777                 st->dclk_mode = 1;
 778                 st->f_div_rclk /= 2;
 779         } else if (st->f_pfd <= ADF4377_FREQ_PFD_320MHZ) {
 780                 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2;
 781                 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2;
 782                 st->dclk_mode = 0;
 783                 st->f_div_rclk /= 4;
 784         } else {
 785                 st->dclk_div1 = ADF4377_002F_DCLK_DIV1_2;
 786                 st->dclk_div2 = ADF4377_0011_DCLK_DIV2_2;
 787                 st->dclk_mode = 1;
 788                 st->f_div_rclk /= 4;
 789         }
 790
 791         st->synth_lock_timeout = DIV_ROUND_UP(st->f_div_rclk, 50000);
 792         st->vco_alc_timeout = DIV_ROUND_UP(st->f_div_rclk, 20000);
 793         st->vco_band_div = DIV_ROUND_UP(st->f_div_rclk, 150000 * 16 * (1 << st->dclk_mode));
 794         st->adc_clk_div = DIV_ROUND_UP((st->f_div_rclk / 400000 - 2), 4);
 795
 796         return 0;
 797 }
 798
 799 static ssize_t adf4377_read(struct iio_dev *indio_dev, uintptr_t private,
 800                             const struct iio_chan_spec *chan, char *buf)
 801 {
 802         struct adf4377_state *st = iio_priv(indio_dev);
 803         u64 val = 0;
 804         int ret;
 805
 806         switch ((u32)private) {
 807         case ADF4377_FREQ:
 808                 ret = adf4377_get_freq(st, &val);
 809                 if (ret)
 810                         return ret;
 811
 812                 return sysfs_emit(buf, "%llu\n", val);
 813         default:
 814                 return -EINVAL;
 815         }
 816 }
 817
 818 static ssize_t adf4377_write(struct iio_dev *indio_dev, uintptr_t private,
 819                              const struct iio_chan_spec *chan, const char *buf,
 820                              size_t len)
 821 {
 822         struct adf4377_state *st = iio_priv(indio_dev);
 823         unsigned long long freq;
 824         int ret;
 825
 826         switch ((u32)private) {
 827         case ADF4377_FREQ:
 828                 ret = kstrtoull(buf, 10, &freq);
 829                 if (ret)
 830                         return ret;
 831
 832                 ret = adf4377_set_freq(st, freq);
 833                 if (ret)
 834                         return ret;
 835
 836                 return len;
 837         default:
 838                 return -EINVAL;
 839         }
 840 }
 841
 842 #define _ADF4377_EXT_INFO(_name, _shared, _ident) { \
 843                 .name = _name, \
 844                 .read = adf4377_read, \
 845                 .write = adf4377_write, \
 846                 .private = _ident, \
 847                 .shared = _shared, \
 848         }
 849
 850 static const struct iio_chan_spec_ext_info adf4377_ext_info[] = {
 851         /*
 852          * Usually we use IIO_CHAN_INFO_FREQUENCY, but there are
 853          * values > 2^32 in order to support the entire frequency range
 854          * in Hz.
 855          */
 856         _ADF4377_EXT_INFO("frequency", IIO_SEPARATE, ADF4377_FREQ),
 857         { }
 858 };
 859
 860 static const struct iio_chan_spec adf4377_channels[] = {
 861         {
 862                 .type = IIO_ALTVOLTAGE,
 863                 .indexed = 1,
 864                 .output = 1,
 865                 .channel = 0,
 866                 .ext_info = adf4377_ext_info,
 867         },
 868 };
 869
 870 static int adf4377_properties_parse(struct adf4377_state *st)
 871 {
 872         struct spi_device *spi = st->spi;
 873         const char *str;
 874         int ret;
 875
 876         st->clkin = devm_clk_get_enabled(&spi->dev, "ref_in");
 877         if (IS_ERR(st->clkin))
 878                 return dev_err_probe(&spi->dev, PTR_ERR(st->clkin),
 879                                      "failed to get the reference input clock\n");
 880
 881         st->gpio_ce = devm_gpiod_get_optional(&st->spi->dev, "chip-enable",
 882                                               GPIOD_OUT_LOW);
 883         if (IS_ERR(st->gpio_ce))
 884                 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_ce),
 885                                      "failed to get the CE GPIO\n");
 886
 887         st->gpio_enclk1 = devm_gpiod_get_optional(&st->spi->dev, "clk1-enable",
 888                                                   GPIOD_OUT_LOW);
 889         if (IS_ERR(st->gpio_enclk1))
 890                 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_enclk1),
 891                                      "failed to get the CE GPIO\n");
 892
 893         st->gpio_enclk2 = devm_gpiod_get_optional(&st->spi->dev, "clk2-enable",
 894                                                   GPIOD_OUT_LOW);
 895         if (IS_ERR(st->gpio_enclk2))
 896                 return dev_err_probe(&spi->dev, PTR_ERR(st->gpio_enclk2),
 897                                      "failed to get the CE GPIO\n");
 898
 899         ret = device_property_read_string(&spi->dev, "adi,muxout-select", &str);
 900         if (ret) {
 901                 st->muxout_select = ADF4377_MUXOUT_HIGH_Z;
 902         } else {
 903                 ret = match_string(adf4377_muxout_modes, ARRAY_SIZE(adf4377_muxout_modes), str);
 904                 if (ret < 0)
 905                         return ret;
 906
 907                 st->muxout_select = ret;
 908         }
 909
 910         return 0;
 911 }
 912
 913 static int adf4377_freq_change(struct notifier_block *nb, unsigned long action, void *data)
 914 {
 915         struct adf4377_state *st = container_of(nb, struct adf4377_state, nb);
 916         int ret;
 917
 918         if (action == POST_RATE_CHANGE) {
 919                 mutex_lock(&st->lock);
 920                 ret = notifier_from_errno(adf4377_init(st));
 921                 mutex_unlock(&st->lock);
 922                 return ret;
 923         }
 924
 925         return NOTIFY_OK;
 926 }
 927
 928 static int adf4377_probe(struct spi_device *spi)
 929 {
 930         struct iio_dev *indio_dev;
 931         struct regmap *regmap;
 932         struct adf4377_state *st;
 933         int ret;
 934
 935         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 936         if (!indio_dev)
 937                 return -ENOMEM;
 938
 939         regmap = devm_regmap_init_spi(spi, &adf4377_regmap_config);
 940         if (IS_ERR(regmap))
 941                 return PTR_ERR(regmap);
 942
 943         st = iio_priv(indio_dev);
 944
 945         indio_dev->info = &adf4377_info;
 946         indio_dev->name = "adf4377";
 947         indio_dev->channels = adf4377_channels;
 948         indio_dev->num_channels = ARRAY_SIZE(adf4377_channels);
 949
 950         st->regmap = regmap;
 951         st->spi = spi;
 952         mutex_init(&st->lock);
 953
 954         ret = adf4377_properties_parse(st);
 955         if (ret)
 956                 return ret;
 957
 958         st->nb.notifier_call = adf4377_freq_change;
 959         ret = devm_clk_notifier_register(&spi->dev, st->clkin, &st->nb);
 960         if (ret)
 961                 return ret;
 962
 963         ret = adf4377_init(st);
 964         if (ret)
 965                 return ret;
 966
 967         return devm_iio_device_register(&spi->dev, indio_dev);
 968 }
 969
 970 static const struct spi_device_id adf4377_id[] = {
 971         { "adf4377", 0 },
 972         {}
 973 };
 974 MODULE_DEVICE_TABLE(spi, adf4377_id);
 975
 976 static const struct of_device_id adf4377_of_match[] = {
 977         { .compatible = "adi,adf4377" },
 978         {}
 979 };
 980 MODULE_DEVICE_TABLE(of, adf4377_of_match);
 981
 982 static struct spi_driver adf4377_driver = {
 983         .driver = {
 984                 .name = "adf4377",
 985                 .of_match_table = adf4377_of_match,
 986         },
 987         .probe = adf4377_probe,
 988         .id_table = adf4377_id,
 989 };
 990 module_spi_driver(adf4377_driver);
 991
 992 MODULE_AUTHOR("Antoniu Miclaus <[email protected]>");
 993 MODULE_DESCRIPTION("Analog Devices ADF4377");
 994 MODULE_LICENSE("GPL");