drivers/iio/adc/ti-ads131e08.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
   4  *
   5  * Copyright (c) 2020 AVL DiTEST GmbH
   6  *   Tomislav Denis <[email protected]>
   7  *
   8  * Datasheet: https://www.ti.com/lit/ds/symlink/ads131e08.pdf
   9  */
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/module.h>
  15
  16 #include <linux/iio/buffer.h>
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/sysfs.h>
  19 #include <linux/iio/trigger.h>
  20 #include <linux/iio/trigger_consumer.h>
  21 #include <linux/iio/triggered_buffer.h>
  22
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/spi/spi.h>
  25
  26 #include <asm/unaligned.h>
  27
  28 /* Commands */
  29 #define ADS131E08_CMD_RESET             0x06
  30 #define ADS131E08_CMD_START             0x08
  31 #define ADS131E08_CMD_STOP              0x0A
  32 #define ADS131E08_CMD_OFFSETCAL         0x1A
  33 #define ADS131E08_CMD_SDATAC            0x11
  34 #define ADS131E08_CMD_RDATA             0x12
  35 #define ADS131E08_CMD_RREG(r)           (BIT(5) | (r & GENMASK(4, 0)))
  36 #define ADS131E08_CMD_WREG(r)           (BIT(6) | (r & GENMASK(4, 0)))
  37
  38 /* Registers */
  39 #define ADS131E08_ADR_CFG1R             0x01
  40 #define ADS131E08_ADR_CFG3R             0x03
  41 #define ADS131E08_ADR_CH0R              0x05
  42
  43 /* Configuration register 1 */
  44 #define ADS131E08_CFG1R_DR_MASK         GENMASK(2, 0)
  45
  46 /* Configuration register 3 */
  47 #define ADS131E08_CFG3R_PDB_REFBUF_MASK BIT(7)
  48 #define ADS131E08_CFG3R_VREF_4V_MASK    BIT(5)
  49
  50 /* Channel settings register */
  51 #define ADS131E08_CHR_GAIN_MASK         GENMASK(6, 4)
  52 #define ADS131E08_CHR_MUX_MASK          GENMASK(2, 0)
  53 #define ADS131E08_CHR_PWD_MASK          BIT(7)
  54
  55 /* ADC  misc */
  56 #define ADS131E08_DEFAULT_DATA_RATE     1
  57 #define ADS131E08_DEFAULT_PGA_GAIN      1
  58 #define ADS131E08_DEFAULT_MUX           0
  59
  60 #define ADS131E08_VREF_2V4_mV           2400
  61 #define ADS131E08_VREF_4V_mV            4000
  62
  63 #define ADS131E08_WAIT_RESET_CYCLES     18
  64 #define ADS131E08_WAIT_SDECODE_CYCLES   4
  65 #define ADS131E08_WAIT_OFFSETCAL_MS     153
  66 #define ADS131E08_MAX_SETTLING_TIME_MS  6
  67
  68 #define ADS131E08_NUM_STATUS_BYTES      3
  69 #define ADS131E08_NUM_DATA_BYTES_MAX    24
  70 #define ADS131E08_NUM_DATA_BYTES(dr)    (((dr) >= 32) ? 2 : 3)
  71 #define ADS131E08_NUM_DATA_BITS(dr)     (ADS131E08_NUM_DATA_BYTES(dr) * 8)
  72 #define ADS131E08_NUM_STORAGE_BYTES     4
  73
  74 enum ads131e08_ids {
  75         ads131e04,
  76         ads131e06,
  77         ads131e08,
  78 };
  79
  80 struct ads131e08_info {
  81         unsigned int max_channels;
  82         const char *name;
  83 };
  84
  85 struct ads131e08_channel_config {
  86         unsigned int pga_gain;
  87         unsigned int mux;
  88 };
  89
  90 struct ads131e08_state {
  91         const struct ads131e08_info *info;
  92         struct spi_device *spi;
  93         struct iio_trigger *trig;
  94         struct clk *adc_clk;
  95         struct regulator *vref_reg;
  96         struct ads131e08_channel_config *channel_config;
  97         unsigned int data_rate;
  98         unsigned int vref_mv;
  99         unsigned int sdecode_delay_us;
 100         unsigned int reset_delay_us;
 101         unsigned int readback_len;
 102         struct completion completion;
 103         struct {
 104                 u8 data[ADS131E08_NUM_DATA_BYTES_MAX];
 105                 s64 ts __aligned(8);
 106         } tmp_buf;
 107
 108         u8 tx_buf[3] __aligned(IIO_DMA_MINALIGN);
 109         /*
 110          * Add extra one padding byte to be able to access the last channel
 111          * value using u32 pointer
 112          */
 113         u8 rx_buf[ADS131E08_NUM_STATUS_BYTES +
 114                 ADS131E08_NUM_DATA_BYTES_MAX + 1];
 115 };
 116
 117 static const struct ads131e08_info ads131e08_info_tbl[] = {
 118         [ads131e04] = {
 119                 .max_channels = 4,
 120                 .name = "ads131e04",
 121         },
 122         [ads131e06] = {
 123                 .max_channels = 6,
 124                 .name = "ads131e06",
 125         },
 126         [ads131e08] = {
 127                 .max_channels = 8,
 128                 .name = "ads131e08",
 129         },
 130 };
 131
 132 struct ads131e08_data_rate_desc {
 133         unsigned int rate;  /* data rate in kSPS */
 134         u8 reg;             /* reg value */
 135 };
 136
 137 static const struct ads131e08_data_rate_desc ads131e08_data_rate_tbl[] = {
 138         { .rate = 64,   .reg = 0x00 },
 139         { .rate = 32,   .reg = 0x01 },
 140         { .rate = 16,   .reg = 0x02 },
 141         { .rate = 8,    .reg = 0x03 },
 142         { .rate = 4,    .reg = 0x04 },
 143         { .rate = 2,    .reg = 0x05 },
 144         { .rate = 1,    .reg = 0x06 },
 145 };
 146
 147 struct ads131e08_pga_gain_desc {
 148         unsigned int gain;  /* PGA gain value */
 149         u8 reg;             /* field value */
 150 };
 151
 152 static const struct ads131e08_pga_gain_desc ads131e08_pga_gain_tbl[] = {
 153         { .gain = 1,   .reg = 0x01 },
 154         { .gain = 2,   .reg = 0x02 },
 155         { .gain = 4,   .reg = 0x04 },
 156         { .gain = 8,   .reg = 0x05 },
 157         { .gain = 12,  .reg = 0x06 },
 158 };
 159
 160 static const u8 ads131e08_valid_channel_mux_values[] = { 0, 1, 3, 4 };
 161
 162 static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd)
 163 {
 164         int ret;
 165
 166         ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0);
 167         if (ret)
 168                 dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd);
 169
 170         return ret;
 171 }
 172
 173 static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg)
 174 {
 175         int ret;
 176         struct spi_transfer transfer[] = {
 177                 {
 178                         .tx_buf = &st->tx_buf,
 179                         .len = 2,
 180                         .delay = {
 181                                 .value = st->sdecode_delay_us,
 182                                 .unit = SPI_DELAY_UNIT_USECS,
 183                         },
 184                 }, {
 185                         .rx_buf = &st->rx_buf,
 186                         .len = 1,
 187                 },
 188         };
 189
 190         st->tx_buf[0] = ADS131E08_CMD_RREG(reg);
 191         st->tx_buf[1] = 0;
 192
 193         ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
 194         if (ret) {
 195                 dev_err(&st->spi->dev, "Read register failed\n");
 196                 return ret;
 197         }
 198
 199         return st->rx_buf[0];
 200 }
 201
 202 static int ads131e08_write_reg(struct ads131e08_state *st, u8 reg, u8 value)
 203 {
 204         int ret;
 205         struct spi_transfer transfer[] = {
 206                 {
 207                         .tx_buf = &st->tx_buf,
 208                         .len = 3,
 209                         .delay = {
 210                                 .value = st->sdecode_delay_us,
 211                                 .unit = SPI_DELAY_UNIT_USECS,
 212                         },
 213                 }
 214         };
 215
 216         st->tx_buf[0] = ADS131E08_CMD_WREG(reg);
 217         st->tx_buf[1] = 0;
 218         st->tx_buf[2] = value;
 219
 220         ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
 221         if (ret)
 222                 dev_err(&st->spi->dev, "Write register failed\n");
 223
 224         return ret;
 225 }
 226
 227 static int ads131e08_read_data(struct ads131e08_state *st, int rx_len)
 228 {
 229         int ret;
 230         struct spi_transfer transfer[] = {
 231                 {
 232                         .tx_buf = &st->tx_buf,
 233                         .len = 1,
 234                 }, {
 235                         .rx_buf = &st->rx_buf,
 236                         .len = rx_len,
 237                 },
 238         };
 239
 240         st->tx_buf[0] = ADS131E08_CMD_RDATA;
 241
 242         ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
 243         if (ret)
 244                 dev_err(&st->spi->dev, "Read data failed\n");
 245
 246         return ret;
 247 }
 248
 249 static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate)
 250 {
 251         int i, reg, ret;
 252
 253         for (i = 0; i < ARRAY_SIZE(ads131e08_data_rate_tbl); i++) {
 254                 if (ads131e08_data_rate_tbl[i].rate == data_rate)
 255                         break;
 256         }
 257
 258         if (i == ARRAY_SIZE(ads131e08_data_rate_tbl)) {
 259                 dev_err(&st->spi->dev, "invalid data rate value\n");
 260                 return -EINVAL;
 261         }
 262
 263         reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG1R);
 264         if (reg < 0)
 265                 return reg;
 266
 267         reg &= ~ADS131E08_CFG1R_DR_MASK;
 268         reg |= FIELD_PREP(ADS131E08_CFG1R_DR_MASK,
 269                 ads131e08_data_rate_tbl[i].reg);
 270
 271         ret = ads131e08_write_reg(st, ADS131E08_ADR_CFG1R, reg);
 272         if (ret)
 273                 return ret;
 274
 275         st->data_rate = data_rate;
 276         st->readback_len = ADS131E08_NUM_STATUS_BYTES +
 277                 ADS131E08_NUM_DATA_BYTES(st->data_rate) *
 278                 st->info->max_channels;
 279
 280         return 0;
 281 }
 282
 283 static int ads131e08_pga_gain_to_field_value(struct ads131e08_state *st,
 284         unsigned int pga_gain)
 285 {
 286         int i;
 287
 288         for (i = 0; i < ARRAY_SIZE(ads131e08_pga_gain_tbl); i++) {
 289                 if (ads131e08_pga_gain_tbl[i].gain == pga_gain)
 290                         break;
 291         }
 292
 293         if (i == ARRAY_SIZE(ads131e08_pga_gain_tbl)) {
 294                 dev_err(&st->spi->dev, "invalid PGA gain value\n");
 295                 return -EINVAL;
 296         }
 297
 298         return ads131e08_pga_gain_tbl[i].reg;
 299 }
 300
 301 static int ads131e08_set_pga_gain(struct ads131e08_state *st,
 302         unsigned int channel, unsigned int pga_gain)
 303 {
 304         int field_value, reg;
 305
 306         field_value = ads131e08_pga_gain_to_field_value(st, pga_gain);
 307         if (field_value < 0)
 308                 return field_value;
 309
 310         reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
 311         if (reg < 0)
 312                 return reg;
 313
 314         reg &= ~ADS131E08_CHR_GAIN_MASK;
 315         reg |= FIELD_PREP(ADS131E08_CHR_GAIN_MASK, field_value);
 316
 317         return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
 318 }
 319
 320 static int ads131e08_validate_channel_mux(struct ads131e08_state *st,
 321         unsigned int mux)
 322 {
 323         int i;
 324
 325         for (i = 0; i < ARRAY_SIZE(ads131e08_valid_channel_mux_values); i++) {
 326                 if (ads131e08_valid_channel_mux_values[i] == mux)
 327                         break;
 328         }
 329
 330         if (i == ARRAY_SIZE(ads131e08_valid_channel_mux_values)) {
 331                 dev_err(&st->spi->dev, "invalid channel mux value\n");
 332                 return -EINVAL;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static int ads131e08_set_channel_mux(struct ads131e08_state *st,
 339         unsigned int channel, unsigned int mux)
 340 {
 341         int reg;
 342
 343         reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
 344         if (reg < 0)
 345                 return reg;
 346
 347         reg &= ~ADS131E08_CHR_MUX_MASK;
 348         reg |= FIELD_PREP(ADS131E08_CHR_MUX_MASK, mux);
 349
 350         return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
 351 }
 352
 353 static int ads131e08_power_down_channel(struct ads131e08_state *st,
 354         unsigned int channel, bool value)
 355 {
 356         int reg;
 357
 358         reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
 359         if (reg < 0)
 360                 return reg;
 361
 362         reg &= ~ADS131E08_CHR_PWD_MASK;
 363         reg |= FIELD_PREP(ADS131E08_CHR_PWD_MASK, value);
 364
 365         return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
 366 }
 367
 368 static int ads131e08_config_reference_voltage(struct ads131e08_state *st)
 369 {
 370         int reg;
 371
 372         reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG3R);
 373         if (reg < 0)
 374                 return reg;
 375
 376         reg &= ~ADS131E08_CFG3R_PDB_REFBUF_MASK;
 377         if (!st->vref_reg) {
 378                 reg |= FIELD_PREP(ADS131E08_CFG3R_PDB_REFBUF_MASK, 1);
 379                 reg &= ~ADS131E08_CFG3R_VREF_4V_MASK;
 380                 reg |= FIELD_PREP(ADS131E08_CFG3R_VREF_4V_MASK,
 381                         st->vref_mv == ADS131E08_VREF_4V_mV);
 382         }
 383
 384         return ads131e08_write_reg(st, ADS131E08_ADR_CFG3R, reg);
 385 }
 386
 387 static int ads131e08_initial_config(struct iio_dev *indio_dev)
 388 {
 389         const struct iio_chan_spec *channel = indio_dev->channels;
 390         struct ads131e08_state *st = iio_priv(indio_dev);
 391         unsigned long active_channels = 0;
 392         int ret, i;
 393
 394         ret = ads131e08_exec_cmd(st, ADS131E08_CMD_RESET);
 395         if (ret)
 396                 return ret;
 397
 398         udelay(st->reset_delay_us);
 399
 400         /* Disable read data in continuous mode (enabled by default) */
 401         ret = ads131e08_exec_cmd(st, ADS131E08_CMD_SDATAC);
 402         if (ret)
 403                 return ret;
 404
 405         ret = ads131e08_set_data_rate(st, ADS131E08_DEFAULT_DATA_RATE);
 406         if (ret)
 407                 return ret;
 408
 409         ret = ads131e08_config_reference_voltage(st);
 410         if (ret)
 411                 return ret;
 412
 413         for (i = 0;  i < indio_dev->num_channels; i++) {
 414                 ret = ads131e08_set_pga_gain(st, channel->channel,
 415                         st->channel_config[i].pga_gain);
 416                 if (ret)
 417                         return ret;
 418
 419                 ret = ads131e08_set_channel_mux(st, channel->channel,
 420                         st->channel_config[i].mux);
 421                 if (ret)
 422                         return ret;
 423
 424                 active_channels |= BIT(channel->channel);
 425                 channel++;
 426         }
 427
 428         /* Power down unused channels */
 429         for_each_clear_bit(i, &active_channels, st->info->max_channels) {
 430                 ret = ads131e08_power_down_channel(st, i, true);
 431                 if (ret)
 432                         return ret;
 433         }
 434
 435         /* Request channel offset calibration */
 436         ret = ads131e08_exec_cmd(st, ADS131E08_CMD_OFFSETCAL);
 437         if (ret)
 438                 return ret;
 439
 440         /*
 441          * Channel offset calibration is triggered with the first START
 442          * command. Since calibration takes more time than settling operation,
 443          * this causes timeout error when command START is sent first
 444          * time (e.g. first call of the ads131e08_read_direct method).
 445          * To avoid this problem offset calibration is triggered here.
 446          */
 447         ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);
 448         if (ret)
 449                 return ret;
 450
 451         msleep(ADS131E08_WAIT_OFFSETCAL_MS);
 452
 453         return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);
 454 }
 455
 456 static int ads131e08_pool_data(struct ads131e08_state *st)
 457 {
 458         unsigned long timeout;
 459         int ret;
 460
 461         reinit_completion(&st->completion);
 462
 463         ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);
 464         if (ret)
 465                 return ret;
 466
 467         timeout = msecs_to_jiffies(ADS131E08_MAX_SETTLING_TIME_MS);
 468         ret = wait_for_completion_timeout(&st->completion, timeout);
 469         if (!ret)
 470                 return -ETIMEDOUT;
 471
 472         ret = ads131e08_read_data(st, st->readback_len);
 473         if (ret)
 474                 return ret;
 475
 476         return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);
 477 }
 478
 479 static int ads131e08_read_direct(struct iio_dev *indio_dev,
 480         struct iio_chan_spec const *channel, int *value)
 481 {
 482         struct ads131e08_state *st = iio_priv(indio_dev);
 483         u8 num_bits, *src;
 484         int ret;
 485
 486         ret = ads131e08_pool_data(st);
 487         if (ret)
 488                 return ret;
 489
 490         src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES +
 491                 channel->channel * ADS131E08_NUM_DATA_BYTES(st->data_rate);
 492
 493         num_bits = ADS131E08_NUM_DATA_BITS(st->data_rate);
 494         *value = sign_extend32(get_unaligned_be32(src) >> (32 - num_bits), num_bits - 1);
 495
 496         return 0;
 497 }
 498
 499 static int ads131e08_read_raw(struct iio_dev *indio_dev,
 500         struct iio_chan_spec const *channel, int *value,
 501         int *value2, long mask)
 502 {
 503         struct ads131e08_state *st = iio_priv(indio_dev);
 504         int ret;
 505
 506         switch (mask) {
 507         case IIO_CHAN_INFO_RAW:
 508                 ret = iio_device_claim_direct_mode(indio_dev);
 509                 if (ret)
 510                         return ret;
 511
 512                 ret = ads131e08_read_direct(indio_dev, channel, value);
 513                 iio_device_release_direct_mode(indio_dev);
 514                 if (ret)
 515                         return ret;
 516
 517                 return IIO_VAL_INT;
 518
 519         case IIO_CHAN_INFO_SCALE:
 520                 if (st->vref_reg) {
 521                         ret = regulator_get_voltage(st->vref_reg);
 522                         if (ret < 0)
 523                                 return ret;
 524
 525                         *value = ret / 1000;
 526                 } else {
 527                         *value = st->vref_mv;
 528                 }
 529
 530                 *value /= st->channel_config[channel->address].pga_gain;
 531                 *value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1;
 532
 533                 return IIO_VAL_FRACTIONAL_LOG2;
 534
 535         case IIO_CHAN_INFO_SAMP_FREQ:
 536                 *value = st->data_rate;
 537
 538                 return IIO_VAL_INT;
 539
 540         default:
 541                 return -EINVAL;
 542         }
 543 }
 544
 545 static int ads131e08_write_raw(struct iio_dev *indio_dev,
 546         struct iio_chan_spec const *channel, int value,
 547         int value2, long mask)
 548 {
 549         struct ads131e08_state *st = iio_priv(indio_dev);
 550         int ret;
 551
 552         switch (mask) {
 553         case IIO_CHAN_INFO_SAMP_FREQ:
 554                 ret = iio_device_claim_direct_mode(indio_dev);
 555                 if (ret)
 556                         return ret;
 557
 558                 ret = ads131e08_set_data_rate(st, value);
 559                 iio_device_release_direct_mode(indio_dev);
 560                 return ret;
 561
 562         default:
 563                 return -EINVAL;
 564         }
 565 }
 566
 567 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1 2 4 8 16 32 64");
 568
 569 static struct attribute *ads131e08_attributes[] = {
 570         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 571         NULL
 572 };
 573
 574 static const struct attribute_group ads131e08_attribute_group = {
 575         .attrs = ads131e08_attributes,
 576 };
 577
 578 static int ads131e08_debugfs_reg_access(struct iio_dev *indio_dev,
 579         unsigned int reg, unsigned int writeval, unsigned int *readval)
 580 {
 581         struct ads131e08_state *st = iio_priv(indio_dev);
 582
 583         if (readval) {
 584                 int ret = ads131e08_read_reg(st, reg);
 585                 *readval = ret;
 586                 return ret;
 587         }
 588
 589         return ads131e08_write_reg(st, reg, writeval);
 590 }
 591
 592 static const struct iio_info ads131e08_iio_info = {
 593         .read_raw = ads131e08_read_raw,
 594         .write_raw = ads131e08_write_raw,
 595         .attrs = &ads131e08_attribute_group,
 596         .debugfs_reg_access = &ads131e08_debugfs_reg_access,
 597 };
 598
 599 static int ads131e08_set_trigger_state(struct iio_trigger *trig, bool state)
 600 {
 601         struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
 602         struct ads131e08_state *st = iio_priv(indio_dev);
 603         u8 cmd = state ? ADS131E08_CMD_START : ADS131E08_CMD_STOP;
 604
 605         return ads131e08_exec_cmd(st, cmd);
 606 }
 607
 608 static const struct iio_trigger_ops ads131e08_trigger_ops = {
 609         .set_trigger_state = &ads131e08_set_trigger_state,
 610         .validate_device = &iio_trigger_validate_own_device,
 611 };
 612
 613 static irqreturn_t ads131e08_trigger_handler(int irq, void *private)
 614 {
 615         struct iio_poll_func *pf = private;
 616         struct iio_dev *indio_dev = pf->indio_dev;
 617         struct ads131e08_state *st = iio_priv(indio_dev);
 618         unsigned int chn, i = 0;
 619         u8 *src, *dest;
 620         int ret;
 621
 622         /*
 623          * The number of data bits per channel depends on the data rate.
 624          * For 32 and 64 ksps data rates, number of data bits per channel
 625          * is 16. This case is not compliant with used (fixed) scan element
 626          * type (be:s24/32>>8). So we use a little tweak to pack properly
 627          * 16 bits of data into the buffer.
 628          */
 629         unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate);
 630         u8 tweek_offset = num_bytes == 2 ? 1 : 0;
 631
 632         if (iio_trigger_using_own(indio_dev))
 633                 ret = ads131e08_read_data(st, st->readback_len);
 634         else
 635                 ret = ads131e08_pool_data(st);
 636
 637         if (ret)
 638                 goto out;
 639
 640         for_each_set_bit(chn, indio_dev->active_scan_mask, indio_dev->masklength) {
 641                 src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES + chn * num_bytes;
 642                 dest = st->tmp_buf.data + i * ADS131E08_NUM_STORAGE_BYTES;
 643
 644                 /*
 645                  * Tweek offset is 0:
 646                  * +---+---+---+---+
 647                  * |D0 |D1 |D2 | X | (3 data bytes)
 648                  * +---+---+---+---+
 649                  *  a+0 a+1 a+2 a+3
 650                  *
 651                  * Tweek offset is 1:
 652                  * +---+---+---+---+
 653                  * |P0 |D0 |D1 | X | (one padding byte and 2 data bytes)
 654                  * +---+---+---+---+
 655                  *  a+0 a+1 a+2 a+3
 656                  */
 657                 memcpy(dest + tweek_offset, src, num_bytes);
 658
 659                 /*
 660                  * Data conversion from 16 bits of data to 24 bits of data
 661                  * is done by sign extension (properly filling padding byte).
 662                  */
 663                 if (tweek_offset)
 664                         *dest = *src & BIT(7) ? 0xff : 0x00;
 665
 666                 i++;
 667         }
 668
 669         iio_push_to_buffers_with_timestamp(indio_dev, st->tmp_buf.data,
 670                 iio_get_time_ns(indio_dev));
 671
 672 out:
 673         iio_trigger_notify_done(indio_dev->trig);
 674
 675         return IRQ_HANDLED;
 676 }
 677
 678 static irqreturn_t ads131e08_interrupt(int irq, void *private)
 679 {
 680         struct iio_dev *indio_dev = private;
 681         struct ads131e08_state *st = iio_priv(indio_dev);
 682
 683         if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev))
 684                 iio_trigger_poll(st->trig);
 685         else
 686                 complete(&st->completion);
 687
 688         return IRQ_HANDLED;
 689 }
 690
 691 static int ads131e08_alloc_channels(struct iio_dev *indio_dev)
 692 {
 693         struct ads131e08_state *st = iio_priv(indio_dev);
 694         struct ads131e08_channel_config *channel_config;
 695         struct device *dev = &st->spi->dev;
 696         struct iio_chan_spec *channels;
 697         struct fwnode_handle *node;
 698         unsigned int channel, tmp;
 699         int num_channels, i, ret;
 700
 701         ret = device_property_read_u32(dev, "ti,vref-internal", &tmp);
 702         if (ret)
 703                 tmp = 0;
 704
 705         switch (tmp) {
 706         case 0:
 707                 st->vref_mv = ADS131E08_VREF_2V4_mV;
 708                 break;
 709         case 1:
 710                 st->vref_mv = ADS131E08_VREF_4V_mV;
 711                 break;
 712         default:
 713                 dev_err(&st->spi->dev, "invalid internal voltage reference\n");
 714                 return -EINVAL;
 715         }
 716
 717         num_channels = device_get_child_node_count(dev);
 718         if (num_channels == 0) {
 719                 dev_err(&st->spi->dev, "no channel children\n");
 720                 return -ENODEV;
 721         }
 722
 723         if (num_channels > st->info->max_channels) {
 724                 dev_err(&st->spi->dev, "num of channel children out of range\n");
 725                 return -EINVAL;
 726         }
 727
 728         channels = devm_kcalloc(&st->spi->dev, num_channels,
 729                 sizeof(*channels), GFP_KERNEL);
 730         if (!channels)
 731                 return -ENOMEM;
 732
 733         channel_config = devm_kcalloc(&st->spi->dev, num_channels,
 734                 sizeof(*channel_config), GFP_KERNEL);
 735         if (!channel_config)
 736                 return -ENOMEM;
 737
 738         i = 0;
 739         device_for_each_child_node(dev, node) {
 740                 ret = fwnode_property_read_u32(node, "reg", &channel);
 741                 if (ret)
 742                         goto err_child_out;
 743
 744                 ret = fwnode_property_read_u32(node, "ti,gain", &tmp);
 745                 if (ret) {
 746                         channel_config[i].pga_gain = ADS131E08_DEFAULT_PGA_GAIN;
 747                 } else {
 748                         ret = ads131e08_pga_gain_to_field_value(st, tmp);
 749                         if (ret < 0)
 750                                 goto err_child_out;
 751
 752                         channel_config[i].pga_gain = tmp;
 753                 }
 754
 755                 ret = fwnode_property_read_u32(node, "ti,mux", &tmp);
 756                 if (ret) {
 757                         channel_config[i].mux = ADS131E08_DEFAULT_MUX;
 758                 } else {
 759                         ret = ads131e08_validate_channel_mux(st, tmp);
 760                         if (ret)
 761                                 goto err_child_out;
 762
 763                         channel_config[i].mux = tmp;
 764                 }
 765
 766                 channels[i].type = IIO_VOLTAGE;
 767                 channels[i].indexed = 1;
 768                 channels[i].channel = channel;
 769                 channels[i].address = i;
 770                 channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 771                                                 BIT(IIO_CHAN_INFO_SCALE);
 772                 channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ);
 773                 channels[i].scan_index = channel;
 774                 channels[i].scan_type.sign = 's';
 775                 channels[i].scan_type.realbits = 24;
 776                 channels[i].scan_type.storagebits = 32;
 777                 channels[i].scan_type.shift = 8;
 778                 channels[i].scan_type.endianness = IIO_BE;
 779                 i++;
 780         }
 781
 782         indio_dev->channels = channels;
 783         indio_dev->num_channels = num_channels;
 784         st->channel_config = channel_config;
 785
 786         return 0;
 787
 788 err_child_out:
 789         fwnode_handle_put(node);
 790         return ret;
 791 }
 792
 793 static void ads131e08_regulator_disable(void *data)
 794 {
 795         struct ads131e08_state *st = data;
 796
 797         regulator_disable(st->vref_reg);
 798 }
 799
 800 static int ads131e08_probe(struct spi_device *spi)
 801 {
 802         const struct ads131e08_info *info;
 803         struct ads131e08_state *st;
 804         struct iio_dev *indio_dev;
 805         unsigned long adc_clk_hz;
 806         unsigned long adc_clk_ns;
 807         int ret;
 808
 809         info = device_get_match_data(&spi->dev);
 810         if (!info)
 811                 info = (void *)spi_get_device_id(spi)->driver_data;
 812         if (!info) {
 813                 dev_err(&spi->dev, "failed to get match data\n");
 814                 return -ENODEV;
 815         }
 816
 817         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 818         if (!indio_dev) {
 819                 dev_err(&spi->dev, "failed to allocate IIO device\n");
 820                 return -ENOMEM;
 821         }
 822
 823         st = iio_priv(indio_dev);
 824         st->info = info;
 825         st->spi = spi;
 826
 827         ret = ads131e08_alloc_channels(indio_dev);
 828         if (ret)
 829                 return ret;
 830
 831         indio_dev->name = st->info->name;
 832         indio_dev->info = &ads131e08_iio_info;
 833         indio_dev->modes = INDIO_DIRECT_MODE;
 834
 835         init_completion(&st->completion);
 836
 837         if (spi->irq) {
 838                 ret = devm_request_irq(&spi->dev, spi->irq,
 839                         ads131e08_interrupt,
 840                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
 841                         spi->dev.driver->name, indio_dev);
 842                 if (ret)
 843                         return dev_err_probe(&spi->dev, ret,
 844                                              "request irq failed\n");
 845         } else {
 846                 dev_err(&spi->dev, "data ready IRQ missing\n");
 847                 return -ENODEV;
 848         }
 849
 850         st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
 851                 indio_dev->name, iio_device_id(indio_dev));
 852         if (!st->trig) {
 853                 dev_err(&spi->dev, "failed to allocate IIO trigger\n");
 854                 return -ENOMEM;
 855         }
 856
 857         st->trig->ops = &ads131e08_trigger_ops;
 858         st->trig->dev.parent = &spi->dev;
 859         iio_trigger_set_drvdata(st->trig, indio_dev);
 860         ret = devm_iio_trigger_register(&spi->dev, st->trig);
 861         if (ret) {
 862                 dev_err(&spi->dev, "failed to register IIO trigger\n");
 863                 return -ENOMEM;
 864         }
 865
 866         indio_dev->trig = iio_trigger_get(st->trig);
 867
 868         ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
 869                 NULL, &ads131e08_trigger_handler, NULL);
 870         if (ret) {
 871                 dev_err(&spi->dev, "failed to setup IIO buffer\n");
 872                 return ret;
 873         }
 874
 875         st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
 876         if (!IS_ERR(st->vref_reg)) {
 877                 ret = regulator_enable(st->vref_reg);
 878                 if (ret) {
 879                         dev_err(&spi->dev,
 880                                 "failed to enable external vref supply\n");
 881                         return ret;
 882                 }
 883
 884                 ret = devm_add_action_or_reset(&spi->dev, ads131e08_regulator_disable, st);
 885                 if (ret)
 886                         return ret;
 887         } else {
 888                 if (PTR_ERR(st->vref_reg) != -ENODEV)
 889                         return PTR_ERR(st->vref_reg);
 890
 891                 st->vref_reg = NULL;
 892         }
 893
 894         st->adc_clk = devm_clk_get_enabled(&spi->dev, "adc-clk");
 895         if (IS_ERR(st->adc_clk))
 896                 return dev_err_probe(&spi->dev, PTR_ERR(st->adc_clk),
 897                                      "failed to get the ADC clock\n");
 898
 899         adc_clk_hz = clk_get_rate(st->adc_clk);
 900         if (!adc_clk_hz) {
 901                 dev_err(&spi->dev, "failed to get the ADC clock rate\n");
 902                 return  -EINVAL;
 903         }
 904
 905         adc_clk_ns = NSEC_PER_SEC / adc_clk_hz;
 906         st->sdecode_delay_us = DIV_ROUND_UP(
 907                 ADS131E08_WAIT_SDECODE_CYCLES * adc_clk_ns, NSEC_PER_USEC);
 908         st->reset_delay_us = DIV_ROUND_UP(
 909                 ADS131E08_WAIT_RESET_CYCLES * adc_clk_ns, NSEC_PER_USEC);
 910
 911         ret = ads131e08_initial_config(indio_dev);
 912         if (ret) {
 913                 dev_err(&spi->dev, "initial configuration failed\n");
 914                 return ret;
 915         }
 916
 917         return devm_iio_device_register(&spi->dev, indio_dev);
 918 }
 919
 920 static const struct of_device_id ads131e08_of_match[] = {
 921         { .compatible = "ti,ads131e04",
 922           .data = &ads131e08_info_tbl[ads131e04], },
 923         { .compatible = "ti,ads131e06",
 924           .data = &ads131e08_info_tbl[ads131e06], },
 925         { .compatible = "ti,ads131e08",
 926           .data = &ads131e08_info_tbl[ads131e08], },
 927         {}
 928 };
 929 MODULE_DEVICE_TABLE(of, ads131e08_of_match);
 930
 931 static const struct spi_device_id ads131e08_ids[] = {
 932         { "ads131e04", (kernel_ulong_t)&ads131e08_info_tbl[ads131e04] },
 933         { "ads131e06", (kernel_ulong_t)&ads131e08_info_tbl[ads131e06] },
 934         { "ads131e08", (kernel_ulong_t)&ads131e08_info_tbl[ads131e08] },
 935         {}
 936 };
 937 MODULE_DEVICE_TABLE(spi, ads131e08_ids);
 938
 939 static struct spi_driver ads131e08_driver = {
 940         .driver = {
 941                 .name = "ads131e08",
 942                 .of_match_table = ads131e08_of_match,
 943         },
 944         .probe = ads131e08_probe,
 945         .id_table = ads131e08_ids,
 946 };
 947 module_spi_driver(ads131e08_driver);
 948
 949 MODULE_AUTHOR("Tomislav Denis <[email protected]>");
 950 MODULE_DESCRIPTION("Driver for ADS131E0x ADC family");
 951 MODULE_LICENSE("GPL v2");