drivers/iio/adc/rockchip_saradc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Rockchip Successive Approximation Register (SAR) A/D Converter
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/mutex.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/completion.h>
  16 #include <linux/delay.h>
  17 #include <linux/reset.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/iio/buffer.h>
  20 #include <linux/iio/iio.h>
  21 #include <linux/iio/trigger_consumer.h>
  22 #include <linux/iio/triggered_buffer.h>
  23
  24 #define SARADC_DATA                     0x00
  25
  26 #define SARADC_STAS                     0x04
  27 #define SARADC_STAS_BUSY                BIT(0)
  28
  29 #define SARADC_CTRL                     0x08
  30 #define SARADC_CTRL_IRQ_STATUS          BIT(6)
  31 #define SARADC_CTRL_IRQ_ENABLE          BIT(5)
  32 #define SARADC_CTRL_POWER_CTRL          BIT(3)
  33 #define SARADC_CTRL_CHN_MASK            0x7
  34
  35 #define SARADC_DLY_PU_SOC               0x0c
  36 #define SARADC_DLY_PU_SOC_MASK          0x3f
  37
  38 #define SARADC_TIMEOUT                  msecs_to_jiffies(100)
  39 #define SARADC_MAX_CHANNELS             8
  40
  41 struct rockchip_saradc_data {
  42         const struct iio_chan_spec      *channels;
  43         int                             num_channels;
  44         unsigned long                   clk_rate;
  45 };
  46
  47 struct rockchip_saradc {
  48         void __iomem            *regs;
  49         struct clk              *pclk;
  50         struct clk              *clk;
  51         struct completion       completion;
  52         struct regulator        *vref;
  53         /* lock to protect against multiple access to the device */
  54         struct mutex            lock;
  55         int                     uv_vref;
  56         struct reset_control    *reset;
  57         const struct rockchip_saradc_data *data;
  58         u16                     last_val;
  59         const struct iio_chan_spec *last_chan;
  60         struct notifier_block nb;
  61 };
  62
  63 static void rockchip_saradc_power_down(struct rockchip_saradc *info)
  64 {
  65         /* Clear irq & power down adc */
  66         writel_relaxed(0, info->regs + SARADC_CTRL);
  67 }
  68
  69 static int rockchip_saradc_conversion(struct rockchip_saradc *info,
  70                                    struct iio_chan_spec const *chan)
  71 {
  72         reinit_completion(&info->completion);
  73
  74         /* 8 clock periods as delay between power up and start cmd */
  75         writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
  76
  77         info->last_chan = chan;
  78
  79         /* Select the channel to be used and trigger conversion */
  80         writel(SARADC_CTRL_POWER_CTRL
  81                         | (chan->channel & SARADC_CTRL_CHN_MASK)
  82                         | SARADC_CTRL_IRQ_ENABLE,
  83                    info->regs + SARADC_CTRL);
  84
  85         if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
  86                 return -ETIMEDOUT;
  87
  88         return 0;
  89 }
  90
  91 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
  92                                     struct iio_chan_spec const *chan,
  93                                     int *val, int *val2, long mask)
  94 {
  95         struct rockchip_saradc *info = iio_priv(indio_dev);
  96         int ret;
  97
  98         switch (mask) {
  99         case IIO_CHAN_INFO_RAW:
 100                 mutex_lock(&info->lock);
 101
 102                 ret = rockchip_saradc_conversion(info, chan);
 103                 if (ret) {
 104                         rockchip_saradc_power_down(info);
 105                         mutex_unlock(&info->lock);
 106                         return ret;
 107                 }
 108
 109                 *val = info->last_val;
 110                 mutex_unlock(&info->lock);
 111                 return IIO_VAL_INT;
 112         case IIO_CHAN_INFO_SCALE:
 113                 *val = info->uv_vref / 1000;
 114                 *val2 = chan->scan_type.realbits;
 115                 return IIO_VAL_FRACTIONAL_LOG2;
 116         default:
 117                 return -EINVAL;
 118         }
 119 }
 120
 121 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
 122 {
 123         struct rockchip_saradc *info = dev_id;
 124
 125         /* Read value */
 126         info->last_val = readl_relaxed(info->regs + SARADC_DATA);
 127         info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
 128
 129         rockchip_saradc_power_down(info);
 130
 131         complete(&info->completion);
 132
 133         return IRQ_HANDLED;
 134 }
 135
 136 static const struct iio_info rockchip_saradc_iio_info = {
 137         .read_raw = rockchip_saradc_read_raw,
 138 };
 139
 140 #define SARADC_CHANNEL(_index, _id, _res) {                     \
 141         .type = IIO_VOLTAGE,                                    \
 142         .indexed = 1,                                           \
 143         .channel = _index,                                      \
 144         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 145         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 146         .datasheet_name = _id,                                  \
 147         .scan_index = _index,                                   \
 148         .scan_type = {                                          \
 149                 .sign = 'u',                                    \
 150                 .realbits = _res,                               \
 151                 .storagebits = 16,                              \
 152                 .endianness = IIO_CPU,                          \
 153         },                                                      \
 154 }
 155
 156 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
 157         SARADC_CHANNEL(0, "adc0", 10),
 158         SARADC_CHANNEL(1, "adc1", 10),
 159         SARADC_CHANNEL(2, "adc2", 10),
 160 };
 161
 162 static const struct rockchip_saradc_data saradc_data = {
 163         .channels = rockchip_saradc_iio_channels,
 164         .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
 165         .clk_rate = 1000000,
 166 };
 167
 168 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
 169         SARADC_CHANNEL(0, "adc0", 12),
 170         SARADC_CHANNEL(1, "adc1", 12),
 171 };
 172
 173 static const struct rockchip_saradc_data rk3066_tsadc_data = {
 174         .channels = rockchip_rk3066_tsadc_iio_channels,
 175         .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
 176         .clk_rate = 50000,
 177 };
 178
 179 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
 180         SARADC_CHANNEL(0, "adc0", 10),
 181         SARADC_CHANNEL(1, "adc1", 10),
 182         SARADC_CHANNEL(2, "adc2", 10),
 183         SARADC_CHANNEL(3, "adc3", 10),
 184         SARADC_CHANNEL(4, "adc4", 10),
 185         SARADC_CHANNEL(5, "adc5", 10),
 186 };
 187
 188 static const struct rockchip_saradc_data rk3399_saradc_data = {
 189         .channels = rockchip_rk3399_saradc_iio_channels,
 190         .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
 191         .clk_rate = 1000000,
 192 };
 193
 194 static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
 195         SARADC_CHANNEL(0, "adc0", 10),
 196         SARADC_CHANNEL(1, "adc1", 10),
 197         SARADC_CHANNEL(2, "adc2", 10),
 198         SARADC_CHANNEL(3, "adc3", 10),
 199         SARADC_CHANNEL(4, "adc4", 10),
 200         SARADC_CHANNEL(5, "adc5", 10),
 201         SARADC_CHANNEL(6, "adc6", 10),
 202         SARADC_CHANNEL(7, "adc7", 10),
 203 };
 204
 205 static const struct rockchip_saradc_data rk3568_saradc_data = {
 206         .channels = rockchip_rk3568_saradc_iio_channels,
 207         .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
 208         .clk_rate = 1000000,
 209 };
 210
 211 static const struct of_device_id rockchip_saradc_match[] = {
 212         {
 213                 .compatible = "rockchip,saradc",
 214                 .data = &saradc_data,
 215         }, {
 216                 .compatible = "rockchip,rk3066-tsadc",
 217                 .data = &rk3066_tsadc_data,
 218         }, {
 219                 .compatible = "rockchip,rk3399-saradc",
 220                 .data = &rk3399_saradc_data,
 221         }, {
 222                 .compatible = "rockchip,rk3568-saradc",
 223                 .data = &rk3568_saradc_data,
 224         },
 225         {},
 226 };
 227 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
 228
 229 /*
 230  * Reset SARADC Controller.
 231  */
 232 static void rockchip_saradc_reset_controller(struct reset_control *reset)
 233 {
 234         reset_control_assert(reset);
 235         usleep_range(10, 20);
 236         reset_control_deassert(reset);
 237 }
 238
 239 static void rockchip_saradc_clk_disable(void *data)
 240 {
 241         struct rockchip_saradc *info = data;
 242
 243         clk_disable_unprepare(info->clk);
 244 }
 245
 246 static void rockchip_saradc_pclk_disable(void *data)
 247 {
 248         struct rockchip_saradc *info = data;
 249
 250         clk_disable_unprepare(info->pclk);
 251 }
 252
 253 static void rockchip_saradc_regulator_disable(void *data)
 254 {
 255         struct rockchip_saradc *info = data;
 256
 257         regulator_disable(info->vref);
 258 }
 259
 260 static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
 261 {
 262         struct iio_poll_func *pf = p;
 263         struct iio_dev *i_dev = pf->indio_dev;
 264         struct rockchip_saradc *info = iio_priv(i_dev);
 265         /*
 266          * @values: each channel takes an u16 value
 267          * @timestamp: will be 8-byte aligned automatically
 268          */
 269         struct {
 270                 u16 values[SARADC_MAX_CHANNELS];
 271                 int64_t timestamp;
 272         } data;
 273         int ret;
 274         int i, j = 0;
 275
 276         mutex_lock(&info->lock);
 277
 278         for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
 279                 const struct iio_chan_spec *chan = &i_dev->channels[i];
 280
 281                 ret = rockchip_saradc_conversion(info, chan);
 282                 if (ret) {
 283                         rockchip_saradc_power_down(info);
 284                         goto out;
 285                 }
 286
 287                 data.values[j] = info->last_val;
 288                 j++;
 289         }
 290
 291         iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
 292 out:
 293         mutex_unlock(&info->lock);
 294
 295         iio_trigger_notify_done(i_dev->trig);
 296
 297         return IRQ_HANDLED;
 298 }
 299
 300 static int rockchip_saradc_volt_notify(struct notifier_block *nb,
 301                                                    unsigned long event,
 302                                                    void *data)
 303 {
 304         struct rockchip_saradc *info =
 305                         container_of(nb, struct rockchip_saradc, nb);
 306
 307         if (event & REGULATOR_EVENT_VOLTAGE_CHANGE)
 308                 info->uv_vref = (unsigned long)data;
 309
 310         return NOTIFY_OK;
 311 }
 312
 313 static void rockchip_saradc_regulator_unreg_notifier(void *data)
 314 {
 315         struct rockchip_saradc *info = data;
 316
 317         regulator_unregister_notifier(info->vref, &info->nb);
 318 }
 319
 320 static int rockchip_saradc_probe(struct platform_device *pdev)
 321 {
 322         struct rockchip_saradc *info = NULL;
 323         struct device_node *np = pdev->dev.of_node;
 324         struct iio_dev *indio_dev = NULL;
 325         const struct of_device_id *match;
 326         int ret;
 327         int irq;
 328
 329         if (!np)
 330                 return -ENODEV;
 331
 332         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
 333         if (!indio_dev) {
 334                 dev_err(&pdev->dev, "failed allocating iio device\n");
 335                 return -ENOMEM;
 336         }
 337         info = iio_priv(indio_dev);
 338
 339         match = of_match_device(rockchip_saradc_match, &pdev->dev);
 340         if (!match) {
 341                 dev_err(&pdev->dev, "failed to match device\n");
 342                 return -ENODEV;
 343         }
 344
 345         info->data = match->data;
 346
 347         /* Sanity check for possible later IP variants with more channels */
 348         if (info->data->num_channels > SARADC_MAX_CHANNELS) {
 349                 dev_err(&pdev->dev, "max channels exceeded");
 350                 return -EINVAL;
 351         }
 352
 353         info->regs = devm_platform_ioremap_resource(pdev, 0);
 354         if (IS_ERR(info->regs))
 355                 return PTR_ERR(info->regs);
 356
 357         /*
 358          * The reset should be an optional property, as it should work
 359          * with old devicetrees as well
 360          */
 361         info->reset = devm_reset_control_get_exclusive(&pdev->dev,
 362                                                        "saradc-apb");
 363         if (IS_ERR(info->reset)) {
 364                 ret = PTR_ERR(info->reset);
 365                 if (ret != -ENOENT)
 366                         return dev_err_probe(&pdev->dev, ret,
 367                                              "failed to get saradc-apb\n");
 368
 369                 dev_dbg(&pdev->dev, "no reset control found\n");
 370                 info->reset = NULL;
 371         }
 372
 373         init_completion(&info->completion);
 374
 375         irq = platform_get_irq(pdev, 0);
 376         if (irq < 0)
 377                 return dev_err_probe(&pdev->dev, irq, "failed to get irq\n");
 378
 379         ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
 380                                0, dev_name(&pdev->dev), info);
 381         if (ret < 0) {
 382                 dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
 383                 return ret;
 384         }
 385
 386         info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 387         if (IS_ERR(info->pclk))
 388                 return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
 389                                      "failed to get pclk\n");
 390
 391         info->clk = devm_clk_get(&pdev->dev, "saradc");
 392         if (IS_ERR(info->clk))
 393                 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
 394                                      "failed to get adc clock\n");
 395
 396         info->vref = devm_regulator_get(&pdev->dev, "vref");
 397         if (IS_ERR(info->vref))
 398                 return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
 399                                      "failed to get regulator\n");
 400
 401         if (info->reset)
 402                 rockchip_saradc_reset_controller(info->reset);
 403
 404         /*
 405          * Use a default value for the converter clock.
 406          * This may become user-configurable in the future.
 407          */
 408         ret = clk_set_rate(info->clk, info->data->clk_rate);
 409         if (ret < 0) {
 410                 dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
 411                 return ret;
 412         }
 413
 414         ret = regulator_enable(info->vref);
 415         if (ret < 0) {
 416                 dev_err(&pdev->dev, "failed to enable vref regulator\n");
 417                 return ret;
 418         }
 419         ret = devm_add_action_or_reset(&pdev->dev,
 420                                        rockchip_saradc_regulator_disable, info);
 421         if (ret) {
 422                 dev_err(&pdev->dev, "failed to register devm action, %d\n",
 423                         ret);
 424                 return ret;
 425         }
 426
 427         ret = regulator_get_voltage(info->vref);
 428         if (ret < 0)
 429                 return ret;
 430
 431         info->uv_vref = ret;
 432
 433         ret = clk_prepare_enable(info->pclk);
 434         if (ret < 0) {
 435                 dev_err(&pdev->dev, "failed to enable pclk\n");
 436                 return ret;
 437         }
 438         ret = devm_add_action_or_reset(&pdev->dev,
 439                                        rockchip_saradc_pclk_disable, info);
 440         if (ret) {
 441                 dev_err(&pdev->dev, "failed to register devm action, %d\n",
 442                         ret);
 443                 return ret;
 444         }
 445
 446         ret = clk_prepare_enable(info->clk);
 447         if (ret < 0) {
 448                 dev_err(&pdev->dev, "failed to enable converter clock\n");
 449                 return ret;
 450         }
 451         ret = devm_add_action_or_reset(&pdev->dev,
 452                                        rockchip_saradc_clk_disable, info);
 453         if (ret) {
 454                 dev_err(&pdev->dev, "failed to register devm action, %d\n",
 455                         ret);
 456                 return ret;
 457         }
 458
 459         platform_set_drvdata(pdev, indio_dev);
 460
 461         indio_dev->name = dev_name(&pdev->dev);
 462         indio_dev->info = &rockchip_saradc_iio_info;
 463         indio_dev->modes = INDIO_DIRECT_MODE;
 464
 465         indio_dev->channels = info->data->channels;
 466         indio_dev->num_channels = info->data->num_channels;
 467         ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
 468                                               rockchip_saradc_trigger_handler,
 469                                               NULL);
 470         if (ret)
 471                 return ret;
 472
 473         info->nb.notifier_call = rockchip_saradc_volt_notify;
 474         ret = regulator_register_notifier(info->vref, &info->nb);
 475         if (ret)
 476                 return ret;
 477
 478         ret = devm_add_action_or_reset(&pdev->dev,
 479                                        rockchip_saradc_regulator_unreg_notifier,
 480                                        info);
 481         if (ret)
 482                 return ret;
 483
 484         mutex_init(&info->lock);
 485
 486         return devm_iio_device_register(&pdev->dev, indio_dev);
 487 }
 488
 489 static int rockchip_saradc_suspend(struct device *dev)
 490 {
 491         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 492         struct rockchip_saradc *info = iio_priv(indio_dev);
 493
 494         clk_disable_unprepare(info->clk);
 495         clk_disable_unprepare(info->pclk);
 496         regulator_disable(info->vref);
 497
 498         return 0;
 499 }
 500
 501 static int rockchip_saradc_resume(struct device *dev)
 502 {
 503         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 504         struct rockchip_saradc *info = iio_priv(indio_dev);
 505         int ret;
 506
 507         ret = regulator_enable(info->vref);
 508         if (ret)
 509                 return ret;
 510
 511         ret = clk_prepare_enable(info->pclk);
 512         if (ret)
 513                 return ret;
 514
 515         ret = clk_prepare_enable(info->clk);
 516         if (ret)
 517                 clk_disable_unprepare(info->pclk);
 518
 519         return ret;
 520 }
 521
 522 static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
 523                                 rockchip_saradc_suspend,
 524                                 rockchip_saradc_resume);
 525
 526 static struct platform_driver rockchip_saradc_driver = {
 527         .probe          = rockchip_saradc_probe,
 528         .driver         = {
 529                 .name   = "rockchip-saradc",
 530                 .of_match_table = rockchip_saradc_match,
 531                 .pm     = pm_sleep_ptr(&rockchip_saradc_pm_ops),
 532         },
 533 };
 534
 535 module_platform_driver(rockchip_saradc_driver);
 536
 537 MODULE_AUTHOR("Heiko Stuebner <[email protected]>");
 538 MODULE_DESCRIPTION("Rockchip SARADC driver");
 539 MODULE_LICENSE("GPL v2");