1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core IIO driver for Bosch BMA400 triaxial acceleration sensor.
8 * - Support for power management
9 * - Support events and interrupts
10 * - Create channel for step count
11 * - Create channel for sensor time
14 #include <linux/bitfield.h>
15 #include <linux/bitops.h>
16 #include <linux/device.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
24 #include <asm/unaligned.h>
26 #include <linux/iio/iio.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/events.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
37 * The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may
38 * be selected with the acc_range bits of the ACC_CONFIG1 register.
39 * NB: This buffer is populated in the device init.
41 static int bma400_scales[8];
44 * See the ACC_CONFIG1 section of the datasheet.
45 * NB: This buffer is populated in the device init.
47 static int bma400_sample_freqs[14];
49 static const int bma400_osr_range[] = { 0, 1, 3 };
51 static int tap_reset_timeout[BMA400_TAP_TIM_LIST_LEN] = {
58 static int tap_max2min_time[BMA400_TAP_TIM_LIST_LEN] = {
65 static int double_tap2_min_delay[BMA400_TAP_TIM_LIST_LEN] = {
72 /* See the ACC_CONFIG0 section of the datasheet */
73 enum bma400_power_mode {
74 POWER_MODE_SLEEP = 0x00,
75 POWER_MODE_LOW = 0x01,
76 POWER_MODE_NORMAL = 0x02,
77 POWER_MODE_INVALID = 0x03,
87 struct bma400_sample_freq {
92 enum bma400_activity {
100 struct regmap *regmap;
101 struct mutex mutex; /* data register lock */
102 struct iio_mount_matrix orientation;
103 enum bma400_power_mode power_mode;
104 struct bma400_sample_freq sample_freq;
105 int oversampling_ratio;
107 struct iio_trigger *trig;
110 bool activity_event_en;
111 unsigned int generic_event_en;
112 unsigned int tap_event_en_bitmask;
113 /* Correct time stamp alignment */
118 } buffer __aligned(IIO_DMA_MINALIGN);
123 static bool bma400_is_writable_reg(struct device *dev, unsigned int reg)
126 case BMA400_CHIP_ID_REG:
128 case BMA400_STATUS_REG:
129 case BMA400_X_AXIS_LSB_REG:
130 case BMA400_X_AXIS_MSB_REG:
131 case BMA400_Y_AXIS_LSB_REG:
132 case BMA400_Y_AXIS_MSB_REG:
133 case BMA400_Z_AXIS_LSB_REG:
134 case BMA400_Z_AXIS_MSB_REG:
135 case BMA400_SENSOR_TIME0:
136 case BMA400_SENSOR_TIME1:
137 case BMA400_SENSOR_TIME2:
138 case BMA400_EVENT_REG:
139 case BMA400_INT_STAT0_REG:
140 case BMA400_INT_STAT1_REG:
141 case BMA400_INT_STAT2_REG:
142 case BMA400_TEMP_DATA_REG:
143 case BMA400_FIFO_LENGTH0_REG:
144 case BMA400_FIFO_LENGTH1_REG:
145 case BMA400_FIFO_DATA_REG:
146 case BMA400_STEP_CNT0_REG:
147 case BMA400_STEP_CNT1_REG:
148 case BMA400_STEP_CNT3_REG:
149 case BMA400_STEP_STAT_REG:
156 static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg)
160 case BMA400_STATUS_REG:
161 case BMA400_X_AXIS_LSB_REG:
162 case BMA400_X_AXIS_MSB_REG:
163 case BMA400_Y_AXIS_LSB_REG:
164 case BMA400_Y_AXIS_MSB_REG:
165 case BMA400_Z_AXIS_LSB_REG:
166 case BMA400_Z_AXIS_MSB_REG:
167 case BMA400_SENSOR_TIME0:
168 case BMA400_SENSOR_TIME1:
169 case BMA400_SENSOR_TIME2:
170 case BMA400_EVENT_REG:
171 case BMA400_INT_STAT0_REG:
172 case BMA400_INT_STAT1_REG:
173 case BMA400_INT_STAT2_REG:
174 case BMA400_TEMP_DATA_REG:
175 case BMA400_FIFO_LENGTH0_REG:
176 case BMA400_FIFO_LENGTH1_REG:
177 case BMA400_FIFO_DATA_REG:
178 case BMA400_STEP_CNT0_REG:
179 case BMA400_STEP_CNT1_REG:
180 case BMA400_STEP_CNT3_REG:
181 case BMA400_STEP_STAT_REG:
188 const struct regmap_config bma400_regmap_config = {
191 .max_register = BMA400_CMD_REG,
192 .cache_type = REGCACHE_RBTREE,
193 .writeable_reg = bma400_is_writable_reg,
194 .volatile_reg = bma400_is_volatile_reg,
196 EXPORT_SYMBOL_NS(bma400_regmap_config, IIO_BMA400);
198 static const struct iio_mount_matrix *
199 bma400_accel_get_mount_matrix(const struct iio_dev *indio_dev,
200 const struct iio_chan_spec *chan)
202 struct bma400_data *data = iio_priv(indio_dev);
204 return &data->orientation;
207 static const struct iio_chan_spec_ext_info bma400_ext_info[] = {
208 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma400_accel_get_mount_matrix),
212 static const struct iio_event_spec bma400_step_detect_event = {
213 .type = IIO_EV_TYPE_CHANGE,
214 .dir = IIO_EV_DIR_NONE,
215 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
218 static const struct iio_event_spec bma400_activity_event = {
219 .type = IIO_EV_TYPE_CHANGE,
220 .dir = IIO_EV_DIR_NONE,
221 .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE),
224 static const struct iio_event_spec bma400_accel_event[] = {
226 .type = IIO_EV_TYPE_MAG,
227 .dir = IIO_EV_DIR_FALLING,
228 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
229 BIT(IIO_EV_INFO_PERIOD) |
230 BIT(IIO_EV_INFO_HYSTERESIS) |
231 BIT(IIO_EV_INFO_ENABLE),
234 .type = IIO_EV_TYPE_MAG,
235 .dir = IIO_EV_DIR_RISING,
236 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
237 BIT(IIO_EV_INFO_PERIOD) |
238 BIT(IIO_EV_INFO_HYSTERESIS) |
239 BIT(IIO_EV_INFO_ENABLE),
242 .type = IIO_EV_TYPE_GESTURE,
243 .dir = IIO_EV_DIR_SINGLETAP,
244 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
245 BIT(IIO_EV_INFO_ENABLE) |
246 BIT(IIO_EV_INFO_RESET_TIMEOUT),
249 .type = IIO_EV_TYPE_GESTURE,
250 .dir = IIO_EV_DIR_DOUBLETAP,
251 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
252 BIT(IIO_EV_INFO_ENABLE) |
253 BIT(IIO_EV_INFO_RESET_TIMEOUT) |
254 BIT(IIO_EV_INFO_TAP2_MIN_DELAY),
258 static int usec_to_tapreg_raw(int usec, const int *time_list)
262 for (index = 0; index < BMA400_TAP_TIM_LIST_LEN; index++) {
263 if (usec == time_list[index])
269 static ssize_t in_accel_gesture_tap_maxtomin_time_show(struct device *dev,
270 struct device_attribute *attr,
273 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
274 struct bma400_data *data = iio_priv(indio_dev);
275 int ret, reg_val, raw, vals[2];
277 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1, ®_val);
281 raw = FIELD_GET(BMA400_TAP_TICSTH_MSK, reg_val);
283 vals[1] = tap_max2min_time[raw];
285 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
288 static ssize_t in_accel_gesture_tap_maxtomin_time_store(struct device *dev,
289 struct device_attribute *attr,
290 const char *buf, size_t len)
292 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
293 struct bma400_data *data = iio_priv(indio_dev);
294 int ret, val_int, val_fract, raw;
296 ret = iio_str_to_fixpoint(buf, 100000, &val_int, &val_fract);
300 raw = usec_to_tapreg_raw(val_fract, tap_max2min_time);
304 ret = regmap_update_bits(data->regmap, BMA400_TAP_CONFIG1,
305 BMA400_TAP_TICSTH_MSK,
306 FIELD_PREP(BMA400_TAP_TICSTH_MSK, raw));
313 static IIO_DEVICE_ATTR_RW(in_accel_gesture_tap_maxtomin_time, 0);
316 * Tap interrupts works with 200 Hz input data rate and the time based tap
317 * controls are in the terms of data samples so the below calculation is
318 * used to convert the configuration values into seconds.
320 * 60 data samples * 0.005 ms = 0.3 seconds.
321 * 80 data samples * 0.005 ms = 0.4 seconds.
324 /* quiet configuration values in seconds */
325 static IIO_CONST_ATTR(in_accel_gesture_tap_reset_timeout_available,
328 /* tics_th configuration values in seconds */
329 static IIO_CONST_ATTR(in_accel_gesture_tap_maxtomin_time_available,
330 "0.03 0.045 0.06 0.09");
332 /* quiet_dt configuration values in seconds */
333 static IIO_CONST_ATTR(in_accel_gesture_doubletap_tap2_min_delay_available,
334 "0.02 0.04 0.06 0.08");
336 /* List of sensitivity values available to configure tap interrupts */
337 static IIO_CONST_ATTR(in_accel_gesture_tap_value_available, "0 1 2 3 4 5 6 7");
339 static struct attribute *bma400_event_attributes[] = {
340 &iio_const_attr_in_accel_gesture_tap_value_available.dev_attr.attr,
341 &iio_const_attr_in_accel_gesture_tap_reset_timeout_available.dev_attr.attr,
342 &iio_const_attr_in_accel_gesture_tap_maxtomin_time_available.dev_attr.attr,
343 &iio_const_attr_in_accel_gesture_doubletap_tap2_min_delay_available.dev_attr.attr,
344 &iio_dev_attr_in_accel_gesture_tap_maxtomin_time.dev_attr.attr,
348 static const struct attribute_group bma400_event_attribute_group = {
349 .attrs = bma400_event_attributes,
352 #define BMA400_ACC_CHANNEL(_index, _axis) { \
355 .channel2 = IIO_MOD_##_axis, \
356 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
357 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
358 BIT(IIO_CHAN_INFO_SCALE) | \
359 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
360 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
361 BIT(IIO_CHAN_INFO_SCALE) | \
362 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
363 .ext_info = bma400_ext_info, \
364 .scan_index = _index, \
369 .endianness = IIO_LE, \
371 .event_spec = bma400_accel_event, \
372 .num_event_specs = ARRAY_SIZE(bma400_accel_event) \
375 #define BMA400_ACTIVITY_CHANNEL(_chan2) { \
376 .type = IIO_ACTIVITY, \
378 .channel2 = _chan2, \
379 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
380 .scan_index = -1, /* No buffer support */ \
381 .event_spec = &bma400_activity_event, \
382 .num_event_specs = 1, \
385 static const struct iio_chan_spec bma400_channels[] = {
386 BMA400_ACC_CHANNEL(0, X),
387 BMA400_ACC_CHANNEL(1, Y),
388 BMA400_ACC_CHANNEL(2, Z),
391 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
392 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),
398 .endianness = IIO_LE,
403 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
404 BIT(IIO_CHAN_INFO_ENABLE),
405 .scan_index = -1, /* No buffer support */
406 .event_spec = &bma400_step_detect_event,
407 .num_event_specs = 1,
409 BMA400_ACTIVITY_CHANNEL(IIO_MOD_STILL),
410 BMA400_ACTIVITY_CHANNEL(IIO_MOD_WALKING),
411 BMA400_ACTIVITY_CHANNEL(IIO_MOD_RUNNING),
412 IIO_CHAN_SOFT_TIMESTAMP(4),
415 static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2)
417 unsigned int raw_temp;
421 if (data->power_mode == POWER_MODE_SLEEP)
424 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &raw_temp);
428 host_temp = sign_extend32(raw_temp, 7);
430 * The formula for the TEMP_DATA register in the datasheet
433 *val = (host_temp >> 1) + 23;
434 *val2 = (host_temp & 0x1) * 500000;
435 return IIO_VAL_INT_PLUS_MICRO;
438 static int bma400_get_accel_reg(struct bma400_data *data,
439 const struct iio_chan_spec *chan,
446 if (data->power_mode == POWER_MODE_SLEEP)
449 switch (chan->channel2) {
451 lsb_reg = BMA400_X_AXIS_LSB_REG;
454 lsb_reg = BMA400_Y_AXIS_LSB_REG;
457 lsb_reg = BMA400_Z_AXIS_LSB_REG;
460 dev_err(data->dev, "invalid axis channel modifier\n");
464 /* bulk read two registers, with the base being the LSB register */
465 ret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel,
470 *val = sign_extend32(le16_to_cpu(raw_accel), 11);
474 static void bma400_output_data_rate_from_raw(int raw, unsigned int *val,
477 *val = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw);
478 if (raw > BMA400_ACC_ODR_MIN_RAW)
484 static int bma400_get_accel_output_data_rate(struct bma400_data *data)
490 switch (data->power_mode) {
493 * Runs at a fixed rate in low-power mode. See section 4.3
496 bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW,
497 &data->sample_freq.hz,
498 &data->sample_freq.uhz);
500 case POWER_MODE_NORMAL:
502 * In normal mode the ODR can be found in the ACC_CONFIG1
505 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
509 odr = val & BMA400_ACC_ODR_MASK;
510 if (odr < BMA400_ACC_ODR_MIN_RAW ||
511 odr > BMA400_ACC_ODR_MAX_RAW) {
516 bma400_output_data_rate_from_raw(odr, &data->sample_freq.hz,
517 &data->sample_freq.uhz);
519 case POWER_MODE_SLEEP:
520 data->sample_freq.hz = 0;
521 data->sample_freq.uhz = 0;
528 data->sample_freq.hz = -1;
529 data->sample_freq.uhz = -1;
533 static int bma400_set_accel_output_data_rate(struct bma400_data *data,
541 if (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) {
542 if (uhz || hz > BMA400_ACC_ODR_MAX_HZ)
545 /* Note this works because MIN_WHOLE_HZ is odd */
548 if (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ)
551 idx += BMA400_ACC_ODR_MIN_RAW + 1;
552 } else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) {
553 idx = BMA400_ACC_ODR_MIN_RAW;
558 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
562 /* preserve the range and normal mode osr */
563 odr = (~BMA400_ACC_ODR_MASK & val) | idx;
565 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr);
569 bma400_output_data_rate_from_raw(idx, &data->sample_freq.hz,
570 &data->sample_freq.uhz);
574 static int bma400_get_accel_oversampling_ratio(struct bma400_data *data)
581 * The oversampling ratio is stored in a different register
582 * based on the power-mode. In normal mode the OSR is stored
583 * in ACC_CONFIG1. In low-power mode it is stored in
586 switch (data->power_mode) {
588 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);
590 data->oversampling_ratio = -1;
594 osr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT;
596 data->oversampling_ratio = osr;
598 case POWER_MODE_NORMAL:
599 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
601 data->oversampling_ratio = -1;
605 osr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT;
607 data->oversampling_ratio = osr;
609 case POWER_MODE_SLEEP:
610 data->oversampling_ratio = 0;
613 data->oversampling_ratio = -1;
618 static int bma400_set_accel_oversampling_ratio(struct bma400_data *data,
621 unsigned int acc_config;
624 if (val & ~BMA400_TWO_BITS_MASK)
628 * The oversampling ratio is stored in a different register
629 * based on the power-mode.
631 switch (data->power_mode) {
633 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG,
638 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,
639 (acc_config & ~BMA400_LP_OSR_MASK) |
640 (val << BMA400_LP_OSR_SHIFT));
642 dev_err(data->dev, "Failed to write out OSR\n");
646 data->oversampling_ratio = val;
648 case POWER_MODE_NORMAL:
649 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG,
654 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,
655 (acc_config & ~BMA400_NP_OSR_MASK) |
656 (val << BMA400_NP_OSR_SHIFT));
658 dev_err(data->dev, "Failed to write out OSR\n");
662 data->oversampling_ratio = val;
670 static int bma400_accel_scale_to_raw(struct bma400_data *data,
678 /* Note this works because BMA400_SCALE_MIN is odd */
681 if (val >> raw != BMA400_SCALE_MIN)
687 static int bma400_get_accel_scale(struct bma400_data *data)
689 unsigned int raw_scale;
693 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
697 raw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT;
698 if (raw_scale > BMA400_TWO_BITS_MASK)
701 data->scale = BMA400_SCALE_MIN << raw_scale;
706 static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val)
708 unsigned int acc_config;
712 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &acc_config);
716 raw = bma400_accel_scale_to_raw(data, val);
720 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,
721 (acc_config & ~BMA400_ACC_SCALE_MASK) |
722 (raw << BMA400_SCALE_SHIFT));
730 static int bma400_get_power_mode(struct bma400_data *data)
735 ret = regmap_read(data->regmap, BMA400_STATUS_REG, &val);
737 dev_err(data->dev, "Failed to read status register\n");
741 data->power_mode = (val >> 1) & BMA400_TWO_BITS_MASK;
745 static int bma400_set_power_mode(struct bma400_data *data,
746 enum bma400_power_mode mode)
751 ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);
755 if (data->power_mode == mode)
758 if (mode == POWER_MODE_INVALID)
761 /* Preserve the low-power oversample ratio etc */
762 ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,
763 mode | (val & ~BMA400_TWO_BITS_MASK));
765 dev_err(data->dev, "Failed to write to power-mode\n");
769 data->power_mode = mode;
772 * Update our cached osr and odr based on the new
775 bma400_get_accel_output_data_rate(data);
776 bma400_get_accel_oversampling_ratio(data);
780 static int bma400_enable_steps(struct bma400_data *data, int val)
784 if (data->steps_enabled == val)
787 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG,
789 FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0));
792 data->steps_enabled = val;
796 static int bma400_get_steps_reg(struct bma400_data *data, int *val)
801 steps_raw = kmalloc(BMA400_STEP_RAW_LEN, GFP_KERNEL);
805 ret = regmap_bulk_read(data->regmap, BMA400_STEP_CNT0_REG,
806 steps_raw, BMA400_STEP_RAW_LEN);
811 *val = get_unaligned_le24(steps_raw);
816 static void bma400_init_tables(void)
821 for (i = 0; i + 1 < ARRAY_SIZE(bma400_sample_freqs); i += 2) {
823 bma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i],
824 &bma400_sample_freqs[i + 1]);
827 for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) {
829 bma400_scales[i] = 0;
830 bma400_scales[i + 1] = BMA400_SCALE_MIN << raw;
834 static void bma400_power_disable(void *data_ptr)
836 struct bma400_data *data = data_ptr;
839 mutex_lock(&data->mutex);
840 ret = bma400_set_power_mode(data, POWER_MODE_SLEEP);
841 mutex_unlock(&data->mutex);
843 dev_warn(data->dev, "Failed to put device into sleep mode (%pe)\n",
847 static enum iio_modifier bma400_act_to_mod(enum bma400_activity activity)
851 return IIO_MOD_STILL;
853 return IIO_MOD_WALKING;
855 return IIO_MOD_RUNNING;
861 static int bma400_init(struct bma400_data *data)
863 static const char * const regulator_names[] = { "vdd", "vddio" };
867 ret = devm_regulator_bulk_get_enable(data->dev,
868 ARRAY_SIZE(regulator_names),
871 return dev_err_probe(data->dev, ret, "Failed to get regulators: %d\n",
874 /* Try to read chip_id register. It must return 0x90. */
875 ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val);
877 dev_err(data->dev, "Failed to read chip id register\n");
881 if (val != BMA400_ID_REG_VAL) {
882 dev_err(data->dev, "Chip ID mismatch\n");
886 ret = bma400_get_power_mode(data);
888 dev_err(data->dev, "Failed to get the initial power-mode\n");
892 if (data->power_mode != POWER_MODE_NORMAL) {
893 ret = bma400_set_power_mode(data, POWER_MODE_NORMAL);
895 dev_err(data->dev, "Failed to wake up the device\n");
899 * TODO: The datasheet waits 1500us here in the example, but
900 * lists 2/ODR as the wakeup time.
902 usleep_range(1500, 2000);
905 ret = devm_add_action_or_reset(data->dev, bma400_power_disable, data);
909 bma400_init_tables();
911 ret = bma400_get_accel_output_data_rate(data);
915 ret = bma400_get_accel_oversampling_ratio(data);
919 ret = bma400_get_accel_scale(data);
923 /* Configure INT1 pin to open drain */
924 ret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06);
928 * Once the interrupt engine is supported we might use the
929 * data_src_reg, but for now ensure this is set to the
930 * variable ODR filter selectable by the sample frequency
933 return regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00);
936 static int bma400_read_raw(struct iio_dev *indio_dev,
937 struct iio_chan_spec const *chan, int *val,
938 int *val2, long mask)
940 struct bma400_data *data = iio_priv(indio_dev);
941 unsigned int activity;
945 case IIO_CHAN_INFO_PROCESSED:
946 switch (chan->type) {
948 mutex_lock(&data->mutex);
949 ret = bma400_get_temp_reg(data, val, val2);
950 mutex_unlock(&data->mutex);
953 return bma400_get_steps_reg(data, val);
955 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG,
960 * The device does not support confidence value levels,
961 * so we will always have 100% for current activity and
964 if (chan->channel2 == bma400_act_to_mod(activity))
972 case IIO_CHAN_INFO_RAW:
973 mutex_lock(&data->mutex);
974 ret = bma400_get_accel_reg(data, chan, val);
975 mutex_unlock(&data->mutex);
977 case IIO_CHAN_INFO_SAMP_FREQ:
978 switch (chan->type) {
980 if (data->sample_freq.hz < 0)
983 *val = data->sample_freq.hz;
984 *val2 = data->sample_freq.uhz;
985 return IIO_VAL_INT_PLUS_MICRO;
988 * Runs at a fixed sampling frequency. See Section 4.4
993 return IIO_VAL_INT_PLUS_MICRO;
997 case IIO_CHAN_INFO_SCALE:
1000 return IIO_VAL_INT_PLUS_MICRO;
1001 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1003 * TODO: We could avoid this logic and returning -EINVAL here if
1004 * we set both the low-power and normal mode OSR registers when
1005 * we configure the device.
1007 if (data->oversampling_ratio < 0)
1010 *val = data->oversampling_ratio;
1012 case IIO_CHAN_INFO_ENABLE:
1013 *val = data->steps_enabled;
1020 static int bma400_read_avail(struct iio_dev *indio_dev,
1021 struct iio_chan_spec const *chan,
1022 const int **vals, int *type, int *length,
1026 case IIO_CHAN_INFO_SCALE:
1027 *type = IIO_VAL_INT_PLUS_MICRO;
1028 *vals = bma400_scales;
1029 *length = ARRAY_SIZE(bma400_scales);
1030 return IIO_AVAIL_LIST;
1031 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1032 *type = IIO_VAL_INT;
1033 *vals = bma400_osr_range;
1034 *length = ARRAY_SIZE(bma400_osr_range);
1035 return IIO_AVAIL_RANGE;
1036 case IIO_CHAN_INFO_SAMP_FREQ:
1037 *type = IIO_VAL_INT_PLUS_MICRO;
1038 *vals = bma400_sample_freqs;
1039 *length = ARRAY_SIZE(bma400_sample_freqs);
1040 return IIO_AVAIL_LIST;
1046 static int bma400_write_raw(struct iio_dev *indio_dev,
1047 struct iio_chan_spec const *chan, int val, int val2,
1050 struct bma400_data *data = iio_priv(indio_dev);
1054 case IIO_CHAN_INFO_SAMP_FREQ:
1056 * The sample frequency is readonly for the temperature
1057 * register and a fixed value in low-power mode.
1059 if (chan->type != IIO_ACCEL)
1062 mutex_lock(&data->mutex);
1063 ret = bma400_set_accel_output_data_rate(data, val, val2);
1064 mutex_unlock(&data->mutex);
1066 case IIO_CHAN_INFO_SCALE:
1068 val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX)
1071 mutex_lock(&data->mutex);
1072 ret = bma400_set_accel_scale(data, val2);
1073 mutex_unlock(&data->mutex);
1075 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1076 mutex_lock(&data->mutex);
1077 ret = bma400_set_accel_oversampling_ratio(data, val);
1078 mutex_unlock(&data->mutex);
1080 case IIO_CHAN_INFO_ENABLE:
1081 mutex_lock(&data->mutex);
1082 ret = bma400_enable_steps(data, val);
1083 mutex_unlock(&data->mutex);
1090 static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev,
1091 struct iio_chan_spec const *chan,
1095 case IIO_CHAN_INFO_SAMP_FREQ:
1096 return IIO_VAL_INT_PLUS_MICRO;
1097 case IIO_CHAN_INFO_SCALE:
1098 return IIO_VAL_INT_PLUS_MICRO;
1099 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1101 case IIO_CHAN_INFO_ENABLE:
1108 static int bma400_read_event_config(struct iio_dev *indio_dev,
1109 const struct iio_chan_spec *chan,
1110 enum iio_event_type type,
1111 enum iio_event_direction dir)
1113 struct bma400_data *data = iio_priv(indio_dev);
1115 switch (chan->type) {
1118 case IIO_EV_DIR_RISING:
1119 return FIELD_GET(BMA400_INT_GEN1_MSK,
1120 data->generic_event_en);
1121 case IIO_EV_DIR_FALLING:
1122 return FIELD_GET(BMA400_INT_GEN2_MSK,
1123 data->generic_event_en);
1124 case IIO_EV_DIR_SINGLETAP:
1125 return FIELD_GET(BMA400_S_TAP_MSK,
1126 data->tap_event_en_bitmask);
1127 case IIO_EV_DIR_DOUBLETAP:
1128 return FIELD_GET(BMA400_D_TAP_MSK,
1129 data->tap_event_en_bitmask);
1134 return data->step_event_en;
1136 return data->activity_event_en;
1142 static int bma400_steps_event_enable(struct bma400_data *data, int state)
1146 ret = bma400_enable_steps(data, 1);
1150 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG,
1151 BMA400_STEP_INT_MSK,
1152 FIELD_PREP(BMA400_STEP_INT_MSK,
1156 data->step_event_en = state;
1160 static int bma400_activity_event_en(struct bma400_data *data,
1161 enum iio_event_direction dir,
1164 int ret, reg, msk, value;
1165 int field_value = 0;
1168 case IIO_EV_DIR_RISING:
1169 reg = BMA400_GEN1INT_CONFIG0;
1170 msk = BMA400_INT_GEN1_MSK;
1172 set_mask_bits(&field_value, BMA400_INT_GEN1_MSK,
1173 FIELD_PREP(BMA400_INT_GEN1_MSK, state));
1175 case IIO_EV_DIR_FALLING:
1176 reg = BMA400_GEN2INT_CONFIG0;
1177 msk = BMA400_INT_GEN2_MSK;
1179 set_mask_bits(&field_value, BMA400_INT_GEN2_MSK,
1180 FIELD_PREP(BMA400_INT_GEN2_MSK, state));
1186 /* Enabling all axis for interrupt evaluation */
1187 ret = regmap_write(data->regmap, reg, 0xF8);
1191 /* OR combination of all axis for interrupt evaluation */
1192 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value);
1196 /* Initial value to avoid interrupts while enabling*/
1197 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A);
1201 /* Initial duration value to avoid interrupts while enabling*/
1202 ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F);
1206 ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk,
1211 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk,
1216 set_mask_bits(&data->generic_event_en, msk, field_value);
1220 static int bma400_tap_event_en(struct bma400_data *data,
1221 enum iio_event_direction dir, int state)
1223 unsigned int mask, field_value;
1227 * Tap interrupts can be configured only in normal mode.
1228 * See table in section 4.3 "Power modes - performance modes" of
1231 if (data->power_mode != POWER_MODE_NORMAL)
1235 * Tap interrupts are operating with a data rate of 200Hz.
1236 * See section 4.7 "Tap sensing interrupt" in datasheet v1.2.
1238 if (data->sample_freq.hz != 200 && state) {
1239 dev_err(data->dev, "Invalid data rate for tap interrupts.\n");
1243 ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG,
1245 FIELD_PREP(BMA400_S_TAP_MSK, state));
1250 case IIO_EV_DIR_SINGLETAP:
1251 mask = BMA400_S_TAP_MSK;
1252 set_mask_bits(&field_value, BMA400_S_TAP_MSK,
1253 FIELD_PREP(BMA400_S_TAP_MSK, state));
1255 case IIO_EV_DIR_DOUBLETAP:
1256 mask = BMA400_D_TAP_MSK;
1257 set_mask_bits(&field_value, BMA400_D_TAP_MSK,
1258 FIELD_PREP(BMA400_D_TAP_MSK, state));
1264 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG, mask,
1269 set_mask_bits(&data->tap_event_en_bitmask, mask, field_value);
1274 static int bma400_disable_adv_interrupt(struct bma400_data *data)
1278 ret = regmap_write(data->regmap, BMA400_INT_CONFIG0_REG, 0);
1282 ret = regmap_write(data->regmap, BMA400_INT_CONFIG1_REG, 0);
1286 data->tap_event_en_bitmask = 0;
1287 data->generic_event_en = 0;
1288 data->step_event_en = false;
1289 data->activity_event_en = false;
1294 static int bma400_write_event_config(struct iio_dev *indio_dev,
1295 const struct iio_chan_spec *chan,
1296 enum iio_event_type type,
1297 enum iio_event_direction dir, int state)
1299 struct bma400_data *data = iio_priv(indio_dev);
1302 switch (chan->type) {
1305 case IIO_EV_TYPE_MAG:
1306 mutex_lock(&data->mutex);
1307 ret = bma400_activity_event_en(data, dir, state);
1308 mutex_unlock(&data->mutex);
1310 case IIO_EV_TYPE_GESTURE:
1311 mutex_lock(&data->mutex);
1312 ret = bma400_tap_event_en(data, dir, state);
1313 mutex_unlock(&data->mutex);
1319 mutex_lock(&data->mutex);
1320 ret = bma400_steps_event_enable(data, state);
1321 mutex_unlock(&data->mutex);
1324 mutex_lock(&data->mutex);
1325 if (!data->step_event_en) {
1326 ret = bma400_steps_event_enable(data, true);
1328 mutex_unlock(&data->mutex);
1332 data->activity_event_en = state;
1333 mutex_unlock(&data->mutex);
1340 static int get_gen_config_reg(enum iio_event_direction dir)
1343 case IIO_EV_DIR_FALLING:
1344 return BMA400_GEN2INT_CONFIG0;
1345 case IIO_EV_DIR_RISING:
1346 return BMA400_GEN1INT_CONFIG0;
1352 static int bma400_read_event_value(struct iio_dev *indio_dev,
1353 const struct iio_chan_spec *chan,
1354 enum iio_event_type type,
1355 enum iio_event_direction dir,
1356 enum iio_event_info info,
1357 int *val, int *val2)
1359 struct bma400_data *data = iio_priv(indio_dev);
1360 int ret, reg, reg_val, raw;
1362 if (chan->type != IIO_ACCEL)
1366 case IIO_EV_TYPE_MAG:
1367 reg = get_gen_config_reg(dir);
1373 case IIO_EV_INFO_VALUE:
1374 ret = regmap_read(data->regmap,
1375 reg + BMA400_GEN_CONFIG2_OFF,
1380 case IIO_EV_INFO_PERIOD:
1381 mutex_lock(&data->mutex);
1382 ret = regmap_bulk_read(data->regmap,
1383 reg + BMA400_GEN_CONFIG3_OFF,
1385 sizeof(data->duration));
1387 mutex_unlock(&data->mutex);
1390 *val = be16_to_cpu(data->duration);
1391 mutex_unlock(&data->mutex);
1393 case IIO_EV_INFO_HYSTERESIS:
1394 ret = regmap_read(data->regmap, reg, val);
1397 *val = FIELD_GET(BMA400_GEN_HYST_MSK, *val);
1402 case IIO_EV_TYPE_GESTURE:
1404 case IIO_EV_INFO_VALUE:
1405 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG,
1410 *val = FIELD_GET(BMA400_TAP_SEN_MSK, reg_val);
1412 case IIO_EV_INFO_RESET_TIMEOUT:
1413 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1,
1418 raw = FIELD_GET(BMA400_TAP_QUIET_MSK, reg_val);
1420 *val2 = tap_reset_timeout[raw];
1421 return IIO_VAL_INT_PLUS_MICRO;
1422 case IIO_EV_INFO_TAP2_MIN_DELAY:
1423 ret = regmap_read(data->regmap, BMA400_TAP_CONFIG1,
1428 raw = FIELD_GET(BMA400_TAP_QUIETDT_MSK, reg_val);
1430 *val2 = double_tap2_min_delay[raw];
1431 return IIO_VAL_INT_PLUS_MICRO;
1440 static int bma400_write_event_value(struct iio_dev *indio_dev,
1441 const struct iio_chan_spec *chan,
1442 enum iio_event_type type,
1443 enum iio_event_direction dir,
1444 enum iio_event_info info,
1447 struct bma400_data *data = iio_priv(indio_dev);
1450 if (chan->type != IIO_ACCEL)
1454 case IIO_EV_TYPE_MAG:
1455 reg = get_gen_config_reg(dir);
1460 case IIO_EV_INFO_VALUE:
1461 if (val < 1 || val > 255)
1464 return regmap_write(data->regmap,
1465 reg + BMA400_GEN_CONFIG2_OFF,
1467 case IIO_EV_INFO_PERIOD:
1468 if (val < 1 || val > 65535)
1471 mutex_lock(&data->mutex);
1472 put_unaligned_be16(val, &data->duration);
1473 ret = regmap_bulk_write(data->regmap,
1474 reg + BMA400_GEN_CONFIG3_OFF,
1476 sizeof(data->duration));
1477 mutex_unlock(&data->mutex);
1479 case IIO_EV_INFO_HYSTERESIS:
1480 if (val < 0 || val > 3)
1483 return regmap_update_bits(data->regmap, reg,
1484 BMA400_GEN_HYST_MSK,
1485 FIELD_PREP(BMA400_GEN_HYST_MSK,
1490 case IIO_EV_TYPE_GESTURE:
1492 case IIO_EV_INFO_VALUE:
1493 if (val < 0 || val > 7)
1496 return regmap_update_bits(data->regmap,
1499 FIELD_PREP(BMA400_TAP_SEN_MSK,
1501 case IIO_EV_INFO_RESET_TIMEOUT:
1502 raw = usec_to_tapreg_raw(val2, tap_reset_timeout);
1506 return regmap_update_bits(data->regmap,
1508 BMA400_TAP_QUIET_MSK,
1509 FIELD_PREP(BMA400_TAP_QUIET_MSK,
1511 case IIO_EV_INFO_TAP2_MIN_DELAY:
1512 raw = usec_to_tapreg_raw(val2, double_tap2_min_delay);
1516 return regmap_update_bits(data->regmap,
1518 BMA400_TAP_QUIETDT_MSK,
1519 FIELD_PREP(BMA400_TAP_QUIETDT_MSK,
1529 static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig,
1532 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1533 struct bma400_data *data = iio_priv(indio_dev);
1536 ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG,
1537 BMA400_INT_DRDY_MSK,
1538 FIELD_PREP(BMA400_INT_DRDY_MSK, state));
1542 return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG,
1543 BMA400_INT_DRDY_MSK,
1544 FIELD_PREP(BMA400_INT_DRDY_MSK, state));
1547 static const unsigned long bma400_avail_scan_masks[] = {
1548 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z),
1549 BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z)
1554 static const struct iio_info bma400_info = {
1555 .read_raw = bma400_read_raw,
1556 .read_avail = bma400_read_avail,
1557 .write_raw = bma400_write_raw,
1558 .write_raw_get_fmt = bma400_write_raw_get_fmt,
1559 .read_event_config = bma400_read_event_config,
1560 .write_event_config = bma400_write_event_config,
1561 .write_event_value = bma400_write_event_value,
1562 .read_event_value = bma400_read_event_value,
1563 .event_attrs = &bma400_event_attribute_group,
1566 static const struct iio_trigger_ops bma400_trigger_ops = {
1567 .set_trigger_state = &bma400_data_rdy_trigger_set_state,
1568 .validate_device = &iio_trigger_validate_own_device,
1571 static irqreturn_t bma400_trigger_handler(int irq, void *p)
1573 struct iio_poll_func *pf = p;
1574 struct iio_dev *indio_dev = pf->indio_dev;
1575 struct bma400_data *data = iio_priv(indio_dev);
1578 /* Lock to protect the data->buffer */
1579 mutex_lock(&data->mutex);
1581 /* bulk read six registers, with the base being the LSB register */
1582 ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG,
1583 &data->buffer.buff, sizeof(data->buffer.buff));
1587 if (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) {
1588 ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp);
1592 data->buffer.temperature = temp;
1595 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1596 iio_get_time_ns(indio_dev));
1598 mutex_unlock(&data->mutex);
1599 iio_trigger_notify_done(indio_dev->trig);
1603 mutex_unlock(&data->mutex);
1607 static irqreturn_t bma400_interrupt(int irq, void *private)
1609 struct iio_dev *indio_dev = private;
1610 struct bma400_data *data = iio_priv(indio_dev);
1611 s64 timestamp = iio_get_time_ns(indio_dev);
1612 unsigned int act, ev_dir = IIO_EV_DIR_NONE;
1615 /* Lock to protect the data->status */
1616 mutex_lock(&data->mutex);
1617 ret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG,
1619 sizeof(data->status));
1621 * if none of the bit is set in the status register then it is
1622 * spurious interrupt.
1624 if (ret || !data->status)
1628 * Disable all advance interrupts if interrupt engine overrun occurs.
1629 * See section 4.7 "Interrupt engine overrun" in datasheet v1.2.
1631 if (FIELD_GET(BMA400_INT_ENG_OVRUN_MSK, le16_to_cpu(data->status))) {
1632 bma400_disable_adv_interrupt(data);
1633 dev_err(data->dev, "Interrupt engine overrun\n");
1637 if (FIELD_GET(BMA400_INT_S_TAP_MSK, le16_to_cpu(data->status)))
1638 iio_push_event(indio_dev,
1639 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1640 IIO_MOD_X_OR_Y_OR_Z,
1641 IIO_EV_TYPE_GESTURE,
1642 IIO_EV_DIR_SINGLETAP),
1645 if (FIELD_GET(BMA400_INT_D_TAP_MSK, le16_to_cpu(data->status)))
1646 iio_push_event(indio_dev,
1647 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1648 IIO_MOD_X_OR_Y_OR_Z,
1649 IIO_EV_TYPE_GESTURE,
1650 IIO_EV_DIR_DOUBLETAP),
1653 if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status)))
1654 ev_dir = IIO_EV_DIR_RISING;
1656 if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status)))
1657 ev_dir = IIO_EV_DIR_FALLING;
1659 if (ev_dir != IIO_EV_DIR_NONE) {
1660 iio_push_event(indio_dev,
1661 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1662 IIO_MOD_X_OR_Y_OR_Z,
1663 IIO_EV_TYPE_MAG, ev_dir),
1667 if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) {
1668 iio_push_event(indio_dev,
1669 IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD,
1674 if (data->activity_event_en) {
1675 ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG,
1680 iio_push_event(indio_dev,
1681 IIO_MOD_EVENT_CODE(IIO_ACTIVITY, 0,
1682 bma400_act_to_mod(act),
1689 if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) {
1690 mutex_unlock(&data->mutex);
1691 iio_trigger_poll_nested(data->trig);
1695 mutex_unlock(&data->mutex);
1699 mutex_unlock(&data->mutex);
1703 int bma400_probe(struct device *dev, struct regmap *regmap, int irq,
1706 struct iio_dev *indio_dev;
1707 struct bma400_data *data;
1710 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1714 data = iio_priv(indio_dev);
1715 data->regmap = regmap;
1718 ret = bma400_init(data);
1722 ret = iio_read_mount_matrix(dev, &data->orientation);
1726 mutex_init(&data->mutex);
1727 indio_dev->name = name;
1728 indio_dev->info = &bma400_info;
1729 indio_dev->channels = bma400_channels;
1730 indio_dev->num_channels = ARRAY_SIZE(bma400_channels);
1731 indio_dev->available_scan_masks = bma400_avail_scan_masks;
1732 indio_dev->modes = INDIO_DIRECT_MODE;
1735 data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
1737 iio_device_id(indio_dev));
1741 data->trig->ops = &bma400_trigger_ops;
1742 iio_trigger_set_drvdata(data->trig, indio_dev);
1744 ret = devm_iio_trigger_register(data->dev, data->trig);
1746 return dev_err_probe(data->dev, ret,
1747 "iio trigger register fail\n");
1749 indio_dev->trig = iio_trigger_get(data->trig);
1750 ret = devm_request_threaded_irq(dev, irq, NULL,
1752 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1753 indio_dev->name, indio_dev);
1755 return dev_err_probe(data->dev, ret,
1756 "request irq %d failed\n", irq);
1759 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
1760 &bma400_trigger_handler, NULL);
1762 return dev_err_probe(data->dev, ret,
1763 "iio triggered buffer setup failed\n");
1765 return devm_iio_device_register(dev, indio_dev);
1767 EXPORT_SYMBOL_NS(bma400_probe, IIO_BMA400);
1771 MODULE_DESCRIPTION("Bosch BMA400 triaxial acceleration sensor core");
1772 MODULE_LICENSE("GPL");