drivers/iio/adc/stm32-dfsdm-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file is part the core part STM32 DFSDM driver
   4  *
   5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6  * Author(s): Arnaud Pouliquen <[email protected]> for STMicroelectronics.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/iio/iio.h>
  11 #include <linux/iio/sysfs.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/module.h>
  14 #include <linux/of_device.h>
  15 #include <linux/regmap.h>
  16 #include <linux/slab.h>
  17
  18 #include "stm32-dfsdm.h"
  19
  20 struct stm32_dfsdm_dev_data {
  21         unsigned int num_filters;
  22         unsigned int num_channels;
  23         const struct regmap_config *regmap_cfg;
  24 };
  25
  26 #define STM32H7_DFSDM_NUM_FILTERS       4
  27 #define STM32H7_DFSDM_NUM_CHANNELS      8
  28
  29 static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
  30 {
  31         if (reg < DFSDM_FILTER_BASE_ADR)
  32                 return false;
  33
  34         /*
  35          * Mask is done on register to avoid to list registers of all
  36          * filter instances.
  37          */
  38         switch (reg & DFSDM_FILTER_REG_MASK) {
  39         case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
  40         case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
  41         case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
  42         case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
  43                 return true;
  44         }
  45
  46         return false;
  47 }
  48
  49 static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
  50         .reg_bits = 32,
  51         .val_bits = 32,
  52         .reg_stride = sizeof(u32),
  53         .max_register = 0x2B8,
  54         .volatile_reg = stm32_dfsdm_volatile_reg,
  55         .fast_io = true,
  56 };
  57
  58 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
  59         .num_filters = STM32H7_DFSDM_NUM_FILTERS,
  60         .num_channels = STM32H7_DFSDM_NUM_CHANNELS,
  61         .regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
  62 };
  63
  64 struct dfsdm_priv {
  65         struct platform_device *pdev; /* platform device */
  66
  67         struct stm32_dfsdm dfsdm; /* common data exported for all instances */
  68
  69         unsigned int spi_clk_out_div; /* SPI clkout divider value */
  70         atomic_t n_active_ch;   /* number of current active channels */
  71
  72         struct clk *clk; /* DFSDM clock */
  73         struct clk *aclk; /* audio clock */
  74 };
  75
  76 /**
  77  * stm32_dfsdm_start_dfsdm - start global dfsdm interface.
  78  *
  79  * Enable interface if n_active_ch is not null.
  80  * @dfsdm: Handle used to retrieve dfsdm context.
  81  */
  82 int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
  83 {
  84         struct dfsdm_priv *priv = container_of(dfsdm, struct dfsdm_priv, dfsdm);
  85         struct device *dev = &priv->pdev->dev;
  86         unsigned int clk_div = priv->spi_clk_out_div, clk_src;
  87         int ret;
  88
  89         if (atomic_inc_return(&priv->n_active_ch) == 1) {
  90                 ret = clk_prepare_enable(priv->clk);
  91                 if (ret < 0) {
  92                         dev_err(dev, "Failed to start clock\n");
  93                         goto error_ret;
  94                 }
  95                 if (priv->aclk) {
  96                         ret = clk_prepare_enable(priv->aclk);
  97                         if (ret < 0) {
  98                                 dev_err(dev, "Failed to start audio clock\n");
  99                                 goto disable_clk;
 100                         }
 101                 }
 102
 103                 /* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
 104                 clk_src = priv->aclk ? 1 : 0;
 105                 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
 106                                          DFSDM_CHCFGR1_CKOUTSRC_MASK,
 107                                          DFSDM_CHCFGR1_CKOUTSRC(clk_src));
 108                 if (ret < 0)
 109                         goto disable_aclk;
 110
 111                 /* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
 112                 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
 113                                          DFSDM_CHCFGR1_CKOUTDIV_MASK,
 114                                          DFSDM_CHCFGR1_CKOUTDIV(clk_div));
 115                 if (ret < 0)
 116                         goto disable_aclk;
 117
 118                 /* Global enable of DFSDM interface */
 119                 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
 120                                          DFSDM_CHCFGR1_DFSDMEN_MASK,
 121                                          DFSDM_CHCFGR1_DFSDMEN(1));
 122                 if (ret < 0)
 123                         goto disable_aclk;
 124         }
 125
 126         dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
 127                 atomic_read(&priv->n_active_ch));
 128
 129         return 0;
 130
 131 disable_aclk:
 132         clk_disable_unprepare(priv->aclk);
 133 disable_clk:
 134         clk_disable_unprepare(priv->clk);
 135
 136 error_ret:
 137         atomic_dec(&priv->n_active_ch);
 138
 139         return ret;
 140 }
 141 EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
 142
 143 /**
 144  * stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
 145  *
 146  * Disable interface if n_active_ch is null
 147  * @dfsdm: Handle used to retrieve dfsdm context.
 148  */
 149 int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
 150 {
 151         struct dfsdm_priv *priv = container_of(dfsdm, struct dfsdm_priv, dfsdm);
 152         int ret;
 153
 154         if (atomic_dec_and_test(&priv->n_active_ch)) {
 155                 /* Global disable of DFSDM interface */
 156                 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
 157                                          DFSDM_CHCFGR1_DFSDMEN_MASK,
 158                                          DFSDM_CHCFGR1_DFSDMEN(0));
 159                 if (ret < 0)
 160                         return ret;
 161
 162                 /* Stop SPI CLKOUT */
 163                 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
 164                                          DFSDM_CHCFGR1_CKOUTDIV_MASK,
 165                                          DFSDM_CHCFGR1_CKOUTDIV(0));
 166                 if (ret < 0)
 167                         return ret;
 168
 169                 clk_disable_unprepare(priv->clk);
 170                 if (priv->aclk)
 171                         clk_disable_unprepare(priv->aclk);
 172         }
 173         dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
 174                 atomic_read(&priv->n_active_ch));
 175
 176         return 0;
 177 }
 178 EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
 179
 180 static int stm32_dfsdm_parse_of(struct platform_device *pdev,
 181                                 struct dfsdm_priv *priv)
 182 {
 183         struct device_node *node = pdev->dev.of_node;
 184         struct resource *res;
 185         unsigned long clk_freq;
 186         unsigned int spi_freq, rem;
 187         int ret;
 188
 189         if (!node)
 190                 return -EINVAL;
 191
 192         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 193         if (!res) {
 194                 dev_err(&pdev->dev, "Failed to get memory resource\n");
 195                 return -ENODEV;
 196         }
 197         priv->dfsdm.phys_base = res->start;
 198         priv->dfsdm.base = devm_ioremap_resource(&pdev->dev, res);
 199
 200         /*
 201          * "dfsdm" clock is mandatory for DFSDM peripheral clocking.
 202          * "dfsdm" or "audio" clocks can be used as source clock for
 203          * the SPI clock out signal and internal processing, depending
 204          * on use case.
 205          */
 206         priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
 207         if (IS_ERR(priv->clk)) {
 208                 dev_err(&pdev->dev, "No stm32_dfsdm_clk clock found\n");
 209                 return -EINVAL;
 210         }
 211
 212         priv->aclk = devm_clk_get(&pdev->dev, "audio");
 213         if (IS_ERR(priv->aclk))
 214                 priv->aclk = NULL;
 215
 216         if (priv->aclk)
 217                 clk_freq = clk_get_rate(priv->aclk);
 218         else
 219                 clk_freq = clk_get_rate(priv->clk);
 220
 221         /* SPI clock out frequency */
 222         ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
 223                                    &spi_freq);
 224         if (ret < 0) {
 225                 /* No SPI master mode */
 226                 return 0;
 227         }
 228
 229         priv->spi_clk_out_div = div_u64_rem(clk_freq, spi_freq, &rem) - 1;
 230         if (!priv->spi_clk_out_div) {
 231                 /* spi_clk_out_div == 0 means ckout is OFF */
 232                 dev_err(&pdev->dev, "spi-max-frequency not achievable\n");
 233                 return -EINVAL;
 234         }
 235         priv->dfsdm.spi_master_freq = spi_freq;
 236
 237         if (rem) {
 238                 dev_warn(&pdev->dev, "SPI clock not accurate\n");
 239                 dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
 240                          clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
 241         }
 242
 243         return 0;
 244 };
 245
 246 static const struct of_device_id stm32_dfsdm_of_match[] = {
 247         {
 248                 .compatible = "st,stm32h7-dfsdm",
 249                 .data = &stm32h7_dfsdm_data,
 250         },
 251         {}
 252 };
 253 MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
 254
 255 static int stm32_dfsdm_probe(struct platform_device *pdev)
 256 {
 257         struct dfsdm_priv *priv;
 258         const struct stm32_dfsdm_dev_data *dev_data;
 259         struct stm32_dfsdm *dfsdm;
 260         int ret;
 261
 262         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 263         if (!priv)
 264                 return -ENOMEM;
 265
 266         priv->pdev = pdev;
 267
 268         dev_data = of_device_get_match_data(&pdev->dev);
 269
 270         dfsdm = &priv->dfsdm;
 271         dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
 272                                       sizeof(*dfsdm->fl_list), GFP_KERNEL);
 273         if (!dfsdm->fl_list)
 274                 return -ENOMEM;
 275
 276         dfsdm->num_fls = dev_data->num_filters;
 277         dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
 278                                       sizeof(*dfsdm->ch_list),
 279                                       GFP_KERNEL);
 280         if (!dfsdm->ch_list)
 281                 return -ENOMEM;
 282         dfsdm->num_chs = dev_data->num_channels;
 283
 284         ret = stm32_dfsdm_parse_of(pdev, priv);
 285         if (ret < 0)
 286                 return ret;
 287
 288         dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
 289                                                   dfsdm->base,
 290                                                   dev_data->regmap_cfg);
 291         if (IS_ERR(dfsdm->regmap)) {
 292                 ret = PTR_ERR(dfsdm->regmap);
 293                 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
 294                         __func__, ret);
 295                 return ret;
 296         }
 297
 298         platform_set_drvdata(pdev, dfsdm);
 299
 300         return devm_of_platform_populate(&pdev->dev);
 301 }
 302
 303 static struct platform_driver stm32_dfsdm_driver = {
 304         .probe = stm32_dfsdm_probe,
 305         .driver = {
 306                 .name = "stm32-dfsdm",
 307                 .of_match_table = stm32_dfsdm_of_match,
 308         },
 309 };
 310
 311 module_platform_driver(stm32_dfsdm_driver);
 312
 313 MODULE_AUTHOR("Arnaud Pouliquen <[email protected]>");
 314 MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
 315 MODULE_LICENSE("GPL v2");