drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "amdgpu_pm.h"
  29 #include "soc15.h"
  30 #include "soc15d.h"
  31 #include "soc15_common.h"
  32
  33 #include "vcn/vcn_1_0_offset.h"
  34 #include "vcn/vcn_1_0_sh_mask.h"
  35 #include "mmhub/mmhub_9_1_offset.h"
  36 #include "mmhub/mmhub_9_1_sh_mask.h"
  37
  38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
  39 #include "jpeg_v1_0.h"
  40 #include "vcn_v1_0.h"
  41
  42 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0           0x05ab
  43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX  1
  44 #define mmUVD_REG_XX_MASK_1_0                   0x05ac
  45 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX          1
  46
  47 static int vcn_v1_0_stop(struct amdgpu_device *adev);
  48 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  49 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  50 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
  51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
  52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
  53                                 int inst_idx, struct dpg_pause_state *new_state);
  54
  55 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
  56 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
  57
  58 /**
  59  * vcn_v1_0_early_init - set function pointers
  60  *
  61  * @handle: amdgpu_device pointer
  62  *
  63  * Set ring and irq function pointers
  64  */
  65 static int vcn_v1_0_early_init(void *handle)
  66 {
  67         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  68
  69         adev->vcn.num_enc_rings = 2;
  70
  71         vcn_v1_0_set_dec_ring_funcs(adev);
  72         vcn_v1_0_set_enc_ring_funcs(adev);
  73         vcn_v1_0_set_irq_funcs(adev);
  74
  75         jpeg_v1_0_early_init(handle);
  76
  77         return 0;
  78 }
  79
  80 /**
  81  * vcn_v1_0_sw_init - sw init for VCN block
  82  *
  83  * @handle: amdgpu_device pointer
  84  *
  85  * Load firmware and sw initialization
  86  */
  87 static int vcn_v1_0_sw_init(void *handle)
  88 {
  89         struct amdgpu_ring *ring;
  90         int i, r;
  91         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  92
  93         /* VCN DEC TRAP */
  94         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  95                         VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
  96         if (r)
  97                 return r;
  98
  99         /* VCN ENC TRAP */
 100         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 101                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
 102                                         &adev->vcn.inst->irq);
 103                 if (r)
 104                         return r;
 105         }
 106
 107         r = amdgpu_vcn_sw_init(adev);
 108         if (r)
 109                 return r;
 110
 111         /* Override the work func */
 112         adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
 113
 114         amdgpu_vcn_setup_ucode(adev);
 115
 116         r = amdgpu_vcn_resume(adev);
 117         if (r)
 118                 return r;
 119
 120         ring = &adev->vcn.inst->ring_dec;
 121         sprintf(ring->name, "vcn_dec");
 122         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
 123                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 124         if (r)
 125                 return r;
 126
 127         adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
 128                 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
 129         adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
 130                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
 131         adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
 132                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
 133         adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
 134                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
 135         adev->vcn.internal.nop = adev->vcn.inst->external.nop =
 136                 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
 137
 138         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 139                 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
 140
 141                 ring = &adev->vcn.inst->ring_enc[i];
 142                 sprintf(ring->name, "vcn_enc%d", i);
 143                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
 144                                      hw_prio, NULL);
 145                 if (r)
 146                         return r;
 147         }
 148
 149         adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
 150
 151         if (amdgpu_vcnfw_log) {
 152                 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr;
 153
 154                 fw_shared->present_flag_0 = 0;
 155                 amdgpu_vcn_fwlog_init(adev->vcn.inst);
 156         }
 157
 158         r = jpeg_v1_0_sw_init(handle);
 159
 160         return r;
 161 }
 162
 163 /**
 164  * vcn_v1_0_sw_fini - sw fini for VCN block
 165  *
 166  * @handle: amdgpu_device pointer
 167  *
 168  * VCN suspend and free up sw allocation
 169  */
 170 static int vcn_v1_0_sw_fini(void *handle)
 171 {
 172         int r;
 173         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 174
 175         r = amdgpu_vcn_suspend(adev);
 176         if (r)
 177                 return r;
 178
 179         jpeg_v1_0_sw_fini(handle);
 180
 181         r = amdgpu_vcn_sw_fini(adev);
 182
 183         return r;
 184 }
 185
 186 /**
 187  * vcn_v1_0_hw_init - start and test VCN block
 188  *
 189  * @handle: amdgpu_device pointer
 190  *
 191  * Initialize the hardware, boot up the VCPU and do some testing
 192  */
 193 static int vcn_v1_0_hw_init(void *handle)
 194 {
 195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 196         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 197         int i, r;
 198
 199         r = amdgpu_ring_test_helper(ring);
 200         if (r)
 201                 goto done;
 202
 203         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 204                 ring = &adev->vcn.inst->ring_enc[i];
 205                 r = amdgpu_ring_test_helper(ring);
 206                 if (r)
 207                         goto done;
 208         }
 209
 210         ring = &adev->jpeg.inst->ring_dec;
 211         r = amdgpu_ring_test_helper(ring);
 212         if (r)
 213                 goto done;
 214
 215 done:
 216         if (!r)
 217                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 218                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 219
 220         return r;
 221 }
 222
 223 /**
 224  * vcn_v1_0_hw_fini - stop the hardware block
 225  *
 226  * @handle: amdgpu_device pointer
 227  *
 228  * Stop the VCN block, mark ring as not ready any more
 229  */
 230 static int vcn_v1_0_hw_fini(void *handle)
 231 {
 232         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 233
 234         cancel_delayed_work_sync(&adev->vcn.idle_work);
 235
 236         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 237                 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
 238                  RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
 239                 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 240         }
 241
 242         return 0;
 243 }
 244
 245 /**
 246  * vcn_v1_0_suspend - suspend VCN block
 247  *
 248  * @handle: amdgpu_device pointer
 249  *
 250  * HW fini and suspend VCN block
 251  */
 252 static int vcn_v1_0_suspend(void *handle)
 253 {
 254         int r;
 255         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 256         bool idle_work_unexecuted;
 257
 258         idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
 259         if (idle_work_unexecuted) {
 260                 if (adev->pm.dpm_enabled)
 261                         amdgpu_dpm_enable_uvd(adev, false);
 262         }
 263
 264         r = vcn_v1_0_hw_fini(adev);
 265         if (r)
 266                 return r;
 267
 268         r = amdgpu_vcn_suspend(adev);
 269
 270         return r;
 271 }
 272
 273 /**
 274  * vcn_v1_0_resume - resume VCN block
 275  *
 276  * @handle: amdgpu_device pointer
 277  *
 278  * Resume firmware and hw init VCN block
 279  */
 280 static int vcn_v1_0_resume(void *handle)
 281 {
 282         int r;
 283         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 284
 285         r = amdgpu_vcn_resume(adev);
 286         if (r)
 287                 return r;
 288
 289         r = vcn_v1_0_hw_init(adev);
 290
 291         return r;
 292 }
 293
 294 /**
 295  * vcn_v1_0_mc_resume_spg_mode - memory controller programming
 296  *
 297  * @adev: amdgpu_device pointer
 298  *
 299  * Let the VCN memory controller know it's offsets
 300  */
 301 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
 302 {
 303         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 304         uint32_t offset;
 305
 306         /* cache window 0: fw */
 307         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 308                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 309                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 310                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 311                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 312                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 313                 offset = 0;
 314         } else {
 315                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 316                         lower_32_bits(adev->vcn.inst->gpu_addr));
 317                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 318                         upper_32_bits(adev->vcn.inst->gpu_addr));
 319                 offset = size;
 320                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 321                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 322         }
 323
 324         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 325
 326         /* cache window 1: stack */
 327         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 328                      lower_32_bits(adev->vcn.inst->gpu_addr + offset));
 329         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 330                      upper_32_bits(adev->vcn.inst->gpu_addr + offset));
 331         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 332         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 333
 334         /* cache window 2: context */
 335         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 336                      lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 337         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 338                      upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 339         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 340         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 341
 342         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 343                         adev->gfx.config.gb_addr_config);
 344         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 345                         adev->gfx.config.gb_addr_config);
 346         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 347                         adev->gfx.config.gb_addr_config);
 348         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 349                         adev->gfx.config.gb_addr_config);
 350         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 351                         adev->gfx.config.gb_addr_config);
 352         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 353                         adev->gfx.config.gb_addr_config);
 354         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 355                         adev->gfx.config.gb_addr_config);
 356         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 357                         adev->gfx.config.gb_addr_config);
 358         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 359                         adev->gfx.config.gb_addr_config);
 360         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 361                         adev->gfx.config.gb_addr_config);
 362         WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
 363                         adev->gfx.config.gb_addr_config);
 364         WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
 365                         adev->gfx.config.gb_addr_config);
 366 }
 367
 368 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
 369 {
 370         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 371         uint32_t offset;
 372
 373         /* cache window 0: fw */
 374         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 375                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 376                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
 377                              0xFFFFFFFF, 0);
 378                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 379                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
 380                              0xFFFFFFFF, 0);
 381                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
 382                              0xFFFFFFFF, 0);
 383                 offset = 0;
 384         } else {
 385                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 386                         lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
 387                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 388                         upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
 389                 offset = size;
 390                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 391                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
 392         }
 393
 394         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
 395
 396         /* cache window 1: stack */
 397         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 398                      lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
 399         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 400                      upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
 401         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
 402                              0xFFFFFFFF, 0);
 403         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
 404                              0xFFFFFFFF, 0);
 405
 406         /* cache window 2: context */
 407         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 408                      lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 409                              0xFFFFFFFF, 0);
 410         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 411                      upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 412                              0xFFFFFFFF, 0);
 413         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
 414         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
 415                              0xFFFFFFFF, 0);
 416
 417         /* VCN global tiling registers */
 418         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 419                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 420         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 421                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 422         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 423                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 424         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 425                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 426         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 427                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 428         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 429                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 430         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 431                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 432         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 433                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 434         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 435                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 436         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 437                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 438 }
 439
 440 /**
 441  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
 442  *
 443  * @adev: amdgpu_device pointer
 444  *
 445  * Disable clock gating for VCN block
 446  */
 447 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 448 {
 449         uint32_t data;
 450
 451         /* JPEG disable CGC */
 452         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 453
 454         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 455                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 456         else
 457                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 458
 459         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 460         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 461         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 462
 463         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 464         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 465         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 466
 467         /* UVD disable CGC */
 468         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 469         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 470                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 471         else
 472                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 473
 474         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 475         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 476         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 477
 478         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 479         data &= ~(UVD_CGC_GATE__SYS_MASK
 480                 | UVD_CGC_GATE__UDEC_MASK
 481                 | UVD_CGC_GATE__MPEG2_MASK
 482                 | UVD_CGC_GATE__REGS_MASK
 483                 | UVD_CGC_GATE__RBC_MASK
 484                 | UVD_CGC_GATE__LMI_MC_MASK
 485                 | UVD_CGC_GATE__LMI_UMC_MASK
 486                 | UVD_CGC_GATE__IDCT_MASK
 487                 | UVD_CGC_GATE__MPRD_MASK
 488                 | UVD_CGC_GATE__MPC_MASK
 489                 | UVD_CGC_GATE__LBSI_MASK
 490                 | UVD_CGC_GATE__LRBBM_MASK
 491                 | UVD_CGC_GATE__UDEC_RE_MASK
 492                 | UVD_CGC_GATE__UDEC_CM_MASK
 493                 | UVD_CGC_GATE__UDEC_IT_MASK
 494                 | UVD_CGC_GATE__UDEC_DB_MASK
 495                 | UVD_CGC_GATE__UDEC_MP_MASK
 496                 | UVD_CGC_GATE__WCB_MASK
 497                 | UVD_CGC_GATE__VCPU_MASK
 498                 | UVD_CGC_GATE__SCPU_MASK);
 499         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 500
 501         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 502         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 503                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 504                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 505                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 506                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 507                 | UVD_CGC_CTRL__SYS_MODE_MASK
 508                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 509                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 510                 | UVD_CGC_CTRL__REGS_MODE_MASK
 511                 | UVD_CGC_CTRL__RBC_MODE_MASK
 512                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 513                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 514                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 515                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 516                 | UVD_CGC_CTRL__MPC_MODE_MASK
 517                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 518                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 519                 | UVD_CGC_CTRL__WCB_MODE_MASK
 520                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 521                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 522         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 523
 524         /* turn on */
 525         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 526         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 527                 | UVD_SUVD_CGC_GATE__SIT_MASK
 528                 | UVD_SUVD_CGC_GATE__SMP_MASK
 529                 | UVD_SUVD_CGC_GATE__SCM_MASK
 530                 | UVD_SUVD_CGC_GATE__SDB_MASK
 531                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 532                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 533                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 534                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 535                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 536                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 537                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 538                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 539                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 540                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 541                 | UVD_SUVD_CGC_GATE__ENT_MASK
 542                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 543                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 544                 | UVD_SUVD_CGC_GATE__SITE_MASK
 545                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 546                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 547                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 548                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 549                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 550         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 551
 552         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 553         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 554                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 555                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 556                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 557                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 558                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 559                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 560                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 561                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 562                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 563         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 564 }
 565
 566 /**
 567  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
 568  *
 569  * @adev: amdgpu_device pointer
 570  *
 571  * Enable clock gating for VCN block
 572  */
 573 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 574 {
 575         uint32_t data = 0;
 576
 577         /* enable JPEG CGC */
 578         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 579         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 580                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 581         else
 582                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 583         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 584         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 585         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 586
 587         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 588         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 589         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 590
 591         /* enable UVD CGC */
 592         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 593         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 594                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 595         else
 596                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 597         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 598         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 599         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 600
 601         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 602         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 603                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 604                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 605                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 606                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 607                 | UVD_CGC_CTRL__SYS_MODE_MASK
 608                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 609                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 610                 | UVD_CGC_CTRL__REGS_MODE_MASK
 611                 | UVD_CGC_CTRL__RBC_MODE_MASK
 612                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 613                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 614                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 615                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 616                 | UVD_CGC_CTRL__MPC_MODE_MASK
 617                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 618                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 619                 | UVD_CGC_CTRL__WCB_MODE_MASK
 620                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 621                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 622         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 623
 624         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 625         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 626                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 627                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 628                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 629                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 630                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 631                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 632                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 633                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 634                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 635         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 636 }
 637
 638 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
 639 {
 640         uint32_t reg_data = 0;
 641
 642         /* disable JPEG CGC */
 643         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 644                 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 645         else
 646                 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 647         reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 648         reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 649         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 650
 651         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 652
 653         /* enable sw clock gating control */
 654         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 655                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 656         else
 657                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 658         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 659         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 660         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 661                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 662                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 663                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 664                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 665                  UVD_CGC_CTRL__SYS_MODE_MASK |
 666                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 667                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 668                  UVD_CGC_CTRL__REGS_MODE_MASK |
 669                  UVD_CGC_CTRL__RBC_MODE_MASK |
 670                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 671                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 672                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 673                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 674                  UVD_CGC_CTRL__MPC_MODE_MASK |
 675                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 676                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 677                  UVD_CGC_CTRL__WCB_MODE_MASK |
 678                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 679                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 680         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 681
 682         /* turn off clock gating */
 683         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 684
 685         /* turn on SUVD clock gating */
 686         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
 687
 688         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 689         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
 690 }
 691
 692 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
 693 {
 694         uint32_t data = 0;
 695
 696         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 697                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 698                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 699                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 700                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 701                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 702                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 703                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 704                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 705                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 706                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 707                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 708
 709                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 710                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
 711         } else {
 712                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 713                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 714                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 715                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 716                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 717                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 718                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 719                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 720                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 721                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 722                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 723                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 724                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF);
 725         }
 726
 727         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
 728
 729         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 730         data &= ~0x103;
 731         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 732                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
 733
 734         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 735 }
 736
 737 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 738 {
 739         uint32_t data = 0;
 740
 741         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 742                 /* Before power off, this indicator has to be turned on */
 743                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 744                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 745                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 746                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 747
 748
 749                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 750                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 751                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 752                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 753                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 754                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 755                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 756                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 757                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 758                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 759                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 760
 761                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 762
 763                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 764                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 765                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 766                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 767                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 768                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 769                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 770                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 771                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 772                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 773                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
 774                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
 775         }
 776 }
 777
 778 /**
 779  * vcn_v1_0_start_spg_mode - start VCN block
 780  *
 781  * @adev: amdgpu_device pointer
 782  *
 783  * Setup and start the VCN block
 784  */
 785 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
 786 {
 787         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 788         uint32_t rb_bufsz, tmp;
 789         uint32_t lmi_swap_cntl;
 790         int i, j, r;
 791
 792         /* disable byte swapping */
 793         lmi_swap_cntl = 0;
 794
 795         vcn_1_0_disable_static_power_gating(adev);
 796
 797         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 798         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 799
 800         /* disable clock gating */
 801         vcn_v1_0_disable_clock_gating(adev);
 802
 803         /* disable interupt */
 804         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 805                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 806
 807         /* initialize VCN memory controller */
 808         tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
 809         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp                |
 810                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 811                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK                       |
 812                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK            |
 813                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 814
 815 #ifdef __BIG_ENDIAN
 816         /* swap (8 in 32) RB and IB */
 817         lmi_swap_cntl = 0xa;
 818 #endif
 819         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 820
 821         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 822         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 823         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 824         WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
 825
 826         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 827                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 828                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 829                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 830                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 831
 832         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 833                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 834                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 835                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 836                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 837
 838         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 839                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 840                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 841                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 842
 843         vcn_v1_0_mc_resume_spg_mode(adev);
 844
 845         WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
 846         WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
 847                 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
 848
 849         /* enable VCPU clock */
 850         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 851
 852         /* boot up the VCPU */
 853         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 854                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 855
 856         /* enable UMC */
 857         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 858                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 859
 860         tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
 861         tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 862         tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 863         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
 864
 865         for (i = 0; i < 10; ++i) {
 866                 uint32_t status;
 867
 868                 for (j = 0; j < 100; ++j) {
 869                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 870                         if (status & UVD_STATUS__IDLE)
 871                                 break;
 872                         mdelay(10);
 873                 }
 874                 r = 0;
 875                 if (status & UVD_STATUS__IDLE)
 876                         break;
 877
 878                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 879                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 880                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 881                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 882                 mdelay(10);
 883                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 884                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 885                 mdelay(10);
 886                 r = -1;
 887         }
 888
 889         if (r) {
 890                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 891                 return r;
 892         }
 893         /* enable master interrupt */
 894         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 895                 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
 896
 897         /* enable system interrupt for JRBC, TODO: move to set interrupt*/
 898         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
 899                 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
 900                 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
 901
 902         /* clear the busy bit of UVD_STATUS */
 903         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
 904         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 905
 906         /* force RBC into idle state */
 907         rb_bufsz = order_base_2(ring->ring_size);
 908         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 909         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 910         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 911         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 912         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 913         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 914
 915         /* set the write pointer delay */
 916         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 917
 918         /* set the wb address */
 919         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 920                         (upper_32_bits(ring->gpu_addr) >> 2));
 921
 922         /* program the RB_BASE for ring buffer */
 923         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 924                         lower_32_bits(ring->gpu_addr));
 925         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 926                         upper_32_bits(ring->gpu_addr));
 927
 928         /* Initialize the ring buffer's read and write pointers */
 929         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 930
 931         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 932
 933         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 934         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 935                         lower_32_bits(ring->wptr));
 936
 937         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
 938                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 939
 940         ring = &adev->vcn.inst->ring_enc[0];
 941         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 942         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 943         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 944         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 945         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 946
 947         ring = &adev->vcn.inst->ring_enc[1];
 948         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 949         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 950         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 951         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 952         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 953
 954         jpeg_v1_0_start(adev, 0);
 955
 956         return 0;
 957 }
 958
 959 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
 960 {
 961         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 962         uint32_t rb_bufsz, tmp;
 963         uint32_t lmi_swap_cntl;
 964
 965         /* disable byte swapping */
 966         lmi_swap_cntl = 0;
 967
 968         vcn_1_0_enable_static_power_gating(adev);
 969
 970         /* enable dynamic power gating mode */
 971         tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 972         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 973         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 974         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
 975
 976         /* enable clock gating */
 977         vcn_v1_0_clock_gating_dpg_mode(adev, 0);
 978
 979         /* enable VCPU clock */
 980         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 981         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 982         tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
 983         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
 984
 985         /* disable interupt */
 986         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
 987                         0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 988
 989         /* initialize VCN memory controller */
 990         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
 991                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 992                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 993                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 994                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 995                 UVD_LMI_CTRL__REQ_MODE_MASK |
 996                 UVD_LMI_CTRL__CRC_RESET_MASK |
 997                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 998                 0x00100000L, 0xFFFFFFFF, 0);
 999
1000 #ifdef __BIG_ENDIAN
1001         /* swap (8 in 32) RB and IB */
1002         lmi_swap_cntl = 0xa;
1003 #endif
1004         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
1005
1006         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
1007                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
1008
1009         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
1010                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1011                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1012                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1013                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1014
1015         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1016                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1017                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1018                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1019                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1020
1021         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1022                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1023                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1024                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1025
1026         vcn_v1_0_mc_resume_dpg_mode(adev);
1027
1028         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1029         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1030
1031         /* boot up the VCPU */
1032         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1033
1034         /* enable UMC */
1035         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1036                 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1037                 0xFFFFFFFF, 0);
1038
1039         /* enable master interrupt */
1040         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1041                         UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1042
1043         vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1044         /* setup mmUVD_LMI_CTRL */
1045         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1046                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1047                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1048                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1049                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1050                 UVD_LMI_CTRL__REQ_MODE_MASK |
1051                 UVD_LMI_CTRL__CRC_RESET_MASK |
1052                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1053                 0x00100000L, 0xFFFFFFFF, 1);
1054
1055         tmp = adev->gfx.config.gb_addr_config;
1056         /* setup VCN global tiling registers */
1057         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1058         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1059
1060         /* enable System Interrupt for JRBC */
1061         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1062                                                                         UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1063
1064         /* force RBC into idle state */
1065         rb_bufsz = order_base_2(ring->ring_size);
1066         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1067         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1068         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1069         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1070         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1071         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1072
1073         /* set the write pointer delay */
1074         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1075
1076         /* set the wb address */
1077         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1078                                                                 (upper_32_bits(ring->gpu_addr) >> 2));
1079
1080         /* program the RB_BASE for ring buffer */
1081         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1082                                                                 lower_32_bits(ring->gpu_addr));
1083         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1084                                                                 upper_32_bits(ring->gpu_addr));
1085
1086         /* Initialize the ring buffer's read and write pointers */
1087         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1088
1089         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1090
1091         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1092         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1093                                                                 lower_32_bits(ring->wptr));
1094
1095         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1096                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1097
1098         jpeg_v1_0_start(adev, 1);
1099
1100         return 0;
1101 }
1102
1103 static int vcn_v1_0_start(struct amdgpu_device *adev)
1104 {
1105         return (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ?
1106                 vcn_v1_0_start_dpg_mode(adev) : vcn_v1_0_start_spg_mode(adev);
1107 }
1108
1109 /**
1110  * vcn_v1_0_stop_spg_mode - stop VCN block
1111  *
1112  * @adev: amdgpu_device pointer
1113  *
1114  * stop the VCN block
1115  */
1116 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1117 {
1118         int tmp;
1119
1120         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1121
1122         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1123                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1124                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1125                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1126         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1127
1128         /* stall UMC channel */
1129         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
1130                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1131                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1132
1133         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1134                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1135         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1136
1137         /* disable VCPU clock */
1138         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1139                 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1140
1141         /* reset LMI UMC/LMI */
1142         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1143                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1144                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1145
1146         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1147                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1148                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1149
1150         /* put VCPU into reset */
1151         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1152                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1153                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1154
1155         WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1156
1157         vcn_v1_0_enable_clock_gating(adev);
1158         vcn_1_0_enable_static_power_gating(adev);
1159         return 0;
1160 }
1161
1162 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1163 {
1164         uint32_t tmp;
1165
1166         /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1167         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1168                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1169                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1170
1171         /* wait for read ptr to be equal to write ptr */
1172         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1173         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1174
1175         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1176         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1177
1178         tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1179         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1180
1181         tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1182         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1183
1184         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1185                 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1186                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1187
1188         /* disable dynamic power gating mode */
1189         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1190                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1191
1192         return 0;
1193 }
1194
1195 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1196 {
1197         int r;
1198
1199         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1200                 r = vcn_v1_0_stop_dpg_mode(adev);
1201         else
1202                 r = vcn_v1_0_stop_spg_mode(adev);
1203
1204         return r;
1205 }
1206
1207 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
1208                                 int inst_idx, struct dpg_pause_state *new_state)
1209 {
1210         int ret_code;
1211         uint32_t reg_data = 0;
1212         uint32_t reg_data2 = 0;
1213         struct amdgpu_ring *ring;
1214
1215         /* pause/unpause if state is changed */
1216         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1217                 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1218                         adev->vcn.inst[inst_idx].pause_state.fw_based,
1219                         adev->vcn.inst[inst_idx].pause_state.jpeg,
1220                         new_state->fw_based, new_state->jpeg);
1221
1222                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1223                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1224
1225                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1226                         ret_code = 0;
1227
1228                         if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1229                                 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1230                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1231                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1232
1233                         if (!ret_code) {
1234                                 /* pause DPG non-jpeg */
1235                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1236                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1237                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1238                                                    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1239                                                    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1240
1241                                 /* Restore */
1242                                 ring = &adev->vcn.inst->ring_enc[0];
1243                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1244                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1245                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1246                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1247                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1248
1249                                 ring = &adev->vcn.inst->ring_enc[1];
1250                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1251                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1252                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1253                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1254                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1255
1256                                 ring = &adev->vcn.inst->ring_dec;
1257                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1258                                                    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1259                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1260                                                    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1261                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1262                         }
1263                 } else {
1264                         /* unpause dpg non-jpeg, no need to wait */
1265                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1266                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1267                 }
1268                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1269         }
1270
1271         /* pause/unpause if state is changed */
1272         if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1273                 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1274                         adev->vcn.inst[inst_idx].pause_state.fw_based,
1275                         adev->vcn.inst[inst_idx].pause_state.jpeg,
1276                         new_state->fw_based, new_state->jpeg);
1277
1278                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1279                         (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1280
1281                 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1282                         ret_code = 0;
1283
1284                         if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1285                                 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1286                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1287                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1288
1289                         if (!ret_code) {
1290                                 /* Make sure JPRG Snoop is disabled before sending the pause */
1291                                 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1292                                 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1293                                 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1294
1295                                 /* pause DPG jpeg */
1296                                 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1297                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1298                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1299                                                         UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1300                                                         UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1301
1302                                 /* Restore */
1303                                 ring = &adev->jpeg.inst->ring_dec;
1304                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1305                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1306                                                         UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1307                                                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1308                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1309                                                         lower_32_bits(ring->gpu_addr));
1310                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1311                                                         upper_32_bits(ring->gpu_addr));
1312                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1313                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1314                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1315                                                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1316
1317                                 ring = &adev->vcn.inst->ring_dec;
1318                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1319                                                    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1320                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1321                                                    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1322                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1323                         }
1324                 } else {
1325                         /* unpause dpg jpeg, no need to wait */
1326                         reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1327                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1328                 }
1329                 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1330         }
1331
1332         return 0;
1333 }
1334
1335 static bool vcn_v1_0_is_idle(void *handle)
1336 {
1337         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1338
1339         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1340 }
1341
1342 static int vcn_v1_0_wait_for_idle(void *handle)
1343 {
1344         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1345         int ret;
1346
1347         ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1348                 UVD_STATUS__IDLE);
1349
1350         return ret;
1351 }
1352
1353 static int vcn_v1_0_set_clockgating_state(void *handle,
1354                                           enum amd_clockgating_state state)
1355 {
1356         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1357         bool enable = (state == AMD_CG_STATE_GATE);
1358
1359         if (enable) {
1360                 /* wait for STATUS to clear */
1361                 if (!vcn_v1_0_is_idle(handle))
1362                         return -EBUSY;
1363                 vcn_v1_0_enable_clock_gating(adev);
1364         } else {
1365                 /* disable HW gating and enable Sw gating */
1366                 vcn_v1_0_disable_clock_gating(adev);
1367         }
1368         return 0;
1369 }
1370
1371 /**
1372  * vcn_v1_0_dec_ring_get_rptr - get read pointer
1373  *
1374  * @ring: amdgpu_ring pointer
1375  *
1376  * Returns the current hardware read pointer
1377  */
1378 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1379 {
1380         struct amdgpu_device *adev = ring->adev;
1381
1382         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1383 }
1384
1385 /**
1386  * vcn_v1_0_dec_ring_get_wptr - get write pointer
1387  *
1388  * @ring: amdgpu_ring pointer
1389  *
1390  * Returns the current hardware write pointer
1391  */
1392 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1393 {
1394         struct amdgpu_device *adev = ring->adev;
1395
1396         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1397 }
1398
1399 /**
1400  * vcn_v1_0_dec_ring_set_wptr - set write pointer
1401  *
1402  * @ring: amdgpu_ring pointer
1403  *
1404  * Commits the write pointer to the hardware
1405  */
1406 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1407 {
1408         struct amdgpu_device *adev = ring->adev;
1409
1410         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1411                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1412                         lower_32_bits(ring->wptr) | 0x80000000);
1413
1414         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1415 }
1416
1417 /**
1418  * vcn_v1_0_dec_ring_insert_start - insert a start command
1419  *
1420  * @ring: amdgpu_ring pointer
1421  *
1422  * Write a start command to the ring.
1423  */
1424 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1425 {
1426         struct amdgpu_device *adev = ring->adev;
1427
1428         amdgpu_ring_write(ring,
1429                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1430         amdgpu_ring_write(ring, 0);
1431         amdgpu_ring_write(ring,
1432                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1433         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1434 }
1435
1436 /**
1437  * vcn_v1_0_dec_ring_insert_end - insert a end command
1438  *
1439  * @ring: amdgpu_ring pointer
1440  *
1441  * Write a end command to the ring.
1442  */
1443 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1444 {
1445         struct amdgpu_device *adev = ring->adev;
1446
1447         amdgpu_ring_write(ring,
1448                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1449         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1450 }
1451
1452 /**
1453  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1454  *
1455  * @ring: amdgpu_ring pointer
1456  * @addr: address
1457  * @seq: sequence number
1458  * @flags: fence related flags
1459  *
1460  * Write a fence and a trap command to the ring.
1461  */
1462 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1463                                      unsigned flags)
1464 {
1465         struct amdgpu_device *adev = ring->adev;
1466
1467         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1468
1469         amdgpu_ring_write(ring,
1470                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1471         amdgpu_ring_write(ring, seq);
1472         amdgpu_ring_write(ring,
1473                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1474         amdgpu_ring_write(ring, addr & 0xffffffff);
1475         amdgpu_ring_write(ring,
1476                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1477         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1478         amdgpu_ring_write(ring,
1479                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1480         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1481
1482         amdgpu_ring_write(ring,
1483                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1484         amdgpu_ring_write(ring, 0);
1485         amdgpu_ring_write(ring,
1486                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1487         amdgpu_ring_write(ring, 0);
1488         amdgpu_ring_write(ring,
1489                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1490         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1491 }
1492
1493 /**
1494  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1495  *
1496  * @ring: amdgpu_ring pointer
1497  * @job: job to retrieve vmid from
1498  * @ib: indirect buffer to execute
1499  * @flags: unused
1500  *
1501  * Write ring commands to execute the indirect buffer
1502  */
1503 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1504                                         struct amdgpu_job *job,
1505                                         struct amdgpu_ib *ib,
1506                                         uint32_t flags)
1507 {
1508         struct amdgpu_device *adev = ring->adev;
1509         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1510
1511         amdgpu_ring_write(ring,
1512                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1513         amdgpu_ring_write(ring, vmid);
1514
1515         amdgpu_ring_write(ring,
1516                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1517         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1518         amdgpu_ring_write(ring,
1519                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1520         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1521         amdgpu_ring_write(ring,
1522                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1523         amdgpu_ring_write(ring, ib->length_dw);
1524 }
1525
1526 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1527                                             uint32_t reg, uint32_t val,
1528                                             uint32_t mask)
1529 {
1530         struct amdgpu_device *adev = ring->adev;
1531
1532         amdgpu_ring_write(ring,
1533                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1534         amdgpu_ring_write(ring, reg << 2);
1535         amdgpu_ring_write(ring,
1536                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1537         amdgpu_ring_write(ring, val);
1538         amdgpu_ring_write(ring,
1539                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1540         amdgpu_ring_write(ring, mask);
1541         amdgpu_ring_write(ring,
1542                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1543         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1544 }
1545
1546 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1547                                             unsigned vmid, uint64_t pd_addr)
1548 {
1549         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1550         uint32_t data0, data1, mask;
1551
1552         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1553
1554         /* wait for register write */
1555         data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1556         data1 = lower_32_bits(pd_addr);
1557         mask = 0xffffffff;
1558         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1559 }
1560
1561 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1562                                         uint32_t reg, uint32_t val)
1563 {
1564         struct amdgpu_device *adev = ring->adev;
1565
1566         amdgpu_ring_write(ring,
1567                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1568         amdgpu_ring_write(ring, reg << 2);
1569         amdgpu_ring_write(ring,
1570                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1571         amdgpu_ring_write(ring, val);
1572         amdgpu_ring_write(ring,
1573                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1574         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1575 }
1576
1577 /**
1578  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1579  *
1580  * @ring: amdgpu_ring pointer
1581  *
1582  * Returns the current hardware enc read pointer
1583  */
1584 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1585 {
1586         struct amdgpu_device *adev = ring->adev;
1587
1588         if (ring == &adev->vcn.inst->ring_enc[0])
1589                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1590         else
1591                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1592 }
1593
1594  /**
1595  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1596  *
1597  * @ring: amdgpu_ring pointer
1598  *
1599  * Returns the current hardware enc write pointer
1600  */
1601 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1602 {
1603         struct amdgpu_device *adev = ring->adev;
1604
1605         if (ring == &adev->vcn.inst->ring_enc[0])
1606                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1607         else
1608                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1609 }
1610
1611  /**
1612  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1613  *
1614  * @ring: amdgpu_ring pointer
1615  *
1616  * Commits the enc write pointer to the hardware
1617  */
1618 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1619 {
1620         struct amdgpu_device *adev = ring->adev;
1621
1622         if (ring == &adev->vcn.inst->ring_enc[0])
1623                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1624                         lower_32_bits(ring->wptr));
1625         else
1626                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1627                         lower_32_bits(ring->wptr));
1628 }
1629
1630 /**
1631  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1632  *
1633  * @ring: amdgpu_ring pointer
1634  * @addr: address
1635  * @seq: sequence number
1636  * @flags: fence related flags
1637  *
1638  * Write enc a fence and a trap command to the ring.
1639  */
1640 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1641                         u64 seq, unsigned flags)
1642 {
1643         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1644
1645         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1646         amdgpu_ring_write(ring, addr);
1647         amdgpu_ring_write(ring, upper_32_bits(addr));
1648         amdgpu_ring_write(ring, seq);
1649         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1650 }
1651
1652 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1653 {
1654         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1655 }
1656
1657 /**
1658  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1659  *
1660  * @ring: amdgpu_ring pointer
1661  * @job: job to retrive vmid from
1662  * @ib: indirect buffer to execute
1663  * @flags: unused
1664  *
1665  * Write enc ring commands to execute the indirect buffer
1666  */
1667 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1668                                         struct amdgpu_job *job,
1669                                         struct amdgpu_ib *ib,
1670                                         uint32_t flags)
1671 {
1672         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1673
1674         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1675         amdgpu_ring_write(ring, vmid);
1676         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1677         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1678         amdgpu_ring_write(ring, ib->length_dw);
1679 }
1680
1681 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1682                                             uint32_t reg, uint32_t val,
1683                                             uint32_t mask)
1684 {
1685         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1686         amdgpu_ring_write(ring, reg << 2);
1687         amdgpu_ring_write(ring, mask);
1688         amdgpu_ring_write(ring, val);
1689 }
1690
1691 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1692                                             unsigned int vmid, uint64_t pd_addr)
1693 {
1694         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1695
1696         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1697
1698         /* wait for reg writes */
1699         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1700                                         vmid * hub->ctx_addr_distance,
1701                                         lower_32_bits(pd_addr), 0xffffffff);
1702 }
1703
1704 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1705                                         uint32_t reg, uint32_t val)
1706 {
1707         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1708         amdgpu_ring_write(ring, reg << 2);
1709         amdgpu_ring_write(ring, val);
1710 }
1711
1712 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1713                                         struct amdgpu_irq_src *source,
1714                                         unsigned type,
1715                                         enum amdgpu_interrupt_state state)
1716 {
1717         return 0;
1718 }
1719
1720 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1721                                       struct amdgpu_irq_src *source,
1722                                       struct amdgpu_iv_entry *entry)
1723 {
1724         DRM_DEBUG("IH: VCN TRAP\n");
1725
1726         switch (entry->src_id) {
1727         case 124:
1728                 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1729                 break;
1730         case 119:
1731                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1732                 break;
1733         case 120:
1734                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1735                 break;
1736         default:
1737                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1738                           entry->src_id, entry->src_data[0]);
1739                 break;
1740         }
1741
1742         return 0;
1743 }
1744
1745 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1746 {
1747         struct amdgpu_device *adev = ring->adev;
1748         int i;
1749
1750         WARN_ON(ring->wptr % 2 || count % 2);
1751
1752         for (i = 0; i < count / 2; i++) {
1753                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1754                 amdgpu_ring_write(ring, 0);
1755         }
1756 }
1757
1758 static int vcn_v1_0_set_powergating_state(void *handle,
1759                                           enum amd_powergating_state state)
1760 {
1761         /* This doesn't actually powergate the VCN block.
1762          * That's done in the dpm code via the SMC.  This
1763          * just re-inits the block as necessary.  The actual
1764          * gating still happens in the dpm code.  We should
1765          * revisit this when there is a cleaner line between
1766          * the smc and the hw blocks
1767          */
1768         int ret;
1769         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1770
1771         if(state == adev->vcn.cur_state)
1772                 return 0;
1773
1774         if (state == AMD_PG_STATE_GATE)
1775                 ret = vcn_v1_0_stop(adev);
1776         else
1777                 ret = vcn_v1_0_start(adev);
1778
1779         if(!ret)
1780                 adev->vcn.cur_state = state;
1781         return ret;
1782 }
1783
1784 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1785 {
1786         struct amdgpu_device *adev =
1787                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
1788         unsigned int fences = 0, i;
1789
1790         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1791                 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1792
1793         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1794                 struct dpg_pause_state new_state;
1795
1796                 if (fences)
1797                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1798                 else
1799                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1800
1801                 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1802                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1803                 else
1804                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1805
1806                 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1807         }
1808
1809         fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec);
1810         fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1811
1812         if (fences == 0) {
1813                 amdgpu_gfx_off_ctrl(adev, true);
1814                 if (adev->pm.dpm_enabled)
1815                         amdgpu_dpm_enable_uvd(adev, false);
1816                 else
1817                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1818                                AMD_PG_STATE_GATE);
1819         } else {
1820                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1821         }
1822 }
1823
1824 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1825 {
1826         struct  amdgpu_device *adev = ring->adev;
1827         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
1828
1829         mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
1830
1831         if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
1832                 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1833
1834         vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1835
1836 }
1837
1838 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1839 {
1840         struct amdgpu_device *adev = ring->adev;
1841
1842         if (set_clocks) {
1843                 amdgpu_gfx_off_ctrl(adev, false);
1844                 if (adev->pm.dpm_enabled)
1845                         amdgpu_dpm_enable_uvd(adev, true);
1846                 else
1847                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1848                                AMD_PG_STATE_UNGATE);
1849         }
1850
1851         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1852                 struct dpg_pause_state new_state;
1853                 unsigned int fences = 0, i;
1854
1855                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1856                         fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1857
1858                 if (fences)
1859                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1860                 else
1861                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1862
1863                 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1864                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1865                 else
1866                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1867
1868                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1869                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1870                 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1871                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1872
1873                 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1874         }
1875 }
1876
1877 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1878 {
1879         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1880         mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1881 }
1882
1883 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1884         .name = "vcn_v1_0",
1885         .early_init = vcn_v1_0_early_init,
1886         .late_init = NULL,
1887         .sw_init = vcn_v1_0_sw_init,
1888         .sw_fini = vcn_v1_0_sw_fini,
1889         .hw_init = vcn_v1_0_hw_init,
1890         .hw_fini = vcn_v1_0_hw_fini,
1891         .suspend = vcn_v1_0_suspend,
1892         .resume = vcn_v1_0_resume,
1893         .is_idle = vcn_v1_0_is_idle,
1894         .wait_for_idle = vcn_v1_0_wait_for_idle,
1895         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
1896         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
1897         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
1898         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
1899         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
1900         .set_powergating_state = vcn_v1_0_set_powergating_state,
1901 };
1902
1903 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
1904         .type = AMDGPU_RING_TYPE_VCN_DEC,
1905         .align_mask = 0xf,
1906         .support_64bit_ptrs = false,
1907         .no_user_fence = true,
1908         .secure_submission_supported = true,
1909         .vmhub = AMDGPU_MMHUB_0,
1910         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
1911         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
1912         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1913         .emit_frame_size =
1914                 6 + 6 + /* hdp invalidate / flush */
1915                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1916                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1917                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1918                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1919                 6,
1920         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
1921         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
1922         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
1923         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
1924         .test_ring = amdgpu_vcn_dec_ring_test_ring,
1925         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1926         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
1927         .insert_start = vcn_v1_0_dec_ring_insert_start,
1928         .insert_end = vcn_v1_0_dec_ring_insert_end,
1929         .pad_ib = amdgpu_ring_generic_pad_ib,
1930         .begin_use = vcn_v1_0_ring_begin_use,
1931         .end_use = vcn_v1_0_ring_end_use,
1932         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
1933         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1934         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1935 };
1936
1937 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
1938         .type = AMDGPU_RING_TYPE_VCN_ENC,
1939         .align_mask = 0x3f,
1940         .nop = VCN_ENC_CMD_NO_OP,
1941         .support_64bit_ptrs = false,
1942         .no_user_fence = true,
1943         .vmhub = AMDGPU_MMHUB_0,
1944         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
1945         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
1946         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
1947         .emit_frame_size =
1948                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1949                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1950                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
1951                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1952                 1, /* vcn_v1_0_enc_ring_insert_end */
1953         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
1954         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
1955         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
1956         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
1957         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1958         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1959         .insert_nop = amdgpu_ring_insert_nop,
1960         .insert_end = vcn_v1_0_enc_ring_insert_end,
1961         .pad_ib = amdgpu_ring_generic_pad_ib,
1962         .begin_use = vcn_v1_0_ring_begin_use,
1963         .end_use = vcn_v1_0_ring_end_use,
1964         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
1965         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1966         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1967 };
1968
1969 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1970 {
1971         adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
1972         DRM_INFO("VCN decode is enabled in VM mode\n");
1973 }
1974
1975 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1976 {
1977         int i;
1978
1979         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1980                 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
1981
1982         DRM_INFO("VCN encode is enabled in VM mode\n");
1983 }
1984
1985 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
1986         .set = vcn_v1_0_set_interrupt_state,
1987         .process = vcn_v1_0_process_interrupt,
1988 };
1989
1990 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
1991 {
1992         adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
1993         adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
1994 }
1995
1996 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
1997 {
1998                 .type = AMD_IP_BLOCK_TYPE_VCN,
1999                 .major = 1,
2000                 .minor = 0,
2001                 .rev = 0,
2002                 .funcs = &vcn_v1_0_ip_funcs,
2003 };