drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include <drm/amdgpu_drm.h>
  29
  30 #include "amdgpu.h"
  31 #include "amdgpu_atombios.h"
  32 #include "amdgpu_ih.h"
  33 #include "amdgpu_uvd.h"
  34 #include "amdgpu_vce.h"
  35 #include "amdgpu_ucode.h"
  36 #include "amdgpu_psp.h"
  37 #include "atom.h"
  38 #include "amd_pcie.h"
  39
  40 #include "gc/gc_10_1_0_offset.h"
  41 #include "gc/gc_10_1_0_sh_mask.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "amdgpu_vkms.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64 #include "smuio_v11_0.h"
  65 #include "smuio_v11_0_6.h"
  66
  67 static const struct amd_ip_funcs nv_common_ip_funcs;
  68
  69 /* Navi */
  70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =
  71 {
  72         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
  73         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
  74 };
  75
  76 static const struct amdgpu_video_codecs nv_video_codecs_encode =
  77 {
  78         .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array),
  79         .codec_array = nv_video_codecs_encode_array,
  80 };
  81
  82 /* Navi1x */
  83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =
  84 {
  85         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
  86         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
  87         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
  88         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
  89         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
  90         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
  91         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
  92 };
  93
  94 static const struct amdgpu_video_codecs nv_video_codecs_decode =
  95 {
  96         .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array),
  97         .codec_array = nv_video_codecs_decode_array,
  98 };
  99
 100 /* Sienna Cichlid */
 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =
 102 {
 103         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
 104         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
 105         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 106         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
 107         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 108         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 109         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 110         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 111 };
 112
 113 static const struct amdgpu_video_codecs sc_video_codecs_decode =
 114 {
 115         .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array),
 116         .codec_array = sc_video_codecs_decode_array,
 117 };
 118
 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */
 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =
 121 {
 122         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
 123         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
 124 };
 125
 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =
 127 {
 128         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},
 129         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},
 130         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 131         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},
 132         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 133         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 134         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 135         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
 136 };
 137
 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
 139 {
 140         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 141         .codec_array = sriov_sc_video_codecs_encode_array,
 142 };
 143
 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode =
 145 {
 146         .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array),
 147         .codec_array = sriov_sc_video_codecs_decode_array,
 148 };
 149
 150 /* Beige Goby*/
 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = {
 152         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 153         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 154         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 155 };
 156
 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = {
 158         .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array),
 159         .codec_array = bg_video_codecs_decode_array,
 160 };
 161
 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = {
 163         .codec_count = 0,
 164         .codec_array = NULL,
 165 };
 166
 167 /* Yellow Carp*/
 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {
 169         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},
 170         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
 171         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
 172         {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
 173 };
 174
 175 static const struct amdgpu_video_codecs yc_video_codecs_decode = {
 176         .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),
 177         .codec_array = yc_video_codecs_decode_array,
 178 };
 179
 180 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
 181                                  const struct amdgpu_video_codecs **codecs)
 182 {
 183         switch (adev->ip_versions[UVD_HWIP][0]) {
 184         case IP_VERSION(3, 0, 0):
 185         case IP_VERSION(3, 0, 64):
 186         case IP_VERSION(3, 0, 192):
 187                 if (amdgpu_sriov_vf(adev)) {
 188                         if (encode)
 189                                 *codecs = &sriov_sc_video_codecs_encode;
 190                         else
 191                                 *codecs = &sriov_sc_video_codecs_decode;
 192                 } else {
 193                         if (encode)
 194                                 *codecs = &nv_video_codecs_encode;
 195                         else
 196                                 *codecs = &sc_video_codecs_decode;
 197                 }
 198                 return 0;
 199         case IP_VERSION(3, 0, 16):
 200         case IP_VERSION(3, 0, 2):
 201                 if (encode)
 202                         *codecs = &nv_video_codecs_encode;
 203                 else
 204                         *codecs = &sc_video_codecs_decode;
 205                 return 0;
 206         case IP_VERSION(3, 1, 1):
 207         case IP_VERSION(3, 1, 2):
 208                 if (encode)
 209                         *codecs = &nv_video_codecs_encode;
 210                 else
 211                         *codecs = &yc_video_codecs_decode;
 212                 return 0;
 213         case IP_VERSION(3, 0, 33):
 214                 if (encode)
 215                         *codecs = &bg_video_codecs_encode;
 216                 else
 217                         *codecs = &bg_video_codecs_decode;
 218                 return 0;
 219         case IP_VERSION(2, 0, 0):
 220         case IP_VERSION(2, 0, 2):
 221                 if (encode)
 222                         *codecs = &nv_video_codecs_encode;
 223                 else
 224                         *codecs = &nv_video_codecs_decode;
 225                 return 0;
 226         default:
 227                 return -EINVAL;
 228         }
 229 }
 230
 231 /*
 232  * Indirect registers accessor
 233  */
 234 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 235 {
 236         unsigned long address, data;
 237         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 238         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 239
 240         return amdgpu_device_indirect_rreg(adev, address, data, reg);
 241 }
 242
 243 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 244 {
 245         unsigned long address, data;
 246
 247         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 248         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 249
 250         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 251 }
 252
 253 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 254 {
 255         unsigned long address, data;
 256         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 257         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 258
 259         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 260 }
 261
 262 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 263 {
 264         unsigned long address, data;
 265
 266         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 267         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 268
 269         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 270 }
 271
 272 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 273 {
 274         unsigned long flags, address, data;
 275         u32 r;
 276
 277         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 278         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 279
 280         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 281         WREG32(address, (reg));
 282         r = RREG32(data);
 283         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 284         return r;
 285 }
 286
 287 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 288 {
 289         unsigned long flags, address, data;
 290
 291         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 292         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 293
 294         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 295         WREG32(address, (reg));
 296         WREG32(data, (v));
 297         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 298 }
 299
 300 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 301 {
 302         return adev->nbio.funcs->get_memsize(adev);
 303 }
 304
 305 static u32 nv_get_xclk(struct amdgpu_device *adev)
 306 {
 307         return adev->clock.spll.reference_freq;
 308 }
 309
 310
 311 void nv_grbm_select(struct amdgpu_device *adev,
 312                      u32 me, u32 pipe, u32 queue, u32 vmid)
 313 {
 314         u32 grbm_gfx_cntl = 0;
 315         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 316         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 317         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 318         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 319
 320         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
 321 }
 322
 323 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 324 {
 325         /* todo */
 326 }
 327
 328 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 329 {
 330         /* todo */
 331         return false;
 332 }
 333
 334 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 335         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 336         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 337         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 338         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 339         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 340         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 341         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 342         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 343         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 344         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 345         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 346         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 347         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 348         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 349         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 350         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 351         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 352         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 353         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 354 };
 355
 356 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 357                                          u32 sh_num, u32 reg_offset)
 358 {
 359         uint32_t val;
 360
 361         mutex_lock(&adev->grbm_idx_mutex);
 362         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 363                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 364
 365         val = RREG32(reg_offset);
 366
 367         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 368                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 369         mutex_unlock(&adev->grbm_idx_mutex);
 370         return val;
 371 }
 372
 373 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 374                                       bool indexed, u32 se_num,
 375                                       u32 sh_num, u32 reg_offset)
 376 {
 377         if (indexed) {
 378                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 379         } else {
 380                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 381                         return adev->gfx.config.gb_addr_config;
 382                 return RREG32(reg_offset);
 383         }
 384 }
 385
 386 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 387                             u32 sh_num, u32 reg_offset, u32 *value)
 388 {
 389         uint32_t i;
 390         struct soc15_allowed_register_entry  *en;
 391
 392         *value = 0;
 393         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 394                 en = &nv_allowed_read_registers[i];
 395                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 396                     reg_offset !=
 397                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 398                         continue;
 399
 400                 *value = nv_get_register_value(adev,
 401                                                nv_allowed_read_registers[i].grbm_indexed,
 402                                                se_num, sh_num, reg_offset);
 403                 return 0;
 404         }
 405         return -EINVAL;
 406 }
 407
 408 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 409 {
 410         u32 i;
 411         int ret = 0;
 412
 413         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 414
 415         /* disable BM */
 416         pci_clear_master(adev->pdev);
 417
 418         amdgpu_device_cache_pci_state(adev->pdev);
 419
 420         ret = amdgpu_dpm_mode2_reset(adev);
 421         if (ret)
 422                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 423
 424         amdgpu_device_load_pci_state(adev->pdev);
 425
 426         /* wait for asic to come out of reset */
 427         for (i = 0; i < adev->usec_timeout; i++) {
 428                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 429
 430                 if (memsize != 0xffffffff)
 431                         break;
 432                 udelay(1);
 433         }
 434
 435         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 436
 437         return ret;
 438 }
 439
 440 static enum amd_reset_method
 441 nv_asic_reset_method(struct amdgpu_device *adev)
 442 {
 443         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 444             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 445             amdgpu_reset_method == AMD_RESET_METHOD_BACO ||
 446             amdgpu_reset_method == AMD_RESET_METHOD_PCI)
 447                 return amdgpu_reset_method;
 448
 449         if (amdgpu_reset_method != -1)
 450                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 451                                   amdgpu_reset_method);
 452
 453         switch (adev->ip_versions[MP1_HWIP][0]) {
 454         case IP_VERSION(11, 5, 0):
 455         case IP_VERSION(13, 0, 1):
 456         case IP_VERSION(13, 0, 3):
 457         case IP_VERSION(13, 0, 5):
 458         case IP_VERSION(13, 0, 8):
 459                 return AMD_RESET_METHOD_MODE2;
 460         case IP_VERSION(11, 0, 7):
 461         case IP_VERSION(11, 0, 11):
 462         case IP_VERSION(11, 0, 12):
 463         case IP_VERSION(11, 0, 13):
 464                 return AMD_RESET_METHOD_MODE1;
 465         default:
 466                 if (amdgpu_dpm_is_baco_supported(adev))
 467                         return AMD_RESET_METHOD_BACO;
 468                 else
 469                         return AMD_RESET_METHOD_MODE1;
 470         }
 471 }
 472
 473 static int nv_asic_reset(struct amdgpu_device *adev)
 474 {
 475         int ret = 0;
 476
 477         switch (nv_asic_reset_method(adev)) {
 478         case AMD_RESET_METHOD_PCI:
 479                 dev_info(adev->dev, "PCI reset\n");
 480                 ret = amdgpu_device_pci_reset(adev);
 481                 break;
 482         case AMD_RESET_METHOD_BACO:
 483                 dev_info(adev->dev, "BACO reset\n");
 484                 ret = amdgpu_dpm_baco_reset(adev);
 485                 break;
 486         case AMD_RESET_METHOD_MODE2:
 487                 dev_info(adev->dev, "MODE2 reset\n");
 488                 ret = nv_asic_mode2_reset(adev);
 489                 break;
 490         default:
 491                 dev_info(adev->dev, "MODE1 reset\n");
 492                 ret = amdgpu_device_mode1_reset(adev);
 493                 break;
 494         }
 495
 496         return ret;
 497 }
 498
 499 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 500 {
 501         /* todo */
 502         return 0;
 503 }
 504
 505 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 506 {
 507         /* todo */
 508         return 0;
 509 }
 510
 511 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 512 {
 513         if (pci_is_root_bus(adev->pdev->bus))
 514                 return;
 515
 516         if (amdgpu_pcie_gen2 == 0)
 517                 return;
 518
 519         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 520                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 521                 return;
 522
 523         /* todo */
 524 }
 525
 526 static void nv_program_aspm(struct amdgpu_device *adev)
 527 {
 528         if (!amdgpu_device_should_use_aspm(adev))
 529                 return;
 530
 531         if (!(adev->flags & AMD_IS_APU) &&
 532             (adev->nbio.funcs->program_aspm))
 533                 adev->nbio.funcs->program_aspm(adev);
 534
 535 }
 536
 537 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 538                                         bool enable)
 539 {
 540         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 541         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 542 }
 543
 544 const struct amdgpu_ip_block_version nv_common_ip_block =
 545 {
 546         .type = AMD_IP_BLOCK_TYPE_COMMON,
 547         .major = 1,
 548         .minor = 0,
 549         .rev = 0,
 550         .funcs = &nv_common_ip_funcs,
 551 };
 552
 553 void nv_set_virt_ops(struct amdgpu_device *adev)
 554 {
 555         adev->virt.ops = &xgpu_nv_virt_ops;
 556 }
 557
 558 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 559 {
 560         return adev->nbio.funcs->get_rev_id(adev);
 561 }
 562
 563 static bool nv_need_full_reset(struct amdgpu_device *adev)
 564 {
 565         return true;
 566 }
 567
 568 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 569 {
 570         u32 sol_reg;
 571
 572         if (adev->flags & AMD_IS_APU)
 573                 return false;
 574
 575         /* Check sOS sign of life register to confirm sys driver and sOS
 576          * are already been loaded.
 577          */
 578         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 579         if (sol_reg)
 580                 return true;
 581
 582         return false;
 583 }
 584
 585 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 586 {
 587
 588         /* TODO
 589          * dummy implement for pcie_replay_count sysfs interface
 590          * */
 591
 592         return 0;
 593 }
 594
 595 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 596 {
 597         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 598         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 599         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 600         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 601         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 602         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 603         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 604         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 605         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 606         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 607         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 608         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 609         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 610         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 611         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 612         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 613         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 614         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 615         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 616         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 617         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 618         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 619         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 620         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 621         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 622
 623         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 624         adev->doorbell_index.sdma_doorbell_range = 20;
 625 }
 626
 627 static void nv_pre_asic_init(struct amdgpu_device *adev)
 628 {
 629 }
 630
 631 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 632                                        bool enter)
 633 {
 634         if (enter)
 635                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 636         else
 637                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 638
 639         if (adev->gfx.funcs->update_perfmon_mgcg)
 640                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 641
 642         if (!(adev->flags & AMD_IS_APU) &&
 643             (adev->nbio.funcs->enable_aspm) &&
 644              amdgpu_device_should_use_aspm(adev))
 645                 adev->nbio.funcs->enable_aspm(adev, !enter);
 646
 647         return 0;
 648 }
 649
 650 static const struct amdgpu_asic_funcs nv_asic_funcs =
 651 {
 652         .read_disabled_bios = &nv_read_disabled_bios,
 653         .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
 654         .read_register = &nv_read_register,
 655         .reset = &nv_asic_reset,
 656         .reset_method = &nv_asic_reset_method,
 657         .set_vga_state = &nv_vga_set_state,
 658         .get_xclk = &nv_get_xclk,
 659         .set_uvd_clocks = &nv_set_uvd_clocks,
 660         .set_vce_clocks = &nv_set_vce_clocks,
 661         .get_config_memsize = &nv_get_config_memsize,
 662         .init_doorbell_index = &nv_init_doorbell_index,
 663         .need_full_reset = &nv_need_full_reset,
 664         .need_reset_on_init = &nv_need_reset_on_init,
 665         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 666         .supports_baco = &amdgpu_dpm_is_baco_supported,
 667         .pre_asic_init = &nv_pre_asic_init,
 668         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 669         .query_video_codecs = &nv_query_video_codecs,
 670 };
 671
 672 static int nv_common_early_init(void *handle)
 673 {
 674 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 675         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 676
 677         if (!amdgpu_sriov_vf(adev)) {
 678                 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 679                 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 680         }
 681         adev->smc_rreg = NULL;
 682         adev->smc_wreg = NULL;
 683         adev->pcie_rreg = &nv_pcie_rreg;
 684         adev->pcie_wreg = &nv_pcie_wreg;
 685         adev->pcie_rreg64 = &nv_pcie_rreg64;
 686         adev->pcie_wreg64 = &nv_pcie_wreg64;
 687         adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
 688         adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
 689
 690         /* TODO: will add them during VCN v2 implementation */
 691         adev->uvd_ctx_rreg = NULL;
 692         adev->uvd_ctx_wreg = NULL;
 693
 694         adev->didt_rreg = &nv_didt_rreg;
 695         adev->didt_wreg = &nv_didt_wreg;
 696
 697         adev->asic_funcs = &nv_asic_funcs;
 698
 699         adev->rev_id = nv_get_rev_id(adev);
 700         adev->external_rev_id = 0xff;
 701         /* TODO: split the GC and PG flags based on the relevant IP version for which
 702          * they are relevant.
 703          */
 704         switch (adev->ip_versions[GC_HWIP][0]) {
 705         case IP_VERSION(10, 1, 10):
 706                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 707                         AMD_CG_SUPPORT_GFX_CGCG |
 708                         AMD_CG_SUPPORT_IH_CG |
 709                         AMD_CG_SUPPORT_HDP_MGCG |
 710                         AMD_CG_SUPPORT_HDP_LS |
 711                         AMD_CG_SUPPORT_SDMA_MGCG |
 712                         AMD_CG_SUPPORT_SDMA_LS |
 713                         AMD_CG_SUPPORT_MC_MGCG |
 714                         AMD_CG_SUPPORT_MC_LS |
 715                         AMD_CG_SUPPORT_ATHUB_MGCG |
 716                         AMD_CG_SUPPORT_ATHUB_LS |
 717                         AMD_CG_SUPPORT_VCN_MGCG |
 718                         AMD_CG_SUPPORT_JPEG_MGCG |
 719                         AMD_CG_SUPPORT_BIF_MGCG |
 720                         AMD_CG_SUPPORT_BIF_LS;
 721                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 722                         AMD_PG_SUPPORT_VCN_DPG |
 723                         AMD_PG_SUPPORT_JPEG |
 724                         AMD_PG_SUPPORT_ATHUB;
 725                 adev->external_rev_id = adev->rev_id + 0x1;
 726                 break;
 727         case IP_VERSION(10, 1, 1):
 728                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 729                         AMD_CG_SUPPORT_GFX_CGCG |
 730                         AMD_CG_SUPPORT_IH_CG |
 731                         AMD_CG_SUPPORT_HDP_MGCG |
 732                         AMD_CG_SUPPORT_HDP_LS |
 733                         AMD_CG_SUPPORT_SDMA_MGCG |
 734                         AMD_CG_SUPPORT_SDMA_LS |
 735                         AMD_CG_SUPPORT_MC_MGCG |
 736                         AMD_CG_SUPPORT_MC_LS |
 737                         AMD_CG_SUPPORT_ATHUB_MGCG |
 738                         AMD_CG_SUPPORT_ATHUB_LS |
 739                         AMD_CG_SUPPORT_VCN_MGCG |
 740                         AMD_CG_SUPPORT_JPEG_MGCG |
 741                         AMD_CG_SUPPORT_BIF_MGCG |
 742                         AMD_CG_SUPPORT_BIF_LS;
 743                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 744                         AMD_PG_SUPPORT_JPEG |
 745                         AMD_PG_SUPPORT_VCN_DPG;
 746                 adev->external_rev_id = adev->rev_id + 20;
 747                 break;
 748         case IP_VERSION(10, 1, 2):
 749                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 750                         AMD_CG_SUPPORT_GFX_MGLS |
 751                         AMD_CG_SUPPORT_GFX_CGCG |
 752                         AMD_CG_SUPPORT_GFX_CP_LS |
 753                         AMD_CG_SUPPORT_GFX_RLC_LS |
 754                         AMD_CG_SUPPORT_IH_CG |
 755                         AMD_CG_SUPPORT_HDP_MGCG |
 756                         AMD_CG_SUPPORT_HDP_LS |
 757                         AMD_CG_SUPPORT_SDMA_MGCG |
 758                         AMD_CG_SUPPORT_SDMA_LS |
 759                         AMD_CG_SUPPORT_MC_MGCG |
 760                         AMD_CG_SUPPORT_MC_LS |
 761                         AMD_CG_SUPPORT_ATHUB_MGCG |
 762                         AMD_CG_SUPPORT_ATHUB_LS |
 763                         AMD_CG_SUPPORT_VCN_MGCG |
 764                         AMD_CG_SUPPORT_JPEG_MGCG;
 765                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 766                         AMD_PG_SUPPORT_VCN_DPG |
 767                         AMD_PG_SUPPORT_JPEG |
 768                         AMD_PG_SUPPORT_ATHUB;
 769                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 770                  * as a consequence, the rev_id and external_rev_id are wrong.
 771                  * workaround it by hardcoding rev_id to 0 (default value).
 772                  */
 773                 if (amdgpu_sriov_vf(adev))
 774                         adev->rev_id = 0;
 775                 adev->external_rev_id = adev->rev_id + 0xa;
 776                 break;
 777         case IP_VERSION(10, 3, 0):
 778                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 779                         AMD_CG_SUPPORT_GFX_CGCG |
 780                         AMD_CG_SUPPORT_GFX_CGLS |
 781                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 782                         AMD_CG_SUPPORT_MC_MGCG |
 783                         AMD_CG_SUPPORT_VCN_MGCG |
 784                         AMD_CG_SUPPORT_JPEG_MGCG |
 785                         AMD_CG_SUPPORT_HDP_MGCG |
 786                         AMD_CG_SUPPORT_HDP_LS |
 787                         AMD_CG_SUPPORT_IH_CG |
 788                         AMD_CG_SUPPORT_MC_LS;
 789                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 790                         AMD_PG_SUPPORT_VCN_DPG |
 791                         AMD_PG_SUPPORT_JPEG |
 792                         AMD_PG_SUPPORT_ATHUB |
 793                         AMD_PG_SUPPORT_MMHUB;
 794                 if (amdgpu_sriov_vf(adev)) {
 795                         /* hypervisor control CG and PG enablement */
 796                         adev->cg_flags = 0;
 797                         adev->pg_flags = 0;
 798                 }
 799                 adev->external_rev_id = adev->rev_id + 0x28;
 800                 break;
 801         case IP_VERSION(10, 3, 2):
 802                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 803                         AMD_CG_SUPPORT_GFX_CGCG |
 804                         AMD_CG_SUPPORT_GFX_CGLS |
 805                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 806                         AMD_CG_SUPPORT_VCN_MGCG |
 807                         AMD_CG_SUPPORT_JPEG_MGCG |
 808                         AMD_CG_SUPPORT_MC_MGCG |
 809                         AMD_CG_SUPPORT_MC_LS |
 810                         AMD_CG_SUPPORT_HDP_MGCG |
 811                         AMD_CG_SUPPORT_HDP_LS |
 812                         AMD_CG_SUPPORT_IH_CG;
 813                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 814                         AMD_PG_SUPPORT_VCN_DPG |
 815                         AMD_PG_SUPPORT_JPEG |
 816                         AMD_PG_SUPPORT_ATHUB |
 817                         AMD_PG_SUPPORT_MMHUB;
 818                 adev->external_rev_id = adev->rev_id + 0x32;
 819                 break;
 820         case IP_VERSION(10, 3, 1):
 821                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 822                         AMD_CG_SUPPORT_GFX_MGLS |
 823                         AMD_CG_SUPPORT_GFX_CP_LS |
 824                         AMD_CG_SUPPORT_GFX_RLC_LS |
 825                         AMD_CG_SUPPORT_GFX_CGCG |
 826                         AMD_CG_SUPPORT_GFX_CGLS |
 827                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 828                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 829                         AMD_CG_SUPPORT_MC_MGCG |
 830                         AMD_CG_SUPPORT_MC_LS |
 831                         AMD_CG_SUPPORT_GFX_FGCG |
 832                         AMD_CG_SUPPORT_VCN_MGCG |
 833                         AMD_CG_SUPPORT_SDMA_MGCG |
 834                         AMD_CG_SUPPORT_SDMA_LS |
 835                         AMD_CG_SUPPORT_JPEG_MGCG;
 836                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 837                         AMD_PG_SUPPORT_VCN |
 838                         AMD_PG_SUPPORT_VCN_DPG |
 839                         AMD_PG_SUPPORT_JPEG;
 840                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
 841                         adev->external_rev_id = adev->rev_id + 0x01;
 842                 break;
 843         case IP_VERSION(10, 3, 4):
 844                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 845                         AMD_CG_SUPPORT_GFX_CGCG |
 846                         AMD_CG_SUPPORT_GFX_CGLS |
 847                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 848                         AMD_CG_SUPPORT_VCN_MGCG |
 849                         AMD_CG_SUPPORT_JPEG_MGCG |
 850                         AMD_CG_SUPPORT_MC_MGCG |
 851                         AMD_CG_SUPPORT_MC_LS |
 852                         AMD_CG_SUPPORT_HDP_MGCG |
 853                         AMD_CG_SUPPORT_HDP_LS |
 854                         AMD_CG_SUPPORT_IH_CG;
 855                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 856                         AMD_PG_SUPPORT_VCN_DPG |
 857                         AMD_PG_SUPPORT_JPEG |
 858                         AMD_PG_SUPPORT_ATHUB |
 859                         AMD_PG_SUPPORT_MMHUB;
 860                 adev->external_rev_id = adev->rev_id + 0x3c;
 861                 break;
 862         case IP_VERSION(10, 3, 5):
 863                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 864                         AMD_CG_SUPPORT_GFX_CGCG |
 865                         AMD_CG_SUPPORT_GFX_CGLS |
 866                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 867                         AMD_CG_SUPPORT_MC_MGCG |
 868                         AMD_CG_SUPPORT_MC_LS |
 869                         AMD_CG_SUPPORT_HDP_MGCG |
 870                         AMD_CG_SUPPORT_HDP_LS |
 871                         AMD_CG_SUPPORT_IH_CG |
 872                         AMD_CG_SUPPORT_VCN_MGCG;
 873                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 874                         AMD_PG_SUPPORT_VCN_DPG |
 875                         AMD_PG_SUPPORT_ATHUB |
 876                         AMD_PG_SUPPORT_MMHUB;
 877                 adev->external_rev_id = adev->rev_id + 0x46;
 878                 break;
 879         case IP_VERSION(10, 3, 3):
 880                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 881                         AMD_CG_SUPPORT_GFX_MGLS |
 882                         AMD_CG_SUPPORT_GFX_CGCG |
 883                         AMD_CG_SUPPORT_GFX_CGLS |
 884                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 885                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 886                         AMD_CG_SUPPORT_GFX_RLC_LS |
 887                         AMD_CG_SUPPORT_GFX_CP_LS |
 888                         AMD_CG_SUPPORT_GFX_FGCG |
 889                         AMD_CG_SUPPORT_MC_MGCG |
 890                         AMD_CG_SUPPORT_MC_LS |
 891                         AMD_CG_SUPPORT_SDMA_LS |
 892                         AMD_CG_SUPPORT_HDP_MGCG |
 893                         AMD_CG_SUPPORT_HDP_LS |
 894                         AMD_CG_SUPPORT_ATHUB_MGCG |
 895                         AMD_CG_SUPPORT_ATHUB_LS |
 896                         AMD_CG_SUPPORT_IH_CG |
 897                         AMD_CG_SUPPORT_VCN_MGCG |
 898                         AMD_CG_SUPPORT_JPEG_MGCG;
 899                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 900                         AMD_PG_SUPPORT_VCN |
 901                         AMD_PG_SUPPORT_VCN_DPG |
 902                         AMD_PG_SUPPORT_JPEG;
 903                 if (adev->pdev->device == 0x1681)
 904                         adev->external_rev_id = 0x20;
 905                 else
 906                         adev->external_rev_id = adev->rev_id + 0x01;
 907                 break;
 908         case IP_VERSION(10, 1, 3):
 909         case IP_VERSION(10, 1, 4):
 910                 adev->cg_flags = 0;
 911                 adev->pg_flags = 0;
 912                 adev->external_rev_id = adev->rev_id + 0x82;
 913                 break;
 914         case IP_VERSION(10, 3, 6):
 915                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 916                         AMD_CG_SUPPORT_GFX_MGLS |
 917                         AMD_CG_SUPPORT_GFX_CGCG |
 918                         AMD_CG_SUPPORT_GFX_CGLS |
 919                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 920                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 921                         AMD_CG_SUPPORT_GFX_RLC_LS |
 922                         AMD_CG_SUPPORT_GFX_CP_LS |
 923                         AMD_CG_SUPPORT_GFX_FGCG |
 924                         AMD_CG_SUPPORT_MC_MGCG |
 925                         AMD_CG_SUPPORT_MC_LS |
 926                         AMD_CG_SUPPORT_SDMA_LS |
 927                         AMD_CG_SUPPORT_HDP_MGCG |
 928                         AMD_CG_SUPPORT_HDP_LS |
 929                         AMD_CG_SUPPORT_ATHUB_MGCG |
 930                         AMD_CG_SUPPORT_ATHUB_LS |
 931                         AMD_CG_SUPPORT_IH_CG |
 932                         AMD_CG_SUPPORT_VCN_MGCG |
 933                         AMD_CG_SUPPORT_JPEG_MGCG;
 934                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 935                         AMD_PG_SUPPORT_VCN |
 936                         AMD_PG_SUPPORT_VCN_DPG |
 937                         AMD_PG_SUPPORT_JPEG;
 938                 adev->external_rev_id = adev->rev_id + 0x01;
 939                 break;
 940         case IP_VERSION(10, 3, 7):
 941                 adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
 942                         AMD_CG_SUPPORT_GFX_MGLS |
 943                         AMD_CG_SUPPORT_GFX_CGCG |
 944                         AMD_CG_SUPPORT_GFX_CGLS |
 945                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 946                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 947                         AMD_CG_SUPPORT_GFX_RLC_LS |
 948                         AMD_CG_SUPPORT_GFX_CP_LS |
 949                         AMD_CG_SUPPORT_GFX_FGCG |
 950                         AMD_CG_SUPPORT_MC_MGCG |
 951                         AMD_CG_SUPPORT_MC_LS |
 952                         AMD_CG_SUPPORT_SDMA_LS |
 953                         AMD_CG_SUPPORT_HDP_MGCG |
 954                         AMD_CG_SUPPORT_HDP_LS |
 955                         AMD_CG_SUPPORT_ATHUB_MGCG |
 956                         AMD_CG_SUPPORT_ATHUB_LS |
 957                         AMD_CG_SUPPORT_IH_CG |
 958                         AMD_CG_SUPPORT_VCN_MGCG |
 959                         AMD_CG_SUPPORT_JPEG_MGCG;
 960                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 961                         AMD_PG_SUPPORT_VCN_DPG |
 962                         AMD_PG_SUPPORT_JPEG |
 963                         AMD_PG_SUPPORT_GFX_PG;
 964                 adev->external_rev_id = adev->rev_id + 0x01;
 965                 break;
 966         default:
 967                 /* FIXME: not supported yet */
 968                 return -EINVAL;
 969         }
 970
 971         if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
 972                 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
 973                                     AMD_PG_SUPPORT_VCN_DPG |
 974                                     AMD_PG_SUPPORT_JPEG);
 975
 976         if (amdgpu_sriov_vf(adev)) {
 977                 amdgpu_virt_init_setting(adev);
 978                 xgpu_nv_mailbox_set_irq_funcs(adev);
 979         }
 980
 981         return 0;
 982 }
 983
 984 static int nv_common_late_init(void *handle)
 985 {
 986         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 987
 988         if (amdgpu_sriov_vf(adev)) {
 989                 xgpu_nv_mailbox_get_irq(adev);
 990                 amdgpu_virt_update_sriov_video_codec(adev,
 991                                 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array),
 992                                 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array));
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int nv_common_sw_init(void *handle)
 999 {
1000         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1001
1002         if (amdgpu_sriov_vf(adev))
1003                 xgpu_nv_mailbox_add_irq_id(adev);
1004
1005         return 0;
1006 }
1007
1008 static int nv_common_sw_fini(void *handle)
1009 {
1010         return 0;
1011 }
1012
1013 static int nv_common_hw_init(void *handle)
1014 {
1015         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1016
1017         if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1018                 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1019
1020         if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1021                 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1022
1023         /* enable pcie gen2/3 link */
1024         nv_pcie_gen3_enable(adev);
1025         /* enable aspm */
1026         nv_program_aspm(adev);
1027         /* setup nbio registers */
1028         adev->nbio.funcs->init_registers(adev);
1029         /* remap HDP registers to a hole in mmio space,
1030          * for the purpose of expose those registers
1031          * to process space
1032          */
1033         if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1034                 adev->nbio.funcs->remap_hdp_registers(adev);
1035         /* enable the doorbell aperture */
1036         nv_enable_doorbell_aperture(adev, true);
1037
1038         return 0;
1039 }
1040
1041 static int nv_common_hw_fini(void *handle)
1042 {
1043         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1044
1045         /* disable the doorbell aperture */
1046         nv_enable_doorbell_aperture(adev, false);
1047
1048         return 0;
1049 }
1050
1051 static int nv_common_suspend(void *handle)
1052 {
1053         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1054
1055         return nv_common_hw_fini(adev);
1056 }
1057
1058 static int nv_common_resume(void *handle)
1059 {
1060         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1061
1062         return nv_common_hw_init(adev);
1063 }
1064
1065 static bool nv_common_is_idle(void *handle)
1066 {
1067         return true;
1068 }
1069
1070 static int nv_common_wait_for_idle(void *handle)
1071 {
1072         return 0;
1073 }
1074
1075 static int nv_common_soft_reset(void *handle)
1076 {
1077         return 0;
1078 }
1079
1080 static int nv_common_set_clockgating_state(void *handle,
1081                                            enum amd_clockgating_state state)
1082 {
1083         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1084
1085         if (amdgpu_sriov_vf(adev))
1086                 return 0;
1087
1088         switch (adev->ip_versions[NBIO_HWIP][0]) {
1089         case IP_VERSION(2, 3, 0):
1090         case IP_VERSION(2, 3, 1):
1091         case IP_VERSION(2, 3, 2):
1092         case IP_VERSION(3, 3, 0):
1093         case IP_VERSION(3, 3, 1):
1094         case IP_VERSION(3, 3, 2):
1095         case IP_VERSION(3, 3, 3):
1096                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1097                                 state == AMD_CG_STATE_GATE);
1098                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1099                                 state == AMD_CG_STATE_GATE);
1100                 adev->hdp.funcs->update_clock_gating(adev,
1101                                 state == AMD_CG_STATE_GATE);
1102                 adev->smuio.funcs->update_rom_clock_gating(adev,
1103                                 state == AMD_CG_STATE_GATE);
1104                 break;
1105         default:
1106                 break;
1107         }
1108         return 0;
1109 }
1110
1111 static int nv_common_set_powergating_state(void *handle,
1112                                            enum amd_powergating_state state)
1113 {
1114         /* TODO */
1115         return 0;
1116 }
1117
1118 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1119 {
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122         if (amdgpu_sriov_vf(adev))
1123                 *flags = 0;
1124
1125         adev->nbio.funcs->get_clockgating_state(adev, flags);
1126
1127         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1128
1129         adev->smuio.funcs->get_clock_gating_state(adev, flags);
1130
1131         return;
1132 }
1133
1134 static const struct amd_ip_funcs nv_common_ip_funcs = {
1135         .name = "nv_common",
1136         .early_init = nv_common_early_init,
1137         .late_init = nv_common_late_init,
1138         .sw_init = nv_common_sw_init,
1139         .sw_fini = nv_common_sw_fini,
1140         .hw_init = nv_common_hw_init,
1141         .hw_fini = nv_common_hw_fini,
1142         .suspend = nv_common_suspend,
1143         .resume = nv_common_resume,
1144         .is_idle = nv_common_is_idle,
1145         .wait_for_idle = nv_common_wait_for_idle,
1146         .soft_reset = nv_common_soft_reset,
1147         .set_clockgating_state = nv_common_set_clockgating_state,
1148         .set_powergating_state = nv_common_set_powergating_state,
1149         .get_clockgating_state = nv_common_get_clockgating_state,
1150 };