drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  */
  36
  37 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
  38 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  39
  40 #define I915_CSR_CNL "i915/cnl_dmc_ver1_07.bin"
  41 MODULE_FIRMWARE(I915_CSR_CNL);
  42 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  43
  44 #define I915_CSR_KBL "i915/kbl_dmc_ver1_04.bin"
  45 MODULE_FIRMWARE(I915_CSR_KBL);
  46 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  47
  48 #define I915_CSR_SKL "i915/skl_dmc_ver1_27.bin"
  49 MODULE_FIRMWARE(I915_CSR_SKL);
  50 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 27)
  51
  52 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin"
  53 MODULE_FIRMWARE(I915_CSR_BXT);
  54 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  55
  56
  57 #define CSR_MAX_FW_SIZE                 0x2FFF
  58 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  59
  60 struct intel_css_header {
  61         /* 0x09 for DMC */
  62         uint32_t module_type;
  63
  64         /* Includes the DMC specific header in dwords */
  65         uint32_t header_len;
  66
  67         /* always value would be 0x10000 */
  68         uint32_t header_ver;
  69
  70         /* Not used */
  71         uint32_t module_id;
  72
  73         /* Not used */
  74         uint32_t module_vendor;
  75
  76         /* in YYYYMMDD format */
  77         uint32_t date;
  78
  79         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  80         uint32_t size;
  81
  82         /* Not used */
  83         uint32_t key_size;
  84
  85         /* Not used */
  86         uint32_t modulus_size;
  87
  88         /* Not used */
  89         uint32_t exponent_size;
  90
  91         /* Not used */
  92         uint32_t reserved1[12];
  93
  94         /* Major Minor */
  95         uint32_t version;
  96
  97         /* Not used */
  98         uint32_t reserved2[8];
  99
 100         /* Not used */
 101         uint32_t kernel_header_info;
 102 } __packed;
 103
 104 struct intel_fw_info {
 105         uint16_t reserved1;
 106
 107         /* Stepping (A, B, C, ..., *). * is a wildcard */
 108         char stepping;
 109
 110         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 111         char substepping;
 112
 113         uint32_t offset;
 114         uint32_t reserved2;
 115 } __packed;
 116
 117 struct intel_package_header {
 118         /* DMC container header length in dwords */
 119         unsigned char header_len;
 120
 121         /* always value would be 0x01 */
 122         unsigned char header_ver;
 123
 124         unsigned char reserved[10];
 125
 126         /* Number of valid entries in the FWInfo array below */
 127         uint32_t num_entries;
 128
 129         struct intel_fw_info fw_info[20];
 130 } __packed;
 131
 132 struct intel_dmc_header {
 133         /* always value would be 0x40403E3E */
 134         uint32_t signature;
 135
 136         /* DMC binary header length */
 137         unsigned char header_len;
 138
 139         /* 0x01 */
 140         unsigned char header_ver;
 141
 142         /* Reserved */
 143         uint16_t dmcc_ver;
 144
 145         /* Major, Minor */
 146         uint32_t        project;
 147
 148         /* Firmware program size (excluding header) in dwords */
 149         uint32_t        fw_size;
 150
 151         /* Major Minor version */
 152         uint32_t fw_version;
 153
 154         /* Number of valid MMIO cycles present. */
 155         uint32_t mmio_count;
 156
 157         /* MMIO address */
 158         uint32_t mmioaddr[8];
 159
 160         /* MMIO data */
 161         uint32_t mmiodata[8];
 162
 163         /* FW filename  */
 164         unsigned char dfile[32];
 165
 166         uint32_t reserved1[2];
 167 } __packed;
 168
 169 struct stepping_info {
 170         char stepping;
 171         char substepping;
 172 };
 173
 174 static const struct stepping_info skl_stepping_info[] = {
 175         {'A', '0'}, {'B', '0'}, {'C', '0'},
 176         {'D', '0'}, {'E', '0'}, {'F', '0'},
 177         {'G', '0'}, {'H', '0'}, {'I', '0'},
 178         {'J', '0'}, {'K', '0'}
 179 };
 180
 181 static const struct stepping_info bxt_stepping_info[] = {
 182         {'A', '0'}, {'A', '1'}, {'A', '2'},
 183         {'B', '0'}, {'B', '1'}, {'B', '2'}
 184 };
 185
 186 static const struct stepping_info no_stepping_info = { '*', '*' };
 187
 188 static const struct stepping_info *
 189 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 190 {
 191         const struct stepping_info *si;
 192         unsigned int size;
 193
 194         if (IS_SKYLAKE(dev_priv)) {
 195                 size = ARRAY_SIZE(skl_stepping_info);
 196                 si = skl_stepping_info;
 197         } else if (IS_BROXTON(dev_priv)) {
 198                 size = ARRAY_SIZE(bxt_stepping_info);
 199                 si = bxt_stepping_info;
 200         } else {
 201                 size = 0;
 202                 si = NULL;
 203         }
 204
 205         if (INTEL_REVID(dev_priv) < size)
 206                 return si + INTEL_REVID(dev_priv);
 207
 208         return &no_stepping_info;
 209 }
 210
 211 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 212 {
 213         uint32_t val, mask;
 214
 215         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 216
 217         if (IS_GEN9_LP(dev_priv))
 218                 mask |= DC_STATE_DEBUG_MASK_CORES;
 219
 220         /* The below bit doesn't need to be cleared ever afterwards */
 221         val = I915_READ(DC_STATE_DEBUG);
 222         if ((val & mask) != mask) {
 223                 val |= mask;
 224                 I915_WRITE(DC_STATE_DEBUG, val);
 225                 POSTING_READ(DC_STATE_DEBUG);
 226         }
 227 }
 228
 229 /**
 230  * intel_csr_load_program() - write the firmware from memory to register.
 231  * @dev_priv: i915 drm device.
 232  *
 233  * CSR firmware is read from a .bin file and kept in internal memory one time.
 234  * Everytime display comes back from low power state this function is called to
 235  * copy the firmware from internal memory to registers.
 236  */
 237 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 238 {
 239         u32 *payload = dev_priv->csr.dmc_payload;
 240         uint32_t i, fw_size;
 241
 242         if (!HAS_CSR(dev_priv)) {
 243                 DRM_ERROR("No CSR support available for this platform\n");
 244                 return;
 245         }
 246
 247         if (!dev_priv->csr.dmc_payload) {
 248                 DRM_ERROR("Tried to program CSR with empty payload\n");
 249                 return;
 250         }
 251
 252         fw_size = dev_priv->csr.dmc_fw_size;
 253         assert_rpm_wakelock_held(dev_priv);
 254
 255         preempt_disable();
 256
 257         for (i = 0; i < fw_size; i++)
 258                 I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
 259
 260         preempt_enable();
 261
 262         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 263                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 264                            dev_priv->csr.mmiodata[i]);
 265         }
 266
 267         dev_priv->csr.dc_state = 0;
 268
 269         gen9_set_dc_state_debugmask(dev_priv);
 270 }
 271
 272 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 273                               const struct firmware *fw)
 274 {
 275         struct intel_css_header *css_header;
 276         struct intel_package_header *package_header;
 277         struct intel_dmc_header *dmc_header;
 278         struct intel_csr *csr = &dev_priv->csr;
 279         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 280         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 281         uint32_t i;
 282         uint32_t *dmc_payload;
 283         uint32_t required_version;
 284
 285         if (!fw)
 286                 return NULL;
 287
 288         /* Extract CSS Header information*/
 289         css_header = (struct intel_css_header *)fw->data;
 290         if (sizeof(struct intel_css_header) !=
 291             (css_header->header_len * 4)) {
 292                 DRM_ERROR("DMC firmware has wrong CSS header length "
 293                           "(%u bytes)\n",
 294                           (css_header->header_len * 4));
 295                 return NULL;
 296         }
 297
 298         csr->version = css_header->version;
 299
 300         if (IS_CANNONLAKE(dev_priv)) {
 301                 required_version = CNL_CSR_VERSION_REQUIRED;
 302         } else if (IS_GEMINILAKE(dev_priv)) {
 303                 required_version = GLK_CSR_VERSION_REQUIRED;
 304         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 305                 required_version = KBL_CSR_VERSION_REQUIRED;
 306         } else if (IS_SKYLAKE(dev_priv)) {
 307                 required_version = SKL_CSR_VERSION_REQUIRED;
 308         } else if (IS_BROXTON(dev_priv)) {
 309                 required_version = BXT_CSR_VERSION_REQUIRED;
 310         } else {
 311                 MISSING_CASE(INTEL_REVID(dev_priv));
 312                 required_version = 0;
 313         }
 314
 315         if (csr->version != required_version) {
 316                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 317                          " please use v%u.%u\n",
 318                          CSR_VERSION_MAJOR(csr->version),
 319                          CSR_VERSION_MINOR(csr->version),
 320                          CSR_VERSION_MAJOR(required_version),
 321                          CSR_VERSION_MINOR(required_version));
 322                 return NULL;
 323         }
 324
 325         readcount += sizeof(struct intel_css_header);
 326
 327         /* Extract Package Header information*/
 328         package_header = (struct intel_package_header *)
 329                 &fw->data[readcount];
 330         if (sizeof(struct intel_package_header) !=
 331             (package_header->header_len * 4)) {
 332                 DRM_ERROR("DMC firmware has wrong package header length "
 333                           "(%u bytes)\n",
 334                           (package_header->header_len * 4));
 335                 return NULL;
 336         }
 337         readcount += sizeof(struct intel_package_header);
 338
 339         /* Search for dmc_offset to find firware binary. */
 340         for (i = 0; i < package_header->num_entries; i++) {
 341                 if (package_header->fw_info[i].substepping == '*' &&
 342                     si->stepping == package_header->fw_info[i].stepping) {
 343                         dmc_offset = package_header->fw_info[i].offset;
 344                         break;
 345                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 346                            si->substepping == package_header->fw_info[i].substepping) {
 347                         dmc_offset = package_header->fw_info[i].offset;
 348                         break;
 349                 } else if (package_header->fw_info[i].stepping == '*' &&
 350                            package_header->fw_info[i].substepping == '*')
 351                         dmc_offset = package_header->fw_info[i].offset;
 352         }
 353         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 354                 DRM_ERROR("DMC firmware not supported for %c stepping\n",
 355                           si->stepping);
 356                 return NULL;
 357         }
 358         readcount += dmc_offset;
 359
 360         /* Extract dmc_header information. */
 361         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 362         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 363                 DRM_ERROR("DMC firmware has wrong dmc header length "
 364                           "(%u bytes)\n",
 365                           (dmc_header->header_len));
 366                 return NULL;
 367         }
 368         readcount += sizeof(struct intel_dmc_header);
 369
 370         /* Cache the dmc header info. */
 371         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 372                 DRM_ERROR("DMC firmware has wrong mmio count %u\n",
 373                           dmc_header->mmio_count);
 374                 return NULL;
 375         }
 376         csr->mmio_count = dmc_header->mmio_count;
 377         for (i = 0; i < dmc_header->mmio_count; i++) {
 378                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 379                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 380                         DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
 381                                   dmc_header->mmioaddr[i]);
 382                         return NULL;
 383                 }
 384                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 385                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 386         }
 387
 388         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 389         nbytes = dmc_header->fw_size * 4;
 390         if (nbytes > CSR_MAX_FW_SIZE) {
 391                 DRM_ERROR("DMC firmware too big (%u bytes)\n", nbytes);
 392                 return NULL;
 393         }
 394         csr->dmc_fw_size = dmc_header->fw_size;
 395
 396         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 397         if (!dmc_payload) {
 398                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 399                 return NULL;
 400         }
 401
 402         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 403 }
 404
 405 static void csr_load_work_fn(struct work_struct *work)
 406 {
 407         struct drm_i915_private *dev_priv;
 408         struct intel_csr *csr;
 409         const struct firmware *fw = NULL;
 410
 411         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 412         csr = &dev_priv->csr;
 413
 414         request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
 415         if (fw)
 416                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 417
 418         if (dev_priv->csr.dmc_payload) {
 419                 intel_csr_load_program(dev_priv);
 420
 421                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 422
 423                 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
 424                          dev_priv->csr.fw_path,
 425                          CSR_VERSION_MAJOR(csr->version),
 426                          CSR_VERSION_MINOR(csr->version));
 427         } else {
 428                 dev_notice(dev_priv->drm.dev,
 429                            "Failed to load DMC firmware %s."
 430                            " Disabling runtime power management.\n",
 431                            csr->fw_path);
 432                 dev_notice(dev_priv->drm.dev, "DMC firmware homepage: %s",
 433                            INTEL_UC_FIRMWARE_URL);
 434         }
 435
 436         release_firmware(fw);
 437 }
 438
 439 /**
 440  * intel_csr_ucode_init() - initialize the firmware loading.
 441  * @dev_priv: i915 drm device.
 442  *
 443  * This function is called at the time of loading the display driver to read
 444  * firmware from a .bin file and copied into a internal memory.
 445  */
 446 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 447 {
 448         struct intel_csr *csr = &dev_priv->csr;
 449
 450         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 451
 452         if (!HAS_CSR(dev_priv))
 453                 return;
 454
 455         if (IS_CANNONLAKE(dev_priv))
 456                 csr->fw_path = I915_CSR_CNL;
 457         else if (IS_GEMINILAKE(dev_priv))
 458                 csr->fw_path = I915_CSR_GLK;
 459         else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 460                 csr->fw_path = I915_CSR_KBL;
 461         else if (IS_SKYLAKE(dev_priv))
 462                 csr->fw_path = I915_CSR_SKL;
 463         else if (IS_BROXTON(dev_priv))
 464                 csr->fw_path = I915_CSR_BXT;
 465         else {
 466                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 467                 return;
 468         }
 469
 470         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 471
 472         /*
 473          * Obtain a runtime pm reference, until CSR is loaded,
 474          * to avoid entering runtime-suspend.
 475          */
 476         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 477
 478         schedule_work(&dev_priv->csr.work);
 479 }
 480
 481 /**
 482  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 483  * @dev_priv: i915 drm device
 484  *
 485  * Prepare the DMC firmware before entering system suspend. This includes
 486  * flushing pending work items and releasing any resources acquired during
 487  * init.
 488  */
 489 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 490 {
 491         if (!HAS_CSR(dev_priv))
 492                 return;
 493
 494         flush_work(&dev_priv->csr.work);
 495
 496         /* Drop the reference held in case DMC isn't loaded. */
 497         if (!dev_priv->csr.dmc_payload)
 498                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 499 }
 500
 501 /**
 502  * intel_csr_ucode_resume() - init CSR firmware during system resume
 503  * @dev_priv: i915 drm device
 504  *
 505  * Reinitialize the DMC firmware during system resume, reacquiring any
 506  * resources released in intel_csr_ucode_suspend().
 507  */
 508 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 509 {
 510         if (!HAS_CSR(dev_priv))
 511                 return;
 512
 513         /*
 514          * Reacquire the reference to keep RPM disabled in case DMC isn't
 515          * loaded.
 516          */
 517         if (!dev_priv->csr.dmc_payload)
 518                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 519 }
 520
 521 /**
 522  * intel_csr_ucode_fini() - unload the CSR firmware.
 523  * @dev_priv: i915 drm device.
 524  *
 525  * Firmmware unloading includes freeing the internal memory and reset the
 526  * firmware loading status.
 527  */
 528 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 529 {
 530         if (!HAS_CSR(dev_priv))
 531                 return;
 532
 533         intel_csr_ucode_suspend(dev_priv);
 534
 535         kfree(dev_priv->csr.dmc_payload);
 536 }