drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #ifndef _AMDGPU_RAS_H
  25 #define _AMDGPU_RAS_H
  26
  27 #include <linux/debugfs.h>
  28 #include <linux/list.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "ta_ras_if.h"
  32 #include "amdgpu_ras_eeprom.h"
  33
  34 #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS           (0x1 << 0)
  35 #define AMDGPU_RAS_FLAG_INIT_NEED_RESET         (0x1 << 1)
  36
  37 enum amdgpu_ras_block {
  38         AMDGPU_RAS_BLOCK__UMC = 0,
  39         AMDGPU_RAS_BLOCK__SDMA,
  40         AMDGPU_RAS_BLOCK__GFX,
  41         AMDGPU_RAS_BLOCK__MMHUB,
  42         AMDGPU_RAS_BLOCK__ATHUB,
  43         AMDGPU_RAS_BLOCK__PCIE_BIF,
  44         AMDGPU_RAS_BLOCK__HDP,
  45         AMDGPU_RAS_BLOCK__XGMI_WAFL,
  46         AMDGPU_RAS_BLOCK__DF,
  47         AMDGPU_RAS_BLOCK__SMN,
  48         AMDGPU_RAS_BLOCK__SEM,
  49         AMDGPU_RAS_BLOCK__MP0,
  50         AMDGPU_RAS_BLOCK__MP1,
  51         AMDGPU_RAS_BLOCK__FUSE,
  52
  53         AMDGPU_RAS_BLOCK__LAST
  54 };
  55
  56 extern const char *ras_block_string[];
  57
  58 #define ras_block_str(i) (ras_block_string[i])
  59 #define AMDGPU_RAS_BLOCK_COUNT  AMDGPU_RAS_BLOCK__LAST
  60 #define AMDGPU_RAS_BLOCK_MASK   ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1)
  61
  62 enum amdgpu_ras_gfx_subblock {
  63         /* CPC */
  64         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0,
  65         AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH =
  66                 AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START,
  67         AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
  68         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1,
  69         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1,
  70         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1,
  71         AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2,
  72         AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2,
  73         AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  74         AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END =
  75                 AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2,
  76         /* CPF */
  77         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  78         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 =
  79                 AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START,
  80         AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1,
  81         AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  82         AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
  83         /* CPG */
  84         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  85         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ =
  86                 AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START,
  87         AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG,
  88         AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  89         AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
  90         /* GDS */
  91         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
  92         AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START,
  93         AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE,
  94         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM,
  95         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM,
  96         AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
  97         AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END =
  98                 AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM,
  99         /* SPI */
 100         AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM,
 101         /* SQ */
 102         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 103         AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START,
 104         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
 105         AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I,
 106         AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 107         AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR,
 108         /* SQC (3 ranges) */
 109         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 110         /* SQC range 0 */
 111         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START =
 112                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START,
 113         AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO =
 114                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START,
 115         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
 116         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
 117         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
 118         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
 119         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
 120         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 121         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END =
 122                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
 123         /* SQC range 1 */
 124         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 125         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM =
 126                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START,
 127         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
 128         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO,
 129         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM,
 130         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM,
 131         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO,
 132         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO,
 133         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
 134         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 135         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END =
 136                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM,
 137         /* SQC range 2 */
 138         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 139         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM =
 140                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START,
 141         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
 142         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO,
 143         AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM,
 144         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM,
 145         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO,
 146         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO,
 147         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
 148         AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 149         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END =
 150                 AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM,
 151         AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END =
 152                 AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END,
 153         /* TA */
 154         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 155         AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO =
 156                 AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START,
 157         AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO,
 158         AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO,
 159         AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO,
 160         AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 161         AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO,
 162         /* TCA */
 163         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 164         AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO =
 165                 AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START,
 166         AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 167         AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END =
 168                 AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO,
 169         /* TCC (5 sub-ranges) */
 170         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 171         /* TCC range 0 */
 172         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START =
 173                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START,
 174         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA =
 175                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START,
 176         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
 177         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
 178         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
 179         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0,
 180         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1,
 181         AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG,
 182         AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 183         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END =
 184                 AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG,
 185         /* TCC range 1 */
 186         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 187         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC =
 188                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START,
 189         AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 190         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END =
 191                 AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER,
 192         /* TCC range 2 */
 193         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 194         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA =
 195                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START,
 196         AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL,
 197         AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO,
 198         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN,
 199         AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ,
 200         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO,
 201         AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM,
 202         AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 203         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END =
 204                 AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO,
 205         /* TCC range 3 */
 206         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 207         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO =
 208                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START,
 209         AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 210         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END =
 211                 AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
 212         /* TCC range 4 */
 213         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 214         AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN =
 215                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START,
 216         AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 217         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END =
 218                 AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER,
 219         AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END =
 220                 AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END,
 221         /* TCI */
 222         AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM,
 223         /* TCP */
 224         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 225         AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM =
 226                 AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START,
 227         AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM,
 228         AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO,
 229         AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO,
 230         AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM,
 231         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0,
 232         AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 233         AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END =
 234                 AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1,
 235         /* TD */
 236         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 237         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO =
 238                 AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START,
 239         AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI,
 240         AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 241         AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO,
 242         /* EA (3 sub-ranges) */
 243         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 244         /* EA range 0 */
 245         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START =
 246                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START,
 247         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM =
 248                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START,
 249         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM,
 250         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM,
 251         AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM,
 252         AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM,
 253         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM,
 254         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM,
 255         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 256         AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END =
 257                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM,
 258         /* EA range 1 */
 259         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 260         AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM =
 261                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START,
 262         AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM,
 263         AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM,
 264         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM,
 265         AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM,
 266         AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM,
 267         AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 268         AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END =
 269                 AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM,
 270         /* EA range 2 */
 271         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 272         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM =
 273                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START,
 274         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM,
 275         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM,
 276         AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 277         AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END =
 278                 AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM,
 279         AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END =
 280                 AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END,
 281         /* UTC VM L2 bank */
 282         AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE,
 283         /* UTC VM walker */
 284         AMDGPU_RAS_BLOCK__UTC_VML2_WALKER,
 285         /* UTC ATC L2 2MB cache */
 286         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK,
 287         /* UTC ATC L2 4KB cache */
 288         AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK,
 289         AMDGPU_RAS_BLOCK__GFX_MAX
 290 };
 291
 292 enum amdgpu_ras_error_type {
 293         AMDGPU_RAS_ERROR__NONE                                                  = 0,
 294         AMDGPU_RAS_ERROR__PARITY                                                = 1,
 295         AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE                                    = 2,
 296         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE                                   = 4,
 297         AMDGPU_RAS_ERROR__POISON                                                = 8,
 298 };
 299
 300 enum amdgpu_ras_ret {
 301         AMDGPU_RAS_SUCCESS = 0,
 302         AMDGPU_RAS_FAIL,
 303         AMDGPU_RAS_UE,
 304         AMDGPU_RAS_CE,
 305         AMDGPU_RAS_PT,
 306 };
 307
 308 struct ras_common_if {
 309         enum amdgpu_ras_block block;
 310         enum amdgpu_ras_error_type type;
 311         uint32_t sub_block_index;
 312 };
 313
 314 struct amdgpu_ras {
 315         /* ras infrastructure */
 316         /* for ras itself. */
 317         uint32_t features;
 318         struct list_head head;
 319         /* sysfs */
 320         struct device_attribute features_attr;
 321         struct bin_attribute badpages_attr;
 322         struct dentry *de_ras_eeprom_table;
 323         /* block array */
 324         struct ras_manager *objs;
 325
 326         /* gpu recovery */
 327         struct work_struct recovery_work;
 328         atomic_t in_recovery;
 329         struct amdgpu_device *adev;
 330         /* error handler data */
 331         struct ras_err_handler_data *eh_data;
 332         struct mutex recovery_lock;
 333
 334         uint32_t flags;
 335         bool reboot;
 336         struct amdgpu_ras_eeprom_control eeprom_control;
 337
 338         bool error_query_ready;
 339
 340         /* bad page count threshold */
 341         uint32_t bad_page_cnt_threshold;
 342
 343         /* disable ras error count harvest in recovery */
 344         bool disable_ras_err_cnt_harvest;
 345
 346         /* RAS count errors delayed work */
 347         struct delayed_work ras_counte_delay_work;
 348         atomic_t ras_ue_count;
 349         atomic_t ras_ce_count;
 350 };
 351
 352 struct ras_fs_data {
 353         char sysfs_name[32];
 354         char debugfs_name[32];
 355 };
 356
 357 struct ras_err_data {
 358         unsigned long ue_count;
 359         unsigned long ce_count;
 360         unsigned long err_addr_cnt;
 361         struct eeprom_table_record *err_addr;
 362 };
 363
 364 struct ras_err_handler_data {
 365         /* point to bad page records array */
 366         struct eeprom_table_record *bps;
 367         /* the count of entries */
 368         int count;
 369         /* the space can place new entries */
 370         int space_left;
 371 };
 372
 373 typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
 374                 void *err_data,
 375                 struct amdgpu_iv_entry *entry);
 376
 377 struct ras_ih_data {
 378         /* interrupt bottom half */
 379         struct work_struct ih_work;
 380         int inuse;
 381         /* IP callback */
 382         ras_ih_cb cb;
 383         /* full of entries */
 384         unsigned char *ring;
 385         unsigned int ring_size;
 386         unsigned int element_size;
 387         unsigned int aligned_element_size;
 388         unsigned int rptr;
 389         unsigned int wptr;
 390 };
 391
 392 struct ras_manager {
 393         struct ras_common_if head;
 394         /* reference count */
 395         int use;
 396         /* ras block link */
 397         struct list_head node;
 398         /* the device */
 399         struct amdgpu_device *adev;
 400         /* sysfs */
 401         struct device_attribute sysfs_attr;
 402         int attr_inuse;
 403
 404         /* fs node name */
 405         struct ras_fs_data fs_data;
 406
 407         /* IH data */
 408         struct ras_ih_data ih_data;
 409
 410         struct ras_err_data err_data;
 411 };
 412
 413 struct ras_badpage {
 414         unsigned int bp;
 415         unsigned int size;
 416         unsigned int flags;
 417 };
 418
 419 /* interfaces for IP */
 420 struct ras_fs_if {
 421         struct ras_common_if head;
 422         char sysfs_name[32];
 423         char debugfs_name[32];
 424 };
 425
 426 struct ras_query_if {
 427         struct ras_common_if head;
 428         unsigned long ue_count;
 429         unsigned long ce_count;
 430 };
 431
 432 struct ras_inject_if {
 433         struct ras_common_if head;
 434         uint64_t address;
 435         uint64_t value;
 436 };
 437
 438 struct ras_cure_if {
 439         struct ras_common_if head;
 440         uint64_t address;
 441 };
 442
 443 struct ras_ih_if {
 444         struct ras_common_if head;
 445         ras_ih_cb cb;
 446 };
 447
 448 struct ras_dispatch_if {
 449         struct ras_common_if head;
 450         struct amdgpu_iv_entry *entry;
 451 };
 452
 453 struct ras_debug_if {
 454         union {
 455                 struct ras_common_if head;
 456                 struct ras_inject_if inject;
 457         };
 458         int op;
 459 };
 460 /* work flow
 461  * vbios
 462  * 1: ras feature enable (enabled by default)
 463  * psp
 464  * 2: ras framework init (in ip_init)
 465  * IP
 466  * 3: IH add
 467  * 4: debugfs/sysfs create
 468  * 5: query/inject
 469  * 6: debugfs/sysfs remove
 470  * 7: IH remove
 471  * 8: feature disable
 472  */
 473
 474 #define amdgpu_ras_get_context(adev)            ((adev)->psp.ras_context.ras)
 475 #define amdgpu_ras_set_context(adev, ras_con)   ((adev)->psp.ras_context.ras = (ras_con))
 476
 477 /* check if ras is supported on block, say, sdma, gfx */
 478 static inline int amdgpu_ras_is_supported(struct amdgpu_device *adev,
 479                 unsigned int block)
 480 {
 481         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 482
 483         if (block >= AMDGPU_RAS_BLOCK_COUNT)
 484                 return 0;
 485         return ras && (adev->ras_enabled & (1 << block));
 486 }
 487
 488 int amdgpu_ras_recovery_init(struct amdgpu_device *adev);
 489 int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev,
 490                 unsigned int block);
 491
 492 void amdgpu_ras_resume(struct amdgpu_device *adev);
 493 void amdgpu_ras_suspend(struct amdgpu_device *adev);
 494
 495 int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
 496                                  unsigned long *ce_count,
 497                                  unsigned long *ue_count);
 498
 499 /* error handling functions */
 500 int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
 501                 struct eeprom_table_record *bps, int pages);
 502
 503 int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev);
 504
 505 static inline int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
 506 {
 507         struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 508
 509         if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
 510                 schedule_work(&ras->recovery_work);
 511         return 0;
 512 }
 513
 514 static inline enum ta_ras_block
 515 amdgpu_ras_block_to_ta(enum amdgpu_ras_block block) {
 516         switch (block) {
 517         case AMDGPU_RAS_BLOCK__UMC:
 518                 return TA_RAS_BLOCK__UMC;
 519         case AMDGPU_RAS_BLOCK__SDMA:
 520                 return TA_RAS_BLOCK__SDMA;
 521         case AMDGPU_RAS_BLOCK__GFX:
 522                 return TA_RAS_BLOCK__GFX;
 523         case AMDGPU_RAS_BLOCK__MMHUB:
 524                 return TA_RAS_BLOCK__MMHUB;
 525         case AMDGPU_RAS_BLOCK__ATHUB:
 526                 return TA_RAS_BLOCK__ATHUB;
 527         case AMDGPU_RAS_BLOCK__PCIE_BIF:
 528                 return TA_RAS_BLOCK__PCIE_BIF;
 529         case AMDGPU_RAS_BLOCK__HDP:
 530                 return TA_RAS_BLOCK__HDP;
 531         case AMDGPU_RAS_BLOCK__XGMI_WAFL:
 532                 return TA_RAS_BLOCK__XGMI_WAFL;
 533         case AMDGPU_RAS_BLOCK__DF:
 534                 return TA_RAS_BLOCK__DF;
 535         case AMDGPU_RAS_BLOCK__SMN:
 536                 return TA_RAS_BLOCK__SMN;
 537         case AMDGPU_RAS_BLOCK__SEM:
 538                 return TA_RAS_BLOCK__SEM;
 539         case AMDGPU_RAS_BLOCK__MP0:
 540                 return TA_RAS_BLOCK__MP0;
 541         case AMDGPU_RAS_BLOCK__MP1:
 542                 return TA_RAS_BLOCK__MP1;
 543         case AMDGPU_RAS_BLOCK__FUSE:
 544                 return TA_RAS_BLOCK__FUSE;
 545         default:
 546                 WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);
 547                 return TA_RAS_BLOCK__UMC;
 548         }
 549 }
 550
 551 static inline enum ta_ras_error_type
 552 amdgpu_ras_error_to_ta(enum amdgpu_ras_error_type error) {
 553         switch (error) {
 554         case AMDGPU_RAS_ERROR__NONE:
 555                 return TA_RAS_ERROR__NONE;
 556         case AMDGPU_RAS_ERROR__PARITY:
 557                 return TA_RAS_ERROR__PARITY;
 558         case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
 559                 return TA_RAS_ERROR__SINGLE_CORRECTABLE;
 560         case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
 561                 return TA_RAS_ERROR__MULTI_UNCORRECTABLE;
 562         case AMDGPU_RAS_ERROR__POISON:
 563                 return TA_RAS_ERROR__POISON;
 564         default:
 565                 WARN_ONCE(1, "RAS ERROR: unexpected error type %d\n", error);
 566                 return TA_RAS_ERROR__NONE;
 567         }
 568 }
 569
 570 /* called in ip_init and ip_fini */
 571 int amdgpu_ras_init(struct amdgpu_device *adev);
 572 int amdgpu_ras_fini(struct amdgpu_device *adev);
 573 int amdgpu_ras_pre_fini(struct amdgpu_device *adev);
 574 int amdgpu_ras_late_init(struct amdgpu_device *adev,
 575                          struct ras_common_if *ras_block,
 576                          struct ras_fs_if *fs_info,
 577                          struct ras_ih_if *ih_info);
 578 void amdgpu_ras_late_fini(struct amdgpu_device *adev,
 579                           struct ras_common_if *ras_block,
 580                           struct ras_ih_if *ih_info);
 581
 582 int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
 583                 struct ras_common_if *head, bool enable);
 584
 585 int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
 586                 struct ras_common_if *head, bool enable);
 587
 588 int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
 589                 struct ras_fs_if *head);
 590
 591 int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
 592                 struct ras_common_if *head);
 593
 594 void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev);
 595
 596 int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
 597                 struct ras_query_if *info);
 598
 599 int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
 600                 enum amdgpu_ras_block block);
 601
 602 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
 603                 struct ras_inject_if *info);
 604
 605 int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
 606                 struct ras_ih_if *info);
 607
 608 int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
 609                 struct ras_ih_if *info);
 610
 611 int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
 612                 struct ras_dispatch_if *info);
 613
 614 struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 615                 struct ras_common_if *head);
 616
 617 extern atomic_t amdgpu_ras_in_intr;
 618
 619 static inline bool amdgpu_ras_intr_triggered(void)
 620 {
 621         return !!atomic_read(&amdgpu_ras_in_intr);
 622 }
 623
 624 static inline void amdgpu_ras_intr_cleared(void)
 625 {
 626         atomic_set(&amdgpu_ras_in_intr, 0);
 627 }
 628
 629 void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev);
 630
 631 void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready);
 632
 633 bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev);
 634
 635 void amdgpu_release_ras_context(struct amdgpu_device *adev);
 636
 637 int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev);
 638
 639 #endif