drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40
  41 #include "amdgpu_ras.h"
  42 #include "amdgpu_securedisplay.h"
  43 #include "amdgpu_atomfirmware.h"
  44
  45 static int psp_sysfs_init(struct amdgpu_device *adev);
  46 static void psp_sysfs_fini(struct amdgpu_device *adev);
  47
  48 static int psp_load_smu_fw(struct psp_context *psp);
  49
  50 /*
  51  * Due to DF Cstate management centralized to PMFW, the firmware
  52  * loading sequence will be updated as below:
  53  *   - Load KDB
  54  *   - Load SYS_DRV
  55  *   - Load tOS
  56  *   - Load PMFW
  57  *   - Setup TMR
  58  *   - Load other non-psp fw
  59  *   - Load ASD
  60  *   - Load XGMI/RAS/HDCP/DTM TA if any
  61  *
  62  * This new sequence is required for
  63  *   - Arcturus and onwards
  64  *   - Navi12 and onwards
  65  */
  66 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  67 {
  68         struct amdgpu_device *adev = psp->adev;
  69
  70         psp->pmfw_centralized_cstate_management = false;
  71
  72         if (amdgpu_sriov_vf(adev))
  73                 return;
  74
  75         if (adev->flags & AMD_IS_APU)
  76                 return;
  77
  78         if ((adev->asic_type >= CHIP_ARCTURUS) ||
  79             (adev->asic_type >= CHIP_NAVI12))
  80                 psp->pmfw_centralized_cstate_management = true;
  81 }
  82
  83 static int psp_early_init(void *handle)
  84 {
  85         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  86         struct psp_context *psp = &adev->psp;
  87
  88         switch (adev->asic_type) {
  89         case CHIP_VEGA10:
  90         case CHIP_VEGA12:
  91                 psp_v3_1_set_psp_funcs(psp);
  92                 psp->autoload_supported = false;
  93                 break;
  94         case CHIP_RAVEN:
  95                 psp_v10_0_set_psp_funcs(psp);
  96                 psp->autoload_supported = false;
  97                 break;
  98         case CHIP_VEGA20:
  99         case CHIP_ARCTURUS:
 100                 psp_v11_0_set_psp_funcs(psp);
 101                 psp->autoload_supported = false;
 102                 break;
 103         case CHIP_NAVI10:
 104         case CHIP_NAVI14:
 105         case CHIP_NAVI12:
 106         case CHIP_SIENNA_CICHLID:
 107         case CHIP_NAVY_FLOUNDER:
 108         case CHIP_VANGOGH:
 109         case CHIP_DIMGREY_CAVEFISH:
 110         case CHIP_BEIGE_GOBY:
 111                 psp_v11_0_set_psp_funcs(psp);
 112                 psp->autoload_supported = true;
 113                 break;
 114         case CHIP_RENOIR:
 115                 psp_v12_0_set_psp_funcs(psp);
 116                 break;
 117         case CHIP_ALDEBARAN:
 118                 psp_v13_0_set_psp_funcs(psp);
 119                 break;
 120         case CHIP_YELLOW_CARP:
 121                 psp_v13_0_set_psp_funcs(psp);
 122                 psp->autoload_supported = true;
 123                 break;
 124         case CHIP_CYAN_SKILLFISH:
 125                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 126                         psp_v11_0_8_set_psp_funcs(psp);
 127                         psp->autoload_supported = false;
 128                 }
 129                 break;
 130         default:
 131                 return -EINVAL;
 132         }
 133
 134         psp->adev = adev;
 135
 136         psp_check_pmfw_centralized_cstate_management(psp);
 137
 138         return 0;
 139 }
 140
 141 static void psp_memory_training_fini(struct psp_context *psp)
 142 {
 143         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 144
 145         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 146         kfree(ctx->sys_cache);
 147         ctx->sys_cache = NULL;
 148 }
 149
 150 static int psp_memory_training_init(struct psp_context *psp)
 151 {
 152         int ret;
 153         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 154
 155         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 156                 DRM_DEBUG("memory training is not supported!\n");
 157                 return 0;
 158         }
 159
 160         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 161         if (ctx->sys_cache == NULL) {
 162                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 163                 ret = -ENOMEM;
 164                 goto Err_out;
 165         }
 166
 167         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 168                   ctx->train_data_size,
 169                   ctx->p2c_train_data_offset,
 170                   ctx->c2p_train_data_offset);
 171         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 172         return 0;
 173
 174 Err_out:
 175         psp_memory_training_fini(psp);
 176         return ret;
 177 }
 178
 179 /*
 180  * Helper funciton to query psp runtime database entry
 181  *
 182  * @adev: amdgpu_device pointer
 183  * @entry_type: the type of psp runtime database entry
 184  * @db_entry: runtime database entry pointer
 185  *
 186  * Return false if runtime database doesn't exit or entry is invalid
 187  * or true if the specific database entry is found, and copy to @db_entry
 188  */
 189 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 190                                      enum psp_runtime_entry_type entry_type,
 191                                      void *db_entry)
 192 {
 193         uint64_t db_header_pos, db_dir_pos;
 194         struct psp_runtime_data_header db_header = {0};
 195         struct psp_runtime_data_directory db_dir = {0};
 196         bool ret = false;
 197         int i;
 198
 199         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 200         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 201
 202         /* read runtime db header from vram */
 203         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 204                         sizeof(struct psp_runtime_data_header), false);
 205
 206         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 207                 /* runtime db doesn't exist, exit */
 208                 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
 209                 return false;
 210         }
 211
 212         /* read runtime database entry from vram */
 213         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 214                         sizeof(struct psp_runtime_data_directory), false);
 215
 216         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 217                 /* invalid db entry count, exit */
 218                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 219                 return false;
 220         }
 221
 222         /* look up for requested entry type */
 223         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 224                 if (db_dir.entry_list[i].entry_type == entry_type) {
 225                         switch (entry_type) {
 226                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 227                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 228                                         /* invalid db entry size */
 229                                         dev_warn(adev->dev, "Invalid PSP runtime database entry size\n");
 230                                         return false;
 231                                 }
 232                                 /* read runtime database entry */
 233                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 234                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 235                                 ret = true;
 236                                 break;
 237                         default:
 238                                 ret = false;
 239                                 break;
 240                         }
 241                 }
 242         }
 243
 244         return ret;
 245 }
 246
 247 static int psp_sw_init(void *handle)
 248 {
 249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 250         struct psp_context *psp = &adev->psp;
 251         int ret;
 252         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 253         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 254
 255         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 256         if (!psp->cmd) {
 257                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 258                 ret = -ENOMEM;
 259         }
 260
 261         if (!amdgpu_sriov_vf(adev)) {
 262                 ret = psp_init_microcode(psp);
 263                 if (ret) {
 264                         DRM_ERROR("Failed to load psp firmware!\n");
 265                         return ret;
 266                 }
 267         } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) {
 268                 ret = psp_init_ta_microcode(psp, "aldebaran");
 269                 if (ret) {
 270                         DRM_ERROR("Failed to initialize ta microcode!\n");
 271                         return ret;
 272                 }
 273         }
 274
 275         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 276         if (psp_get_runtime_db_entry(adev,
 277                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 278                                 &boot_cfg_entry)) {
 279                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 280                 if ((psp->boot_cfg_bitmask) &
 281                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 282                         /* If psp runtime database exists, then
 283                          * only enable two stage memory training
 284                          * when TWO_STAGE_DRAM_TRAINING bit is set
 285                          * in runtime database */
 286                         mem_training_ctx->enable_mem_training = true;
 287                 }
 288
 289         } else {
 290                 /* If psp runtime database doesn't exist or
 291                  * is invalid, force enable two stage memory
 292                  * training */
 293                 mem_training_ctx->enable_mem_training = true;
 294         }
 295
 296         if (mem_training_ctx->enable_mem_training) {
 297                 ret = psp_memory_training_init(psp);
 298                 if (ret) {
 299                         DRM_ERROR("Failed to initialize memory training!\n");
 300                         return ret;
 301                 }
 302
 303                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 304                 if (ret) {
 305                         DRM_ERROR("Failed to process memory training!\n");
 306                         return ret;
 307                 }
 308         }
 309
 310         if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
 311                 ret= psp_sysfs_init(adev);
 312                 if (ret) {
 313                         return ret;
 314                 }
 315         }
 316
 317         return 0;
 318 }
 319
 320 static int psp_sw_fini(void *handle)
 321 {
 322         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 323         struct psp_context *psp = &adev->psp;
 324         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 325
 326         psp_memory_training_fini(psp);
 327         if (psp->sos_fw) {
 328                 release_firmware(psp->sos_fw);
 329                 psp->sos_fw = NULL;
 330         }
 331         if (psp->asd_fw) {
 332                 release_firmware(psp->asd_fw);
 333                 psp->asd_fw = NULL;
 334         }
 335         if (psp->ta_fw) {
 336                 release_firmware(psp->ta_fw);
 337                 psp->ta_fw = NULL;
 338         }
 339
 340         if (adev->asic_type == CHIP_NAVI10 ||
 341             adev->asic_type == CHIP_SIENNA_CICHLID)
 342                 psp_sysfs_fini(adev);
 343
 344         kfree(cmd);
 345         cmd = NULL;
 346
 347         return 0;
 348 }
 349
 350 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 351                  uint32_t reg_val, uint32_t mask, bool check_changed)
 352 {
 353         uint32_t val;
 354         int i;
 355         struct amdgpu_device *adev = psp->adev;
 356
 357         if (psp->adev->no_hw_access)
 358                 return 0;
 359
 360         for (i = 0; i < adev->usec_timeout; i++) {
 361                 val = RREG32(reg_index);
 362                 if (check_changed) {
 363                         if (val != reg_val)
 364                                 return 0;
 365                 } else {
 366                         if ((val & mask) == reg_val)
 367                                 return 0;
 368                 }
 369                 udelay(1);
 370         }
 371
 372         return -ETIME;
 373 }
 374
 375 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 376 {
 377         switch (cmd_id) {
 378         case GFX_CMD_ID_LOAD_TA:
 379                 return "LOAD_TA";
 380         case GFX_CMD_ID_UNLOAD_TA:
 381                 return "UNLOAD_TA";
 382         case GFX_CMD_ID_INVOKE_CMD:
 383                 return "INVOKE_CMD";
 384         case GFX_CMD_ID_LOAD_ASD:
 385                 return "LOAD_ASD";
 386         case GFX_CMD_ID_SETUP_TMR:
 387                 return "SETUP_TMR";
 388         case GFX_CMD_ID_LOAD_IP_FW:
 389                 return "LOAD_IP_FW";
 390         case GFX_CMD_ID_DESTROY_TMR:
 391                 return "DESTROY_TMR";
 392         case GFX_CMD_ID_SAVE_RESTORE:
 393                 return "SAVE_RESTORE_IP_FW";
 394         case GFX_CMD_ID_SETUP_VMR:
 395                 return "SETUP_VMR";
 396         case GFX_CMD_ID_DESTROY_VMR:
 397                 return "DESTROY_VMR";
 398         case GFX_CMD_ID_PROG_REG:
 399                 return "PROG_REG";
 400         case GFX_CMD_ID_GET_FW_ATTESTATION:
 401                 return "GET_FW_ATTESTATION";
 402         case GFX_CMD_ID_LOAD_TOC:
 403                 return "ID_LOAD_TOC";
 404         case GFX_CMD_ID_AUTOLOAD_RLC:
 405                 return "AUTOLOAD_RLC";
 406         case GFX_CMD_ID_BOOT_CFG:
 407                 return "BOOT_CFG";
 408         default:
 409                 return "UNKNOWN CMD";
 410         }
 411 }
 412
 413 static int
 414 psp_cmd_submit_buf(struct psp_context *psp,
 415                    struct amdgpu_firmware_info *ucode,
 416                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 417 {
 418         int ret;
 419         int index, idx;
 420         int timeout = 20000;
 421         bool ras_intr = false;
 422         bool skip_unsupport = false;
 423
 424         if (psp->adev->no_hw_access)
 425                 return 0;
 426
 427         if (!drm_dev_enter(&psp->adev->ddev, &idx))
 428                 return 0;
 429
 430         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 431
 432         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 433
 434         index = atomic_inc_return(&psp->fence_value);
 435         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 436         if (ret) {
 437                 atomic_dec(&psp->fence_value);
 438                 goto exit;
 439         }
 440
 441         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 442         while (*((unsigned int *)psp->fence_buf) != index) {
 443                 if (--timeout == 0)
 444                         break;
 445                 /*
 446                  * Shouldn't wait for timeout when err_event_athub occurs,
 447                  * because gpu reset thread triggered and lock resource should
 448                  * be released for psp resume sequence.
 449                  */
 450                 ras_intr = amdgpu_ras_intr_triggered();
 451                 if (ras_intr)
 452                         break;
 453                 usleep_range(10, 100);
 454                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 455         }
 456
 457         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 458         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 459                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 460
 461         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 462
 463         /* In some cases, psp response status is not 0 even there is no
 464          * problem while the command is submitted. Some version of PSP FW
 465          * doesn't write 0 to that field.
 466          * So here we would like to only print a warning instead of an error
 467          * during psp initialization to avoid breaking hw_init and it doesn't
 468          * return -EINVAL.
 469          */
 470         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 471                 if (ucode)
 472                         DRM_WARN("failed to load ucode (%s) ",
 473                                   amdgpu_ucode_name(ucode->ucode_id));
 474                 DRM_WARN("psp gfx command (%s) failed and response status is (0x%X)\n",
 475                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id),
 476                          psp->cmd_buf_mem->resp.status);
 477                 if (!timeout) {
 478                         ret = -EINVAL;
 479                         goto exit;
 480                 }
 481         }
 482
 483         if (ucode) {
 484                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 485                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 486         }
 487
 488 exit:
 489         drm_dev_exit(idx);
 490         return ret;
 491 }
 492
 493 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 494 {
 495         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 496
 497         mutex_lock(&psp->mutex);
 498
 499         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 500
 501         return cmd;
 502 }
 503
 504 void release_psp_cmd_buf(struct psp_context *psp)
 505 {
 506         mutex_unlock(&psp->mutex);
 507 }
 508
 509 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 510                                  struct psp_gfx_cmd_resp *cmd,
 511                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 512 {
 513         struct amdgpu_device *adev = psp->adev;
 514         uint32_t size = amdgpu_bo_size(tmr_bo);
 515         uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 516
 517         if (amdgpu_sriov_vf(psp->adev))
 518                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 519         else
 520                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 521         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 522         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 523         cmd->cmd.cmd_setup_tmr.buf_size = size;
 524         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 525         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 526         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 527 }
 528
 529 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 530                                       uint64_t pri_buf_mc, uint32_t size)
 531 {
 532         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 533         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 534         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 535         cmd->cmd.cmd_load_toc.toc_size = size;
 536 }
 537
 538 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 539 static int psp_load_toc(struct psp_context *psp,
 540                         uint32_t *tmr_size)
 541 {
 542         int ret;
 543         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 544
 545         /* Copy toc to psp firmware private buffer */
 546         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 547
 548         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 549
 550         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 551                                  psp->fence_buf_mc_addr);
 552         if (!ret)
 553                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 554
 555         release_psp_cmd_buf(psp);
 556
 557         return ret;
 558 }
 559
 560 /* Set up Trusted Memory Region */
 561 static int psp_tmr_init(struct psp_context *psp)
 562 {
 563         int ret;
 564         int tmr_size;
 565         void *tmr_buf;
 566         void **pptr;
 567
 568         /*
 569          * According to HW engineer, they prefer the TMR address be "naturally
 570          * aligned" , e.g. the start address be an integer divide of TMR size.
 571          *
 572          * Note: this memory need be reserved till the driver
 573          * uninitializes.
 574          */
 575         tmr_size = PSP_TMR_SIZE(psp->adev);
 576
 577         /* For ASICs support RLC autoload, psp will parse the toc
 578          * and calculate the total size of TMR needed */
 579         if (!amdgpu_sriov_vf(psp->adev) &&
 580             psp->toc.start_addr &&
 581             psp->toc.size_bytes &&
 582             psp->fw_pri_buf) {
 583                 ret = psp_load_toc(psp, &tmr_size);
 584                 if (ret) {
 585                         DRM_ERROR("Failed to load toc\n");
 586                         return ret;
 587                 }
 588         }
 589
 590         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 591         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
 592                                       AMDGPU_GEM_DOMAIN_VRAM,
 593                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 594
 595         return ret;
 596 }
 597
 598 static bool psp_skip_tmr(struct psp_context *psp)
 599 {
 600         switch (psp->adev->asic_type) {
 601         case CHIP_NAVI12:
 602         case CHIP_SIENNA_CICHLID:
 603         case CHIP_ALDEBARAN:
 604                 return true;
 605         default:
 606                 return false;
 607         }
 608 }
 609
 610 static int psp_tmr_load(struct psp_context *psp)
 611 {
 612         int ret;
 613         struct psp_gfx_cmd_resp *cmd;
 614
 615         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 616          * Already set up by host driver.
 617          */
 618         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 619                 return 0;
 620
 621         cmd = acquire_psp_cmd_buf(psp);
 622
 623         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 624         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 625                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 626
 627         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 628                                  psp->fence_buf_mc_addr);
 629
 630         release_psp_cmd_buf(psp);
 631
 632         return ret;
 633 }
 634
 635 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 636                                         struct psp_gfx_cmd_resp *cmd)
 637 {
 638         if (amdgpu_sriov_vf(psp->adev))
 639                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 640         else
 641                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 642 }
 643
 644 static int psp_tmr_unload(struct psp_context *psp)
 645 {
 646         int ret;
 647         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 648
 649         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 650         DRM_INFO("free PSP TMR buffer\n");
 651
 652         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 653                                  psp->fence_buf_mc_addr);
 654
 655         release_psp_cmd_buf(psp);
 656
 657         return ret;
 658 }
 659
 660 static int psp_tmr_terminate(struct psp_context *psp)
 661 {
 662         int ret;
 663         void *tmr_buf;
 664         void **pptr;
 665
 666         ret = psp_tmr_unload(psp);
 667         if (ret)
 668                 return ret;
 669
 670         /* free TMR memory buffer */
 671         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 672         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 673
 674         return 0;
 675 }
 676
 677 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 678                                         uint64_t *output_ptr)
 679 {
 680         int ret;
 681         struct psp_gfx_cmd_resp *cmd;
 682
 683         if (!output_ptr)
 684                 return -EINVAL;
 685
 686         if (amdgpu_sriov_vf(psp->adev))
 687                 return 0;
 688
 689         cmd = acquire_psp_cmd_buf(psp);
 690
 691         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 692
 693         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 694                                  psp->fence_buf_mc_addr);
 695
 696         if (!ret) {
 697                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 698                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 699         }
 700
 701         release_psp_cmd_buf(psp);
 702
 703         return ret;
 704 }
 705
 706 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 707 {
 708         struct psp_context *psp = &adev->psp;
 709         struct psp_gfx_cmd_resp *cmd;
 710         int ret;
 711
 712         if (amdgpu_sriov_vf(adev))
 713                 return 0;
 714
 715         cmd = acquire_psp_cmd_buf(psp);
 716
 717         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 718         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 719
 720         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 721         if (!ret) {
 722                 *boot_cfg =
 723                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 724         }
 725
 726         release_psp_cmd_buf(psp);
 727
 728         return ret;
 729 }
 730
 731 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 732 {
 733         int ret;
 734         struct psp_context *psp = &adev->psp;
 735         struct psp_gfx_cmd_resp *cmd;
 736
 737         if (amdgpu_sriov_vf(adev))
 738                 return 0;
 739
 740         cmd = acquire_psp_cmd_buf(psp);
 741
 742         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 743         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 744         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 745         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 746
 747         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 748
 749         release_psp_cmd_buf(psp);
 750
 751         return ret;
 752 }
 753
 754 static int psp_rl_load(struct amdgpu_device *adev)
 755 {
 756         int ret;
 757         struct psp_context *psp = &adev->psp;
 758         struct psp_gfx_cmd_resp *cmd;
 759
 760         if (!is_psp_fw_valid(psp->rl))
 761                 return 0;
 762
 763         cmd = acquire_psp_cmd_buf(psp);
 764
 765         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 766         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 767
 768         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 769         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 770         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 771         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 772         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 773
 774         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 775
 776         release_psp_cmd_buf(psp);
 777
 778         return ret;
 779 }
 780
 781 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 782                                 uint64_t asd_mc, uint32_t size)
 783 {
 784         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 785         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 786         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 787         cmd->cmd.cmd_load_ta.app_len = size;
 788
 789         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
 790         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
 791         cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
 792 }
 793
 794 static int psp_asd_load(struct psp_context *psp)
 795 {
 796         int ret;
 797         struct psp_gfx_cmd_resp *cmd;
 798
 799         /* If PSP version doesn't match ASD version, asd loading will be failed.
 800          * add workaround to bypass it for sriov now.
 801          * TODO: add version check to make it common
 802          */
 803         if (amdgpu_sriov_vf(psp->adev) || !psp->asd.size_bytes)
 804                 return 0;
 805
 806         cmd = acquire_psp_cmd_buf(psp);
 807
 808         psp_copy_fw(psp, psp->asd.start_addr, psp->asd.size_bytes);
 809
 810         psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 811                                   psp->asd.size_bytes);
 812
 813         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 814                                  psp->fence_buf_mc_addr);
 815         if (!ret) {
 816                 psp->asd_context.asd_initialized = true;
 817                 psp->asd_context.session_id = cmd->resp.session_id;
 818         }
 819
 820         release_psp_cmd_buf(psp);
 821
 822         return ret;
 823 }
 824
 825 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 826                                        uint32_t session_id)
 827 {
 828         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 829         cmd->cmd.cmd_unload_ta.session_id = session_id;
 830 }
 831
 832 static int psp_asd_unload(struct psp_context *psp)
 833 {
 834         int ret;
 835         struct psp_gfx_cmd_resp *cmd;
 836
 837         if (amdgpu_sriov_vf(psp->adev))
 838                 return 0;
 839
 840         if (!psp->asd_context.asd_initialized)
 841                 return 0;
 842
 843         cmd = acquire_psp_cmd_buf(psp);
 844
 845         psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
 846
 847         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 848                                  psp->fence_buf_mc_addr);
 849         if (!ret)
 850                 psp->asd_context.asd_initialized = false;
 851
 852         release_psp_cmd_buf(psp);
 853
 854         return ret;
 855 }
 856
 857 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 858                 uint32_t id, uint32_t value)
 859 {
 860         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 861         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 862         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 863 }
 864
 865 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 866                 uint32_t value)
 867 {
 868         struct psp_gfx_cmd_resp *cmd;
 869         int ret = 0;
 870
 871         if (reg >= PSP_REG_LAST)
 872                 return -EINVAL;
 873
 874         cmd = acquire_psp_cmd_buf(psp);
 875
 876         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 877         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 878         if (ret)
 879                 DRM_ERROR("PSP failed to program reg id %d", reg);
 880
 881         release_psp_cmd_buf(psp);
 882
 883         return ret;
 884 }
 885
 886 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 887                                      uint64_t ta_bin_mc,
 888                                      uint32_t ta_bin_size,
 889                                      uint64_t ta_shared_mc,
 890                                      uint32_t ta_shared_size)
 891 {
 892         cmd->cmd_id                             = GFX_CMD_ID_LOAD_TA;
 893         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
 894         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
 895         cmd->cmd.cmd_load_ta.app_len            = ta_bin_size;
 896
 897         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
 898         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
 899         cmd->cmd.cmd_load_ta.cmd_buf_len         = ta_shared_size;
 900 }
 901
 902 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 903 {
 904         int ret;
 905
 906         /*
 907          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 908          * physical) for xgmi ta <-> Driver
 909          */
 910         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 911                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 912                                       &psp->xgmi_context.context.mem_context.shared_bo,
 913                                       &psp->xgmi_context.context.mem_context.shared_mc_addr,
 914                                       &psp->xgmi_context.context.mem_context.shared_buf);
 915
 916         return ret;
 917 }
 918
 919 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 920                                        uint32_t ta_cmd_id,
 921                                        uint32_t session_id)
 922 {
 923         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
 924         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
 925         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
 926 }
 927
 928 static int psp_ta_invoke(struct psp_context *psp,
 929                   uint32_t ta_cmd_id,
 930                   uint32_t session_id)
 931 {
 932         int ret;
 933         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 934
 935         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
 936
 937         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 938                                  psp->fence_buf_mc_addr);
 939
 940         release_psp_cmd_buf(psp);
 941
 942         return ret;
 943 }
 944
 945 static int psp_xgmi_load(struct psp_context *psp)
 946 {
 947         int ret;
 948         struct psp_gfx_cmd_resp *cmd;
 949
 950         /*
 951          * TODO: bypass the loading in sriov for now
 952          */
 953
 954         cmd = acquire_psp_cmd_buf(psp);
 955
 956         psp_copy_fw(psp, psp->xgmi.start_addr, psp->xgmi.size_bytes);
 957
 958         psp_prep_ta_load_cmd_buf(cmd,
 959                                  psp->fw_pri_mc_addr,
 960                                  psp->xgmi.size_bytes,
 961                                  psp->xgmi_context.context.mem_context.shared_mc_addr,
 962                                  PSP_XGMI_SHARED_MEM_SIZE);
 963
 964         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 965                                  psp->fence_buf_mc_addr);
 966
 967         if (!ret) {
 968                 psp->xgmi_context.context.initialized = true;
 969                 psp->xgmi_context.context.session_id = cmd->resp.session_id;
 970         }
 971
 972         release_psp_cmd_buf(psp);
 973
 974         return ret;
 975 }
 976
 977 static int psp_xgmi_unload(struct psp_context *psp)
 978 {
 979         int ret;
 980         struct psp_gfx_cmd_resp *cmd;
 981         struct amdgpu_device *adev = psp->adev;
 982
 983         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
 984         if (adev->asic_type == CHIP_ARCTURUS ||
 985                 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
 986                 return 0;
 987
 988         /*
 989          * TODO: bypass the unloading in sriov for now
 990          */
 991
 992         cmd = acquire_psp_cmd_buf(psp);
 993
 994         psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.context.session_id);
 995
 996         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 997                                  psp->fence_buf_mc_addr);
 998
 999         release_psp_cmd_buf(psp);
1000
1001         return ret;
1002 }
1003
1004 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1005 {
1006         return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.context.session_id);
1007 }
1008
1009 int psp_xgmi_terminate(struct psp_context *psp)
1010 {
1011         int ret;
1012
1013         if (!psp->xgmi_context.context.initialized)
1014                 return 0;
1015
1016         ret = psp_xgmi_unload(psp);
1017         if (ret)
1018                 return ret;
1019
1020         psp->xgmi_context.context.initialized = false;
1021
1022         /* free xgmi shared memory */
1023         amdgpu_bo_free_kernel(&psp->xgmi_context.context.mem_context.shared_bo,
1024                         &psp->xgmi_context.context.mem_context.shared_mc_addr,
1025                         &psp->xgmi_context.context.mem_context.shared_buf);
1026
1027         return 0;
1028 }
1029
1030 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1031 {
1032         struct ta_xgmi_shared_memory *xgmi_cmd;
1033         int ret;
1034
1035         if (!psp->ta_fw ||
1036             !psp->xgmi.size_bytes ||
1037             !psp->xgmi.start_addr)
1038                 return -ENOENT;
1039
1040         if (!load_ta)
1041                 goto invoke;
1042
1043         if (!psp->xgmi_context.context.initialized) {
1044                 ret = psp_xgmi_init_shared_buf(psp);
1045                 if (ret)
1046                         return ret;
1047         }
1048
1049         /* Load XGMI TA */
1050         ret = psp_xgmi_load(psp);
1051         if (ret)
1052                 return ret;
1053
1054 invoke:
1055         /* Initialize XGMI session */
1056         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1057         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1058         xgmi_cmd->flag_extend_link_record = set_extended_data;
1059         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1060
1061         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1062
1063         return ret;
1064 }
1065
1066 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1067 {
1068         struct ta_xgmi_shared_memory *xgmi_cmd;
1069         int ret;
1070
1071         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1072         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1073
1074         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1075
1076         /* Invoke xgmi ta to get hive id */
1077         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1078         if (ret)
1079                 return ret;
1080
1081         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1082
1083         return 0;
1084 }
1085
1086 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1087 {
1088         struct ta_xgmi_shared_memory *xgmi_cmd;
1089         int ret;
1090
1091         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1092         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1093
1094         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1095
1096         /* Invoke xgmi ta to get the node id */
1097         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1098         if (ret)
1099                 return ret;
1100
1101         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1102
1103         return 0;
1104 }
1105
1106 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1107 {
1108         return psp->adev->asic_type == CHIP_ALDEBARAN &&
1109                                 psp->xgmi.feature_version >= 0x2000000b;
1110 }
1111
1112 /*
1113  * Chips that support extended topology information require the driver to
1114  * reflect topology information in the opposite direction.  This is
1115  * because the TA has already exceeded its link record limit and if the
1116  * TA holds bi-directional information, the driver would have to do
1117  * multiple fetches instead of just two.
1118  */
1119 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1120                                         struct psp_xgmi_node_info node_info)
1121 {
1122         struct amdgpu_device *mirror_adev;
1123         struct amdgpu_hive_info *hive;
1124         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1125         uint64_t dst_node_id = node_info.node_id;
1126         uint8_t dst_num_hops = node_info.num_hops;
1127         uint8_t dst_num_links = node_info.num_links;
1128
1129         hive = amdgpu_get_xgmi_hive(psp->adev);
1130         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1131                 struct psp_xgmi_topology_info *mirror_top_info;
1132                 int j;
1133
1134                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1135                         continue;
1136
1137                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1138                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1139                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1140                                 continue;
1141
1142                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1143                         /*
1144                          * prevent 0 num_links value re-reflection since reflection
1145                          * criteria is based on num_hops (direct or indirect).
1146                          *
1147                          */
1148                         if (dst_num_links)
1149                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1150
1151                         break;
1152                 }
1153
1154                 break;
1155         }
1156 }
1157
1158 int psp_xgmi_get_topology_info(struct psp_context *psp,
1159                                int number_devices,
1160                                struct psp_xgmi_topology_info *topology,
1161                                bool get_extended_data)
1162 {
1163         struct ta_xgmi_shared_memory *xgmi_cmd;
1164         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1165         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1166         int i;
1167         int ret;
1168
1169         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1170                 return -EINVAL;
1171
1172         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1173         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1174         xgmi_cmd->flag_extend_link_record = get_extended_data;
1175
1176         /* Fill in the shared memory with topology information as input */
1177         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1178         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1179         topology_info_input->num_nodes = number_devices;
1180
1181         for (i = 0; i < topology_info_input->num_nodes; i++) {
1182                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1183                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1184                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1185                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1186         }
1187
1188         /* Invoke xgmi ta to get the topology information */
1189         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1190         if (ret)
1191                 return ret;
1192
1193         /* Read the output topology information from the shared memory */
1194         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1195         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1196         for (i = 0; i < topology->num_nodes; i++) {
1197                 /* extended data will either be 0 or equal to non-extended data */
1198                 if (topology_info_output->nodes[i].num_hops)
1199                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1200
1201                 /* non-extended data gets everything here so no need to update */
1202                 if (!get_extended_data) {
1203                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1204                         topology->nodes[i].is_sharing_enabled =
1205                                         topology_info_output->nodes[i].is_sharing_enabled;
1206                         topology->nodes[i].sdma_engine =
1207                                         topology_info_output->nodes[i].sdma_engine;
1208                 }
1209
1210         }
1211
1212         /* Invoke xgmi ta again to get the link information */
1213         if (psp_xgmi_peer_link_info_supported(psp)) {
1214                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1215
1216                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1217
1218                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1219
1220                 if (ret)
1221                         return ret;
1222
1223                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1224                 for (i = 0; i < topology->num_nodes; i++) {
1225                         /* accumulate num_links on extended data */
1226                         topology->nodes[i].num_links = get_extended_data ?
1227                                         topology->nodes[i].num_links +
1228                                                         link_info_output->nodes[i].num_links :
1229                                         link_info_output->nodes[i].num_links;
1230
1231                         /* reflect the topology information for bi-directionality */
1232                         if (psp->xgmi_context.supports_extended_data &&
1233                                         get_extended_data && topology->nodes[i].num_hops)
1234                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1235                 }
1236         }
1237
1238         return 0;
1239 }
1240
1241 int psp_xgmi_set_topology_info(struct psp_context *psp,
1242                                int number_devices,
1243                                struct psp_xgmi_topology_info *topology)
1244 {
1245         struct ta_xgmi_shared_memory *xgmi_cmd;
1246         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1247         int i;
1248
1249         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1250                 return -EINVAL;
1251
1252         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1253         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1254
1255         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1256         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1257         topology_info_input->num_nodes = number_devices;
1258
1259         for (i = 0; i < topology_info_input->num_nodes; i++) {
1260                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1261                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1262                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1263                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1264         }
1265
1266         /* Invoke xgmi ta to set topology information */
1267         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1268 }
1269
1270 // ras begin
1271 static int psp_ras_init_shared_buf(struct psp_context *psp)
1272 {
1273         int ret;
1274
1275         /*
1276          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1277          * physical) for ras ta <-> Driver
1278          */
1279         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
1280                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1281                         &psp->ras_context.context.mem_context.shared_bo,
1282                         &psp->ras_context.context.mem_context.shared_mc_addr,
1283                         &psp->ras_context.context.mem_context.shared_buf);
1284
1285         return ret;
1286 }
1287
1288 static int psp_ras_load(struct psp_context *psp)
1289 {
1290         int ret;
1291         struct psp_gfx_cmd_resp *cmd;
1292         struct ta_ras_shared_memory *ras_cmd;
1293
1294         /*
1295          * TODO: bypass the loading in sriov for now
1296          */
1297         if (amdgpu_sriov_vf(psp->adev))
1298                 return 0;
1299
1300         psp_copy_fw(psp, psp->ras.start_addr, psp->ras.size_bytes);
1301
1302         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1303
1304         if (psp->adev->gmc.xgmi.connected_to_cpu)
1305                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1306         else
1307                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1308
1309         cmd = acquire_psp_cmd_buf(psp);
1310
1311         psp_prep_ta_load_cmd_buf(cmd,
1312                                  psp->fw_pri_mc_addr,
1313                                  psp->ras.size_bytes,
1314                                  psp->ras_context.context.mem_context.shared_mc_addr,
1315                                  PSP_RAS_SHARED_MEM_SIZE);
1316
1317         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1318                         psp->fence_buf_mc_addr);
1319
1320         if (!ret) {
1321                 psp->ras_context.context.session_id = cmd->resp.session_id;
1322
1323                 if (!ras_cmd->ras_status)
1324                         psp->ras_context.context.initialized = true;
1325                 else
1326                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1327         }
1328
1329         release_psp_cmd_buf(psp);
1330
1331         if (ret || ras_cmd->ras_status)
1332                 amdgpu_ras_fini(psp->adev);
1333
1334         return ret;
1335 }
1336
1337 static int psp_ras_unload(struct psp_context *psp)
1338 {
1339         int ret;
1340         struct psp_gfx_cmd_resp *cmd;
1341
1342         /*
1343          * TODO: bypass the unloading in sriov for now
1344          */
1345         if (amdgpu_sriov_vf(psp->adev))
1346                 return 0;
1347
1348         cmd = acquire_psp_cmd_buf(psp);
1349
1350         psp_prep_ta_unload_cmd_buf(cmd, psp->ras_context.context.session_id);
1351
1352         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1353                         psp->fence_buf_mc_addr);
1354
1355         release_psp_cmd_buf(psp);
1356
1357         return ret;
1358 }
1359
1360 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1361 {
1362         struct ta_ras_shared_memory *ras_cmd;
1363         int ret;
1364
1365         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1366
1367         /*
1368          * TODO: bypass the loading in sriov for now
1369          */
1370         if (amdgpu_sriov_vf(psp->adev))
1371                 return 0;
1372
1373         ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras_context.context.session_id);
1374
1375         if (amdgpu_ras_intr_triggered())
1376                 return ret;
1377
1378         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1379         {
1380                 DRM_WARN("RAS: Unsupported Interface");
1381                 return -EINVAL;
1382         }
1383
1384         if (!ret) {
1385                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1386                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1387
1388                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1389                 }
1390                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1391                         dev_warn(psp->adev->dev,
1392                                  "RAS internal register access blocked\n");
1393         }
1394
1395         return ret;
1396 }
1397
1398 static int psp_ras_status_to_errno(struct amdgpu_device *adev,
1399                                          enum ta_ras_status ras_status)
1400 {
1401         int ret = -EINVAL;
1402
1403         switch (ras_status) {
1404         case TA_RAS_STATUS__SUCCESS:
1405                 ret = 0;
1406                 break;
1407         case TA_RAS_STATUS__RESET_NEEDED:
1408                 ret = -EAGAIN;
1409                 break;
1410         case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE:
1411                 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n");
1412                 break;
1413         case TA_RAS_STATUS__ERROR_ASD_READ_WRITE:
1414                 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n");
1415                 break;
1416         default:
1417                 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret);
1418         }
1419
1420         return ret;
1421 }
1422
1423 int psp_ras_enable_features(struct psp_context *psp,
1424                 union ta_ras_cmd_input *info, bool enable)
1425 {
1426         struct ta_ras_shared_memory *ras_cmd;
1427         int ret;
1428
1429         if (!psp->ras_context.context.initialized)
1430                 return -EINVAL;
1431
1432         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1433         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1434
1435         if (enable)
1436                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1437         else
1438                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1439
1440         ras_cmd->ras_in_message = *info;
1441
1442         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1443         if (ret)
1444                 return -EINVAL;
1445
1446         return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1447 }
1448
1449 static int psp_ras_terminate(struct psp_context *psp)
1450 {
1451         int ret;
1452
1453         /*
1454          * TODO: bypass the terminate in sriov for now
1455          */
1456         if (amdgpu_sriov_vf(psp->adev))
1457                 return 0;
1458
1459         if (!psp->ras_context.context.initialized)
1460                 return 0;
1461
1462         ret = psp_ras_unload(psp);
1463         if (ret)
1464                 return ret;
1465
1466         psp->ras_context.context.initialized = false;
1467
1468         /* free ras shared memory */
1469         amdgpu_bo_free_kernel(&psp->ras_context.context.mem_context.shared_bo,
1470                         &psp->ras_context.context.mem_context.shared_mc_addr,
1471                         &psp->ras_context.context.mem_context.shared_buf);
1472
1473         return 0;
1474 }
1475
1476 static int psp_ras_initialize(struct psp_context *psp)
1477 {
1478         int ret;
1479         uint32_t boot_cfg = 0xFF;
1480         struct amdgpu_device *adev = psp->adev;
1481
1482         /*
1483          * TODO: bypass the initialize in sriov for now
1484          */
1485         if (amdgpu_sriov_vf(adev))
1486                 return 0;
1487
1488         if (!adev->psp.ras.size_bytes ||
1489             !adev->psp.ras.start_addr) {
1490                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1491                 return 0;
1492         }
1493
1494         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1495                 /* query GECC enablement status from boot config
1496                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1497                  */
1498                 ret = psp_boot_config_get(adev, &boot_cfg);
1499                 if (ret)
1500                         dev_warn(adev->dev, "PSP get boot config failed\n");
1501
1502                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1503                         if (!boot_cfg) {
1504                                 dev_info(adev->dev, "GECC is disabled\n");
1505                         } else {
1506                                 /* disable GECC in next boot cycle if ras is
1507                                  * disabled by module parameter amdgpu_ras_enable
1508                                  * and/or amdgpu_ras_mask, or boot_config_get call
1509                                  * is failed
1510                                  */
1511                                 ret = psp_boot_config_set(adev, 0);
1512                                 if (ret)
1513                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1514                                 else
1515                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1516                                                  "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1517                         }
1518                 } else {
1519                         if (1 == boot_cfg) {
1520                                 dev_info(adev->dev, "GECC is enabled\n");
1521                         } else {
1522                                 /* enable GECC in next boot cycle if it is disabled
1523                                  * in boot config, or force enable GECC if failed to
1524                                  * get boot configuration
1525                                  */
1526                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1527                                 if (ret)
1528                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1529                                 else
1530                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1531                         }
1532                 }
1533         }
1534
1535         if (!psp->ras_context.context.initialized) {
1536                 ret = psp_ras_init_shared_buf(psp);
1537                 if (ret)
1538                         return ret;
1539         }
1540
1541         ret = psp_ras_load(psp);
1542         if (ret)
1543                 return ret;
1544
1545         return 0;
1546 }
1547
1548 int psp_ras_trigger_error(struct psp_context *psp,
1549                           struct ta_ras_trigger_error_input *info)
1550 {
1551         struct ta_ras_shared_memory *ras_cmd;
1552         int ret;
1553
1554         if (!psp->ras_context.context.initialized)
1555                 return -EINVAL;
1556
1557         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1558         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1559
1560         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1561         ras_cmd->ras_in_message.trigger_error = *info;
1562
1563         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1564         if (ret)
1565                 return -EINVAL;
1566
1567         /* If err_event_athub occurs error inject was successful, however
1568            return status from TA is no long reliable */
1569         if (amdgpu_ras_intr_triggered())
1570                 return 0;
1571
1572         return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status);
1573 }
1574 // ras end
1575
1576 // HDCP start
1577 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1578 {
1579         int ret;
1580
1581         /*
1582          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1583          * physical) for hdcp ta <-> Driver
1584          */
1585         ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1586                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1587                                       &psp->hdcp_context.context.mem_context.shared_bo,
1588                                       &psp->hdcp_context.context.mem_context.shared_mc_addr,
1589                                       &psp->hdcp_context.context.mem_context.shared_buf);
1590
1591         return ret;
1592 }
1593
1594 static int psp_hdcp_load(struct psp_context *psp)
1595 {
1596         int ret;
1597         struct psp_gfx_cmd_resp *cmd;
1598
1599         /*
1600          * TODO: bypass the loading in sriov for now
1601          */
1602         if (amdgpu_sriov_vf(psp->adev))
1603                 return 0;
1604
1605         psp_copy_fw(psp, psp->hdcp.start_addr,
1606                     psp->hdcp.size_bytes);
1607
1608         cmd = acquire_psp_cmd_buf(psp);
1609
1610         psp_prep_ta_load_cmd_buf(cmd,
1611                                  psp->fw_pri_mc_addr,
1612                                  psp->hdcp.size_bytes,
1613                                  psp->hdcp_context.context.mem_context.shared_mc_addr,
1614                                  PSP_HDCP_SHARED_MEM_SIZE);
1615
1616         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1617
1618         if (!ret) {
1619                 psp->hdcp_context.context.initialized = true;
1620                 psp->hdcp_context.context.session_id = cmd->resp.session_id;
1621                 mutex_init(&psp->hdcp_context.mutex);
1622         }
1623
1624         release_psp_cmd_buf(psp);
1625
1626         return ret;
1627 }
1628 static int psp_hdcp_initialize(struct psp_context *psp)
1629 {
1630         int ret;
1631
1632         /*
1633          * TODO: bypass the initialize in sriov for now
1634          */
1635         if (amdgpu_sriov_vf(psp->adev))
1636                 return 0;
1637
1638         if (!psp->hdcp.size_bytes ||
1639             !psp->hdcp.start_addr) {
1640                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1641                 return 0;
1642         }
1643
1644         if (!psp->hdcp_context.context.initialized) {
1645                 ret = psp_hdcp_init_shared_buf(psp);
1646                 if (ret)
1647                         return ret;
1648         }
1649
1650         ret = psp_hdcp_load(psp);
1651         if (ret)
1652                 return ret;
1653
1654         return 0;
1655 }
1656
1657 static int psp_hdcp_unload(struct psp_context *psp)
1658 {
1659         int ret;
1660         struct psp_gfx_cmd_resp *cmd;
1661
1662         /*
1663          * TODO: bypass the unloading in sriov for now
1664          */
1665         if (amdgpu_sriov_vf(psp->adev))
1666                 return 0;
1667
1668         cmd = acquire_psp_cmd_buf(psp);
1669
1670         psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.context.session_id);
1671
1672         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1673
1674         release_psp_cmd_buf(psp);
1675
1676         return ret;
1677 }
1678
1679 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1680 {
1681         /*
1682          * TODO: bypass the loading in sriov for now
1683          */
1684         if (amdgpu_sriov_vf(psp->adev))
1685                 return 0;
1686
1687         return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.context.session_id);
1688 }
1689
1690 static int psp_hdcp_terminate(struct psp_context *psp)
1691 {
1692         int ret;
1693
1694         /*
1695          * TODO: bypass the terminate in sriov for now
1696          */
1697         if (amdgpu_sriov_vf(psp->adev))
1698                 return 0;
1699
1700         if (!psp->hdcp_context.context.initialized) {
1701                 if (psp->hdcp_context.context.mem_context.shared_buf)
1702                         goto out;
1703                 else
1704                         return 0;
1705         }
1706
1707         ret = psp_hdcp_unload(psp);
1708         if (ret)
1709                 return ret;
1710
1711         psp->hdcp_context.context.initialized = false;
1712
1713 out:
1714         /* free hdcp shared memory */
1715         amdgpu_bo_free_kernel(&psp->hdcp_context.context.mem_context.shared_bo,
1716                               &psp->hdcp_context.context.mem_context.shared_mc_addr,
1717                               &psp->hdcp_context.context.mem_context.shared_buf);
1718
1719         return 0;
1720 }
1721 // HDCP end
1722
1723 // DTM start
1724 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1725 {
1726         int ret;
1727
1728         /*
1729          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1730          * physical) for dtm ta <-> Driver
1731          */
1732         ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1733                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1734                                       &psp->dtm_context.context.mem_context.shared_bo,
1735                                       &psp->dtm_context.context.mem_context.shared_mc_addr,
1736                                       &psp->dtm_context.context.mem_context.shared_buf);
1737
1738         return ret;
1739 }
1740
1741 static int psp_dtm_load(struct psp_context *psp)
1742 {
1743         int ret;
1744         struct psp_gfx_cmd_resp *cmd;
1745
1746         /*
1747          * TODO: bypass the loading in sriov for now
1748          */
1749         if (amdgpu_sriov_vf(psp->adev))
1750                 return 0;
1751
1752         psp_copy_fw(psp, psp->dtm.start_addr, psp->dtm.size_bytes);
1753
1754         cmd = acquire_psp_cmd_buf(psp);
1755
1756         psp_prep_ta_load_cmd_buf(cmd,
1757                                  psp->fw_pri_mc_addr,
1758                                  psp->dtm.size_bytes,
1759                                  psp->dtm_context.context.mem_context.shared_mc_addr,
1760                                  PSP_DTM_SHARED_MEM_SIZE);
1761
1762         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1763
1764         if (!ret) {
1765                 psp->dtm_context.context.initialized = true;
1766                 psp->dtm_context.context.session_id = cmd->resp.session_id;
1767                 mutex_init(&psp->dtm_context.mutex);
1768         }
1769
1770         release_psp_cmd_buf(psp);
1771
1772         return ret;
1773 }
1774
1775 static int psp_dtm_initialize(struct psp_context *psp)
1776 {
1777         int ret;
1778
1779         /*
1780          * TODO: bypass the initialize in sriov for now
1781          */
1782         if (amdgpu_sriov_vf(psp->adev))
1783                 return 0;
1784
1785         if (!psp->dtm.size_bytes ||
1786             !psp->dtm.start_addr) {
1787                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1788                 return 0;
1789         }
1790
1791         if (!psp->dtm_context.context.initialized) {
1792                 ret = psp_dtm_init_shared_buf(psp);
1793                 if (ret)
1794                         return ret;
1795         }
1796
1797         ret = psp_dtm_load(psp);
1798         if (ret)
1799                 return ret;
1800
1801         return 0;
1802 }
1803
1804 static int psp_dtm_unload(struct psp_context *psp)
1805 {
1806         int ret;
1807         struct psp_gfx_cmd_resp *cmd;
1808
1809         /*
1810          * TODO: bypass the unloading in sriov for now
1811          */
1812         if (amdgpu_sriov_vf(psp->adev))
1813                 return 0;
1814
1815         cmd = acquire_psp_cmd_buf(psp);
1816
1817         psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.context.session_id);
1818
1819         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1820
1821         release_psp_cmd_buf(psp);
1822
1823         return ret;
1824 }
1825
1826 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1827 {
1828         /*
1829          * TODO: bypass the loading in sriov for now
1830          */
1831         if (amdgpu_sriov_vf(psp->adev))
1832                 return 0;
1833
1834         return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.context.session_id);
1835 }
1836
1837 static int psp_dtm_terminate(struct psp_context *psp)
1838 {
1839         int ret;
1840
1841         /*
1842          * TODO: bypass the terminate in sriov for now
1843          */
1844         if (amdgpu_sriov_vf(psp->adev))
1845                 return 0;
1846
1847         if (!psp->dtm_context.context.initialized) {
1848                 if (psp->dtm_context.context.mem_context.shared_buf)
1849                         goto out;
1850                 else
1851                         return 0;
1852         }
1853
1854         ret = psp_dtm_unload(psp);
1855         if (ret)
1856                 return ret;
1857
1858         psp->dtm_context.context.initialized = false;
1859
1860 out:
1861         /* free hdcp shared memory */
1862         amdgpu_bo_free_kernel(&psp->dtm_context.context.mem_context.shared_bo,
1863                               &psp->dtm_context.context.mem_context.shared_mc_addr,
1864                               &psp->dtm_context.context.mem_context.shared_buf);
1865
1866         return 0;
1867 }
1868 // DTM end
1869
1870 // RAP start
1871 static int psp_rap_init_shared_buf(struct psp_context *psp)
1872 {
1873         int ret;
1874
1875         /*
1876          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1877          * physical) for rap ta <-> Driver
1878          */
1879         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1880                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1881                                       &psp->rap_context.context.mem_context.shared_bo,
1882                                       &psp->rap_context.context.mem_context.shared_mc_addr,
1883                                       &psp->rap_context.context.mem_context.shared_buf);
1884
1885         return ret;
1886 }
1887
1888 static int psp_rap_load(struct psp_context *psp)
1889 {
1890         int ret;
1891         struct psp_gfx_cmd_resp *cmd;
1892
1893         psp_copy_fw(psp, psp->rap.start_addr, psp->rap.size_bytes);
1894
1895         cmd = acquire_psp_cmd_buf(psp);
1896
1897         psp_prep_ta_load_cmd_buf(cmd,
1898                                  psp->fw_pri_mc_addr,
1899                                  psp->rap.size_bytes,
1900                                  psp->rap_context.context.mem_context.shared_mc_addr,
1901                                  PSP_RAP_SHARED_MEM_SIZE);
1902
1903         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1904
1905         if (!ret) {
1906                 psp->rap_context.context.initialized = true;
1907                 psp->rap_context.context.session_id = cmd->resp.session_id;
1908                 mutex_init(&psp->rap_context.mutex);
1909         }
1910
1911         release_psp_cmd_buf(psp);
1912
1913         return ret;
1914 }
1915
1916 static int psp_rap_unload(struct psp_context *psp)
1917 {
1918         int ret;
1919         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1920
1921         psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.context.session_id);
1922
1923         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1924
1925         release_psp_cmd_buf(psp);
1926
1927         return ret;
1928 }
1929
1930 static int psp_rap_initialize(struct psp_context *psp)
1931 {
1932         int ret;
1933         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1934
1935         /*
1936          * TODO: bypass the initialize in sriov for now
1937          */
1938         if (amdgpu_sriov_vf(psp->adev))
1939                 return 0;
1940
1941         if (!psp->rap.size_bytes ||
1942             !psp->rap.start_addr) {
1943                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1944                 return 0;
1945         }
1946
1947         if (!psp->rap_context.context.initialized) {
1948                 ret = psp_rap_init_shared_buf(psp);
1949                 if (ret)
1950                         return ret;
1951         }
1952
1953         ret = psp_rap_load(psp);
1954         if (ret)
1955                 return ret;
1956
1957         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1958         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1959                 psp_rap_unload(psp);
1960
1961                 amdgpu_bo_free_kernel(&psp->rap_context.context.mem_context.shared_bo,
1962                               &psp->rap_context.context.mem_context.shared_mc_addr,
1963                               &psp->rap_context.context.mem_context.shared_buf);
1964
1965                 psp->rap_context.context.initialized = false;
1966
1967                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1968                          ret, status);
1969
1970                 return ret;
1971         }
1972
1973         return 0;
1974 }
1975
1976 static int psp_rap_terminate(struct psp_context *psp)
1977 {
1978         int ret;
1979
1980         if (!psp->rap_context.context.initialized)
1981                 return 0;
1982
1983         ret = psp_rap_unload(psp);
1984
1985         psp->rap_context.context.initialized = false;
1986
1987         /* free rap shared memory */
1988         amdgpu_bo_free_kernel(&psp->rap_context.context.mem_context.shared_bo,
1989                               &psp->rap_context.context.mem_context.shared_mc_addr,
1990                               &psp->rap_context.context.mem_context.shared_buf);
1991
1992         return ret;
1993 }
1994
1995 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1996 {
1997         struct ta_rap_shared_memory *rap_cmd;
1998         int ret = 0;
1999
2000         if (!psp->rap_context.context.initialized)
2001                 return 0;
2002
2003         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
2004             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
2005                 return -EINVAL;
2006
2007         mutex_lock(&psp->rap_context.mutex);
2008
2009         rap_cmd = (struct ta_rap_shared_memory *)
2010                   psp->rap_context.context.mem_context.shared_buf;
2011         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
2012
2013         rap_cmd->cmd_id = ta_cmd_id;
2014         rap_cmd->validation_method_id = METHOD_A;
2015
2016         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.context.session_id);
2017         if (ret)
2018                 goto out_unlock;
2019
2020         if (status)
2021                 *status = rap_cmd->rap_status;
2022
2023 out_unlock:
2024         mutex_unlock(&psp->rap_context.mutex);
2025
2026         return ret;
2027 }
2028 // RAP end
2029
2030 /* securedisplay start */
2031 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
2032 {
2033         int ret;
2034
2035         /*
2036          * Allocate 16k memory aligned to 4k from Frame Buffer (local
2037          * physical) for sa ta <-> Driver
2038          */
2039         ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE,
2040                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
2041                                       &psp->securedisplay_context.context.mem_context.shared_bo,
2042                                       &psp->securedisplay_context.context.mem_context.shared_mc_addr,
2043                                       &psp->securedisplay_context.context.mem_context.shared_buf);
2044
2045         return ret;
2046 }
2047
2048 static int psp_securedisplay_load(struct psp_context *psp)
2049 {
2050         int ret;
2051         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2052
2053         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
2054         memcpy(psp->fw_pri_buf, psp->securedisplay.start_addr, psp->securedisplay.size_bytes);
2055
2056         psp_prep_ta_load_cmd_buf(cmd,
2057                                  psp->fw_pri_mc_addr,
2058                                  psp->securedisplay.size_bytes,
2059                                  psp->securedisplay_context.context.mem_context.shared_mc_addr,
2060                                  PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
2061
2062         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
2063
2064         if (!ret) {
2065                 psp->securedisplay_context.context.initialized = true;
2066                 psp->securedisplay_context.context.session_id = cmd->resp.session_id;
2067                 mutex_init(&psp->securedisplay_context.mutex);
2068         }
2069
2070         release_psp_cmd_buf(psp);
2071
2072         return ret;
2073 }
2074
2075 static int psp_securedisplay_unload(struct psp_context *psp)
2076 {
2077         int ret;
2078         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2079
2080         psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.context.session_id);
2081
2082         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
2083
2084         release_psp_cmd_buf(psp);
2085
2086         return ret;
2087 }
2088
2089 static int psp_securedisplay_initialize(struct psp_context *psp)
2090 {
2091         int ret;
2092         struct securedisplay_cmd *securedisplay_cmd;
2093
2094         /*
2095          * TODO: bypass the initialize in sriov for now
2096          */
2097         if (amdgpu_sriov_vf(psp->adev))
2098                 return 0;
2099
2100         if (!psp->securedisplay.size_bytes ||
2101             !psp->securedisplay.start_addr) {
2102                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
2103                 return 0;
2104         }
2105
2106         if (!psp->securedisplay_context.context.initialized) {
2107                 ret = psp_securedisplay_init_shared_buf(psp);
2108                 if (ret)
2109                         return ret;
2110         }
2111
2112         ret = psp_securedisplay_load(psp);
2113         if (ret)
2114                 return ret;
2115
2116         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2117                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2118
2119         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2120         if (ret) {
2121                 psp_securedisplay_unload(psp);
2122
2123                 amdgpu_bo_free_kernel(&psp->securedisplay_context.context.mem_context.shared_bo,
2124                               &psp->securedisplay_context.context.mem_context.shared_mc_addr,
2125                               &psp->securedisplay_context.context.mem_context.shared_buf);
2126
2127                 psp->securedisplay_context.context.initialized = false;
2128
2129                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2130                 return -EINVAL;
2131         }
2132
2133         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2134                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2135                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2136                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2137         }
2138
2139         return 0;
2140 }
2141
2142 static int psp_securedisplay_terminate(struct psp_context *psp)
2143 {
2144         int ret;
2145
2146         /*
2147          * TODO:bypass the terminate in sriov for now
2148          */
2149         if (amdgpu_sriov_vf(psp->adev))
2150                 return 0;
2151
2152         if (!psp->securedisplay_context.context.initialized)
2153                 return 0;
2154
2155         ret = psp_securedisplay_unload(psp);
2156         if (ret)
2157                 return ret;
2158
2159         psp->securedisplay_context.context.initialized = false;
2160
2161         /* free securedisplay shared memory */
2162         amdgpu_bo_free_kernel(&psp->securedisplay_context.context.mem_context.shared_bo,
2163                               &psp->securedisplay_context.context.mem_context.shared_mc_addr,
2164                               &psp->securedisplay_context.context.mem_context.shared_buf);
2165
2166         return ret;
2167 }
2168
2169 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2170 {
2171         int ret;
2172
2173         if (!psp->securedisplay_context.context.initialized)
2174                 return -EINVAL;
2175
2176         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2177             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2178                 return -EINVAL;
2179
2180         mutex_lock(&psp->securedisplay_context.mutex);
2181
2182         ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.context.session_id);
2183
2184         mutex_unlock(&psp->securedisplay_context.mutex);
2185
2186         return ret;
2187 }
2188 /* SECUREDISPLAY end */
2189
2190 static int psp_hw_start(struct psp_context *psp)
2191 {
2192         struct amdgpu_device *adev = psp->adev;
2193         int ret;
2194
2195         if (!amdgpu_sriov_vf(adev)) {
2196                 if ((is_psp_fw_valid(psp->kdb)) &&
2197                     (psp->funcs->bootloader_load_kdb != NULL)) {
2198                         ret = psp_bootloader_load_kdb(psp);
2199                         if (ret) {
2200                                 DRM_ERROR("PSP load kdb failed!\n");
2201                                 return ret;
2202                         }
2203                 }
2204
2205                 if ((is_psp_fw_valid(psp->spl)) &&
2206                     (psp->funcs->bootloader_load_spl != NULL)) {
2207                         ret = psp_bootloader_load_spl(psp);
2208                         if (ret) {
2209                                 DRM_ERROR("PSP load spl failed!\n");
2210                                 return ret;
2211                         }
2212                 }
2213
2214                 if ((is_psp_fw_valid(psp->sys)) &&
2215                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2216                         ret = psp_bootloader_load_sysdrv(psp);
2217                         if (ret) {
2218                                 DRM_ERROR("PSP load sys drv failed!\n");
2219                                 return ret;
2220                         }
2221                 }
2222
2223                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2224                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2225                         ret = psp_bootloader_load_soc_drv(psp);
2226                         if (ret) {
2227                                 DRM_ERROR("PSP load soc drv failed!\n");
2228                                 return ret;
2229                         }
2230                 }
2231
2232                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2233                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2234                         ret = psp_bootloader_load_intf_drv(psp);
2235                         if (ret) {
2236                                 DRM_ERROR("PSP load intf drv failed!\n");
2237                                 return ret;
2238                         }
2239                 }
2240
2241                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2242                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2243                         ret = psp_bootloader_load_dbg_drv(psp);
2244                         if (ret) {
2245                                 DRM_ERROR("PSP load dbg drv failed!\n");
2246                                 return ret;
2247                         }
2248                 }
2249
2250                 if ((is_psp_fw_valid(psp->sos)) &&
2251                     (psp->funcs->bootloader_load_sos != NULL)) {
2252                         ret = psp_bootloader_load_sos(psp);
2253                         if (ret) {
2254                                 DRM_ERROR("PSP load sos failed!\n");
2255                                 return ret;
2256                         }
2257                 }
2258         }
2259
2260         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2261         if (ret) {
2262                 DRM_ERROR("PSP create ring failed!\n");
2263                 return ret;
2264         }
2265
2266         ret = psp_tmr_init(psp);
2267         if (ret) {
2268                 DRM_ERROR("PSP tmr init failed!\n");
2269                 return ret;
2270         }
2271
2272         /*
2273          * For ASICs with DF Cstate management centralized
2274          * to PMFW, TMR setup should be performed after PMFW
2275          * loaded and before other non-psp firmware loaded.
2276          */
2277         if (psp->pmfw_centralized_cstate_management) {
2278                 ret = psp_load_smu_fw(psp);
2279                 if (ret)
2280                         return ret;
2281         }
2282
2283         ret = psp_tmr_load(psp);
2284         if (ret) {
2285                 DRM_ERROR("PSP load tmr failed!\n");
2286                 return ret;
2287         }
2288
2289         return 0;
2290 }
2291
2292 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2293                            enum psp_gfx_fw_type *type)
2294 {
2295         switch (ucode->ucode_id) {
2296         case AMDGPU_UCODE_ID_SDMA0:
2297                 *type = GFX_FW_TYPE_SDMA0;
2298                 break;
2299         case AMDGPU_UCODE_ID_SDMA1:
2300                 *type = GFX_FW_TYPE_SDMA1;
2301                 break;
2302         case AMDGPU_UCODE_ID_SDMA2:
2303                 *type = GFX_FW_TYPE_SDMA2;
2304                 break;
2305         case AMDGPU_UCODE_ID_SDMA3:
2306                 *type = GFX_FW_TYPE_SDMA3;
2307                 break;
2308         case AMDGPU_UCODE_ID_SDMA4:
2309                 *type = GFX_FW_TYPE_SDMA4;
2310                 break;
2311         case AMDGPU_UCODE_ID_SDMA5:
2312                 *type = GFX_FW_TYPE_SDMA5;
2313                 break;
2314         case AMDGPU_UCODE_ID_SDMA6:
2315                 *type = GFX_FW_TYPE_SDMA6;
2316                 break;
2317         case AMDGPU_UCODE_ID_SDMA7:
2318                 *type = GFX_FW_TYPE_SDMA7;
2319                 break;
2320         case AMDGPU_UCODE_ID_CP_MES:
2321                 *type = GFX_FW_TYPE_CP_MES;
2322                 break;
2323         case AMDGPU_UCODE_ID_CP_MES_DATA:
2324                 *type = GFX_FW_TYPE_MES_STACK;
2325                 break;
2326         case AMDGPU_UCODE_ID_CP_CE:
2327                 *type = GFX_FW_TYPE_CP_CE;
2328                 break;
2329         case AMDGPU_UCODE_ID_CP_PFP:
2330                 *type = GFX_FW_TYPE_CP_PFP;
2331                 break;
2332         case AMDGPU_UCODE_ID_CP_ME:
2333                 *type = GFX_FW_TYPE_CP_ME;
2334                 break;
2335         case AMDGPU_UCODE_ID_CP_MEC1:
2336                 *type = GFX_FW_TYPE_CP_MEC;
2337                 break;
2338         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2339                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2340                 break;
2341         case AMDGPU_UCODE_ID_CP_MEC2:
2342                 *type = GFX_FW_TYPE_CP_MEC;
2343                 break;
2344         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2345                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2346                 break;
2347         case AMDGPU_UCODE_ID_RLC_G:
2348                 *type = GFX_FW_TYPE_RLC_G;
2349                 break;
2350         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2351                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2352                 break;
2353         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2354                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2355                 break;
2356         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2357                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2358                 break;
2359         case AMDGPU_UCODE_ID_RLC_IRAM:
2360                 *type = GFX_FW_TYPE_RLC_IRAM;
2361                 break;
2362         case AMDGPU_UCODE_ID_RLC_DRAM:
2363                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2364                 break;
2365         case AMDGPU_UCODE_ID_SMC:
2366                 *type = GFX_FW_TYPE_SMU;
2367                 break;
2368         case AMDGPU_UCODE_ID_UVD:
2369                 *type = GFX_FW_TYPE_UVD;
2370                 break;
2371         case AMDGPU_UCODE_ID_UVD1:
2372                 *type = GFX_FW_TYPE_UVD1;
2373                 break;
2374         case AMDGPU_UCODE_ID_VCE:
2375                 *type = GFX_FW_TYPE_VCE;
2376                 break;
2377         case AMDGPU_UCODE_ID_VCN:
2378                 *type = GFX_FW_TYPE_VCN;
2379                 break;
2380         case AMDGPU_UCODE_ID_VCN1:
2381                 *type = GFX_FW_TYPE_VCN1;
2382                 break;
2383         case AMDGPU_UCODE_ID_DMCU_ERAM:
2384                 *type = GFX_FW_TYPE_DMCU_ERAM;
2385                 break;
2386         case AMDGPU_UCODE_ID_DMCU_INTV:
2387                 *type = GFX_FW_TYPE_DMCU_ISR;
2388                 break;
2389         case AMDGPU_UCODE_ID_VCN0_RAM:
2390                 *type = GFX_FW_TYPE_VCN0_RAM;
2391                 break;
2392         case AMDGPU_UCODE_ID_VCN1_RAM:
2393                 *type = GFX_FW_TYPE_VCN1_RAM;
2394                 break;
2395         case AMDGPU_UCODE_ID_DMCUB:
2396                 *type = GFX_FW_TYPE_DMUB;
2397                 break;
2398         case AMDGPU_UCODE_ID_MAXIMUM:
2399         default:
2400                 return -EINVAL;
2401         }
2402
2403         return 0;
2404 }
2405
2406 static void psp_print_fw_hdr(struct psp_context *psp,
2407                              struct amdgpu_firmware_info *ucode)
2408 {
2409         struct amdgpu_device *adev = psp->adev;
2410         struct common_firmware_header *hdr;
2411
2412         switch (ucode->ucode_id) {
2413         case AMDGPU_UCODE_ID_SDMA0:
2414         case AMDGPU_UCODE_ID_SDMA1:
2415         case AMDGPU_UCODE_ID_SDMA2:
2416         case AMDGPU_UCODE_ID_SDMA3:
2417         case AMDGPU_UCODE_ID_SDMA4:
2418         case AMDGPU_UCODE_ID_SDMA5:
2419         case AMDGPU_UCODE_ID_SDMA6:
2420         case AMDGPU_UCODE_ID_SDMA7:
2421                 hdr = (struct common_firmware_header *)
2422                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2423                 amdgpu_ucode_print_sdma_hdr(hdr);
2424                 break;
2425         case AMDGPU_UCODE_ID_CP_CE:
2426                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2427                 amdgpu_ucode_print_gfx_hdr(hdr);
2428                 break;
2429         case AMDGPU_UCODE_ID_CP_PFP:
2430                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2431                 amdgpu_ucode_print_gfx_hdr(hdr);
2432                 break;
2433         case AMDGPU_UCODE_ID_CP_ME:
2434                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2435                 amdgpu_ucode_print_gfx_hdr(hdr);
2436                 break;
2437         case AMDGPU_UCODE_ID_CP_MEC1:
2438                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2439                 amdgpu_ucode_print_gfx_hdr(hdr);
2440                 break;
2441         case AMDGPU_UCODE_ID_RLC_G:
2442                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2443                 amdgpu_ucode_print_rlc_hdr(hdr);
2444                 break;
2445         case AMDGPU_UCODE_ID_SMC:
2446                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2447                 amdgpu_ucode_print_smc_hdr(hdr);
2448                 break;
2449         default:
2450                 break;
2451         }
2452 }
2453
2454 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2455                                        struct psp_gfx_cmd_resp *cmd)
2456 {
2457         int ret;
2458         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2459
2460         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2461         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2462         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2463         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2464
2465         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2466         if (ret)
2467                 DRM_ERROR("Unknown firmware type\n");
2468
2469         return ret;
2470 }
2471
2472 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2473                                   struct amdgpu_firmware_info *ucode)
2474 {
2475         int ret = 0;
2476         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2477
2478         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2479         if (!ret) {
2480                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2481                                          psp->fence_buf_mc_addr);
2482         }
2483
2484         release_psp_cmd_buf(psp);
2485
2486         return ret;
2487 }
2488
2489 static int psp_load_smu_fw(struct psp_context *psp)
2490 {
2491         int ret;
2492         struct amdgpu_device *adev = psp->adev;
2493         struct amdgpu_firmware_info *ucode =
2494                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2495         struct amdgpu_ras *ras = psp->ras_context.ras;
2496
2497         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2498                 return 0;
2499
2500         if ((amdgpu_in_reset(adev) &&
2501              ras && adev->ras_enabled &&
2502              (adev->asic_type == CHIP_ARCTURUS ||
2503               adev->asic_type == CHIP_VEGA20))) {
2504                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2505                 if (ret) {
2506                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2507                 }
2508         }
2509
2510         ret = psp_execute_non_psp_fw_load(psp, ucode);
2511
2512         if (ret)
2513                 DRM_ERROR("PSP load smu failed!\n");
2514
2515         return ret;
2516 }
2517
2518 static bool fw_load_skip_check(struct psp_context *psp,
2519                                struct amdgpu_firmware_info *ucode)
2520 {
2521         if (!ucode->fw)
2522                 return true;
2523
2524         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2525             (psp_smu_reload_quirk(psp) ||
2526              psp->autoload_supported ||
2527              psp->pmfw_centralized_cstate_management))
2528                 return true;
2529
2530         if (amdgpu_sriov_vf(psp->adev) &&
2531            (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2532             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2533             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2534             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2535             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2536             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2537             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2538             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2539             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2540             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2541             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2542             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2543             || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2544                 /*skip ucode loading in SRIOV VF */
2545                 return true;
2546
2547         if (psp->autoload_supported &&
2548             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2549              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2550                 /* skip mec JT when autoload is enabled */
2551                 return true;
2552
2553         return false;
2554 }
2555
2556 int psp_load_fw_list(struct psp_context *psp,
2557                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2558 {
2559         int ret = 0, i;
2560         struct amdgpu_firmware_info *ucode;
2561
2562         for (i = 0; i < ucode_count; ++i) {
2563                 ucode = ucode_list[i];
2564                 psp_print_fw_hdr(psp, ucode);
2565                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2566                 if (ret)
2567                         return ret;
2568         }
2569         return ret;
2570 }
2571
2572 static int psp_load_non_psp_fw(struct psp_context *psp)
2573 {
2574         int i, ret;
2575         struct amdgpu_firmware_info *ucode;
2576         struct amdgpu_device *adev = psp->adev;
2577
2578         if (psp->autoload_supported &&
2579             !psp->pmfw_centralized_cstate_management) {
2580                 ret = psp_load_smu_fw(psp);
2581                 if (ret)
2582                         return ret;
2583         }
2584
2585         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2586                 ucode = &adev->firmware.ucode[i];
2587
2588                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2589                     !fw_load_skip_check(psp, ucode)) {
2590                         ret = psp_load_smu_fw(psp);
2591                         if (ret)
2592                                 return ret;
2593                         continue;
2594                 }
2595
2596                 if (fw_load_skip_check(psp, ucode))
2597                         continue;
2598
2599                 if (psp->autoload_supported &&
2600                     (adev->asic_type >= CHIP_SIENNA_CICHLID &&
2601                      adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
2602                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2603                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2604                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2605                         /* PSP only receive one SDMA fw for sienna_cichlid,
2606                          * as all four sdma fw are same */
2607                         continue;
2608
2609                 psp_print_fw_hdr(psp, ucode);
2610
2611                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2612                 if (ret)
2613                         return ret;
2614
2615                 /* Start rlc autoload after psp recieved all the gfx firmware */
2616                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2617                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2618                         ret = psp_rlc_autoload_start(psp);
2619                         if (ret) {
2620                                 DRM_ERROR("Failed to start rlc autoload\n");
2621                                 return ret;
2622                         }
2623                 }
2624         }
2625
2626         return 0;
2627 }
2628
2629 static int psp_load_fw(struct amdgpu_device *adev)
2630 {
2631         int ret;
2632         struct psp_context *psp = &adev->psp;
2633
2634         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2635                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2636                 goto skip_memalloc;
2637         }
2638
2639         if (amdgpu_sriov_vf(adev)) {
2640                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2641                                                 AMDGPU_GEM_DOMAIN_VRAM,
2642                                                 &psp->fw_pri_bo,
2643                                                 &psp->fw_pri_mc_addr,
2644                                                 &psp->fw_pri_buf);
2645         } else {
2646                 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2647                                                 AMDGPU_GEM_DOMAIN_GTT,
2648                                                 &psp->fw_pri_bo,
2649                                                 &psp->fw_pri_mc_addr,
2650                                                 &psp->fw_pri_buf);
2651         }
2652
2653         if (ret)
2654                 goto failed;
2655
2656         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2657                                         AMDGPU_GEM_DOMAIN_VRAM,
2658                                         &psp->fence_buf_bo,
2659                                         &psp->fence_buf_mc_addr,
2660                                         &psp->fence_buf);
2661         if (ret)
2662                 goto failed;
2663
2664         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2665                                       AMDGPU_GEM_DOMAIN_VRAM,
2666                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2667                                       (void **)&psp->cmd_buf_mem);
2668         if (ret)
2669                 goto failed;
2670
2671         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2672
2673         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2674         if (ret) {
2675                 DRM_ERROR("PSP ring init failed!\n");
2676                 goto failed;
2677         }
2678
2679 skip_memalloc:
2680         ret = psp_hw_start(psp);
2681         if (ret)
2682                 goto failed;
2683
2684         ret = psp_load_non_psp_fw(psp);
2685         if (ret)
2686                 goto failed;
2687
2688         ret = psp_asd_load(psp);
2689         if (ret) {
2690                 DRM_ERROR("PSP load asd failed!\n");
2691                 return ret;
2692         }
2693
2694         ret = psp_rl_load(adev);
2695         if (ret) {
2696                 DRM_ERROR("PSP load RL failed!\n");
2697                 return ret;
2698         }
2699
2700         if (psp->ta_fw) {
2701                 ret = psp_ras_initialize(psp);
2702                 if (ret)
2703                         dev_err(psp->adev->dev,
2704                                         "RAS: Failed to initialize RAS\n");
2705
2706                 ret = psp_hdcp_initialize(psp);
2707                 if (ret)
2708                         dev_err(psp->adev->dev,
2709                                 "HDCP: Failed to initialize HDCP\n");
2710
2711                 ret = psp_dtm_initialize(psp);
2712                 if (ret)
2713                         dev_err(psp->adev->dev,
2714                                 "DTM: Failed to initialize DTM\n");
2715
2716                 ret = psp_rap_initialize(psp);
2717                 if (ret)
2718                         dev_err(psp->adev->dev,
2719                                 "RAP: Failed to initialize RAP\n");
2720
2721                 ret = psp_securedisplay_initialize(psp);
2722                 if (ret)
2723                         dev_err(psp->adev->dev,
2724                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2725         }
2726
2727         return 0;
2728
2729 failed:
2730         /*
2731          * all cleanup jobs (xgmi terminate, ras terminate,
2732          * ring destroy, cmd/fence/fw buffers destory,
2733          * psp->cmd destory) are delayed to psp_hw_fini
2734          */
2735         return ret;
2736 }
2737
2738 static int psp_hw_init(void *handle)
2739 {
2740         int ret;
2741         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2742
2743         mutex_lock(&adev->firmware.mutex);
2744         /*
2745          * This sequence is just used on hw_init only once, no need on
2746          * resume.
2747          */
2748         ret = amdgpu_ucode_init_bo(adev);
2749         if (ret)
2750                 goto failed;
2751
2752         ret = psp_load_fw(adev);
2753         if (ret) {
2754                 DRM_ERROR("PSP firmware loading failed\n");
2755                 goto failed;
2756         }
2757
2758         mutex_unlock(&adev->firmware.mutex);
2759         return 0;
2760
2761 failed:
2762         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2763         mutex_unlock(&adev->firmware.mutex);
2764         return -EINVAL;
2765 }
2766
2767 static int psp_hw_fini(void *handle)
2768 {
2769         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2770         struct psp_context *psp = &adev->psp;
2771
2772         if (psp->ta_fw) {
2773                 psp_ras_terminate(psp);
2774                 psp_securedisplay_terminate(psp);
2775                 psp_rap_terminate(psp);
2776                 psp_dtm_terminate(psp);
2777                 psp_hdcp_terminate(psp);
2778         }
2779
2780         psp_asd_unload(psp);
2781
2782         psp_tmr_terminate(psp);
2783         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2784
2785         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2786                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2787         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2788                               &psp->fence_buf_mc_addr, &psp->fence_buf);
2789         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2790                               (void **)&psp->cmd_buf_mem);
2791
2792         return 0;
2793 }
2794
2795 static int psp_suspend(void *handle)
2796 {
2797         int ret;
2798         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2799         struct psp_context *psp = &adev->psp;
2800
2801         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2802             psp->xgmi_context.context.initialized) {
2803                 ret = psp_xgmi_terminate(psp);
2804                 if (ret) {
2805                         DRM_ERROR("Failed to terminate xgmi ta\n");
2806                         return ret;
2807                 }
2808         }
2809
2810         if (psp->ta_fw) {
2811                 ret = psp_ras_terminate(psp);
2812                 if (ret) {
2813                         DRM_ERROR("Failed to terminate ras ta\n");
2814                         return ret;
2815                 }
2816                 ret = psp_hdcp_terminate(psp);
2817                 if (ret) {
2818                         DRM_ERROR("Failed to terminate hdcp ta\n");
2819                         return ret;
2820                 }
2821                 ret = psp_dtm_terminate(psp);
2822                 if (ret) {
2823                         DRM_ERROR("Failed to terminate dtm ta\n");
2824                         return ret;
2825                 }
2826                 ret = psp_rap_terminate(psp);
2827                 if (ret) {
2828                         DRM_ERROR("Failed to terminate rap ta\n");
2829                         return ret;
2830                 }
2831                 ret = psp_securedisplay_terminate(psp);
2832                 if (ret) {
2833                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2834                         return ret;
2835                 }
2836         }
2837
2838         ret = psp_asd_unload(psp);
2839         if (ret) {
2840                 DRM_ERROR("Failed to unload asd\n");
2841                 return ret;
2842         }
2843
2844         ret = psp_tmr_terminate(psp);
2845         if (ret) {
2846                 DRM_ERROR("Failed to terminate tmr\n");
2847                 return ret;
2848         }
2849
2850         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2851         if (ret) {
2852                 DRM_ERROR("PSP ring stop failed\n");
2853                 return ret;
2854         }
2855
2856         return 0;
2857 }
2858
2859 static int psp_resume(void *handle)
2860 {
2861         int ret;
2862         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2863         struct psp_context *psp = &adev->psp;
2864
2865         DRM_INFO("PSP is resuming...\n");
2866
2867         if (psp->mem_train_ctx.enable_mem_training) {
2868                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2869                 if (ret) {
2870                         DRM_ERROR("Failed to process memory training!\n");
2871                         return ret;
2872                 }
2873         }
2874
2875         mutex_lock(&adev->firmware.mutex);
2876
2877         ret = psp_hw_start(psp);
2878         if (ret)
2879                 goto failed;
2880
2881         ret = psp_load_non_psp_fw(psp);
2882         if (ret)
2883                 goto failed;
2884
2885         ret = psp_asd_load(psp);
2886         if (ret) {
2887                 DRM_ERROR("PSP load asd failed!\n");
2888                 goto failed;
2889         }
2890
2891         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2892                 ret = psp_xgmi_initialize(psp, false, true);
2893                 /* Warning the XGMI seesion initialize failure
2894                  * Instead of stop driver initialization
2895                  */
2896                 if (ret)
2897                         dev_err(psp->adev->dev,
2898                                 "XGMI: Failed to initialize XGMI session\n");
2899         }
2900
2901         if (psp->ta_fw) {
2902                 ret = psp_ras_initialize(psp);
2903                 if (ret)
2904                         dev_err(psp->adev->dev,
2905                                         "RAS: Failed to initialize RAS\n");
2906
2907                 ret = psp_hdcp_initialize(psp);
2908                 if (ret)
2909                         dev_err(psp->adev->dev,
2910                                 "HDCP: Failed to initialize HDCP\n");
2911
2912                 ret = psp_dtm_initialize(psp);
2913                 if (ret)
2914                         dev_err(psp->adev->dev,
2915                                 "DTM: Failed to initialize DTM\n");
2916
2917                 ret = psp_rap_initialize(psp);
2918                 if (ret)
2919                         dev_err(psp->adev->dev,
2920                                 "RAP: Failed to initialize RAP\n");
2921
2922                 ret = psp_securedisplay_initialize(psp);
2923                 if (ret)
2924                         dev_err(psp->adev->dev,
2925                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2926         }
2927
2928         mutex_unlock(&adev->firmware.mutex);
2929
2930         return 0;
2931
2932 failed:
2933         DRM_ERROR("PSP resume failed\n");
2934         mutex_unlock(&adev->firmware.mutex);
2935         return ret;
2936 }
2937
2938 int psp_gpu_reset(struct amdgpu_device *adev)
2939 {
2940         int ret;
2941
2942         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2943                 return 0;
2944
2945         mutex_lock(&adev->psp.mutex);
2946         ret = psp_mode1_reset(&adev->psp);
2947         mutex_unlock(&adev->psp.mutex);
2948
2949         return ret;
2950 }
2951
2952 int psp_rlc_autoload_start(struct psp_context *psp)
2953 {
2954         int ret;
2955         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2956
2957         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2958
2959         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2960                                  psp->fence_buf_mc_addr);
2961
2962         release_psp_cmd_buf(psp);
2963
2964         return ret;
2965 }
2966
2967 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2968                         uint64_t cmd_gpu_addr, int cmd_size)
2969 {
2970         struct amdgpu_firmware_info ucode = {0};
2971
2972         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2973                 AMDGPU_UCODE_ID_VCN0_RAM;
2974         ucode.mc_addr = cmd_gpu_addr;
2975         ucode.ucode_size = cmd_size;
2976
2977         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2978 }
2979
2980 int psp_ring_cmd_submit(struct psp_context *psp,
2981                         uint64_t cmd_buf_mc_addr,
2982                         uint64_t fence_mc_addr,
2983                         int index)
2984 {
2985         unsigned int psp_write_ptr_reg = 0;
2986         struct psp_gfx_rb_frame *write_frame;
2987         struct psp_ring *ring = &psp->km_ring;
2988         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2989         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2990                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2991         struct amdgpu_device *adev = psp->adev;
2992         uint32_t ring_size_dw = ring->ring_size / 4;
2993         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2994
2995         /* KM (GPCOM) prepare write pointer */
2996         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2997
2998         /* Update KM RB frame pointer to new frame */
2999         /* write_frame ptr increments by size of rb_frame in bytes */
3000         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
3001         if ((psp_write_ptr_reg % ring_size_dw) == 0)
3002                 write_frame = ring_buffer_start;
3003         else
3004                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
3005         /* Check invalid write_frame ptr address */
3006         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
3007                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
3008                           ring_buffer_start, ring_buffer_end, write_frame);
3009                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
3010                 return -EINVAL;
3011         }
3012
3013         /* Initialize KM RB frame */
3014         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
3015
3016         /* Update KM RB frame */
3017         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
3018         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
3019         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
3020         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
3021         write_frame->fence_value = index;
3022         amdgpu_device_flush_hdp(adev, NULL);
3023
3024         /* Update the write Pointer in DWORDs */
3025         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
3026         psp_ring_set_wptr(psp, psp_write_ptr_reg);
3027         return 0;
3028 }
3029
3030 int psp_init_asd_microcode(struct psp_context *psp,
3031                            const char *chip_name)
3032 {
3033         struct amdgpu_device *adev = psp->adev;
3034         char fw_name[PSP_FW_NAME_LEN];
3035         const struct psp_firmware_header_v1_0 *asd_hdr;
3036         int err = 0;
3037
3038         if (!chip_name) {
3039                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
3040                 return -EINVAL;
3041         }
3042
3043         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
3044         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
3045         if (err)
3046                 goto out;
3047
3048         err = amdgpu_ucode_validate(adev->psp.asd_fw);
3049         if (err)
3050                 goto out;
3051
3052         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
3053         adev->psp.asd.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
3054         adev->psp.asd.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
3055         adev->psp.asd.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3056         adev->psp.asd.start_addr = (uint8_t *)asd_hdr +
3057                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3058         return 0;
3059 out:
3060         dev_err(adev->dev, "fail to initialize asd microcode\n");
3061         release_firmware(adev->psp.asd_fw);
3062         adev->psp.asd_fw = NULL;
3063         return err;
3064 }
3065
3066 int psp_init_toc_microcode(struct psp_context *psp,
3067                            const char *chip_name)
3068 {
3069         struct amdgpu_device *adev = psp->adev;
3070         char fw_name[PSP_FW_NAME_LEN];
3071         const struct psp_firmware_header_v1_0 *toc_hdr;
3072         int err = 0;
3073
3074         if (!chip_name) {
3075                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
3076                 return -EINVAL;
3077         }
3078
3079         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3080         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
3081         if (err)
3082                 goto out;
3083
3084         err = amdgpu_ucode_validate(adev->psp.toc_fw);
3085         if (err)
3086                 goto out;
3087
3088         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3089         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3090         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3091         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3092         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3093                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3094         return 0;
3095 out:
3096         dev_err(adev->dev, "fail to request/validate toc microcode\n");
3097         release_firmware(adev->psp.toc_fw);
3098         adev->psp.toc_fw = NULL;
3099         return err;
3100 }
3101
3102 static int parse_sos_bin_descriptor(struct psp_context *psp,
3103                                    const struct psp_fw_bin_desc *desc,
3104                                    const struct psp_firmware_header_v2_0 *sos_hdr)
3105 {
3106         uint8_t *ucode_start_addr  = NULL;
3107
3108         if (!psp || !desc || !sos_hdr)
3109                 return -EINVAL;
3110
3111         ucode_start_addr  = (uint8_t *)sos_hdr +
3112                             le32_to_cpu(desc->offset_bytes) +
3113                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3114
3115         switch (desc->fw_type) {
3116         case PSP_FW_TYPE_PSP_SOS:
3117                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
3118                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
3119                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
3120                 psp->sos.start_addr        = ucode_start_addr;
3121                 break;
3122         case PSP_FW_TYPE_PSP_SYS_DRV:
3123                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
3124                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
3125                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
3126                 psp->sys.start_addr        = ucode_start_addr;
3127                 break;
3128         case PSP_FW_TYPE_PSP_KDB:
3129                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
3130                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
3131                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
3132                 psp->kdb.start_addr        = ucode_start_addr;
3133                 break;
3134         case PSP_FW_TYPE_PSP_TOC:
3135                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
3136                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
3137                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
3138                 psp->toc.start_addr        = ucode_start_addr;
3139                 break;
3140         case PSP_FW_TYPE_PSP_SPL:
3141                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
3142                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
3143                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
3144                 psp->spl.start_addr        = ucode_start_addr;
3145                 break;
3146         case PSP_FW_TYPE_PSP_RL:
3147                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
3148                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
3149                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3150                 psp->rl.start_addr         = ucode_start_addr;
3151                 break;
3152         case PSP_FW_TYPE_PSP_SOC_DRV:
3153                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3154                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3155                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3156                 psp->soc_drv.start_addr         = ucode_start_addr;
3157                 break;
3158         case PSP_FW_TYPE_PSP_INTF_DRV:
3159                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3160                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3161                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3162                 psp->intf_drv.start_addr        = ucode_start_addr;
3163                 break;
3164         case PSP_FW_TYPE_PSP_DBG_DRV:
3165                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3166                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3167                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3168                 psp->dbg_drv.start_addr         = ucode_start_addr;
3169                 break;
3170         default:
3171                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3172                 break;
3173         }
3174
3175         return 0;
3176 }
3177
3178 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3179 {
3180         const struct psp_firmware_header_v1_0 *sos_hdr;
3181         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3182         uint8_t *ucode_array_start_addr;
3183
3184         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3185         ucode_array_start_addr = (uint8_t *)sos_hdr +
3186                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3187
3188         if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) {
3189                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3190                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3191
3192                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3193                 adev->psp.sys.start_addr = ucode_array_start_addr;
3194
3195                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3196                 adev->psp.sos.start_addr = ucode_array_start_addr +
3197                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3198                 adev->psp.xgmi_context.supports_extended_data = false;
3199         } else {
3200                 /* Load alternate PSP SOS FW */
3201                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3202
3203                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3204                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3205
3206                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3207                 adev->psp.sys.start_addr = ucode_array_start_addr +
3208                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3209
3210                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3211                 adev->psp.sos.start_addr = ucode_array_start_addr +
3212                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3213                 adev->psp.xgmi_context.supports_extended_data = true;
3214         }
3215
3216         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3217                 dev_warn(adev->dev, "PSP SOS FW not available");
3218                 return -EINVAL;
3219         }
3220
3221         return 0;
3222 }
3223
3224 int psp_init_sos_microcode(struct psp_context *psp,
3225                            const char *chip_name)
3226 {
3227         struct amdgpu_device *adev = psp->adev;
3228         char fw_name[PSP_FW_NAME_LEN];
3229         const struct psp_firmware_header_v1_0 *sos_hdr;
3230         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3231         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3232         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3233         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3234         int err = 0;
3235         uint8_t *ucode_array_start_addr;
3236         int fw_index = 0;
3237
3238         if (!chip_name) {
3239                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3240                 return -EINVAL;
3241         }
3242
3243         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3244         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3245         if (err)
3246                 goto out;
3247
3248         err = amdgpu_ucode_validate(adev->psp.sos_fw);
3249         if (err)
3250                 goto out;
3251
3252         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3253         ucode_array_start_addr = (uint8_t *)sos_hdr +
3254                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3255         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3256
3257         switch (sos_hdr->header.header_version_major) {
3258         case 1:
3259                 err = psp_init_sos_base_fw(adev);
3260                 if (err)
3261                         goto out;
3262
3263                 if (sos_hdr->header.header_version_minor == 1) {
3264                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3265                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3266                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3267                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3268                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3269                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3270                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3271                 }
3272                 if (sos_hdr->header.header_version_minor == 2) {
3273                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3274                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3275                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3276                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3277                 }
3278                 if (sos_hdr->header.header_version_minor == 3) {
3279                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3280                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3281                         adev->psp.toc.start_addr = ucode_array_start_addr +
3282                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3283                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3284                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3285                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3286                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3287                         adev->psp.spl.start_addr = ucode_array_start_addr +
3288                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3289                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3290                         adev->psp.rl.start_addr = ucode_array_start_addr +
3291                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3292                 }
3293                 break;
3294         case 2:
3295                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3296
3297                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3298                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3299                         err = -EINVAL;
3300                         goto out;
3301                 }
3302
3303                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3304                         err = parse_sos_bin_descriptor(psp,
3305                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3306                                                        sos_hdr_v2_0);
3307                         if (err)
3308                                 goto out;
3309                 }
3310                 break;
3311         default:
3312                 dev_err(adev->dev,
3313                         "unsupported psp sos firmware\n");
3314                 err = -EINVAL;
3315                 goto out;
3316         }
3317
3318         return 0;
3319 out:
3320         dev_err(adev->dev,
3321                 "failed to init sos firmware\n");
3322         release_firmware(adev->psp.sos_fw);
3323         adev->psp.sos_fw = NULL;
3324
3325         return err;
3326 }
3327
3328 static int parse_ta_bin_descriptor(struct psp_context *psp,
3329                                    const struct psp_fw_bin_desc *desc,
3330                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3331 {
3332         uint8_t *ucode_start_addr  = NULL;
3333
3334         if (!psp || !desc || !ta_hdr)
3335                 return -EINVAL;
3336
3337         ucode_start_addr  = (uint8_t *)ta_hdr +
3338                             le32_to_cpu(desc->offset_bytes) +
3339                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3340
3341         switch (desc->fw_type) {
3342         case TA_FW_TYPE_PSP_ASD:
3343                 psp->asd.fw_version        = le32_to_cpu(desc->fw_version);
3344                 psp->asd.feature_version   = le32_to_cpu(desc->fw_version);
3345                 psp->asd.size_bytes        = le32_to_cpu(desc->size_bytes);
3346                 psp->asd.start_addr        = ucode_start_addr;
3347                 break;
3348         case TA_FW_TYPE_PSP_XGMI:
3349                 psp->xgmi.feature_version  = le32_to_cpu(desc->fw_version);
3350                 psp->xgmi.size_bytes       = le32_to_cpu(desc->size_bytes);
3351                 psp->xgmi.start_addr       = ucode_start_addr;
3352                 break;
3353         case TA_FW_TYPE_PSP_RAS:
3354                 psp->ras.feature_version   = le32_to_cpu(desc->fw_version);
3355                 psp->ras.size_bytes        = le32_to_cpu(desc->size_bytes);
3356                 psp->ras.start_addr        = ucode_start_addr;
3357                 break;
3358         case TA_FW_TYPE_PSP_HDCP:
3359                 psp->hdcp.feature_version  = le32_to_cpu(desc->fw_version);
3360                 psp->hdcp.size_bytes       = le32_to_cpu(desc->size_bytes);
3361                 psp->hdcp.start_addr       = ucode_start_addr;
3362                 break;
3363         case TA_FW_TYPE_PSP_DTM:
3364                 psp->dtm.feature_version  = le32_to_cpu(desc->fw_version);
3365                 psp->dtm.size_bytes       = le32_to_cpu(desc->size_bytes);
3366                 psp->dtm.start_addr       = ucode_start_addr;
3367                 break;
3368         case TA_FW_TYPE_PSP_RAP:
3369                 psp->rap.feature_version  = le32_to_cpu(desc->fw_version);
3370                 psp->rap.size_bytes       = le32_to_cpu(desc->size_bytes);
3371                 psp->rap.start_addr       = ucode_start_addr;
3372                 break;
3373         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3374                 psp->securedisplay.feature_version  = le32_to_cpu(desc->fw_version);
3375                 psp->securedisplay.size_bytes       = le32_to_cpu(desc->size_bytes);
3376                 psp->securedisplay.start_addr       = ucode_start_addr;
3377                 break;
3378         default:
3379                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3380                 break;
3381         }
3382
3383         return 0;
3384 }
3385
3386 int psp_init_ta_microcode(struct psp_context *psp,
3387                           const char *chip_name)
3388 {
3389         struct amdgpu_device *adev = psp->adev;
3390         char fw_name[PSP_FW_NAME_LEN];
3391         const struct ta_firmware_header_v2_0 *ta_hdr;
3392         int err = 0;
3393         int ta_index = 0;
3394
3395         if (!chip_name) {
3396                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3397                 return -EINVAL;
3398         }
3399
3400         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3401         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3402         if (err)
3403                 goto out;
3404
3405         err = amdgpu_ucode_validate(adev->psp.ta_fw);
3406         if (err)
3407                 goto out;
3408
3409         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3410
3411         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3412                 dev_err(adev->dev, "unsupported TA header version\n");
3413                 err = -EINVAL;
3414                 goto out;
3415         }
3416
3417         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3418                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3419                 err = -EINVAL;
3420                 goto out;
3421         }
3422
3423         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3424                 err = parse_ta_bin_descriptor(psp,
3425                                               &ta_hdr->ta_fw_bin[ta_index],
3426                                               ta_hdr);
3427                 if (err)
3428                         goto out;
3429         }
3430
3431         return 0;
3432 out:
3433         dev_err(adev->dev, "fail to initialize ta microcode\n");
3434         release_firmware(adev->psp.ta_fw);
3435         adev->psp.ta_fw = NULL;
3436         return err;
3437 }
3438
3439 static int psp_set_clockgating_state(void *handle,
3440                                      enum amd_clockgating_state state)
3441 {
3442         return 0;
3443 }
3444
3445 static int psp_set_powergating_state(void *handle,
3446                                      enum amd_powergating_state state)
3447 {
3448         return 0;
3449 }
3450
3451 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3452                                          struct device_attribute *attr,
3453                                          char *buf)
3454 {
3455         struct drm_device *ddev = dev_get_drvdata(dev);
3456         struct amdgpu_device *adev = drm_to_adev(ddev);
3457         uint32_t fw_ver;
3458         int ret;
3459
3460         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3461                 DRM_INFO("PSP block is not ready yet.");
3462                 return -EBUSY;
3463         }
3464
3465         mutex_lock(&adev->psp.mutex);
3466         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3467         mutex_unlock(&adev->psp.mutex);
3468
3469         if (ret) {
3470                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3471                 return ret;
3472         }
3473
3474         return sysfs_emit(buf, "%x\n", fw_ver);
3475 }
3476
3477 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3478                                                        struct device_attribute *attr,
3479                                                        const char *buf,
3480                                                        size_t count)
3481 {
3482         struct drm_device *ddev = dev_get_drvdata(dev);
3483         struct amdgpu_device *adev = drm_to_adev(ddev);
3484         int ret, idx;
3485         char fw_name[100];
3486         const struct firmware *usbc_pd_fw;
3487         struct amdgpu_bo *fw_buf_bo = NULL;
3488         uint64_t fw_pri_mc_addr;
3489         void *fw_pri_cpu_addr;
3490
3491         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3492                 DRM_INFO("PSP block is not ready yet.");
3493                 return -EBUSY;
3494         }
3495
3496         if (!drm_dev_enter(ddev, &idx))
3497                 return -ENODEV;
3498
3499         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3500         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3501         if (ret)
3502                 goto fail;
3503
3504         /* LFB address which is aligned to 1MB boundary per PSP request */
3505         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3506                                                 AMDGPU_GEM_DOMAIN_VRAM,
3507                                                 &fw_buf_bo,
3508                                                 &fw_pri_mc_addr,
3509                                                 &fw_pri_cpu_addr);
3510         if (ret)
3511                 goto rel_buf;
3512
3513         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3514
3515         mutex_lock(&adev->psp.mutex);
3516         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3517         mutex_unlock(&adev->psp.mutex);
3518
3519         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3520
3521 rel_buf:
3522         release_firmware(usbc_pd_fw);
3523 fail:
3524         if (ret) {
3525                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3526                 count = ret;
3527         }
3528
3529         drm_dev_exit(idx);
3530         return count;
3531 }
3532
3533 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3534 {
3535         int idx;
3536
3537         if (!drm_dev_enter(&psp->adev->ddev, &idx))
3538                 return;
3539
3540         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3541         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3542
3543         drm_dev_exit(idx);
3544 }
3545
3546 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3547                    psp_usbc_pd_fw_sysfs_read,
3548                    psp_usbc_pd_fw_sysfs_write);
3549
3550 int is_psp_fw_valid(struct psp_bin_desc bin)
3551 {
3552         return bin.size_bytes;
3553 }
3554
3555 const struct amd_ip_funcs psp_ip_funcs = {
3556         .name = "psp",
3557         .early_init = psp_early_init,
3558         .late_init = NULL,
3559         .sw_init = psp_sw_init,
3560         .sw_fini = psp_sw_fini,
3561         .hw_init = psp_hw_init,
3562         .hw_fini = psp_hw_fini,
3563         .suspend = psp_suspend,
3564         .resume = psp_resume,
3565         .is_idle = NULL,
3566         .check_soft_reset = NULL,
3567         .wait_for_idle = NULL,
3568         .soft_reset = NULL,
3569         .set_clockgating_state = psp_set_clockgating_state,
3570         .set_powergating_state = psp_set_powergating_state,
3571 };
3572
3573 static int psp_sysfs_init(struct amdgpu_device *adev)
3574 {
3575         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3576
3577         if (ret)
3578                 DRM_ERROR("Failed to create USBC PD FW control file!");
3579
3580         return ret;
3581 }
3582
3583 static void psp_sysfs_fini(struct amdgpu_device *adev)
3584 {
3585         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3586 }
3587
3588 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3589 {
3590         .type = AMD_IP_BLOCK_TYPE_PSP,
3591         .major = 3,
3592         .minor = 1,
3593         .rev = 0,
3594         .funcs = &psp_ip_funcs,
3595 };
3596
3597 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3598 {
3599         .type = AMD_IP_BLOCK_TYPE_PSP,
3600         .major = 10,
3601         .minor = 0,
3602         .rev = 0,
3603         .funcs = &psp_ip_funcs,
3604 };
3605
3606 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3607 {
3608         .type = AMD_IP_BLOCK_TYPE_PSP,
3609         .major = 11,
3610         .minor = 0,
3611         .rev = 0,
3612         .funcs = &psp_ip_funcs,
3613 };
3614
3615 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3616         .type = AMD_IP_BLOCK_TYPE_PSP,
3617         .major = 11,
3618         .minor = 0,
3619         .rev = 8,
3620         .funcs = &psp_ip_funcs,
3621 };
3622
3623 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3624 {
3625         .type = AMD_IP_BLOCK_TYPE_PSP,
3626         .major = 12,
3627         .minor = 0,
3628         .rev = 0,
3629         .funcs = &psp_ip_funcs,
3630 };
3631
3632 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3633         .type = AMD_IP_BLOCK_TYPE_PSP,
3634         .major = 13,
3635         .minor = 0,
3636         .rev = 0,
3637         .funcs = &psp_ip_funcs,
3638 };