drivers/gpu/drm/vc4/vc4_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 KMS
   8  *
   9  * This is the general code for implementing KMS mode setting that
  10  * doesn't clearly associate with any of the other objects (plane,
  11  * crtc, HDMI encoder).
  12  */
  13
  14 #include <linux/clk.h>
  15
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_fourcc.h>
  20 #include <drm/drm_gem_framebuffer_helper.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/drm_vblank.h>
  23
  24 #include "vc4_drv.h"
  25 #include "vc4_regs.h"
  26
  27 #define HVS_NUM_CHANNELS 3
  28
  29 struct vc4_ctm_state {
  30         struct drm_private_state base;
  31         struct drm_color_ctm *ctm;
  32         int fifo;
  33 };
  34
  35 static struct vc4_ctm_state *
  36 to_vc4_ctm_state(const struct drm_private_state *priv)
  37 {
  38         return container_of(priv, struct vc4_ctm_state, base);
  39 }
  40
  41 struct vc4_hvs_state {
  42         struct drm_private_state base;
  43         unsigned long core_clock_rate;
  44
  45         struct {
  46                 unsigned in_use: 1;
  47                 unsigned long fifo_load;
  48                 struct drm_crtc_commit *pending_commit;
  49         } fifo_state[HVS_NUM_CHANNELS];
  50 };
  51
  52 static struct vc4_hvs_state *
  53 to_vc4_hvs_state(const struct drm_private_state *priv)
  54 {
  55         return container_of(priv, struct vc4_hvs_state, base);
  56 }
  57
  58 struct vc4_load_tracker_state {
  59         struct drm_private_state base;
  60         u64 hvs_load;
  61         u64 membus_load;
  62 };
  63
  64 static struct vc4_load_tracker_state *
  65 to_vc4_load_tracker_state(const struct drm_private_state *priv)
  66 {
  67         return container_of(priv, struct vc4_load_tracker_state, base);
  68 }
  69
  70 static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  71                                                struct drm_private_obj *manager)
  72 {
  73         struct drm_device *dev = state->dev;
  74         struct vc4_dev *vc4 = to_vc4_dev(dev);
  75         struct drm_private_state *priv_state;
  76         int ret;
  77
  78         ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  79         if (ret)
  80                 return ERR_PTR(ret);
  81
  82         priv_state = drm_atomic_get_private_obj_state(state, manager);
  83         if (IS_ERR(priv_state))
  84                 return ERR_CAST(priv_state);
  85
  86         return to_vc4_ctm_state(priv_state);
  87 }
  88
  89 static struct drm_private_state *
  90 vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  91 {
  92         struct vc4_ctm_state *state;
  93
  94         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  95         if (!state)
  96                 return NULL;
  97
  98         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  99
 100         return &state->base;
 101 }
 102
 103 static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
 104                                   struct drm_private_state *state)
 105 {
 106         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
 107
 108         kfree(ctm_state);
 109 }
 110
 111 static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
 112         .atomic_duplicate_state = vc4_ctm_duplicate_state,
 113         .atomic_destroy_state = vc4_ctm_destroy_state,
 114 };
 115
 116 static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
 117 {
 118         struct vc4_dev *vc4 = to_vc4_dev(dev);
 119
 120         drm_atomic_private_obj_fini(&vc4->ctm_manager);
 121 }
 122
 123 static int vc4_ctm_obj_init(struct vc4_dev *vc4)
 124 {
 125         struct vc4_ctm_state *ctm_state;
 126
 127         drm_modeset_lock_init(&vc4->ctm_state_lock);
 128
 129         ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
 130         if (!ctm_state)
 131                 return -ENOMEM;
 132
 133         drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
 134                                     &vc4_ctm_state_funcs);
 135
 136         return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
 137 }
 138
 139 /* Converts a DRM S31.32 value to the HW S0.9 format. */
 140 static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
 141 {
 142         u16 r;
 143
 144         /* Sign bit. */
 145         r = in & BIT_ULL(63) ? BIT(9) : 0;
 146
 147         if ((in & GENMASK_ULL(62, 32)) > 0) {
 148                 /* We have zero integer bits so we can only saturate here. */
 149                 r |= GENMASK(8, 0);
 150         } else {
 151                 /* Otherwise take the 9 most important fractional bits. */
 152                 r |= (in >> 23) & GENMASK(8, 0);
 153         }
 154
 155         return r;
 156 }
 157
 158 static void
 159 vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
 160 {
 161         struct vc4_hvs *hvs = vc4->hvs;
 162         struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
 163         struct drm_color_ctm *ctm = ctm_state->ctm;
 164
 165         if (ctm_state->fifo) {
 166                 HVS_WRITE(SCALER_OLEDCOEF2,
 167                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
 168                                         SCALER_OLEDCOEF2_R_TO_R) |
 169                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
 170                                         SCALER_OLEDCOEF2_R_TO_G) |
 171                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
 172                                         SCALER_OLEDCOEF2_R_TO_B));
 173                 HVS_WRITE(SCALER_OLEDCOEF1,
 174                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
 175                                         SCALER_OLEDCOEF1_G_TO_R) |
 176                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
 177                                         SCALER_OLEDCOEF1_G_TO_G) |
 178                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
 179                                         SCALER_OLEDCOEF1_G_TO_B));
 180                 HVS_WRITE(SCALER_OLEDCOEF0,
 181                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
 182                                         SCALER_OLEDCOEF0_B_TO_R) |
 183                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
 184                                         SCALER_OLEDCOEF0_B_TO_G) |
 185                           VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
 186                                         SCALER_OLEDCOEF0_B_TO_B));
 187         }
 188
 189         HVS_WRITE(SCALER_OLEDOFFS,
 190                   VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
 191 }
 192
 193 static struct vc4_hvs_state *
 194 vc4_hvs_get_new_global_state(struct drm_atomic_state *state)
 195 {
 196         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 197         struct drm_private_state *priv_state;
 198
 199         priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);
 200         if (!priv_state)
 201                 return ERR_PTR(-EINVAL);
 202
 203         return to_vc4_hvs_state(priv_state);
 204 }
 205
 206 static struct vc4_hvs_state *
 207 vc4_hvs_get_old_global_state(struct drm_atomic_state *state)
 208 {
 209         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 210         struct drm_private_state *priv_state;
 211
 212         priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels);
 213         if (!priv_state)
 214                 return ERR_PTR(-EINVAL);
 215
 216         return to_vc4_hvs_state(priv_state);
 217 }
 218
 219 static struct vc4_hvs_state *
 220 vc4_hvs_get_global_state(struct drm_atomic_state *state)
 221 {
 222         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 223         struct drm_private_state *priv_state;
 224
 225         priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels);
 226         if (IS_ERR(priv_state))
 227                 return ERR_CAST(priv_state);
 228
 229         return to_vc4_hvs_state(priv_state);
 230 }
 231
 232 static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 233                                      struct drm_atomic_state *state)
 234 {
 235         struct vc4_hvs *hvs = vc4->hvs;
 236         struct drm_crtc_state *crtc_state;
 237         struct drm_crtc *crtc;
 238         unsigned int i;
 239
 240         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 241                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 242                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 243                 u32 dispctrl;
 244                 u32 dsp3_mux;
 245
 246                 if (!crtc_state->active)
 247                         continue;
 248
 249                 if (vc4_state->assigned_channel != 2)
 250                         continue;
 251
 252                 /*
 253                  * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
 254                  * FIFO X'.
 255                  * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
 256                  *
 257                  * DSP3 is connected to FIFO2 unless the transposer is
 258                  * enabled. In this case, FIFO 2 is directly accessed by the
 259                  * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
 260                  * route.
 261                  */
 262                 if (vc4_crtc->feeds_txp)
 263                         dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
 264                 else
 265                         dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
 266
 267                 dispctrl = HVS_READ(SCALER_DISPCTRL) &
 268                            ~SCALER_DISPCTRL_DSP3_MUX_MASK;
 269                 HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
 270         }
 271 }
 272
 273 static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
 274                                      struct drm_atomic_state *state)
 275 {
 276         struct vc4_hvs *hvs = vc4->hvs;
 277         struct drm_crtc_state *crtc_state;
 278         struct drm_crtc *crtc;
 279         unsigned char mux;
 280         unsigned int i;
 281         u32 reg;
 282
 283         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 284                 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 285                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 286                 unsigned int channel = vc4_state->assigned_channel;
 287
 288                 if (!vc4_state->update_muxing)
 289                         continue;
 290
 291                 switch (vc4_crtc->data->hvs_output) {
 292                 case 2:
 293                         drm_WARN_ON(&vc4->base,
 294                                     VC4_GET_FIELD(HVS_READ(SCALER_DISPCTRL),
 295                                                   SCALER_DISPCTRL_DSP3_MUX) == channel);
 296
 297                         mux = (channel == 2) ? 0 : 1;
 298                         reg = HVS_READ(SCALER_DISPECTRL);
 299                         HVS_WRITE(SCALER_DISPECTRL,
 300                                   (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
 301                                   VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));
 302                         break;
 303
 304                 case 3:
 305                         if (channel == VC4_HVS_CHANNEL_DISABLED)
 306                                 mux = 3;
 307                         else
 308                                 mux = channel;
 309
 310                         reg = HVS_READ(SCALER_DISPCTRL);
 311                         HVS_WRITE(SCALER_DISPCTRL,
 312                                   (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
 313                                   VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
 314                         break;
 315
 316                 case 4:
 317                         if (channel == VC4_HVS_CHANNEL_DISABLED)
 318                                 mux = 3;
 319                         else
 320                                 mux = channel;
 321
 322                         reg = HVS_READ(SCALER_DISPEOLN);
 323                         HVS_WRITE(SCALER_DISPEOLN,
 324                                   (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
 325                                   VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
 326
 327                         break;
 328
 329                 case 5:
 330                         if (channel == VC4_HVS_CHANNEL_DISABLED)
 331                                 mux = 3;
 332                         else
 333                                 mux = channel;
 334
 335                         reg = HVS_READ(SCALER_DISPDITHER);
 336                         HVS_WRITE(SCALER_DISPDITHER,
 337                                   (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
 338                                   VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX));
 339                         break;
 340
 341                 default:
 342                         break;
 343                 }
 344         }
 345 }
 346
 347 static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
 348 {
 349         struct drm_device *dev = state->dev;
 350         struct vc4_dev *vc4 = to_vc4_dev(dev);
 351         struct vc4_hvs *hvs = vc4->hvs;
 352         struct drm_crtc_state *new_crtc_state;
 353         struct vc4_hvs_state *new_hvs_state;
 354         struct drm_crtc *crtc;
 355         struct vc4_hvs_state *old_hvs_state;
 356         unsigned int channel;
 357         int i;
 358
 359         old_hvs_state = vc4_hvs_get_old_global_state(state);
 360         if (WARN_ON(IS_ERR(old_hvs_state)))
 361                 return;
 362
 363         new_hvs_state = vc4_hvs_get_new_global_state(state);
 364         if (WARN_ON(IS_ERR(new_hvs_state)))
 365                 return;
 366
 367         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 368                 struct vc4_crtc_state *vc4_crtc_state;
 369
 370                 if (!new_crtc_state->commit)
 371                         continue;
 372
 373                 vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
 374                 vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel);
 375         }
 376
 377         for (channel = 0; channel < HVS_NUM_CHANNELS; channel++) {
 378                 struct drm_crtc_commit *commit;
 379                 int ret;
 380
 381                 if (!old_hvs_state->fifo_state[channel].in_use)
 382                         continue;
 383
 384                 commit = old_hvs_state->fifo_state[channel].pending_commit;
 385                 if (!commit)
 386                         continue;
 387
 388                 ret = drm_crtc_commit_wait(commit);
 389                 if (ret)
 390                         drm_err(dev, "Timed out waiting for commit\n");
 391
 392                 drm_crtc_commit_put(commit);
 393                 old_hvs_state->fifo_state[channel].pending_commit = NULL;
 394         }
 395
 396         if (vc4->is_vc5) {
 397                 unsigned long state_rate = max(old_hvs_state->core_clock_rate,
 398                                                new_hvs_state->core_clock_rate);
 399                 unsigned long core_rate = max_t(unsigned long,
 400                                                 500000000, state_rate);
 401
 402                 drm_dbg(dev, "Raising the core clock at %lu Hz\n", core_rate);
 403
 404                 /*
 405                  * Do a temporary request on the core clock during the
 406                  * modeset.
 407                  */
 408                 WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
 409         }
 410
 411         drm_atomic_helper_commit_modeset_disables(dev, state);
 412
 413         vc4_ctm_commit(vc4, state);
 414
 415         if (vc4->is_vc5)
 416                 vc5_hvs_pv_muxing_commit(vc4, state);
 417         else
 418                 vc4_hvs_pv_muxing_commit(vc4, state);
 419
 420         drm_atomic_helper_commit_planes(dev, state,
 421                                         DRM_PLANE_COMMIT_ACTIVE_ONLY);
 422
 423         drm_atomic_helper_commit_modeset_enables(dev, state);
 424
 425         drm_atomic_helper_fake_vblank(state);
 426
 427         drm_atomic_helper_commit_hw_done(state);
 428
 429         drm_atomic_helper_wait_for_flip_done(dev, state);
 430
 431         drm_atomic_helper_cleanup_planes(dev, state);
 432
 433         if (vc4->is_vc5) {
 434                 drm_dbg(dev, "Running the core clock at %lu Hz\n",
 435                         new_hvs_state->core_clock_rate);
 436
 437                 /*
 438                  * Request a clock rate based on the current HVS
 439                  * requirements.
 440                  */
 441                 WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate));
 442
 443                 drm_dbg(dev, "Core clock actual rate: %lu Hz\n",
 444                         clk_get_rate(hvs->core_clk));
 445         }
 446 }
 447
 448 static int vc4_atomic_commit_setup(struct drm_atomic_state *state)
 449 {
 450         struct drm_crtc_state *crtc_state;
 451         struct vc4_hvs_state *hvs_state;
 452         struct drm_crtc *crtc;
 453         unsigned int i;
 454
 455         hvs_state = vc4_hvs_get_new_global_state(state);
 456         if (WARN_ON(IS_ERR(hvs_state)))
 457                 return PTR_ERR(hvs_state);
 458
 459         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 460                 struct vc4_crtc_state *vc4_crtc_state =
 461                         to_vc4_crtc_state(crtc_state);
 462                 unsigned int channel =
 463                         vc4_crtc_state->assigned_channel;
 464
 465                 if (channel == VC4_HVS_CHANNEL_DISABLED)
 466                         continue;
 467
 468                 if (!hvs_state->fifo_state[channel].in_use)
 469                         continue;
 470
 471                 hvs_state->fifo_state[channel].pending_commit =
 472                         drm_crtc_commit_get(crtc_state->commit);
 473         }
 474
 475         return 0;
 476 }
 477
 478 static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
 479                                              struct drm_file *file_priv,
 480                                              const struct drm_mode_fb_cmd2 *mode_cmd)
 481 {
 482         struct vc4_dev *vc4 = to_vc4_dev(dev);
 483         struct drm_mode_fb_cmd2 mode_cmd_local;
 484
 485         if (WARN_ON_ONCE(vc4->is_vc5))
 486                 return ERR_PTR(-ENODEV);
 487
 488         /* If the user didn't specify a modifier, use the
 489          * vc4_set_tiling_ioctl() state for the BO.
 490          */
 491         if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
 492                 struct drm_gem_object *gem_obj;
 493                 struct vc4_bo *bo;
 494
 495                 gem_obj = drm_gem_object_lookup(file_priv,
 496                                                 mode_cmd->handles[0]);
 497                 if (!gem_obj) {
 498                         DRM_DEBUG("Failed to look up GEM BO %d\n",
 499                                   mode_cmd->handles[0]);
 500                         return ERR_PTR(-ENOENT);
 501                 }
 502                 bo = to_vc4_bo(gem_obj);
 503
 504                 mode_cmd_local = *mode_cmd;
 505
 506                 if (bo->t_format) {
 507                         mode_cmd_local.modifier[0] =
 508                                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
 509                 } else {
 510                         mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
 511                 }
 512
 513                 drm_gem_object_put(gem_obj);
 514
 515                 mode_cmd = &mode_cmd_local;
 516         }
 517
 518         return drm_gem_fb_create(dev, file_priv, mode_cmd);
 519 }
 520
 521 /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
 522  * at a time and the HW only supports S0.9 scalars. To account for the latter,
 523  * we don't allow userland to set a CTM that we have no hope of approximating.
 524  */
 525 static int
 526 vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 527 {
 528         struct vc4_dev *vc4 = to_vc4_dev(dev);
 529         struct vc4_ctm_state *ctm_state = NULL;
 530         struct drm_crtc *crtc;
 531         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 532         struct drm_color_ctm *ctm;
 533         int i;
 534
 535         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 536                 /* CTM is being disabled. */
 537                 if (!new_crtc_state->ctm && old_crtc_state->ctm) {
 538                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 539                         if (IS_ERR(ctm_state))
 540                                 return PTR_ERR(ctm_state);
 541                         ctm_state->fifo = 0;
 542                 }
 543         }
 544
 545         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 546                 if (new_crtc_state->ctm == old_crtc_state->ctm)
 547                         continue;
 548
 549                 if (!ctm_state) {
 550                         ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
 551                         if (IS_ERR(ctm_state))
 552                                 return PTR_ERR(ctm_state);
 553                 }
 554
 555                 /* CTM is being enabled or the matrix changed. */
 556                 if (new_crtc_state->ctm) {
 557                         struct vc4_crtc_state *vc4_crtc_state =
 558                                 to_vc4_crtc_state(new_crtc_state);
 559
 560                         /* fifo is 1-based since 0 disables CTM. */
 561                         int fifo = vc4_crtc_state->assigned_channel + 1;
 562
 563                         /* Check userland isn't trying to turn on CTM for more
 564                          * than one CRTC at a time.
 565                          */
 566                         if (ctm_state->fifo && ctm_state->fifo != fifo) {
 567                                 DRM_DEBUG_DRIVER("Too many CTM configured\n");
 568                                 return -EINVAL;
 569                         }
 570
 571                         /* Check we can approximate the specified CTM.
 572                          * We disallow scalars |c| > 1.0 since the HW has
 573                          * no integer bits.
 574                          */
 575                         ctm = new_crtc_state->ctm->data;
 576                         for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
 577                                 u64 val = ctm->matrix[i];
 578
 579                                 val &= ~BIT_ULL(63);
 580                                 if (val > BIT_ULL(32))
 581                                         return -EINVAL;
 582                         }
 583
 584                         ctm_state->fifo = fifo;
 585                         ctm_state->ctm = ctm;
 586                 }
 587         }
 588
 589         return 0;
 590 }
 591
 592 static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
 593 {
 594         struct drm_plane_state *old_plane_state, *new_plane_state;
 595         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 596         struct vc4_load_tracker_state *load_state;
 597         struct drm_private_state *priv_state;
 598         struct drm_plane *plane;
 599         int i;
 600
 601         priv_state = drm_atomic_get_private_obj_state(state,
 602                                                       &vc4->load_tracker);
 603         if (IS_ERR(priv_state))
 604                 return PTR_ERR(priv_state);
 605
 606         load_state = to_vc4_load_tracker_state(priv_state);
 607         for_each_oldnew_plane_in_state(state, plane, old_plane_state,
 608                                        new_plane_state, i) {
 609                 struct vc4_plane_state *vc4_plane_state;
 610
 611                 if (old_plane_state->fb && old_plane_state->crtc) {
 612                         vc4_plane_state = to_vc4_plane_state(old_plane_state);
 613                         load_state->membus_load -= vc4_plane_state->membus_load;
 614                         load_state->hvs_load -= vc4_plane_state->hvs_load;
 615                 }
 616
 617                 if (new_plane_state->fb && new_plane_state->crtc) {
 618                         vc4_plane_state = to_vc4_plane_state(new_plane_state);
 619                         load_state->membus_load += vc4_plane_state->membus_load;
 620                         load_state->hvs_load += vc4_plane_state->hvs_load;
 621                 }
 622         }
 623
 624         /* Don't check the load when the tracker is disabled. */
 625         if (!vc4->load_tracker_enabled)
 626                 return 0;
 627
 628         /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
 629          * the system work when other blocks are accessing the memory.
 630          */
 631         if (load_state->membus_load > SZ_1G + SZ_512M)
 632                 return -ENOSPC;
 633
 634         /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
 635          * consider the maximum number of cycles is 240M.
 636          */
 637         if (load_state->hvs_load > 240000000ULL)
 638                 return -ENOSPC;
 639
 640         return 0;
 641 }
 642
 643 static struct drm_private_state *
 644 vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
 645 {
 646         struct vc4_load_tracker_state *state;
 647
 648         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 649         if (!state)
 650                 return NULL;
 651
 652         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 653
 654         return &state->base;
 655 }
 656
 657 static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
 658                                            struct drm_private_state *state)
 659 {
 660         struct vc4_load_tracker_state *load_state;
 661
 662         load_state = to_vc4_load_tracker_state(state);
 663         kfree(load_state);
 664 }
 665
 666 static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
 667         .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
 668         .atomic_destroy_state = vc4_load_tracker_destroy_state,
 669 };
 670
 671 static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
 672 {
 673         struct vc4_dev *vc4 = to_vc4_dev(dev);
 674
 675         drm_atomic_private_obj_fini(&vc4->load_tracker);
 676 }
 677
 678 static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
 679 {
 680         struct vc4_load_tracker_state *load_state;
 681
 682         load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
 683         if (!load_state)
 684                 return -ENOMEM;
 685
 686         drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
 687                                     &load_state->base,
 688                                     &vc4_load_tracker_state_funcs);
 689
 690         return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL);
 691 }
 692
 693 static struct drm_private_state *
 694 vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
 695 {
 696         struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state);
 697         struct vc4_hvs_state *state;
 698         unsigned int i;
 699
 700         state = kzalloc(sizeof(*state), GFP_KERNEL);
 701         if (!state)
 702                 return NULL;
 703
 704         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 705
 706         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 707                 state->fifo_state[i].in_use = old_state->fifo_state[i].in_use;
 708                 state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load;
 709         }
 710
 711         state->core_clock_rate = old_state->core_clock_rate;
 712
 713         return &state->base;
 714 }
 715
 716 static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,
 717                                            struct drm_private_state *state)
 718 {
 719         struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
 720         unsigned int i;
 721
 722         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 723                 if (!hvs_state->fifo_state[i].pending_commit)
 724                         continue;
 725
 726                 drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit);
 727         }
 728
 729         kfree(hvs_state);
 730 }
 731
 732 static void vc4_hvs_channels_print_state(struct drm_printer *p,
 733                                          const struct drm_private_state *state)
 734 {
 735         struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
 736         unsigned int i;
 737
 738         drm_printf(p, "HVS State\n");
 739         drm_printf(p, "\tCore Clock Rate: %lu\n", hvs_state->core_clock_rate);
 740
 741         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 742                 drm_printf(p, "\tChannel %d\n", i);
 743                 drm_printf(p, "\t\tin use=%d\n", hvs_state->fifo_state[i].in_use);
 744                 drm_printf(p, "\t\tload=%lu\n", hvs_state->fifo_state[i].fifo_load);
 745         }
 746 }
 747
 748 static const struct drm_private_state_funcs vc4_hvs_state_funcs = {
 749         .atomic_duplicate_state = vc4_hvs_channels_duplicate_state,
 750         .atomic_destroy_state = vc4_hvs_channels_destroy_state,
 751         .atomic_print_state = vc4_hvs_channels_print_state,
 752 };
 753
 754 static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused)
 755 {
 756         struct vc4_dev *vc4 = to_vc4_dev(dev);
 757
 758         drm_atomic_private_obj_fini(&vc4->hvs_channels);
 759 }
 760
 761 static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
 762 {
 763         struct vc4_hvs_state *state;
 764
 765         state = kzalloc(sizeof(*state), GFP_KERNEL);
 766         if (!state)
 767                 return -ENOMEM;
 768
 769         drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels,
 770                                     &state->base,
 771                                     &vc4_hvs_state_funcs);
 772
 773         return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL);
 774 }
 775
 776 /*
 777  * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
 778  * the TXP (and therefore all the CRTCs found on that platform).
 779  *
 780  * The naive (and our initial) implementation would just iterate over
 781  * all the active CRTCs, try to find a suitable FIFO, and then remove it
 782  * from the pool of available FIFOs. However, there are a few corner
 783  * cases that need to be considered:
 784  *
 785  * - When running in a dual-display setup (so with two CRTCs involved),
 786  *   we can update the state of a single CRTC (for example by changing
 787  *   its mode using xrandr under X11) without affecting the other. In
 788  *   this case, the other CRTC wouldn't be in the state at all, so we
 789  *   need to consider all the running CRTCs in the DRM device to assign
 790  *   a FIFO, not just the one in the state.
 791  *
 792  * - To fix the above, we can't use drm_atomic_get_crtc_state on all
 793  *   enabled CRTCs to pull their CRTC state into the global state, since
 794  *   a page flip would start considering their vblank to complete. Since
 795  *   we don't have a guarantee that they are actually active, that
 796  *   vblank might never happen, and shouldn't even be considered if we
 797  *   want to do a page flip on a single CRTC. That can be tested by
 798  *   doing a modetest -v first on HDMI1 and then on HDMI0.
 799  *
 800  * - Since we need the pixelvalve to be disabled and enabled back when
 801  *   the FIFO is changed, we should keep the FIFO assigned for as long
 802  *   as the CRTC is enabled, only considering it free again once that
 803  *   CRTC has been disabled. This can be tested by booting X11 on a
 804  *   single display, and changing the resolution down and then back up.
 805  */
 806 static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
 807                                       struct drm_atomic_state *state)
 808 {
 809         struct vc4_hvs_state *hvs_new_state;
 810         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 811         struct drm_crtc *crtc;
 812         unsigned int unassigned_channels = 0;
 813         unsigned int i;
 814
 815         hvs_new_state = vc4_hvs_get_global_state(state);
 816         if (IS_ERR(hvs_new_state))
 817                 return PTR_ERR(hvs_new_state);
 818
 819         for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++)
 820                 if (!hvs_new_state->fifo_state[i].in_use)
 821                         unassigned_channels |= BIT(i);
 822
 823         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 824                 struct vc4_crtc_state *old_vc4_crtc_state =
 825                         to_vc4_crtc_state(old_crtc_state);
 826                 struct vc4_crtc_state *new_vc4_crtc_state =
 827                         to_vc4_crtc_state(new_crtc_state);
 828                 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 829                 unsigned int matching_channels;
 830                 unsigned int channel;
 831
 832                 drm_dbg(dev, "%s: Trying to find a channel.\n", crtc->name);
 833
 834                 /* Nothing to do here, let's skip it */
 835                 if (old_crtc_state->enable == new_crtc_state->enable) {
 836                         if (new_crtc_state->enable)
 837                                 drm_dbg(dev, "%s: Already enabled, reusing channel %d.\n",
 838                                         crtc->name, new_vc4_crtc_state->assigned_channel);
 839                         else
 840                                 drm_dbg(dev, "%s: Disabled, ignoring.\n", crtc->name);
 841
 842                         continue;
 843                 }
 844
 845                 /* Muxing will need to be modified, mark it as such */
 846                 new_vc4_crtc_state->update_muxing = true;
 847
 848                 /* If we're disabling our CRTC, we put back our channel */
 849                 if (!new_crtc_state->enable) {
 850                         channel = old_vc4_crtc_state->assigned_channel;
 851
 852                         drm_dbg(dev, "%s: Disabling, Freeing channel %d\n",
 853                                 crtc->name, channel);
 854
 855                         hvs_new_state->fifo_state[channel].in_use = false;
 856                         new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
 857                         continue;
 858                 }
 859
 860                 /*
 861                  * The problem we have to solve here is that we have
 862                  * up to 7 encoders, connected to up to 6 CRTCs.
 863                  *
 864                  * Those CRTCs, depending on the instance, can be
 865                  * routed to 1, 2 or 3 HVS FIFOs, and we need to set
 866                  * the change the muxing between FIFOs and outputs in
 867                  * the HVS accordingly.
 868                  *
 869                  * It would be pretty hard to come up with an
 870                  * algorithm that would generically solve
 871                  * this. However, the current routing trees we support
 872                  * allow us to simplify a bit the problem.
 873                  *
 874                  * Indeed, with the current supported layouts, if we
 875                  * try to assign in the ascending crtc index order the
 876                  * FIFOs, we can't fall into the situation where an
 877                  * earlier CRTC that had multiple routes is assigned
 878                  * one that was the only option for a later CRTC.
 879                  *
 880                  * If the layout changes and doesn't give us that in
 881                  * the future, we will need to have something smarter,
 882                  * but it works so far.
 883                  */
 884                 matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels;
 885                 if (!matching_channels)
 886                         return -EINVAL;
 887
 888                 channel = ffs(matching_channels) - 1;
 889
 890                 drm_dbg(dev, "Assigned HVS channel %d to CRTC %s\n", channel, crtc->name);
 891                 new_vc4_crtc_state->assigned_channel = channel;
 892                 unassigned_channels &= ~BIT(channel);
 893                 hvs_new_state->fifo_state[channel].in_use = true;
 894         }
 895
 896         return 0;
 897 }
 898
 899 static int
 900 vc4_core_clock_atomic_check(struct drm_atomic_state *state)
 901 {
 902         struct vc4_dev *vc4 = to_vc4_dev(state->dev);
 903         struct drm_private_state *priv_state;
 904         struct vc4_hvs_state *hvs_new_state;
 905         struct vc4_load_tracker_state *load_state;
 906         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 907         struct drm_crtc *crtc;
 908         unsigned int num_outputs;
 909         unsigned long pixel_rate;
 910         unsigned long cob_rate;
 911         unsigned int i;
 912
 913         priv_state = drm_atomic_get_private_obj_state(state,
 914                                                       &vc4->load_tracker);
 915         if (IS_ERR(priv_state))
 916                 return PTR_ERR(priv_state);
 917
 918         load_state = to_vc4_load_tracker_state(priv_state);
 919
 920         hvs_new_state = vc4_hvs_get_global_state(state);
 921         if (IS_ERR(hvs_new_state))
 922                 return PTR_ERR(hvs_new_state);
 923
 924         for_each_oldnew_crtc_in_state(state, crtc,
 925                                       old_crtc_state,
 926                                       new_crtc_state,
 927                                       i) {
 928                 if (old_crtc_state->active) {
 929                         struct vc4_crtc_state *old_vc4_state =
 930                                 to_vc4_crtc_state(old_crtc_state);
 931                         unsigned int channel = old_vc4_state->assigned_channel;
 932
 933                         hvs_new_state->fifo_state[channel].fifo_load = 0;
 934                 }
 935
 936                 if (new_crtc_state->active) {
 937                         struct vc4_crtc_state *new_vc4_state =
 938                                 to_vc4_crtc_state(new_crtc_state);
 939                         unsigned int channel = new_vc4_state->assigned_channel;
 940
 941                         hvs_new_state->fifo_state[channel].fifo_load =
 942                                 new_vc4_state->hvs_load;
 943                 }
 944         }
 945
 946         cob_rate = 0;
 947         num_outputs = 0;
 948         for (i = 0; i < HVS_NUM_CHANNELS; i++) {
 949                 if (!hvs_new_state->fifo_state[i].in_use)
 950                         continue;
 951
 952                 num_outputs++;
 953                 cob_rate = max_t(unsigned long,
 954                                  hvs_new_state->fifo_state[i].fifo_load,
 955                                  cob_rate);
 956         }
 957
 958         pixel_rate = load_state->hvs_load;
 959         if (num_outputs > 1) {
 960                 pixel_rate = (pixel_rate * 40) / 100;
 961         } else {
 962                 pixel_rate = (pixel_rate * 60) / 100;
 963         }
 964
 965         hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate);
 966
 967         return 0;
 968 }
 969
 970
 971 static int
 972 vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
 973 {
 974         int ret;
 975
 976         ret = vc4_pv_muxing_atomic_check(dev, state);
 977         if (ret)
 978                 return ret;
 979
 980         ret = vc4_ctm_atomic_check(dev, state);
 981         if (ret < 0)
 982                 return ret;
 983
 984         ret = drm_atomic_helper_check(dev, state);
 985         if (ret)
 986                 return ret;
 987
 988         ret = vc4_load_tracker_atomic_check(state);
 989         if (ret)
 990                 return ret;
 991
 992         return vc4_core_clock_atomic_check(state);
 993 }
 994
 995 static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = {
 996         .atomic_commit_setup    = vc4_atomic_commit_setup,
 997         .atomic_commit_tail     = vc4_atomic_commit_tail,
 998 };
 999
1000 static const struct drm_mode_config_funcs vc4_mode_funcs = {
1001         .atomic_check = vc4_atomic_check,
1002         .atomic_commit = drm_atomic_helper_commit,
1003         .fb_create = vc4_fb_create,
1004 };
1005
1006 static const struct drm_mode_config_funcs vc5_mode_funcs = {
1007         .atomic_check = vc4_atomic_check,
1008         .atomic_commit = drm_atomic_helper_commit,
1009         .fb_create = drm_gem_fb_create,
1010 };
1011
1012 int vc4_kms_load(struct drm_device *dev)
1013 {
1014         struct vc4_dev *vc4 = to_vc4_dev(dev);
1015         int ret;
1016
1017         /*
1018          * The limits enforced by the load tracker aren't relevant for
1019          * the BCM2711, but the load tracker computations are used for
1020          * the core clock rate calculation.
1021          */
1022         if (!vc4->is_vc5) {
1023                 /* Start with the load tracker enabled. Can be
1024                  * disabled through the debugfs load_tracker file.
1025                  */
1026                 vc4->load_tracker_enabled = true;
1027         }
1028
1029         /* Set support for vblank irq fast disable, before drm_vblank_init() */
1030         dev->vblank_disable_immediate = true;
1031
1032         ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
1033         if (ret < 0) {
1034                 dev_err(dev->dev, "failed to initialize vblank\n");
1035                 return ret;
1036         }
1037
1038         if (vc4->is_vc5) {
1039                 dev->mode_config.max_width = 7680;
1040                 dev->mode_config.max_height = 7680;
1041         } else {
1042                 dev->mode_config.max_width = 2048;
1043                 dev->mode_config.max_height = 2048;
1044         }
1045
1046         dev->mode_config.funcs = vc4->is_vc5 ? &vc5_mode_funcs : &vc4_mode_funcs;
1047         dev->mode_config.helper_private = &vc4_mode_config_helpers;
1048         dev->mode_config.preferred_depth = 24;
1049         dev->mode_config.async_page_flip = true;
1050
1051         ret = vc4_ctm_obj_init(vc4);
1052         if (ret)
1053                 return ret;
1054
1055         ret = vc4_load_tracker_obj_init(vc4);
1056         if (ret)
1057                 return ret;
1058
1059         ret = vc4_hvs_channels_obj_init(vc4);
1060         if (ret)
1061                 return ret;
1062
1063         drm_mode_config_reset(dev);
1064
1065         drm_kms_helper_poll_init(dev);
1066
1067         return 0;
1068 }