drivers/gpu/drm/i915/display/intel_tv.c

   1 /*
   2  * Copyright © 2006-2008 Intel Corporation
   3  *   Jesse Barnes <[email protected]>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Eric Anholt <[email protected]>
  26  *
  27  */
  28
  29 /** @file
  30  * Integrated TV-out support for the 915GM and 945GM.
  31  */
  32
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include "i915_drv.h"
  38 #include "intel_connector.h"
  39 #include "intel_crtc.h"
  40 #include "intel_de.h"
  41 #include "intel_display_types.h"
  42 #include "intel_dpll.h"
  43 #include "intel_hotplug.h"
  44 #include "intel_tv.h"
  45
  46 enum tv_margin {
  47         TV_MARGIN_LEFT, TV_MARGIN_TOP,
  48         TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
  49 };
  50
  51 struct intel_tv {
  52         struct intel_encoder base;
  53
  54         int type;
  55 };
  56
  57 struct video_levels {
  58         u16 blank, black;
  59         u8 burst;
  60 };
  61
  62 struct color_conversion {
  63         u16 ry, gy, by, ay;
  64         u16 ru, gu, bu, au;
  65         u16 rv, gv, bv, av;
  66 };
  67
  68 static const u32 filter_table[] = {
  69         0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
  70         0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
  71         0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
  72         0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
  73         0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
  74         0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
  75         0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
  76         0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
  77         0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
  78         0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
  79         0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
  80         0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
  81         0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
  82         0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
  83         0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
  84         0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
  85         0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
  86         0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
  87         0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
  88         0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
  89         0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
  90         0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
  91         0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
  92         0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
  93         0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
  94         0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
  95         0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
  96         0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
  97         0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
  98         0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
  99         0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
 100         0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
 101         0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
 102         0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
 103         0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
 104         0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
 105         0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
 106         0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
 107         0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
 108         0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
 109         0x28003100, 0x28002F00, 0x00003100, 0x36403000,
 110         0x2D002CC0, 0x30003640, 0x2D0036C0,
 111         0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
 112         0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
 113         0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
 114         0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
 115         0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
 116         0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
 117         0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
 118         0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
 119         0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
 120         0x28003100, 0x28002F00, 0x00003100,
 121 };
 122
 123 /*
 124  * Color conversion values have 3 separate fixed point formats:
 125  *
 126  * 10 bit fields (ay, au)
 127  *   1.9 fixed point (b.bbbbbbbbb)
 128  * 11 bit fields (ry, by, ru, gu, gv)
 129  *   exp.mantissa (ee.mmmmmmmmm)
 130  *   ee = 00 = 10^-1 (0.mmmmmmmmm)
 131  *   ee = 01 = 10^-2 (0.0mmmmmmmmm)
 132  *   ee = 10 = 10^-3 (0.00mmmmmmmmm)
 133  *   ee = 11 = 10^-4 (0.000mmmmmmmmm)
 134  * 12 bit fields (gy, rv, bu)
 135  *   exp.mantissa (eee.mmmmmmmmm)
 136  *   eee = 000 = 10^-1 (0.mmmmmmmmm)
 137  *   eee = 001 = 10^-2 (0.0mmmmmmmmm)
 138  *   eee = 010 = 10^-3 (0.00mmmmmmmmm)
 139  *   eee = 011 = 10^-4 (0.000mmmmmmmmm)
 140  *   eee = 100 = reserved
 141  *   eee = 101 = reserved
 142  *   eee = 110 = reserved
 143  *   eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
 144  *
 145  * Saturation and contrast are 8 bits, with their own representation:
 146  * 8 bit field (saturation, contrast)
 147  *   exp.mantissa (ee.mmmmmm)
 148  *   ee = 00 = 10^-1 (0.mmmmmm)
 149  *   ee = 01 = 10^0 (m.mmmmm)
 150  *   ee = 10 = 10^1 (mm.mmmm)
 151  *   ee = 11 = 10^2 (mmm.mmm)
 152  *
 153  * Simple conversion function:
 154  *
 155  * static u32
 156  * float_to_csc_11(float f)
 157  * {
 158  *     u32 exp;
 159  *     u32 mant;
 160  *     u32 ret;
 161  *
 162  *     if (f < 0)
 163  *         f = -f;
 164  *
 165  *     if (f >= 1) {
 166  *         exp = 0x7;
 167  *         mant = 1 << 8;
 168  *     } else {
 169  *         for (exp = 0; exp < 3 && f < 0.5; exp++)
 170  *         f *= 2.0;
 171  *         mant = (f * (1 << 9) + 0.5);
 172  *         if (mant >= (1 << 9))
 173  *             mant = (1 << 9) - 1;
 174  *     }
 175  *     ret = (exp << 9) | mant;
 176  *     return ret;
 177  * }
 178  */
 179
 180 /*
 181  * Behold, magic numbers!  If we plant them they might grow a big
 182  * s-video cable to the sky... or something.
 183  *
 184  * Pre-converted to appropriate hex value.
 185  */
 186
 187 /*
 188  * PAL & NTSC values for composite & s-video connections
 189  */
 190 static const struct color_conversion ntsc_m_csc_composite = {
 191         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
 192         .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
 193         .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
 194 };
 195
 196 static const struct video_levels ntsc_m_levels_composite = {
 197         .blank = 225, .black = 267, .burst = 113,
 198 };
 199
 200 static const struct color_conversion ntsc_m_csc_svideo = {
 201         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
 202         .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
 203         .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
 204 };
 205
 206 static const struct video_levels ntsc_m_levels_svideo = {
 207         .blank = 266, .black = 316, .burst = 133,
 208 };
 209
 210 static const struct color_conversion ntsc_j_csc_composite = {
 211         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
 212         .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
 213         .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
 214 };
 215
 216 static const struct video_levels ntsc_j_levels_composite = {
 217         .blank = 225, .black = 225, .burst = 113,
 218 };
 219
 220 static const struct color_conversion ntsc_j_csc_svideo = {
 221         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
 222         .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
 223         .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
 224 };
 225
 226 static const struct video_levels ntsc_j_levels_svideo = {
 227         .blank = 266, .black = 266, .burst = 133,
 228 };
 229
 230 static const struct color_conversion pal_csc_composite = {
 231         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
 232         .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
 233         .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
 234 };
 235
 236 static const struct video_levels pal_levels_composite = {
 237         .blank = 237, .black = 237, .burst = 118,
 238 };
 239
 240 static const struct color_conversion pal_csc_svideo = {
 241         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
 242         .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
 243         .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
 244 };
 245
 246 static const struct video_levels pal_levels_svideo = {
 247         .blank = 280, .black = 280, .burst = 139,
 248 };
 249
 250 static const struct color_conversion pal_m_csc_composite = {
 251         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
 252         .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
 253         .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
 254 };
 255
 256 static const struct video_levels pal_m_levels_composite = {
 257         .blank = 225, .black = 267, .burst = 113,
 258 };
 259
 260 static const struct color_conversion pal_m_csc_svideo = {
 261         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
 262         .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
 263         .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
 264 };
 265
 266 static const struct video_levels pal_m_levels_svideo = {
 267         .blank = 266, .black = 316, .burst = 133,
 268 };
 269
 270 static const struct color_conversion pal_n_csc_composite = {
 271         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
 272         .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
 273         .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
 274 };
 275
 276 static const struct video_levels pal_n_levels_composite = {
 277         .blank = 225, .black = 267, .burst = 118,
 278 };
 279
 280 static const struct color_conversion pal_n_csc_svideo = {
 281         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
 282         .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
 283         .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
 284 };
 285
 286 static const struct video_levels pal_n_levels_svideo = {
 287         .blank = 266, .black = 316, .burst = 139,
 288 };
 289
 290 /*
 291  * Component connections
 292  */
 293 static const struct color_conversion sdtv_csc_yprpb = {
 294         .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
 295         .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
 296         .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
 297 };
 298
 299 static const struct color_conversion hdtv_csc_yprpb = {
 300         .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
 301         .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
 302         .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
 303 };
 304
 305 static const struct video_levels component_levels = {
 306         .blank = 279, .black = 279, .burst = 0,
 307 };
 308
 309
 310 struct tv_mode {
 311         const char *name;
 312
 313         u32 clock;
 314         u16 refresh; /* in millihertz (for precision) */
 315         u8 oversample;
 316         u8 hsync_end;
 317         u16 hblank_start, hblank_end, htotal;
 318         bool progressive : 1, trilevel_sync : 1, component_only : 1;
 319         u8 vsync_start_f1, vsync_start_f2, vsync_len;
 320         bool veq_ena : 1;
 321         u8 veq_start_f1, veq_start_f2, veq_len;
 322         u8 vi_end_f1, vi_end_f2;
 323         u16 nbr_end;
 324         bool burst_ena : 1;
 325         u8 hburst_start, hburst_len;
 326         u8 vburst_start_f1;
 327         u16 vburst_end_f1;
 328         u8 vburst_start_f2;
 329         u16 vburst_end_f2;
 330         u8 vburst_start_f3;
 331         u16 vburst_end_f3;
 332         u8 vburst_start_f4;
 333         u16 vburst_end_f4;
 334         /*
 335          * subcarrier programming
 336          */
 337         u16 dda2_size, dda3_size;
 338         u8 dda1_inc;
 339         u16 dda2_inc, dda3_inc;
 340         u32 sc_reset;
 341         bool pal_burst : 1;
 342         /*
 343          * blank/black levels
 344          */
 345         const struct video_levels *composite_levels, *svideo_levels;
 346         const struct color_conversion *composite_color, *svideo_color;
 347         const u32 *filter_table;
 348 };
 349
 350
 351 /*
 352  * Sub carrier DDA
 353  *
 354  *  I think this works as follows:
 355  *
 356  *  subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
 357  *
 358  * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
 359  *
 360  * So,
 361  *  dda1_ideal = subcarrier/pixel * 4096
 362  *  dda1_inc = floor (dda1_ideal)
 363  *  dda2 = dda1_ideal - dda1_inc
 364  *
 365  *  then pick a ratio for dda2 that gives the closest approximation. If
 366  *  you can't get close enough, you can play with dda3 as well. This
 367  *  seems likely to happen when dda2 is small as the jumps would be larger
 368  *
 369  * To invert this,
 370  *
 371  *  pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
 372  *
 373  * The constants below were all computed using a 107.520MHz clock
 374  */
 375
 376 /*
 377  * Register programming values for TV modes.
 378  *
 379  * These values account for -1s required.
 380  */
 381 static const struct tv_mode tv_modes[] = {
 382         {
 383                 .name           = "NTSC-M",
 384                 .clock          = 108000,
 385                 .refresh        = 59940,
 386                 .oversample     = 8,
 387                 .component_only = false,
 388                 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
 389
 390                 .hsync_end      = 64,               .hblank_end         = 124,
 391                 .hblank_start   = 836,              .htotal             = 857,
 392
 393                 .progressive    = false,            .trilevel_sync = false,
 394
 395                 .vsync_start_f1 = 6,                .vsync_start_f2     = 7,
 396                 .vsync_len      = 6,
 397
 398                 .veq_ena        = true,             .veq_start_f1       = 0,
 399                 .veq_start_f2   = 1,                .veq_len            = 18,
 400
 401                 .vi_end_f1      = 20,               .vi_end_f2          = 21,
 402                 .nbr_end        = 240,
 403
 404                 .burst_ena      = true,
 405                 .hburst_start   = 72,               .hburst_len         = 34,
 406                 .vburst_start_f1 = 9,               .vburst_end_f1      = 240,
 407                 .vburst_start_f2 = 10,              .vburst_end_f2      = 240,
 408                 .vburst_start_f3 = 9,               .vburst_end_f3      = 240,
 409                 .vburst_start_f4 = 10,              .vburst_end_f4      = 240,
 410
 411                 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
 412                 .dda1_inc       =    135,
 413                 .dda2_inc       =  20800,           .dda2_size          =  27456,
 414                 .dda3_inc       =      0,           .dda3_size          =      0,
 415                 .sc_reset       = TV_SC_RESET_EVERY_4,
 416                 .pal_burst      = false,
 417
 418                 .composite_levels = &ntsc_m_levels_composite,
 419                 .composite_color = &ntsc_m_csc_composite,
 420                 .svideo_levels  = &ntsc_m_levels_svideo,
 421                 .svideo_color = &ntsc_m_csc_svideo,
 422
 423                 .filter_table = filter_table,
 424         },
 425         {
 426                 .name           = "NTSC-443",
 427                 .clock          = 108000,
 428                 .refresh        = 59940,
 429                 .oversample     = 8,
 430                 .component_only = false,
 431                 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
 432                 .hsync_end      = 64,               .hblank_end         = 124,
 433                 .hblank_start   = 836,              .htotal             = 857,
 434
 435                 .progressive    = false,            .trilevel_sync = false,
 436
 437                 .vsync_start_f1 = 6,                .vsync_start_f2     = 7,
 438                 .vsync_len      = 6,
 439
 440                 .veq_ena        = true,             .veq_start_f1       = 0,
 441                 .veq_start_f2   = 1,                .veq_len            = 18,
 442
 443                 .vi_end_f1      = 20,               .vi_end_f2          = 21,
 444                 .nbr_end        = 240,
 445
 446                 .burst_ena      = true,
 447                 .hburst_start   = 72,               .hburst_len         = 34,
 448                 .vburst_start_f1 = 9,               .vburst_end_f1      = 240,
 449                 .vburst_start_f2 = 10,              .vburst_end_f2      = 240,
 450                 .vburst_start_f3 = 9,               .vburst_end_f3      = 240,
 451                 .vburst_start_f4 = 10,              .vburst_end_f4      = 240,
 452
 453                 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
 454                 .dda1_inc       =    168,
 455                 .dda2_inc       =   4093,       .dda2_size      =  27456,
 456                 .dda3_inc       =    310,       .dda3_size      =    525,
 457                 .sc_reset   = TV_SC_RESET_NEVER,
 458                 .pal_burst  = false,
 459
 460                 .composite_levels = &ntsc_m_levels_composite,
 461                 .composite_color = &ntsc_m_csc_composite,
 462                 .svideo_levels  = &ntsc_m_levels_svideo,
 463                 .svideo_color = &ntsc_m_csc_svideo,
 464
 465                 .filter_table = filter_table,
 466         },
 467         {
 468                 .name           = "NTSC-J",
 469                 .clock          = 108000,
 470                 .refresh        = 59940,
 471                 .oversample     = 8,
 472                 .component_only = false,
 473
 474                 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
 475                 .hsync_end      = 64,               .hblank_end         = 124,
 476                 .hblank_start = 836,        .htotal             = 857,
 477
 478                 .progressive    = false,    .trilevel_sync = false,
 479
 480                 .vsync_start_f1 = 6,        .vsync_start_f2     = 7,
 481                 .vsync_len      = 6,
 482
 483                 .veq_ena      = true,       .veq_start_f1       = 0,
 484                 .veq_start_f2 = 1,          .veq_len            = 18,
 485
 486                 .vi_end_f1      = 20,               .vi_end_f2          = 21,
 487                 .nbr_end        = 240,
 488
 489                 .burst_ena      = true,
 490                 .hburst_start   = 72,               .hburst_len         = 34,
 491                 .vburst_start_f1 = 9,               .vburst_end_f1      = 240,
 492                 .vburst_start_f2 = 10,              .vburst_end_f2      = 240,
 493                 .vburst_start_f3 = 9,               .vburst_end_f3      = 240,
 494                 .vburst_start_f4 = 10,              .vburst_end_f4      = 240,
 495
 496                 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
 497                 .dda1_inc       =    135,
 498                 .dda2_inc       =  20800,           .dda2_size          =  27456,
 499                 .dda3_inc       =      0,           .dda3_size          =      0,
 500                 .sc_reset       = TV_SC_RESET_EVERY_4,
 501                 .pal_burst      = false,
 502
 503                 .composite_levels = &ntsc_j_levels_composite,
 504                 .composite_color = &ntsc_j_csc_composite,
 505                 .svideo_levels  = &ntsc_j_levels_svideo,
 506                 .svideo_color = &ntsc_j_csc_svideo,
 507
 508                 .filter_table = filter_table,
 509         },
 510         {
 511                 .name           = "PAL-M",
 512                 .clock          = 108000,
 513                 .refresh        = 59940,
 514                 .oversample     = 8,
 515                 .component_only = false,
 516
 517                 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
 518                 .hsync_end      = 64,             .hblank_end           = 124,
 519                 .hblank_start = 836,      .htotal               = 857,
 520
 521                 .progressive    = false,            .trilevel_sync = false,
 522
 523                 .vsync_start_f1 = 6,                .vsync_start_f2     = 7,
 524                 .vsync_len      = 6,
 525
 526                 .veq_ena        = true,             .veq_start_f1       = 0,
 527                 .veq_start_f2   = 1,                .veq_len            = 18,
 528
 529                 .vi_end_f1      = 20,               .vi_end_f2          = 21,
 530                 .nbr_end        = 240,
 531
 532                 .burst_ena      = true,
 533                 .hburst_start   = 72,               .hburst_len         = 34,
 534                 .vburst_start_f1 = 9,               .vburst_end_f1      = 240,
 535                 .vburst_start_f2 = 10,              .vburst_end_f2      = 240,
 536                 .vburst_start_f3 = 9,               .vburst_end_f3      = 240,
 537                 .vburst_start_f4 = 10,              .vburst_end_f4      = 240,
 538
 539                 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
 540                 .dda1_inc       =    135,
 541                 .dda2_inc       =  16704,           .dda2_size          =  27456,
 542                 .dda3_inc       =      0,           .dda3_size          =      0,
 543                 .sc_reset       = TV_SC_RESET_EVERY_8,
 544                 .pal_burst  = true,
 545
 546                 .composite_levels = &pal_m_levels_composite,
 547                 .composite_color = &pal_m_csc_composite,
 548                 .svideo_levels  = &pal_m_levels_svideo,
 549                 .svideo_color = &pal_m_csc_svideo,
 550
 551                 .filter_table = filter_table,
 552         },
 553         {
 554                 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
 555                 .name       = "PAL-N",
 556                 .clock          = 108000,
 557                 .refresh        = 50000,
 558                 .oversample     = 8,
 559                 .component_only = false,
 560
 561                 .hsync_end      = 64,               .hblank_end         = 128,
 562                 .hblank_start = 844,        .htotal             = 863,
 563
 564                 .progressive  = false,    .trilevel_sync = false,
 565
 566
 567                 .vsync_start_f1 = 6,       .vsync_start_f2      = 7,
 568                 .vsync_len      = 6,
 569
 570                 .veq_ena        = true,             .veq_start_f1       = 0,
 571                 .veq_start_f2   = 1,                .veq_len            = 18,
 572
 573                 .vi_end_f1      = 24,               .vi_end_f2          = 25,
 574                 .nbr_end        = 286,
 575
 576                 .burst_ena      = true,
 577                 .hburst_start = 73,         .hburst_len         = 34,
 578                 .vburst_start_f1 = 8,       .vburst_end_f1      = 285,
 579                 .vburst_start_f2 = 8,       .vburst_end_f2      = 286,
 580                 .vburst_start_f3 = 9,       .vburst_end_f3      = 286,
 581                 .vburst_start_f4 = 9,       .vburst_end_f4      = 285,
 582
 583
 584                 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
 585                 .dda1_inc       =    135,
 586                 .dda2_inc       =  23578,       .dda2_size      =  27648,
 587                 .dda3_inc       =    134,       .dda3_size      =    625,
 588                 .sc_reset   = TV_SC_RESET_EVERY_8,
 589                 .pal_burst  = true,
 590
 591                 .composite_levels = &pal_n_levels_composite,
 592                 .composite_color = &pal_n_csc_composite,
 593                 .svideo_levels  = &pal_n_levels_svideo,
 594                 .svideo_color = &pal_n_csc_svideo,
 595
 596                 .filter_table = filter_table,
 597         },
 598         {
 599                 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
 600                 .name       = "PAL",
 601                 .clock          = 108000,
 602                 .refresh        = 50000,
 603                 .oversample     = 8,
 604                 .component_only = false,
 605
 606                 .hsync_end      = 64,               .hblank_end         = 142,
 607                 .hblank_start   = 844,      .htotal             = 863,
 608
 609                 .progressive    = false,    .trilevel_sync = false,
 610
 611                 .vsync_start_f1 = 5,        .vsync_start_f2     = 6,
 612                 .vsync_len      = 5,
 613
 614                 .veq_ena        = true,     .veq_start_f1       = 0,
 615                 .veq_start_f2   = 1,        .veq_len            = 15,
 616
 617                 .vi_end_f1      = 24,               .vi_end_f2          = 25,
 618                 .nbr_end        = 286,
 619
 620                 .burst_ena      = true,
 621                 .hburst_start   = 73,               .hburst_len         = 32,
 622                 .vburst_start_f1 = 8,               .vburst_end_f1      = 285,
 623                 .vburst_start_f2 = 8,               .vburst_end_f2      = 286,
 624                 .vburst_start_f3 = 9,               .vburst_end_f3      = 286,
 625                 .vburst_start_f4 = 9,               .vburst_end_f4      = 285,
 626
 627                 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
 628                 .dda1_inc       =    168,
 629                 .dda2_inc       =   4122,       .dda2_size      =  27648,
 630                 .dda3_inc       =     67,       .dda3_size      =    625,
 631                 .sc_reset   = TV_SC_RESET_EVERY_8,
 632                 .pal_burst  = true,
 633
 634                 .composite_levels = &pal_levels_composite,
 635                 .composite_color = &pal_csc_composite,
 636                 .svideo_levels  = &pal_levels_svideo,
 637                 .svideo_color = &pal_csc_svideo,
 638
 639                 .filter_table = filter_table,
 640         },
 641         {
 642                 .name       = "480p",
 643                 .clock          = 108000,
 644                 .refresh        = 59940,
 645                 .oversample     = 4,
 646                 .component_only = true,
 647
 648                 .hsync_end      = 64,               .hblank_end         = 122,
 649                 .hblank_start   = 842,              .htotal             = 857,
 650
 651                 .progressive    = true,             .trilevel_sync = false,
 652
 653                 .vsync_start_f1 = 12,               .vsync_start_f2     = 12,
 654                 .vsync_len      = 12,
 655
 656                 .veq_ena        = false,
 657
 658                 .vi_end_f1      = 44,               .vi_end_f2          = 44,
 659                 .nbr_end        = 479,
 660
 661                 .burst_ena      = false,
 662
 663                 .filter_table = filter_table,
 664         },
 665         {
 666                 .name       = "576p",
 667                 .clock          = 108000,
 668                 .refresh        = 50000,
 669                 .oversample     = 4,
 670                 .component_only = true,
 671
 672                 .hsync_end      = 64,               .hblank_end         = 139,
 673                 .hblank_start   = 859,              .htotal             = 863,
 674
 675                 .progressive    = true,             .trilevel_sync = false,
 676
 677                 .vsync_start_f1 = 10,               .vsync_start_f2     = 10,
 678                 .vsync_len      = 10,
 679
 680                 .veq_ena        = false,
 681
 682                 .vi_end_f1      = 48,               .vi_end_f2          = 48,
 683                 .nbr_end        = 575,
 684
 685                 .burst_ena      = false,
 686
 687                 .filter_table = filter_table,
 688         },
 689         {
 690                 .name       = "720p@60Hz",
 691                 .clock          = 148500,
 692                 .refresh        = 60000,
 693                 .oversample     = 2,
 694                 .component_only = true,
 695
 696                 .hsync_end      = 80,               .hblank_end         = 300,
 697                 .hblank_start   = 1580,             .htotal             = 1649,
 698
 699                 .progressive    = true,             .trilevel_sync = true,
 700
 701                 .vsync_start_f1 = 10,               .vsync_start_f2     = 10,
 702                 .vsync_len      = 10,
 703
 704                 .veq_ena        = false,
 705
 706                 .vi_end_f1      = 29,               .vi_end_f2          = 29,
 707                 .nbr_end        = 719,
 708
 709                 .burst_ena      = false,
 710
 711                 .filter_table = filter_table,
 712         },
 713         {
 714                 .name       = "720p@50Hz",
 715                 .clock          = 148500,
 716                 .refresh        = 50000,
 717                 .oversample     = 2,
 718                 .component_only = true,
 719
 720                 .hsync_end      = 80,               .hblank_end         = 300,
 721                 .hblank_start   = 1580,             .htotal             = 1979,
 722
 723                 .progressive    = true,             .trilevel_sync = true,
 724
 725                 .vsync_start_f1 = 10,               .vsync_start_f2     = 10,
 726                 .vsync_len      = 10,
 727
 728                 .veq_ena        = false,
 729
 730                 .vi_end_f1      = 29,               .vi_end_f2          = 29,
 731                 .nbr_end        = 719,
 732
 733                 .burst_ena      = false,
 734
 735                 .filter_table = filter_table,
 736         },
 737         {
 738                 .name       = "1080i@50Hz",
 739                 .clock          = 148500,
 740                 .refresh        = 50000,
 741                 .oversample     = 2,
 742                 .component_only = true,
 743
 744                 .hsync_end      = 88,               .hblank_end         = 235,
 745                 .hblank_start   = 2155,             .htotal             = 2639,
 746
 747                 .progressive    = false,          .trilevel_sync = true,
 748
 749                 .vsync_start_f1 = 4,              .vsync_start_f2     = 5,
 750                 .vsync_len      = 10,
 751
 752                 .veq_ena        = true,     .veq_start_f1       = 4,
 753                 .veq_start_f2   = 4,        .veq_len            = 10,
 754
 755
 756                 .vi_end_f1      = 21,           .vi_end_f2          = 22,
 757                 .nbr_end        = 539,
 758
 759                 .burst_ena      = false,
 760
 761                 .filter_table = filter_table,
 762         },
 763         {
 764                 .name       = "1080i@60Hz",
 765                 .clock          = 148500,
 766                 .refresh        = 60000,
 767                 .oversample     = 2,
 768                 .component_only = true,
 769
 770                 .hsync_end      = 88,               .hblank_end         = 235,
 771                 .hblank_start   = 2155,             .htotal             = 2199,
 772
 773                 .progressive    = false,            .trilevel_sync = true,
 774
 775                 .vsync_start_f1 = 4,               .vsync_start_f2     = 5,
 776                 .vsync_len      = 10,
 777
 778                 .veq_ena        = true,             .veq_start_f1       = 4,
 779                 .veq_start_f2   = 4,                .veq_len            = 10,
 780
 781
 782                 .vi_end_f1      = 21,               .vi_end_f2          = 22,
 783                 .nbr_end        = 539,
 784
 785                 .burst_ena      = false,
 786
 787                 .filter_table = filter_table,
 788         },
 789
 790         {
 791                 .name       = "1080p@30Hz",
 792                 .clock          = 148500,
 793                 .refresh        = 30000,
 794                 .oversample     = 2,
 795                 .component_only = true,
 796
 797                 .hsync_end      = 88,               .hblank_end         = 235,
 798                 .hblank_start   = 2155,             .htotal             = 2199,
 799
 800                 .progressive    = true,             .trilevel_sync = true,
 801
 802                 .vsync_start_f1 = 8,               .vsync_start_f2     = 8,
 803                 .vsync_len      = 10,
 804
 805                 .veq_ena        = false,        .veq_start_f1   = 0,
 806                 .veq_start_f2   = 0,                .veq_len            = 0,
 807
 808                 .vi_end_f1      = 44,               .vi_end_f2          = 44,
 809                 .nbr_end        = 1079,
 810
 811                 .burst_ena      = false,
 812
 813                 .filter_table = filter_table,
 814         },
 815
 816         {
 817                 .name       = "1080p@50Hz",
 818                 .clock          = 148500,
 819                 .refresh        = 50000,
 820                 .oversample     = 1,
 821                 .component_only = true,
 822
 823                 .hsync_end      = 88,               .hblank_end         = 235,
 824                 .hblank_start   = 2155,             .htotal             = 2639,
 825
 826                 .progressive    = true,             .trilevel_sync = true,
 827
 828                 .vsync_start_f1 = 8,               .vsync_start_f2     = 8,
 829                 .vsync_len      = 10,
 830
 831                 .veq_ena        = false,        .veq_start_f1   = 0,
 832                 .veq_start_f2   = 0,                .veq_len            = 0,
 833
 834                 .vi_end_f1      = 44,               .vi_end_f2          = 44,
 835                 .nbr_end        = 1079,
 836
 837                 .burst_ena      = false,
 838
 839                 .filter_table = filter_table,
 840         },
 841
 842         {
 843                 .name       = "1080p@60Hz",
 844                 .clock          = 148500,
 845                 .refresh        = 60000,
 846                 .oversample     = 1,
 847                 .component_only = true,
 848
 849                 .hsync_end      = 88,               .hblank_end         = 235,
 850                 .hblank_start   = 2155,             .htotal             = 2199,
 851
 852                 .progressive    = true,             .trilevel_sync = true,
 853
 854                 .vsync_start_f1 = 8,               .vsync_start_f2     = 8,
 855                 .vsync_len      = 10,
 856
 857                 .veq_ena        = false,                    .veq_start_f1       = 0,
 858                 .veq_start_f2   = 0,                .veq_len            = 0,
 859
 860                 .vi_end_f1      = 44,               .vi_end_f2          = 44,
 861                 .nbr_end        = 1079,
 862
 863                 .burst_ena      = false,
 864
 865                 .filter_table = filter_table,
 866         },
 867 };
 868
 869 struct intel_tv_connector_state {
 870         struct drm_connector_state base;
 871
 872         /*
 873          * May need to override the user margins for
 874          * gen3 >1024 wide source vertical centering.
 875          */
 876         struct {
 877                 u16 top, bottom;
 878         } margins;
 879
 880         bool bypass_vfilter;
 881 };
 882
 883 #define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base)
 884
 885 static struct drm_connector_state *
 886 intel_tv_connector_duplicate_state(struct drm_connector *connector)
 887 {
 888         struct intel_tv_connector_state *state;
 889
 890         state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
 891         if (!state)
 892                 return NULL;
 893
 894         __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
 895         return &state->base;
 896 }
 897
 898 static struct intel_tv *enc_to_tv(struct intel_encoder *encoder)
 899 {
 900         return container_of(encoder, struct intel_tv, base);
 901 }
 902
 903 static struct intel_tv *intel_attached_tv(struct intel_connector *connector)
 904 {
 905         return enc_to_tv(intel_attached_encoder(connector));
 906 }
 907
 908 static bool
 909 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
 910 {
 911         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 912         u32 tmp = intel_de_read(dev_priv, TV_CTL);
 913
 914         *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
 915
 916         return tmp & TV_ENC_ENABLE;
 917 }
 918
 919 static void
 920 intel_enable_tv(struct intel_atomic_state *state,
 921                 struct intel_encoder *encoder,
 922                 const struct intel_crtc_state *pipe_config,
 923                 const struct drm_connector_state *conn_state)
 924 {
 925         struct drm_device *dev = encoder->base.dev;
 926         struct drm_i915_private *dev_priv = to_i915(dev);
 927
 928         /* Prevents vblank waits from timing out in intel_tv_detect_type() */
 929         intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc));
 930
 931         intel_de_write(dev_priv, TV_CTL,
 932                        intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE);
 933 }
 934
 935 static void
 936 intel_disable_tv(struct intel_atomic_state *state,
 937                  struct intel_encoder *encoder,
 938                  const struct intel_crtc_state *old_crtc_state,
 939                  const struct drm_connector_state *old_conn_state)
 940 {
 941         struct drm_device *dev = encoder->base.dev;
 942         struct drm_i915_private *dev_priv = to_i915(dev);
 943
 944         intel_de_write(dev_priv, TV_CTL,
 945                        intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE);
 946 }
 947
 948 static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
 949 {
 950         int format = conn_state->tv.mode;
 951
 952         return &tv_modes[format];
 953 }
 954
 955 static enum drm_mode_status
 956 intel_tv_mode_valid(struct drm_connector *connector,
 957                     struct drm_display_mode *mode)
 958 {
 959         const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
 960         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 961
 962         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 963                 return MODE_NO_DBLESCAN;
 964
 965         if (mode->clock > max_dotclk)
 966                 return MODE_CLOCK_HIGH;
 967
 968         /* Ensure TV refresh is close to desired refresh */
 969         if (abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000) >= 1000)
 970                 return MODE_CLOCK_RANGE;
 971
 972         return MODE_OK;
 973 }
 974
 975 static int
 976 intel_tv_mode_vdisplay(const struct tv_mode *tv_mode)
 977 {
 978         if (tv_mode->progressive)
 979                 return tv_mode->nbr_end + 1;
 980         else
 981                 return 2 * (tv_mode->nbr_end + 1);
 982 }
 983
 984 static void
 985 intel_tv_mode_to_mode(struct drm_display_mode *mode,
 986                       const struct tv_mode *tv_mode,
 987                       int clock)
 988 {
 989         mode->clock = clock / (tv_mode->oversample >> !tv_mode->progressive);
 990
 991         /*
 992          * tv_mode horizontal timings:
 993          *
 994          * hsync_end
 995          *    | hblank_end
 996          *    |    | hblank_start
 997          *    |    |       | htotal
 998          *    |     _______    |
 999          *     ____/       \___
1000          * \__/                \
1001          */
1002         mode->hdisplay =
1003                 tv_mode->hblank_start - tv_mode->hblank_end;
1004         mode->hsync_start = mode->hdisplay +
1005                 tv_mode->htotal - tv_mode->hblank_start;
1006         mode->hsync_end = mode->hsync_start +
1007                 tv_mode->hsync_end;
1008         mode->htotal = tv_mode->htotal + 1;
1009
1010         /*
1011          * tv_mode vertical timings:
1012          *
1013          * vsync_start
1014          *    | vsync_end
1015          *    |  | vi_end nbr_end
1016          *    |  |    |       |
1017          *    |  |     _______
1018          * \__    ____/       \
1019          *    \__/
1020          */
1021         mode->vdisplay = intel_tv_mode_vdisplay(tv_mode);
1022         if (tv_mode->progressive) {
1023                 mode->vsync_start = mode->vdisplay +
1024                         tv_mode->vsync_start_f1 + 1;
1025                 mode->vsync_end = mode->vsync_start +
1026                         tv_mode->vsync_len;
1027                 mode->vtotal = mode->vdisplay +
1028                         tv_mode->vi_end_f1 + 1;
1029         } else {
1030                 mode->vsync_start = mode->vdisplay +
1031                         tv_mode->vsync_start_f1 + 1 +
1032                         tv_mode->vsync_start_f2 + 1;
1033                 mode->vsync_end = mode->vsync_start +
1034                         2 * tv_mode->vsync_len;
1035                 mode->vtotal = mode->vdisplay +
1036                         tv_mode->vi_end_f1 + 1 +
1037                         tv_mode->vi_end_f2 + 1;
1038         }
1039
1040         /* TV has it's own notion of sync and other mode flags, so clear them. */
1041         mode->flags = 0;
1042
1043         snprintf(mode->name, sizeof(mode->name),
1044                  "%dx%d%c (%s)",
1045                  mode->hdisplay, mode->vdisplay,
1046                  tv_mode->progressive ? 'p' : 'i',
1047                  tv_mode->name);
1048 }
1049
1050 static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode,
1051                                       int hdisplay, int left_margin,
1052                                       int right_margin)
1053 {
1054         int hsync_start = mode->hsync_start - mode->hdisplay + right_margin;
1055         int hsync_end = mode->hsync_end - mode->hdisplay + right_margin;
1056         int new_htotal = mode->htotal * hdisplay /
1057                 (mode->hdisplay - left_margin - right_margin);
1058
1059         mode->clock = mode->clock * new_htotal / mode->htotal;
1060
1061         mode->hdisplay = hdisplay;
1062         mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal;
1063         mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal;
1064         mode->htotal = new_htotal;
1065 }
1066
1067 static void intel_tv_scale_mode_vert(struct drm_display_mode *mode,
1068                                      int vdisplay, int top_margin,
1069                                      int bottom_margin)
1070 {
1071         int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin;
1072         int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin;
1073         int new_vtotal = mode->vtotal * vdisplay /
1074                 (mode->vdisplay - top_margin - bottom_margin);
1075
1076         mode->clock = mode->clock * new_vtotal / mode->vtotal;
1077
1078         mode->vdisplay = vdisplay;
1079         mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal;
1080         mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal;
1081         mode->vtotal = new_vtotal;
1082 }
1083
1084 static void
1085 intel_tv_get_config(struct intel_encoder *encoder,
1086                     struct intel_crtc_state *pipe_config)
1087 {
1088         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1089         struct drm_display_mode *adjusted_mode =
1090                 &pipe_config->hw.adjusted_mode;
1091         struct drm_display_mode mode = {};
1092         u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
1093         struct tv_mode tv_mode = {};
1094         int hdisplay = adjusted_mode->crtc_hdisplay;
1095         int vdisplay = adjusted_mode->crtc_vdisplay;
1096         int xsize, ysize, xpos, ypos;
1097
1098         pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
1099
1100         tv_ctl = intel_de_read(dev_priv, TV_CTL);
1101         hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
1102         hctl3 = intel_de_read(dev_priv, TV_H_CTL_3);
1103         vctl1 = intel_de_read(dev_priv, TV_V_CTL_1);
1104         vctl2 = intel_de_read(dev_priv, TV_V_CTL_2);
1105
1106         tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
1107         tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
1108
1109         tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT;
1110         tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT;
1111
1112         tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT;
1113         tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT;
1114         tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT;
1115
1116         tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT;
1117         tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT;
1118         tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT;
1119
1120         tv_mode.clock = pipe_config->port_clock;
1121
1122         tv_mode.progressive = tv_ctl & TV_PROGRESSIVE;
1123
1124         switch (tv_ctl & TV_OVERSAMPLE_MASK) {
1125         case TV_OVERSAMPLE_8X:
1126                 tv_mode.oversample = 8;
1127                 break;
1128         case TV_OVERSAMPLE_4X:
1129                 tv_mode.oversample = 4;
1130                 break;
1131         case TV_OVERSAMPLE_2X:
1132                 tv_mode.oversample = 2;
1133                 break;
1134         default:
1135                 tv_mode.oversample = 1;
1136                 break;
1137         }
1138
1139         tmp = intel_de_read(dev_priv, TV_WIN_POS);
1140         xpos = tmp >> 16;
1141         ypos = tmp & 0xffff;
1142
1143         tmp = intel_de_read(dev_priv, TV_WIN_SIZE);
1144         xsize = tmp >> 16;
1145         ysize = tmp & 0xffff;
1146
1147         intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock);
1148
1149         drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1150                     DRM_MODE_ARG(&mode));
1151
1152         intel_tv_scale_mode_horiz(&mode, hdisplay,
1153                                   xpos, mode.hdisplay - xsize - xpos);
1154         intel_tv_scale_mode_vert(&mode, vdisplay,
1155                                  ypos, mode.vdisplay - ysize - ypos);
1156
1157         adjusted_mode->crtc_clock = mode.clock;
1158         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1159                 adjusted_mode->crtc_clock /= 2;
1160
1161         /* pixel counter doesn't work on i965gm TV output */
1162         if (IS_I965GM(dev_priv))
1163                 pipe_config->mode_flags |=
1164                         I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1165 }
1166
1167 static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
1168                                      int hdisplay)
1169 {
1170         return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024;
1171 }
1172
1173 static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
1174                                   const struct drm_connector_state *conn_state,
1175                                   int vdisplay)
1176 {
1177         return tv_mode->crtc_vdisplay -
1178                 conn_state->tv.margins.top -
1179                 conn_state->tv.margins.bottom !=
1180                 vdisplay;
1181 }
1182
1183 static int
1184 intel_tv_compute_config(struct intel_encoder *encoder,
1185                         struct intel_crtc_state *pipe_config,
1186                         struct drm_connector_state *conn_state)
1187 {
1188         struct intel_atomic_state *state =
1189                 to_intel_atomic_state(pipe_config->uapi.state);
1190         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1191         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1192         struct intel_tv_connector_state *tv_conn_state =
1193                 to_intel_tv_connector_state(conn_state);
1194         const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
1195         struct drm_display_mode *adjusted_mode =
1196                 &pipe_config->hw.adjusted_mode;
1197         int hdisplay = adjusted_mode->crtc_hdisplay;
1198         int vdisplay = adjusted_mode->crtc_vdisplay;
1199         int ret;
1200
1201         if (!tv_mode)
1202                 return -EINVAL;
1203
1204         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1205                 return -EINVAL;
1206
1207         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1208
1209         drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n");
1210         pipe_config->pipe_bpp = 8*3;
1211
1212         pipe_config->port_clock = tv_mode->clock;
1213
1214         ret = intel_dpll_crtc_compute_clock(state, crtc);
1215         if (ret)
1216                 return ret;
1217
1218         pipe_config->clock_set = true;
1219
1220         intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock);
1221         drm_mode_set_crtcinfo(adjusted_mode, 0);
1222
1223         if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
1224             !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
1225                 int extra, top, bottom;
1226
1227                 extra = adjusted_mode->crtc_vdisplay - vdisplay;
1228
1229                 if (extra < 0) {
1230                         drm_dbg_kms(&dev_priv->drm,
1231                                     "No vertical scaling for >1024 pixel wide modes\n");
1232                         return -EINVAL;
1233                 }
1234
1235                 /* Need to turn off the vertical filter and center the image */
1236
1237                 /* Attempt to maintain the relative sizes of the margins */
1238                 top = conn_state->tv.margins.top;
1239                 bottom = conn_state->tv.margins.bottom;
1240
1241                 if (top + bottom)
1242                         top = extra * top / (top + bottom);
1243                 else
1244                         top = extra / 2;
1245                 bottom = extra - top;
1246
1247                 tv_conn_state->margins.top = top;
1248                 tv_conn_state->margins.bottom = bottom;
1249
1250                 tv_conn_state->bypass_vfilter = true;
1251
1252                 if (!tv_mode->progressive) {
1253                         adjusted_mode->clock /= 2;
1254                         adjusted_mode->crtc_clock /= 2;
1255                         adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
1256                 }
1257         } else {
1258                 tv_conn_state->margins.top = conn_state->tv.margins.top;
1259                 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom;
1260
1261                 tv_conn_state->bypass_vfilter = false;
1262         }
1263
1264         drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1265                     DRM_MODE_ARG(adjusted_mode));
1266
1267         /*
1268          * The pipe scanline counter behaviour looks as follows when
1269          * using the TV encoder:
1270          *
1271          * time ->
1272          *
1273          * dsl=vtotal-1       |             |
1274          *                   ||            ||
1275          *               ___| |        ___| |
1276          *              /     |       /     |
1277          *             /      |      /      |
1278          * dsl=0   ___/       |_____/       |
1279          *        | | |  |  | |
1280          *         ^ ^ ^   ^ ^
1281          *         | | |   | pipe vblank/first part of tv vblank
1282          *         | | |   bottom margin
1283          *         | | active
1284          *         | top margin
1285          *         remainder of tv vblank
1286          *
1287          * When the TV encoder is used the pipe wants to run faster
1288          * than expected rate. During the active portion the TV
1289          * encoder stalls the pipe every few lines to keep it in
1290          * check. When the TV encoder reaches the bottom margin the
1291          * pipe simply stops. Once we reach the TV vblank the pipe is
1292          * no longer stalled and it runs at the max rate (apparently
1293          * oversample clock on gen3, cdclk on gen4). Once the pipe
1294          * reaches the pipe vtotal the pipe stops for the remainder
1295          * of the TV vblank/top margin. The pipe starts up again when
1296          * the TV encoder exits the top margin.
1297          *
1298          * To avoid huge hassles for vblank timestamping we scale
1299          * the pipe timings as if the pipe always runs at the average
1300          * rate it maintains during the active period. This also
1301          * gives us a reasonable guesstimate as to the pixel rate.
1302          * Due to the variation in the actual pipe speed the scanline
1303          * counter will give us slightly erroneous results during the
1304          * TV vblank/margins. But since vtotal was selected such that
1305          * it matches the average rate of the pipe during the active
1306          * portion the error shouldn't cause any serious grief to
1307          * vblank timestamps.
1308          *
1309          * For posterity here is the empirically derived formula
1310          * that gives us the maximum length of the pipe vblank
1311          * we can use without causing display corruption. Following
1312          * this would allow us to have a ticking scanline counter
1313          * everywhere except during the bottom margin (there the
1314          * pipe always stops). Ie. this would eliminate the second
1315          * flat portion of the above graph. However this would also
1316          * complicate vblank timestamping as the pipe vtotal would
1317          * no longer match the average rate the pipe runs at during
1318          * the active portion. Hence following this formula seems
1319          * more trouble that it's worth.
1320          *
1321          * if (GRAPHICS_VER(dev_priv) == 4) {
1322          *      num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
1323          *      den = tv_mode->clock;
1324          * } else {
1325          *      num = tv_mode->oversample >> !tv_mode->progressive;
1326          *      den = 1;
1327          * }
1328          * max_pipe_vblank_len ~=
1329          *      (num * tv_htotal * (tv_vblank_len + top_margin)) /
1330          *      (den * pipe_htotal);
1331          */
1332         intel_tv_scale_mode_horiz(adjusted_mode, hdisplay,
1333                                   conn_state->tv.margins.left,
1334                                   conn_state->tv.margins.right);
1335         intel_tv_scale_mode_vert(adjusted_mode, vdisplay,
1336                                  tv_conn_state->margins.top,
1337                                  tv_conn_state->margins.bottom);
1338         drm_mode_set_crtcinfo(adjusted_mode, 0);
1339         adjusted_mode->name[0] = '\0';
1340
1341         /* pixel counter doesn't work on i965gm TV output */
1342         if (IS_I965GM(dev_priv))
1343                 pipe_config->mode_flags |=
1344                         I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1345
1346         return 0;
1347 }
1348
1349 static void
1350 set_tv_mode_timings(struct drm_i915_private *dev_priv,
1351                     const struct tv_mode *tv_mode,
1352                     bool burst_ena)
1353 {
1354         u32 hctl1, hctl2, hctl3;
1355         u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
1356
1357         hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
1358                 (tv_mode->htotal << TV_HTOTAL_SHIFT);
1359
1360         hctl2 = (tv_mode->hburst_start << 16) |
1361                 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
1362
1363         if (burst_ena)
1364                 hctl2 |= TV_BURST_ENA;
1365
1366         hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
1367                 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
1368
1369         vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
1370                 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
1371                 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
1372
1373         vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
1374                 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
1375                 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
1376
1377         vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
1378                 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
1379                 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1380
1381         if (tv_mode->veq_ena)
1382                 vctl3 |= TV_EQUAL_ENA;
1383
1384         vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1385                 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1386
1387         vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1388                 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1389
1390         vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1391                 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1392
1393         vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1394                 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1395
1396         intel_de_write(dev_priv, TV_H_CTL_1, hctl1);
1397         intel_de_write(dev_priv, TV_H_CTL_2, hctl2);
1398         intel_de_write(dev_priv, TV_H_CTL_3, hctl3);
1399         intel_de_write(dev_priv, TV_V_CTL_1, vctl1);
1400         intel_de_write(dev_priv, TV_V_CTL_2, vctl2);
1401         intel_de_write(dev_priv, TV_V_CTL_3, vctl3);
1402         intel_de_write(dev_priv, TV_V_CTL_4, vctl4);
1403         intel_de_write(dev_priv, TV_V_CTL_5, vctl5);
1404         intel_de_write(dev_priv, TV_V_CTL_6, vctl6);
1405         intel_de_write(dev_priv, TV_V_CTL_7, vctl7);
1406 }
1407
1408 static void set_color_conversion(struct drm_i915_private *dev_priv,
1409                                  const struct color_conversion *color_conversion)
1410 {
1411         if (!color_conversion)
1412                 return;
1413
1414         intel_de_write(dev_priv, TV_CSC_Y,
1415                        (color_conversion->ry << 16) | color_conversion->gy);
1416         intel_de_write(dev_priv, TV_CSC_Y2,
1417                        (color_conversion->by << 16) | color_conversion->ay);
1418         intel_de_write(dev_priv, TV_CSC_U,
1419                        (color_conversion->ru << 16) | color_conversion->gu);
1420         intel_de_write(dev_priv, TV_CSC_U2,
1421                        (color_conversion->bu << 16) | color_conversion->au);
1422         intel_de_write(dev_priv, TV_CSC_V,
1423                        (color_conversion->rv << 16) | color_conversion->gv);
1424         intel_de_write(dev_priv, TV_CSC_V2,
1425                        (color_conversion->bv << 16) | color_conversion->av);
1426 }
1427
1428 static void intel_tv_pre_enable(struct intel_atomic_state *state,
1429                                 struct intel_encoder *encoder,
1430                                 const struct intel_crtc_state *pipe_config,
1431                                 const struct drm_connector_state *conn_state)
1432 {
1433         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1434         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1435         struct intel_tv *intel_tv = enc_to_tv(encoder);
1436         const struct intel_tv_connector_state *tv_conn_state =
1437                 to_intel_tv_connector_state(conn_state);
1438         const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
1439         u32 tv_ctl, tv_filter_ctl;
1440         u32 scctl1, scctl2, scctl3;
1441         int i, j;
1442         const struct video_levels *video_levels;
1443         const struct color_conversion *color_conversion;
1444         bool burst_ena;
1445         int xpos, ypos;
1446         unsigned int xsize, ysize;
1447
1448         if (!tv_mode)
1449                 return; /* can't happen (mode_prepare prevents this) */
1450
1451         tv_ctl = intel_de_read(dev_priv, TV_CTL);
1452         tv_ctl &= TV_CTL_SAVE;
1453
1454         switch (intel_tv->type) {
1455         default:
1456         case DRM_MODE_CONNECTOR_Unknown:
1457         case DRM_MODE_CONNECTOR_Composite:
1458                 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
1459                 video_levels = tv_mode->composite_levels;
1460                 color_conversion = tv_mode->composite_color;
1461                 burst_ena = tv_mode->burst_ena;
1462                 break;
1463         case DRM_MODE_CONNECTOR_Component:
1464                 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
1465                 video_levels = &component_levels;
1466                 if (tv_mode->burst_ena)
1467                         color_conversion = &sdtv_csc_yprpb;
1468                 else
1469                         color_conversion = &hdtv_csc_yprpb;
1470                 burst_ena = false;
1471                 break;
1472         case DRM_MODE_CONNECTOR_SVIDEO:
1473                 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
1474                 video_levels = tv_mode->svideo_levels;
1475                 color_conversion = tv_mode->svideo_color;
1476                 burst_ena = tv_mode->burst_ena;
1477                 break;
1478         }
1479
1480         tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);
1481
1482         switch (tv_mode->oversample) {
1483         case 8:
1484                 tv_ctl |= TV_OVERSAMPLE_8X;
1485                 break;
1486         case 4:
1487                 tv_ctl |= TV_OVERSAMPLE_4X;
1488                 break;
1489         case 2:
1490                 tv_ctl |= TV_OVERSAMPLE_2X;
1491                 break;
1492         default:
1493                 tv_ctl |= TV_OVERSAMPLE_NONE;
1494                 break;
1495         }
1496
1497         if (tv_mode->progressive)
1498                 tv_ctl |= TV_PROGRESSIVE;
1499         if (tv_mode->trilevel_sync)
1500                 tv_ctl |= TV_TRILEVEL_SYNC;
1501         if (tv_mode->pal_burst)
1502                 tv_ctl |= TV_PAL_BURST;
1503
1504         scctl1 = 0;
1505         if (tv_mode->dda1_inc)
1506                 scctl1 |= TV_SC_DDA1_EN;
1507         if (tv_mode->dda2_inc)
1508                 scctl1 |= TV_SC_DDA2_EN;
1509         if (tv_mode->dda3_inc)
1510                 scctl1 |= TV_SC_DDA3_EN;
1511         scctl1 |= tv_mode->sc_reset;
1512         if (video_levels)
1513                 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
1514         scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1515
1516         scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1517                 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1518
1519         scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1520                 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1521
1522         /* Enable two fixes for the chips that need them. */
1523         if (IS_I915GM(dev_priv))
1524                 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1525
1526         set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
1527
1528         intel_de_write(dev_priv, TV_SC_CTL_1, scctl1);
1529         intel_de_write(dev_priv, TV_SC_CTL_2, scctl2);
1530         intel_de_write(dev_priv, TV_SC_CTL_3, scctl3);
1531
1532         set_color_conversion(dev_priv, color_conversion);
1533
1534         if (DISPLAY_VER(dev_priv) >= 4)
1535                 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000);
1536         else
1537                 intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000);
1538
1539         if (video_levels)
1540                 intel_de_write(dev_priv, TV_CLR_LEVEL,
1541                                ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1542
1543         assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);
1544
1545         /* Filter ctl must be set before TV_WIN_SIZE */
1546         tv_filter_ctl = TV_AUTO_SCALE;
1547         if (tv_conn_state->bypass_vfilter)
1548                 tv_filter_ctl |= TV_V_FILTER_BYPASS;
1549         intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl);
1550
1551         xsize = tv_mode->hblank_start - tv_mode->hblank_end;
1552         ysize = intel_tv_mode_vdisplay(tv_mode);
1553
1554         xpos = conn_state->tv.margins.left;
1555         ypos = tv_conn_state->margins.top;
1556         xsize -= (conn_state->tv.margins.left +
1557                   conn_state->tv.margins.right);
1558         ysize -= (tv_conn_state->margins.top +
1559                   tv_conn_state->margins.bottom);
1560         intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos);
1561         intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize);
1562
1563         j = 0;
1564         for (i = 0; i < 60; i++)
1565                 intel_de_write(dev_priv, TV_H_LUMA(i),
1566                                tv_mode->filter_table[j++]);
1567         for (i = 0; i < 60; i++)
1568                 intel_de_write(dev_priv, TV_H_CHROMA(i),
1569                                tv_mode->filter_table[j++]);
1570         for (i = 0; i < 43; i++)
1571                 intel_de_write(dev_priv, TV_V_LUMA(i),
1572                                tv_mode->filter_table[j++]);
1573         for (i = 0; i < 43; i++)
1574                 intel_de_write(dev_priv, TV_V_CHROMA(i),
1575                                tv_mode->filter_table[j++]);
1576         intel_de_write(dev_priv, TV_DAC,
1577                        intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE);
1578         intel_de_write(dev_priv, TV_CTL, tv_ctl);
1579 }
1580
1581 static int
1582 intel_tv_detect_type(struct intel_tv *intel_tv,
1583                       struct drm_connector *connector)
1584 {
1585         struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc);
1586         struct drm_device *dev = connector->dev;
1587         struct drm_i915_private *dev_priv = to_i915(dev);
1588         u32 tv_ctl, save_tv_ctl;
1589         u32 tv_dac, save_tv_dac;
1590         int type;
1591
1592         /* Disable TV interrupts around load detect or we'll recurse */
1593         if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1594                 spin_lock_irq(&dev_priv->irq_lock);
1595                 i915_disable_pipestat(dev_priv, 0,
1596                                       PIPE_HOTPLUG_INTERRUPT_STATUS |
1597                                       PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
1598                 spin_unlock_irq(&dev_priv->irq_lock);
1599         }
1600
1601         save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC);
1602         save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL);
1603
1604         /* Poll for TV detection */
1605         tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
1606         tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
1607         tv_ctl |= TV_ENC_PIPE_SEL(crtc->pipe);
1608
1609         tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
1610         tv_dac |= (TVDAC_STATE_CHG_EN |
1611                    TVDAC_A_SENSE_CTL |
1612                    TVDAC_B_SENSE_CTL |
1613                    TVDAC_C_SENSE_CTL |
1614                    DAC_CTL_OVERRIDE |
1615                    DAC_A_0_7_V |
1616                    DAC_B_0_7_V |
1617                    DAC_C_0_7_V);
1618
1619
1620         /*
1621          * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1622          * the TV is misdetected. This is hardware requirement.
1623          */
1624         if (IS_GM45(dev_priv))
1625                 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1626                             TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1627
1628         intel_de_write(dev_priv, TV_CTL, tv_ctl);
1629         intel_de_write(dev_priv, TV_DAC, tv_dac);
1630         intel_de_posting_read(dev_priv, TV_DAC);
1631
1632         intel_crtc_wait_for_next_vblank(crtc);
1633
1634         type = -1;
1635         tv_dac = intel_de_read(dev_priv, TV_DAC);
1636         drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac);
1637         /*
1638          *  A B C
1639          *  0 1 1 Composite
1640          *  1 0 X svideo
1641          *  0 0 0 Component
1642          */
1643         if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1644                 drm_dbg_kms(&dev_priv->drm,
1645                             "Detected Composite TV connection\n");
1646                 type = DRM_MODE_CONNECTOR_Composite;
1647         } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1648                 drm_dbg_kms(&dev_priv->drm,
1649                             "Detected S-Video TV connection\n");
1650                 type = DRM_MODE_CONNECTOR_SVIDEO;
1651         } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1652                 drm_dbg_kms(&dev_priv->drm,
1653                             "Detected Component TV connection\n");
1654                 type = DRM_MODE_CONNECTOR_Component;
1655         } else {
1656                 drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n");
1657                 type = -1;
1658         }
1659
1660         intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1661         intel_de_write(dev_priv, TV_CTL, save_tv_ctl);
1662         intel_de_posting_read(dev_priv, TV_CTL);
1663
1664         /* For unknown reasons the hw barfs if we don't do this vblank wait. */
1665         intel_crtc_wait_for_next_vblank(crtc);
1666
1667         /* Restore interrupt config */
1668         if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1669                 spin_lock_irq(&dev_priv->irq_lock);
1670                 i915_enable_pipestat(dev_priv, 0,
1671                                      PIPE_HOTPLUG_INTERRUPT_STATUS |
1672                                      PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
1673                 spin_unlock_irq(&dev_priv->irq_lock);
1674         }
1675
1676         return type;
1677 }
1678
1679 /*
1680  * Here we set accurate tv format according to connector type
1681  * i.e Component TV should not be assigned by NTSC or PAL
1682  */
1683 static void intel_tv_find_better_format(struct drm_connector *connector)
1684 {
1685         struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
1686         const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
1687         int i;
1688
1689         /* Component supports everything so we can keep the current mode */
1690         if (intel_tv->type == DRM_MODE_CONNECTOR_Component)
1691                 return;
1692
1693         /* If the current mode is fine don't change it */
1694         if (!tv_mode->component_only)
1695                 return;
1696
1697         for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1698                 tv_mode = &tv_modes[i];
1699
1700                 if (!tv_mode->component_only)
1701                         break;
1702         }
1703
1704         connector->state->tv.mode = i;
1705 }
1706
1707 static int
1708 intel_tv_detect(struct drm_connector *connector,
1709                 struct drm_modeset_acquire_ctx *ctx,
1710                 bool force)
1711 {
1712         struct drm_i915_private *i915 = to_i915(connector->dev);
1713         struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector));
1714         enum drm_connector_status status;
1715         int type;
1716
1717         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n",
1718                     connector->base.id, connector->name, force);
1719
1720         if (!INTEL_DISPLAY_ENABLED(i915))
1721                 return connector_status_disconnected;
1722
1723         if (force) {
1724                 struct intel_load_detect_pipe tmp;
1725                 int ret;
1726
1727                 ret = intel_get_load_detect_pipe(connector, &tmp, ctx);
1728                 if (ret < 0)
1729                         return ret;
1730
1731                 if (ret > 0) {
1732                         type = intel_tv_detect_type(intel_tv, connector);
1733                         intel_release_load_detect_pipe(connector, &tmp, ctx);
1734                         status = type < 0 ?
1735                                 connector_status_disconnected :
1736                                 connector_status_connected;
1737                 } else
1738                         status = connector_status_unknown;
1739
1740                 if (status == connector_status_connected) {
1741                         intel_tv->type = type;
1742                         intel_tv_find_better_format(connector);
1743                 }
1744
1745                 return status;
1746         } else
1747                 return connector->status;
1748 }
1749
1750 static const struct input_res {
1751         u16 w, h;
1752 } input_res_table[] = {
1753         { 640, 480 },
1754         { 800, 600 },
1755         { 1024, 768 },
1756         { 1280, 1024 },
1757         { 848, 480 },
1758         { 1280, 720 },
1759         { 1920, 1080 },
1760 };
1761
1762 /* Choose preferred mode according to line number of TV format */
1763 static bool
1764 intel_tv_is_preferred_mode(const struct drm_display_mode *mode,
1765                            const struct tv_mode *tv_mode)
1766 {
1767         int vdisplay = intel_tv_mode_vdisplay(tv_mode);
1768
1769         /* prefer 480 line modes for all SD TV modes */
1770         if (vdisplay <= 576)
1771                 vdisplay = 480;
1772
1773         return vdisplay == mode->vdisplay;
1774 }
1775
1776 static void
1777 intel_tv_set_mode_type(struct drm_display_mode *mode,
1778                        const struct tv_mode *tv_mode)
1779 {
1780         mode->type = DRM_MODE_TYPE_DRIVER;
1781
1782         if (intel_tv_is_preferred_mode(mode, tv_mode))
1783                 mode->type |= DRM_MODE_TYPE_PREFERRED;
1784 }
1785
1786 static int
1787 intel_tv_get_modes(struct drm_connector *connector)
1788 {
1789         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1790         const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
1791         int i, count = 0;
1792
1793         for (i = 0; i < ARRAY_SIZE(input_res_table); i++) {
1794                 const struct input_res *input = &input_res_table[i];
1795                 struct drm_display_mode *mode;
1796
1797                 if (input->w > 1024 &&
1798                     !tv_mode->progressive &&
1799                     !tv_mode->component_only)
1800                         continue;
1801
1802                 /* no vertical scaling with wide sources on gen3 */
1803                 if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 &&
1804                     input->h > intel_tv_mode_vdisplay(tv_mode))
1805                         continue;
1806
1807                 mode = drm_mode_create(connector->dev);
1808                 if (!mode)
1809                         continue;
1810
1811                 /*
1812                  * We take the TV mode and scale it to look
1813                  * like it had the expected h/vdisplay. This
1814                  * provides the most information to userspace
1815                  * about the actual timings of the mode. We
1816                  * do ignore the margins though.
1817                  */
1818                 intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock);
1819                 if (count == 0) {
1820                         drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n",
1821                                     DRM_MODE_ARG(mode));
1822                 }
1823                 intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
1824                 intel_tv_scale_mode_vert(mode, input->h, 0, 0);
1825                 intel_tv_set_mode_type(mode, tv_mode);
1826
1827                 drm_mode_set_name(mode);
1828
1829                 drm_mode_probed_add(connector, mode);
1830                 count++;
1831         }
1832
1833         return count;
1834 }
1835
1836 static const struct drm_connector_funcs intel_tv_connector_funcs = {
1837         .late_register = intel_connector_register,
1838         .early_unregister = intel_connector_unregister,
1839         .destroy = intel_connector_destroy,
1840         .fill_modes = drm_helper_probe_single_connector_modes,
1841         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1842         .atomic_duplicate_state = intel_tv_connector_duplicate_state,
1843 };
1844
1845 static int intel_tv_atomic_check(struct drm_connector *connector,
1846                                  struct drm_atomic_state *state)
1847 {
1848         struct drm_connector_state *new_state;
1849         struct drm_crtc_state *new_crtc_state;
1850         struct drm_connector_state *old_state;
1851
1852         new_state = drm_atomic_get_new_connector_state(state, connector);
1853         if (!new_state->crtc)
1854                 return 0;
1855
1856         old_state = drm_atomic_get_old_connector_state(state, connector);
1857         new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
1858
1859         if (old_state->tv.mode != new_state->tv.mode ||
1860             old_state->tv.margins.left != new_state->tv.margins.left ||
1861             old_state->tv.margins.right != new_state->tv.margins.right ||
1862             old_state->tv.margins.top != new_state->tv.margins.top ||
1863             old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
1864                 /* Force a modeset. */
1865
1866                 new_crtc_state->connectors_changed = true;
1867         }
1868
1869         return 0;
1870 }
1871
1872 static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
1873         .detect_ctx = intel_tv_detect,
1874         .mode_valid = intel_tv_mode_valid,
1875         .get_modes = intel_tv_get_modes,
1876         .atomic_check = intel_tv_atomic_check,
1877 };
1878
1879 static const struct drm_encoder_funcs intel_tv_enc_funcs = {
1880         .destroy = intel_encoder_destroy,
1881 };
1882
1883 void
1884 intel_tv_init(struct drm_i915_private *dev_priv)
1885 {
1886         struct drm_device *dev = &dev_priv->drm;
1887         struct drm_connector *connector;
1888         struct intel_tv *intel_tv;
1889         struct intel_encoder *intel_encoder;
1890         struct intel_connector *intel_connector;
1891         u32 tv_dac_on, tv_dac_off, save_tv_dac;
1892         const char *tv_format_names[ARRAY_SIZE(tv_modes)];
1893         int i, initial_mode = 0;
1894         struct drm_connector_state *state;
1895
1896         if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1897                 return;
1898
1899         if (!intel_bios_is_tv_present(dev_priv)) {
1900                 drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n");
1901                 return;
1902         }
1903
1904         /*
1905          * Sanity check the TV output by checking to see if the
1906          * DAC register holds a value
1907          */
1908         save_tv_dac = intel_de_read(dev_priv, TV_DAC);
1909
1910         intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1911         tv_dac_on = intel_de_read(dev_priv, TV_DAC);
1912
1913         intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1914         tv_dac_off = intel_de_read(dev_priv, TV_DAC);
1915
1916         intel_de_write(dev_priv, TV_DAC, save_tv_dac);
1917
1918         /*
1919          * If the register does not hold the state change enable
1920          * bit, (either as a 0 or a 1), assume it doesn't really
1921          * exist
1922          */
1923         if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1924             (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1925                 return;
1926
1927         intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
1928         if (!intel_tv) {
1929                 return;
1930         }
1931
1932         intel_connector = intel_connector_alloc();
1933         if (!intel_connector) {
1934                 kfree(intel_tv);
1935                 return;
1936         }
1937
1938         intel_encoder = &intel_tv->base;
1939         connector = &intel_connector->base;
1940         state = connector->state;
1941
1942         /*
1943          * The documentation, for the older chipsets at least, recommend
1944          * using a polling method rather than hotplug detection for TVs.
1945          * This is because in order to perform the hotplug detection, the PLLs
1946          * for the TV must be kept alive increasing power drain and starving
1947          * bandwidth from other encoders. Notably for instance, it causes
1948          * pipe underruns on Crestline when this encoder is supposedly idle.
1949          *
1950          * More recent chipsets favour HDMI rather than integrated S-Video.
1951          */
1952         intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1953
1954         drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1955                            DRM_MODE_CONNECTOR_SVIDEO);
1956
1957         drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
1958                          DRM_MODE_ENCODER_TVDAC, "TV");
1959
1960         intel_encoder->compute_config = intel_tv_compute_config;
1961         intel_encoder->get_config = intel_tv_get_config;
1962         intel_encoder->pre_enable = intel_tv_pre_enable;
1963         intel_encoder->enable = intel_enable_tv;
1964         intel_encoder->disable = intel_disable_tv;
1965         intel_encoder->get_hw_state = intel_tv_get_hw_state;
1966         intel_connector->get_hw_state = intel_connector_get_hw_state;
1967
1968         intel_connector_attach_encoder(intel_connector, intel_encoder);
1969
1970         intel_encoder->type = INTEL_OUTPUT_TVOUT;
1971         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1972         intel_encoder->port = PORT_NONE;
1973         intel_encoder->pipe_mask = ~0;
1974         intel_encoder->cloneable = 0;
1975         intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
1976
1977         /* BIOS margin values */
1978         state->tv.margins.left = 54;
1979         state->tv.margins.top = 36;
1980         state->tv.margins.right = 46;
1981         state->tv.margins.bottom = 37;
1982
1983         state->tv.mode = initial_mode;
1984
1985         drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1986         connector->interlace_allowed = false;
1987         connector->doublescan_allowed = false;
1988
1989         /* Create TV properties then attach current values */
1990         for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1991                 /* 1080p50/1080p60 not supported on gen3 */
1992                 if (DISPLAY_VER(dev_priv) == 3 &&
1993                     tv_modes[i].oversample == 1)
1994                         break;
1995
1996                 tv_format_names[i] = tv_modes[i].name;
1997         }
1998         drm_mode_create_tv_properties(dev, i, tv_format_names);
1999
2000         drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property,
2001                                    state->tv.mode);
2002         drm_object_attach_property(&connector->base,
2003                                    dev->mode_config.tv_left_margin_property,
2004                                    state->tv.margins.left);
2005         drm_object_attach_property(&connector->base,
2006                                    dev->mode_config.tv_top_margin_property,
2007                                    state->tv.margins.top);
2008         drm_object_attach_property(&connector->base,
2009                                    dev->mode_config.tv_right_margin_property,
2010                                    state->tv.margins.right);
2011         drm_object_attach_property(&connector->base,
2012                                    dev->mode_config.tv_bottom_margin_property,
2013                                    state->tv.margins.bottom);
2014 }