drivers/gpu/drm/i915/display/intel_tc.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "i915_reg.h"
   8 #include "intel_display.h"
   9 #include "intel_display_power_map.h"
  10 #include "intel_display_types.h"
  11 #include "intel_dp_mst.h"
  12 #include "intel_tc.h"
  13 #include "intel_tc_phy_regs.h"
  14
  15 static const char *tc_port_mode_name(enum tc_port_mode mode)
  16 {
  17         static const char * const names[] = {
  18                 [TC_PORT_DISCONNECTED] = "disconnected",
  19                 [TC_PORT_TBT_ALT] = "tbt-alt",
  20                 [TC_PORT_DP_ALT] = "dp-alt",
  21                 [TC_PORT_LEGACY] = "legacy",
  22         };
  23
  24         if (WARN_ON(mode >= ARRAY_SIZE(names)))
  25                 mode = TC_PORT_DISCONNECTED;
  26
  27         return names[mode];
  28 }
  29
  30 static bool intel_tc_port_in_mode(struct intel_digital_port *dig_port,
  31                                   enum tc_port_mode mode)
  32 {
  33         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  34         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
  35
  36         return intel_phy_is_tc(i915, phy) && dig_port->tc_mode == mode;
  37 }
  38
  39 bool intel_tc_port_in_tbt_alt_mode(struct intel_digital_port *dig_port)
  40 {
  41         return intel_tc_port_in_mode(dig_port, TC_PORT_TBT_ALT);
  42 }
  43
  44 bool intel_tc_port_in_dp_alt_mode(struct intel_digital_port *dig_port)
  45 {
  46         return intel_tc_port_in_mode(dig_port, TC_PORT_DP_ALT);
  47 }
  48
  49 bool intel_tc_port_in_legacy_mode(struct intel_digital_port *dig_port)
  50 {
  51         return intel_tc_port_in_mode(dig_port, TC_PORT_LEGACY);
  52 }
  53
  54 bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
  55 {
  56         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  57
  58         return (DISPLAY_VER(i915) == 11 && dig_port->tc_legacy_port) ||
  59                 IS_ALDERLAKE_P(i915);
  60 }
  61
  62 static enum intel_display_power_domain
  63 tc_cold_get_power_domain(struct intel_digital_port *dig_port, enum tc_port_mode mode)
  64 {
  65         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  66
  67         if (mode == TC_PORT_TBT_ALT || !intel_tc_cold_requires_aux_pw(dig_port))
  68                 return POWER_DOMAIN_TC_COLD_OFF;
  69
  70         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
  71 }
  72
  73 static intel_wakeref_t
  74 tc_cold_block_in_mode(struct intel_digital_port *dig_port, enum tc_port_mode mode,
  75                       enum intel_display_power_domain *domain)
  76 {
  77         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  78
  79         *domain = tc_cold_get_power_domain(dig_port, mode);
  80
  81         return intel_display_power_get(i915, *domain);
  82 }
  83
  84 static intel_wakeref_t
  85 tc_cold_block(struct intel_digital_port *dig_port, enum intel_display_power_domain *domain)
  86 {
  87         return tc_cold_block_in_mode(dig_port, dig_port->tc_mode, domain);
  88 }
  89
  90 static void
  91 tc_cold_unblock(struct intel_digital_port *dig_port, enum intel_display_power_domain domain,
  92                 intel_wakeref_t wakeref)
  93 {
  94         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  95
  96         /*
  97          * wakeref == -1, means some error happened saving save_depot_stack but
  98          * power should still be put down and 0 is a invalid save_depot_stack
  99          * id so can be used to skip it for non TC legacy ports.
 100          */
 101         if (wakeref == 0)
 102                 return;
 103
 104         intel_display_power_put(i915, domain, wakeref);
 105 }
 106
 107 static void
 108 assert_tc_cold_blocked(struct intel_digital_port *dig_port)
 109 {
 110         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 111         bool enabled;
 112
 113         enabled = intel_display_power_is_enabled(i915,
 114                                                  tc_cold_get_power_domain(dig_port,
 115                                                                           dig_port->tc_mode));
 116         drm_WARN_ON(&i915->drm, !enabled);
 117 }
 118
 119 u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
 120 {
 121         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 122         struct intel_uncore *uncore = &i915->uncore;
 123         u32 lane_mask;
 124
 125         lane_mask = intel_uncore_read(uncore,
 126                                       PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
 127
 128         drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
 129         assert_tc_cold_blocked(dig_port);
 130
 131         lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
 132         return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
 133 }
 134
 135 u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
 136 {
 137         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 138         struct intel_uncore *uncore = &i915->uncore;
 139         u32 pin_mask;
 140
 141         pin_mask = intel_uncore_read(uncore,
 142                                      PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
 143
 144         drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
 145         assert_tc_cold_blocked(dig_port);
 146
 147         return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
 148                DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
 149 }
 150
 151 int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 152 {
 153         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 154         intel_wakeref_t wakeref;
 155         u32 lane_mask;
 156
 157         if (dig_port->tc_mode != TC_PORT_DP_ALT)
 158                 return 4;
 159
 160         assert_tc_cold_blocked(dig_port);
 161
 162         lane_mask = 0;
 163         with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
 164                 lane_mask = intel_tc_port_get_lane_mask(dig_port);
 165
 166         switch (lane_mask) {
 167         default:
 168                 MISSING_CASE(lane_mask);
 169                 fallthrough;
 170         case 0x1:
 171         case 0x2:
 172         case 0x4:
 173         case 0x8:
 174                 return 1;
 175         case 0x3:
 176         case 0xc:
 177                 return 2;
 178         case 0xf:
 179                 return 4;
 180         }
 181 }
 182
 183 void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 184                                       int required_lanes)
 185 {
 186         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 187         bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
 188         struct intel_uncore *uncore = &i915->uncore;
 189         u32 val;
 190
 191         drm_WARN_ON(&i915->drm,
 192                     lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
 193
 194         assert_tc_cold_blocked(dig_port);
 195
 196         val = intel_uncore_read(uncore,
 197                                 PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
 198         val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
 199
 200         switch (required_lanes) {
 201         case 1:
 202                 val |= lane_reversal ?
 203                         DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) :
 204                         DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx);
 205                 break;
 206         case 2:
 207                 val |= lane_reversal ?
 208                         DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) :
 209                         DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx);
 210                 break;
 211         case 4:
 212                 val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx);
 213                 break;
 214         default:
 215                 MISSING_CASE(required_lanes);
 216         }
 217
 218         intel_uncore_write(uncore,
 219                            PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
 220 }
 221
 222 static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
 223                                       u32 live_status_mask)
 224 {
 225         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 226         u32 valid_hpd_mask;
 227
 228         if (dig_port->tc_legacy_port)
 229                 valid_hpd_mask = BIT(TC_PORT_LEGACY);
 230         else
 231                 valid_hpd_mask = BIT(TC_PORT_DP_ALT) |
 232                                  BIT(TC_PORT_TBT_ALT);
 233
 234         if (!(live_status_mask & ~valid_hpd_mask))
 235                 return;
 236
 237         /* If live status mismatches the VBT flag, trust the live status. */
 238         drm_dbg_kms(&i915->drm,
 239                     "Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag\n",
 240                     dig_port->tc_port_name, live_status_mask, valid_hpd_mask);
 241
 242         dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
 243 }
 244
 245 static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
 246 {
 247         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 248         struct intel_uncore *uncore = &i915->uncore;
 249         u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
 250         u32 mask = 0;
 251         u32 val;
 252
 253         val = intel_uncore_read(uncore,
 254                                 PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
 255
 256         if (val == 0xffffffff) {
 257                 drm_dbg_kms(&i915->drm,
 258                             "Port %s: PHY in TCCOLD, nothing connected\n",
 259                             dig_port->tc_port_name);
 260                 return mask;
 261         }
 262
 263         if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
 264                 mask |= BIT(TC_PORT_TBT_ALT);
 265         if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
 266                 mask |= BIT(TC_PORT_DP_ALT);
 267
 268         if (intel_uncore_read(uncore, SDEISR) & isr_bit)
 269                 mask |= BIT(TC_PORT_LEGACY);
 270
 271         /* The sink can be connected only in a single mode. */
 272         if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1))
 273                 tc_port_fixup_legacy_flag(dig_port, mask);
 274
 275         return mask;
 276 }
 277
 278 static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
 279 {
 280         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 281         enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
 282         u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
 283         struct intel_uncore *uncore = &i915->uncore;
 284         u32 val, mask = 0;
 285
 286         /*
 287          * On ADL-P HW/FW will wake from TCCOLD to complete the read access of
 288          * registers in IOM. Note that this doesn't apply to PHY and FIA
 289          * registers.
 290          */
 291         val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
 292         if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
 293                 mask |= BIT(TC_PORT_DP_ALT);
 294         if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)
 295                 mask |= BIT(TC_PORT_TBT_ALT);
 296
 297         if (intel_uncore_read(uncore, SDEISR) & isr_bit)
 298                 mask |= BIT(TC_PORT_LEGACY);
 299
 300         /* The sink can be connected only in a single mode. */
 301         if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1))
 302                 tc_port_fixup_legacy_flag(dig_port, mask);
 303
 304         return mask;
 305 }
 306
 307 static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
 308 {
 309         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 310
 311         if (IS_ALDERLAKE_P(i915))
 312                 return adl_tc_port_live_status_mask(dig_port);
 313
 314         return icl_tc_port_live_status_mask(dig_port);
 315 }
 316
 317 /*
 318  * Return the PHY status complete flag indicating that display can acquire the
 319  * PHY ownership. The IOM firmware sets this flag when a DP-alt or legacy sink
 320  * is connected and it's ready to switch the ownership to display. The flag
 321  * will be left cleared when a TBT-alt sink is connected, where the PHY is
 322  * owned by the TBT subsystem and so switching the ownership to display is not
 323  * required.
 324  */
 325 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
 326 {
 327         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 328         struct intel_uncore *uncore = &i915->uncore;
 329         u32 val;
 330
 331         val = intel_uncore_read(uncore,
 332                                 PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
 333         if (val == 0xffffffff) {
 334                 drm_dbg_kms(&i915->drm,
 335                             "Port %s: PHY in TCCOLD, assuming not complete\n",
 336                             dig_port->tc_port_name);
 337                 return false;
 338         }
 339
 340         return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
 341 }
 342
 343 /*
 344  * Return the PHY status complete flag indicating that display can acquire the
 345  * PHY ownership. The IOM firmware sets this flag when it's ready to switch
 346  * the ownership to display, regardless of what sink is connected (TBT-alt,
 347  * DP-alt, legacy or nothing). For TBT-alt sinks the PHY is owned by the TBT
 348  * subsystem and so switching the ownership to display is not required.
 349  */
 350 static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
 351 {
 352         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 353         enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
 354         struct intel_uncore *uncore = &i915->uncore;
 355         u32 val;
 356
 357         val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
 358         if (val == 0xffffffff) {
 359                 drm_dbg_kms(&i915->drm,
 360                             "Port %s: PHY in TCCOLD, assuming not complete\n",
 361                             dig_port->tc_port_name);
 362                 return false;
 363         }
 364
 365         return val & TCSS_DDI_STATUS_READY;
 366 }
 367
 368 static bool tc_phy_status_complete(struct intel_digital_port *dig_port)
 369 {
 370         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 371
 372         if (IS_ALDERLAKE_P(i915))
 373                 return adl_tc_phy_status_complete(dig_port);
 374
 375         return icl_tc_phy_status_complete(dig_port);
 376 }
 377
 378 static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
 379                                       bool take)
 380 {
 381         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 382         struct intel_uncore *uncore = &i915->uncore;
 383         u32 val;
 384
 385         val = intel_uncore_read(uncore,
 386                                 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
 387         if (val == 0xffffffff) {
 388                 drm_dbg_kms(&i915->drm,
 389                             "Port %s: PHY in TCCOLD, can't %s ownership\n",
 390                             dig_port->tc_port_name, take ? "take" : "release");
 391
 392                 return false;
 393         }
 394
 395         val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
 396         if (take)
 397                 val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
 398
 399         intel_uncore_write(uncore,
 400                            PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
 401
 402         return true;
 403 }
 404
 405 static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
 406                                       bool take)
 407 {
 408         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 409         struct intel_uncore *uncore = &i915->uncore;
 410         enum port port = dig_port->base.port;
 411         u32 val;
 412
 413         val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
 414         if (take)
 415                 val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 416         else
 417                 val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 418         intel_uncore_write(uncore, DDI_BUF_CTL(port), val);
 419
 420         return true;
 421 }
 422
 423 static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take)
 424 {
 425         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 426
 427         if (IS_ALDERLAKE_P(i915))
 428                 return adl_tc_phy_take_ownership(dig_port, take);
 429
 430         return icl_tc_phy_take_ownership(dig_port, take);
 431 }
 432
 433 static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
 434 {
 435         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 436         struct intel_uncore *uncore = &i915->uncore;
 437         u32 val;
 438
 439         val = intel_uncore_read(uncore,
 440                                 PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
 441         if (val == 0xffffffff) {
 442                 drm_dbg_kms(&i915->drm,
 443                             "Port %s: PHY in TCCOLD, assume safe mode\n",
 444                             dig_port->tc_port_name);
 445                 return true;
 446         }
 447
 448         return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
 449 }
 450
 451 static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
 452 {
 453         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 454         struct intel_uncore *uncore = &i915->uncore;
 455         enum port port = dig_port->base.port;
 456         u32 val;
 457
 458         val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
 459         return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 460 }
 461
 462 static bool tc_phy_is_owned(struct intel_digital_port *dig_port)
 463 {
 464         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 465
 466         if (IS_ALDERLAKE_P(i915))
 467                 return adl_tc_phy_is_owned(dig_port);
 468
 469         return icl_tc_phy_is_owned(dig_port);
 470 }
 471
 472 /*
 473  * This function implements the first part of the Connect Flow described by our
 474  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
 475  * lanes, EDID, etc) is done as needed in the typical places.
 476  *
 477  * Unlike the other ports, type-C ports are not available to use as soon as we
 478  * get a hotplug. The type-C PHYs can be shared between multiple controllers:
 479  * display, USB, etc. As a result, handshaking through FIA is required around
 480  * connect and disconnect to cleanly transfer ownership with the controller and
 481  * set the type-C power state.
 482  */
 483 static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
 484                                int required_lanes)
 485 {
 486         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 487         u32 live_status_mask;
 488         int max_lanes;
 489
 490         if (!tc_phy_status_complete(dig_port)) {
 491                 drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
 492                             dig_port->tc_port_name);
 493                 goto out_set_tbt_alt_mode;
 494         }
 495
 496         live_status_mask = tc_port_live_status_mask(dig_port);
 497         if (!(live_status_mask & (BIT(TC_PORT_DP_ALT) | BIT(TC_PORT_LEGACY))) &&
 498             !dig_port->tc_legacy_port) {
 499                 drm_dbg_kms(&i915->drm, "Port %s: PHY ownership not required (live status %02x)\n",
 500                             dig_port->tc_port_name, live_status_mask);
 501                 goto out_set_tbt_alt_mode;
 502         }
 503
 504         if (!tc_phy_take_ownership(dig_port, true) &&
 505             !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
 506                 goto out_set_tbt_alt_mode;
 507
 508         max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
 509         if (dig_port->tc_legacy_port) {
 510                 drm_WARN_ON(&i915->drm, max_lanes != 4);
 511                 dig_port->tc_mode = TC_PORT_LEGACY;
 512
 513                 return;
 514         }
 515
 516         /*
 517          * Now we have to re-check the live state, in case the port recently
 518          * became disconnected. Not necessary for legacy mode.
 519          */
 520         if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
 521                 drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
 522                             dig_port->tc_port_name);
 523                 goto out_release_phy;
 524         }
 525
 526         if (max_lanes < required_lanes) {
 527                 drm_dbg_kms(&i915->drm,
 528                             "Port %s: PHY max lanes %d < required lanes %d\n",
 529                             dig_port->tc_port_name,
 530                             max_lanes, required_lanes);
 531                 goto out_release_phy;
 532         }
 533
 534         dig_port->tc_mode = TC_PORT_DP_ALT;
 535
 536         return;
 537
 538 out_release_phy:
 539         tc_phy_take_ownership(dig_port, false);
 540 out_set_tbt_alt_mode:
 541         dig_port->tc_mode = TC_PORT_TBT_ALT;
 542 }
 543
 544 /*
 545  * See the comment at the connect function. This implements the Disconnect
 546  * Flow.
 547  */
 548 static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
 549 {
 550         switch (dig_port->tc_mode) {
 551         case TC_PORT_LEGACY:
 552         case TC_PORT_DP_ALT:
 553                 tc_phy_take_ownership(dig_port, false);
 554                 fallthrough;
 555         case TC_PORT_TBT_ALT:
 556                 dig_port->tc_mode = TC_PORT_DISCONNECTED;
 557                 fallthrough;
 558         case TC_PORT_DISCONNECTED:
 559                 break;
 560         default:
 561                 MISSING_CASE(dig_port->tc_mode);
 562         }
 563 }
 564
 565 static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
 566 {
 567         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 568
 569         if (!tc_phy_status_complete(dig_port)) {
 570                 drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n",
 571                             dig_port->tc_port_name);
 572                 return dig_port->tc_mode == TC_PORT_TBT_ALT;
 573         }
 574
 575         /* On ADL-P the PHY complete flag is set in TBT mode as well. */
 576         if (IS_ALDERLAKE_P(i915) && dig_port->tc_mode == TC_PORT_TBT_ALT)
 577                 return true;
 578
 579         if (!tc_phy_is_owned(dig_port)) {
 580                 drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
 581                             dig_port->tc_port_name);
 582
 583                 return false;
 584         }
 585
 586         return dig_port->tc_mode == TC_PORT_DP_ALT ||
 587                dig_port->tc_mode == TC_PORT_LEGACY;
 588 }
 589
 590 static enum tc_port_mode
 591 intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
 592 {
 593         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 594         u32 live_status_mask = tc_port_live_status_mask(dig_port);
 595         enum tc_port_mode mode;
 596
 597         if (!tc_phy_is_owned(dig_port) ||
 598             drm_WARN_ON(&i915->drm, !tc_phy_status_complete(dig_port)))
 599                 return TC_PORT_TBT_ALT;
 600
 601         mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
 602         if (live_status_mask) {
 603                 enum tc_port_mode live_mode = fls(live_status_mask) - 1;
 604
 605                 if (!drm_WARN_ON(&i915->drm, live_mode == TC_PORT_TBT_ALT))
 606                         mode = live_mode;
 607         }
 608
 609         return mode;
 610 }
 611
 612 static enum tc_port_mode
 613 intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
 614 {
 615         u32 live_status_mask = tc_port_live_status_mask(dig_port);
 616
 617         if (live_status_mask)
 618                 return fls(live_status_mask) - 1;
 619
 620         return TC_PORT_TBT_ALT;
 621 }
 622
 623 static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
 624                                      int required_lanes, bool force_disconnect)
 625 {
 626         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 627         enum tc_port_mode old_tc_mode = dig_port->tc_mode;
 628
 629         intel_display_power_flush_work(i915);
 630         if (!intel_tc_cold_requires_aux_pw(dig_port)) {
 631                 enum intel_display_power_domain aux_domain;
 632                 bool aux_powered;
 633
 634                 aux_domain = intel_aux_power_domain(dig_port);
 635                 aux_powered = intel_display_power_is_enabled(i915, aux_domain);
 636                 drm_WARN_ON(&i915->drm, aux_powered);
 637         }
 638
 639         icl_tc_phy_disconnect(dig_port);
 640         if (!force_disconnect)
 641                 icl_tc_phy_connect(dig_port, required_lanes);
 642
 643         drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n",
 644                     dig_port->tc_port_name,
 645                     tc_port_mode_name(old_tc_mode),
 646                     tc_port_mode_name(dig_port->tc_mode));
 647 }
 648
 649 static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
 650 {
 651         return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode;
 652 }
 653
 654 static void intel_tc_port_update_mode(struct intel_digital_port *dig_port,
 655                                       int required_lanes, bool force_disconnect)
 656 {
 657         enum intel_display_power_domain domain;
 658         intel_wakeref_t wref;
 659         bool needs_reset = force_disconnect;
 660
 661         if (!needs_reset) {
 662                 /* Get power domain required to check the hotplug live status. */
 663                 wref = tc_cold_block(dig_port, &domain);
 664                 needs_reset = intel_tc_port_needs_reset(dig_port);
 665                 tc_cold_unblock(dig_port, domain, wref);
 666         }
 667
 668         if (!needs_reset)
 669                 return;
 670
 671         /* Get power domain required for resetting the mode. */
 672         wref = tc_cold_block_in_mode(dig_port, TC_PORT_DISCONNECTED, &domain);
 673
 674         intel_tc_port_reset_mode(dig_port, required_lanes, force_disconnect);
 675
 676         /* Get power domain matching the new mode after reset. */
 677         tc_cold_unblock(dig_port, dig_port->tc_lock_power_domain,
 678                         fetch_and_zero(&dig_port->tc_lock_wakeref));
 679         if (dig_port->tc_mode != TC_PORT_DISCONNECTED)
 680                 dig_port->tc_lock_wakeref = tc_cold_block(dig_port,
 681                                                           &dig_port->tc_lock_power_domain);
 682
 683         tc_cold_unblock(dig_port, domain, wref);
 684 }
 685
 686 static void
 687 intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
 688                                  int refcount)
 689 {
 690         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 691
 692         drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount);
 693         dig_port->tc_link_refcount = refcount;
 694 }
 695
 696 void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
 697 {
 698         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 699         struct intel_encoder *encoder = &dig_port->base;
 700         intel_wakeref_t tc_cold_wref;
 701         enum intel_display_power_domain domain;
 702         int active_links = 0;
 703
 704         mutex_lock(&dig_port->tc_lock);
 705
 706         if (dig_port->dp.is_mst)
 707                 active_links = intel_dp_mst_encoder_active_links(dig_port);
 708         else if (encoder->base.crtc)
 709                 active_links = to_intel_crtc(encoder->base.crtc)->active;
 710
 711         drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_DISCONNECTED);
 712         drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
 713
 714         tc_cold_wref = tc_cold_block(dig_port, &domain);
 715
 716         dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
 717         if (active_links) {
 718                 if (!icl_tc_phy_is_connected(dig_port))
 719                         drm_dbg_kms(&i915->drm,
 720                                     "Port %s: PHY disconnected with %d active link(s)\n",
 721                                     dig_port->tc_port_name, active_links);
 722                 intel_tc_port_link_init_refcount(dig_port, active_links);
 723
 724                 dig_port->tc_lock_wakeref = tc_cold_block(dig_port,
 725                                                           &dig_port->tc_lock_power_domain);
 726         } else {
 727                 /*
 728                  * TBT-alt is the default mode in any case the PHY ownership is not
 729                  * held (regardless of the sink's connected live state), so
 730                  * we'll just switch to disconnected mode from it here without
 731                  * a note.
 732                  */
 733                 if (dig_port->tc_mode != TC_PORT_TBT_ALT)
 734                         drm_dbg_kms(&i915->drm,
 735                                     "Port %s: PHY left in %s mode on disabled port, disconnecting it\n",
 736                                     dig_port->tc_port_name,
 737                                     tc_port_mode_name(dig_port->tc_mode));
 738                 icl_tc_phy_disconnect(dig_port);
 739         }
 740
 741         tc_cold_unblock(dig_port, domain, tc_cold_wref);
 742
 743         drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n",
 744                     dig_port->tc_port_name,
 745                     tc_port_mode_name(dig_port->tc_mode));
 746
 747         mutex_unlock(&dig_port->tc_lock);
 748 }
 749
 750 /*
 751  * The type-C ports are different because even when they are connected, they may
 752  * not be available/usable by the graphics driver: see the comment on
 753  * icl_tc_phy_connect(). So in our driver instead of adding the additional
 754  * concept of "usable" and make everything check for "connected and usable" we
 755  * define a port as "connected" when it is not only connected, but also when it
 756  * is usable by the rest of the driver. That maintains the old assumption that
 757  * connected ports are usable, and avoids exposing to the users objects they
 758  * can't really use.
 759  */
 760 bool intel_tc_port_connected(struct intel_encoder *encoder)
 761 {
 762         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 763         bool is_connected;
 764
 765         intel_tc_port_lock(dig_port);
 766
 767         is_connected = tc_port_live_status_mask(dig_port) &
 768                        BIT(dig_port->tc_mode);
 769
 770         intel_tc_port_unlock(dig_port);
 771
 772         return is_connected;
 773 }
 774
 775 static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
 776                                  int required_lanes)
 777 {
 778         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 779
 780         mutex_lock(&dig_port->tc_lock);
 781
 782         cancel_delayed_work(&dig_port->tc_disconnect_phy_work);
 783
 784         if (!dig_port->tc_link_refcount)
 785                 intel_tc_port_update_mode(dig_port, required_lanes,
 786                                           false);
 787
 788         drm_WARN_ON(&i915->drm, dig_port->tc_mode == TC_PORT_DISCONNECTED);
 789         drm_WARN_ON(&i915->drm, dig_port->tc_mode != TC_PORT_TBT_ALT &&
 790                                 !tc_phy_is_owned(dig_port));
 791 }
 792
 793 void intel_tc_port_lock(struct intel_digital_port *dig_port)
 794 {
 795         __intel_tc_port_lock(dig_port, 1);
 796 }
 797
 798 /**
 799  * intel_tc_port_disconnect_phy_work: disconnect TypeC PHY from display port
 800  * @dig_port: digital port
 801  *
 802  * Disconnect the given digital port from its TypeC PHY (handing back the
 803  * control of the PHY to the TypeC subsystem). This will happen in a delayed
 804  * manner after each aux transactions and modeset disables.
 805  */
 806 static void intel_tc_port_disconnect_phy_work(struct work_struct *work)
 807 {
 808         struct intel_digital_port *dig_port =
 809                 container_of(work, struct intel_digital_port, tc_disconnect_phy_work.work);
 810
 811         mutex_lock(&dig_port->tc_lock);
 812
 813         if (!dig_port->tc_link_refcount)
 814                 intel_tc_port_update_mode(dig_port, 1, true);
 815
 816         mutex_unlock(&dig_port->tc_lock);
 817 }
 818
 819 /**
 820  * intel_tc_port_flush_work: flush the work disconnecting the PHY
 821  * @dig_port: digital port
 822  *
 823  * Flush the delayed work disconnecting an idle PHY.
 824  */
 825 void intel_tc_port_flush_work(struct intel_digital_port *dig_port)
 826 {
 827         flush_delayed_work(&dig_port->tc_disconnect_phy_work);
 828 }
 829
 830 void intel_tc_port_unlock(struct intel_digital_port *dig_port)
 831 {
 832         if (!dig_port->tc_link_refcount && dig_port->tc_mode != TC_PORT_DISCONNECTED)
 833                 queue_delayed_work(system_unbound_wq, &dig_port->tc_disconnect_phy_work,
 834                                    msecs_to_jiffies(1000));
 835
 836         mutex_unlock(&dig_port->tc_lock);
 837 }
 838
 839 bool intel_tc_port_ref_held(struct intel_digital_port *dig_port)
 840 {
 841         return mutex_is_locked(&dig_port->tc_lock) ||
 842                dig_port->tc_link_refcount;
 843 }
 844
 845 void intel_tc_port_get_link(struct intel_digital_port *dig_port,
 846                             int required_lanes)
 847 {
 848         __intel_tc_port_lock(dig_port, required_lanes);
 849         dig_port->tc_link_refcount++;
 850         intel_tc_port_unlock(dig_port);
 851 }
 852
 853 void intel_tc_port_put_link(struct intel_digital_port *dig_port)
 854 {
 855         intel_tc_port_lock(dig_port);
 856         --dig_port->tc_link_refcount;
 857         intel_tc_port_unlock(dig_port);
 858
 859         /*
 860          * Disconnecting the PHY after the PHY's PLL gets disabled may
 861          * hang the system on ADL-P, so disconnect the PHY here synchronously.
 862          * TODO: remove this once the root cause of the ordering requirement
 863          * is found/fixed.
 864          */
 865         intel_tc_port_flush_work(dig_port);
 866 }
 867
 868 static bool
 869 tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
 870 {
 871         enum intel_display_power_domain domain;
 872         intel_wakeref_t wakeref;
 873         u32 val;
 874
 875         if (!INTEL_INFO(i915)->display.has_modular_fia)
 876                 return false;
 877
 878         mutex_lock(&dig_port->tc_lock);
 879         wakeref = tc_cold_block(dig_port, &domain);
 880         val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));
 881         tc_cold_unblock(dig_port, domain, wakeref);
 882         mutex_unlock(&dig_port->tc_lock);
 883
 884         drm_WARN_ON(&i915->drm, val == 0xffffffff);
 885
 886         return val & MODULAR_FIA_MASK;
 887 }
 888
 889 static void
 890 tc_port_load_fia_params(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
 891 {
 892         enum port port = dig_port->base.port;
 893         enum tc_port tc_port = intel_port_to_tc(i915, port);
 894
 895         /*
 896          * Each Modular FIA instance houses 2 TC ports. In SOC that has more
 897          * than two TC ports, there are multiple instances of Modular FIA.
 898          */
 899         if (tc_has_modular_fia(i915, dig_port)) {
 900                 dig_port->tc_phy_fia = tc_port / 2;
 901                 dig_port->tc_phy_fia_idx = tc_port % 2;
 902         } else {
 903                 dig_port->tc_phy_fia = FIA1;
 904                 dig_port->tc_phy_fia_idx = tc_port;
 905         }
 906 }
 907
 908 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
 909 {
 910         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 911         enum port port = dig_port->base.port;
 912         enum tc_port tc_port = intel_port_to_tc(i915, port);
 913
 914         if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
 915                 return;
 916
 917         snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
 918                  "%c/TC#%d", port_name(port), tc_port + 1);
 919
 920         mutex_init(&dig_port->tc_lock);
 921         INIT_DELAYED_WORK(&dig_port->tc_disconnect_phy_work, intel_tc_port_disconnect_phy_work);
 922         dig_port->tc_legacy_port = is_legacy;
 923         dig_port->tc_mode = TC_PORT_DISCONNECTED;
 924         dig_port->tc_link_refcount = 0;
 925         tc_port_load_fia_params(i915, dig_port);
 926 }