drivers/gpu/drm/i915/display/intel_psr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <drm/drm_atomic_helper.h>
  25 #include <drm/drm_damage_helper.h>
  26
  27 #include "display/intel_dp.h"
  28
  29 #include "i915_drv.h"
  30 #include "intel_atomic.h"
  31 #include "intel_crtc.h"
  32 #include "intel_de.h"
  33 #include "intel_display_types.h"
  34 #include "intel_dp_aux.h"
  35 #include "intel_hdmi.h"
  36 #include "intel_psr.h"
  37 #include "intel_snps_phy.h"
  38 #include "skl_universal_plane.h"
  39
  40 /**
  41  * DOC: Panel Self Refresh (PSR/SRD)
  42  *
  43  * Since Haswell Display controller supports Panel Self-Refresh on display
  44  * panels witch have a remote frame buffer (RFB) implemented according to PSR
  45  * spec in eDP1.3. PSR feature allows the display to go to lower standby states
  46  * when system is idle but display is on as it eliminates display refresh
  47  * request to DDR memory completely as long as the frame buffer for that
  48  * display is unchanged.
  49  *
  50  * Panel Self Refresh must be supported by both Hardware (source) and
  51  * Panel (sink).
  52  *
  53  * PSR saves power by caching the framebuffer in the panel RFB, which allows us
  54  * to power down the link and memory controller. For DSI panels the same idea
  55  * is called "manual mode".
  56  *
  57  * The implementation uses the hardware-based PSR support which automatically
  58  * enters/exits self-refresh mode. The hardware takes care of sending the
  59  * required DP aux message and could even retrain the link (that part isn't
  60  * enabled yet though). The hardware also keeps track of any frontbuffer
  61  * changes to know when to exit self-refresh mode again. Unfortunately that
  62  * part doesn't work too well, hence why the i915 PSR support uses the
  63  * software frontbuffer tracking to make sure it doesn't miss a screen
  64  * update. For this integration intel_psr_invalidate() and intel_psr_flush()
  65  * get called by the frontbuffer tracking code. Note that because of locking
  66  * issues the self-refresh re-enable code is done from a work queue, which
  67  * must be correctly synchronized/cancelled when shutting down the pipe."
  68  *
  69  * DC3CO (DC3 clock off)
  70  *
  71  * On top of PSR2, GEN12 adds a intermediate power savings state that turns
  72  * clock off automatically during PSR2 idle state.
  73  * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
  74  * entry/exit allows the HW to enter a low-power state even when page flipping
  75  * periodically (for instance a 30fps video playback scenario).
  76  *
  77  * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
  78  * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
  79  * frames, if no other flip occurs and the function above is executed, DC3CO is
  80  * disabled and PSR2 is configured to enter deep sleep, resetting again in case
  81  * of another flip.
  82  * Front buffer modifications do not trigger DC3CO activation on purpose as it
  83  * would bring a lot of complexity and most of the moderns systems will only
  84  * use page flips.
  85  */
  86
  87 static bool psr_global_enabled(struct intel_dp *intel_dp)
  88 {
  89         struct intel_connector *connector = intel_dp->attached_connector;
  90         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
  91
  92         switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
  93         case I915_PSR_DEBUG_DEFAULT:
  94                 if (i915->params.enable_psr == -1)
  95                         return connector->panel.vbt.psr.enable;
  96                 return i915->params.enable_psr;
  97         case I915_PSR_DEBUG_DISABLE:
  98                 return false;
  99         default:
 100                 return true;
 101         }
 102 }
 103
 104 static bool psr2_global_enabled(struct intel_dp *intel_dp)
 105 {
 106         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 107
 108         switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
 109         case I915_PSR_DEBUG_DISABLE:
 110         case I915_PSR_DEBUG_FORCE_PSR1:
 111                 return false;
 112         default:
 113                 if (i915->params.enable_psr == 1)
 114                         return false;
 115                 return true;
 116         }
 117 }
 118
 119 static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp)
 120 {
 121         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 122
 123         return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_ERROR :
 124                 EDP_PSR_ERROR(intel_dp->psr.transcoder);
 125 }
 126
 127 static u32 psr_irq_post_exit_bit_get(struct intel_dp *intel_dp)
 128 {
 129         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 130
 131         return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_POST_EXIT :
 132                 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);
 133 }
 134
 135 static u32 psr_irq_pre_entry_bit_get(struct intel_dp *intel_dp)
 136 {
 137         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 138
 139         return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_PRE_ENTRY :
 140                 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);
 141 }
 142
 143 static u32 psr_irq_mask_get(struct intel_dp *intel_dp)
 144 {
 145         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 146
 147         return DISPLAY_VER(dev_priv) >= 12 ? TGL_PSR_MASK :
 148                 EDP_PSR_MASK(intel_dp->psr.transcoder);
 149 }
 150
 151 static void psr_irq_control(struct intel_dp *intel_dp)
 152 {
 153         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 154         i915_reg_t imr_reg;
 155         u32 mask, val;
 156
 157         if (DISPLAY_VER(dev_priv) >= 12)
 158                 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
 159         else
 160                 imr_reg = EDP_PSR_IMR;
 161
 162         mask = psr_irq_psr_error_bit_get(intel_dp);
 163         if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)
 164                 mask |= psr_irq_post_exit_bit_get(intel_dp) |
 165                         psr_irq_pre_entry_bit_get(intel_dp);
 166
 167         val = intel_de_read(dev_priv, imr_reg);
 168         val &= ~psr_irq_mask_get(intel_dp);
 169         val |= ~mask;
 170         intel_de_write(dev_priv, imr_reg, val);
 171 }
 172
 173 static void psr_event_print(struct drm_i915_private *i915,
 174                             u32 val, bool psr2_enabled)
 175 {
 176         drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val);
 177         if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE)
 178                 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n");
 179         if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)
 180                 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n");
 181         if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN)
 182                 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n");
 183         if (val & PSR_EVENT_SU_CRC_FIFO_UNDERRUN)
 184                 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n");
 185         if (val & PSR_EVENT_GRAPHICS_RESET)
 186                 drm_dbg_kms(&i915->drm, "\tGraphics reset\n");
 187         if (val & PSR_EVENT_PCH_INTERRUPT)
 188                 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n");
 189         if (val & PSR_EVENT_MEMORY_UP)
 190                 drm_dbg_kms(&i915->drm, "\tMemory up\n");
 191         if (val & PSR_EVENT_FRONT_BUFFER_MODIFY)
 192                 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n");
 193         if (val & PSR_EVENT_WD_TIMER_EXPIRE)
 194                 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n");
 195         if (val & PSR_EVENT_PIPE_REGISTERS_UPDATE)
 196                 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n");
 197         if (val & PSR_EVENT_REGISTER_UPDATE)
 198                 drm_dbg_kms(&i915->drm, "\tRegister updated\n");
 199         if (val & PSR_EVENT_HDCP_ENABLE)
 200                 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n");
 201         if (val & PSR_EVENT_KVMR_SESSION_ENABLE)
 202                 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n");
 203         if (val & PSR_EVENT_VBI_ENABLE)
 204                 drm_dbg_kms(&i915->drm, "\tVBI enabled\n");
 205         if (val & PSR_EVENT_LPSP_MODE_EXIT)
 206                 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n");
 207         if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)
 208                 drm_dbg_kms(&i915->drm, "\tPSR disabled\n");
 209 }
 210
 211 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
 212 {
 213         enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 214         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 215         ktime_t time_ns =  ktime_get();
 216         i915_reg_t imr_reg;
 217
 218         if (DISPLAY_VER(dev_priv) >= 12)
 219                 imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder);
 220         else
 221                 imr_reg = EDP_PSR_IMR;
 222
 223         if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) {
 224                 intel_dp->psr.last_entry_attempt = time_ns;
 225                 drm_dbg_kms(&dev_priv->drm,
 226                             "[transcoder %s] PSR entry attempt in 2 vblanks\n",
 227                             transcoder_name(cpu_transcoder));
 228         }
 229
 230         if (psr_iir & psr_irq_post_exit_bit_get(intel_dp)) {
 231                 intel_dp->psr.last_exit = time_ns;
 232                 drm_dbg_kms(&dev_priv->drm,
 233                             "[transcoder %s] PSR exit completed\n",
 234                             transcoder_name(cpu_transcoder));
 235
 236                 if (DISPLAY_VER(dev_priv) >= 9) {
 237                         u32 val = intel_de_read(dev_priv,
 238                                                 PSR_EVENT(cpu_transcoder));
 239                         bool psr2_enabled = intel_dp->psr.psr2_enabled;
 240
 241                         intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
 242                                        val);
 243                         psr_event_print(dev_priv, val, psr2_enabled);
 244                 }
 245         }
 246
 247         if (psr_iir & psr_irq_psr_error_bit_get(intel_dp)) {
 248                 u32 val;
 249
 250                 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n",
 251                          transcoder_name(cpu_transcoder));
 252
 253                 intel_dp->psr.irq_aux_error = true;
 254
 255                 /*
 256                  * If this interruption is not masked it will keep
 257                  * interrupting so fast that it prevents the scheduled
 258                  * work to run.
 259                  * Also after a PSR error, we don't want to arm PSR
 260                  * again so we don't care about unmask the interruption
 261                  * or unset irq_aux_error.
 262                  */
 263                 val = intel_de_read(dev_priv, imr_reg);
 264                 val |= psr_irq_psr_error_bit_get(intel_dp);
 265                 intel_de_write(dev_priv, imr_reg, val);
 266
 267                 schedule_work(&intel_dp->psr.work);
 268         }
 269 }
 270
 271 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
 272 {
 273         u8 alpm_caps = 0;
 274
 275         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
 276                               &alpm_caps) != 1)
 277                 return false;
 278         return alpm_caps & DP_ALPM_CAP;
 279 }
 280
 281 static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
 282 {
 283         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 284         u8 val = 8; /* assume the worst if we can't read the value */
 285
 286         if (drm_dp_dpcd_readb(&intel_dp->aux,
 287                               DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
 288                 val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
 289         else
 290                 drm_dbg_kms(&i915->drm,
 291                             "Unable to get sink synchronization latency, assuming 8 frames\n");
 292         return val;
 293 }
 294
 295 static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 296 {
 297         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 298         ssize_t r;
 299         u16 w;
 300         u8 y;
 301
 302         /* If sink don't have specific granularity requirements set legacy ones */
 303         if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) {
 304                 /* As PSR2 HW sends full lines, we do not care about x granularity */
 305                 w = 4;
 306                 y = 4;
 307                 goto exit;
 308         }
 309
 310         r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2);
 311         if (r != 2)
 312                 drm_dbg_kms(&i915->drm,
 313                             "Unable to read DP_PSR2_SU_X_GRANULARITY\n");
 314         /*
 315          * Spec says that if the value read is 0 the default granularity should
 316          * be used instead.
 317          */
 318         if (r != 2 || w == 0)
 319                 w = 4;
 320
 321         r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1);
 322         if (r != 1) {
 323                 drm_dbg_kms(&i915->drm,
 324                             "Unable to read DP_PSR2_SU_Y_GRANULARITY\n");
 325                 y = 4;
 326         }
 327         if (y == 0)
 328                 y = 1;
 329
 330 exit:
 331         intel_dp->psr.su_w_granularity = w;
 332         intel_dp->psr.su_y_granularity = y;
 333 }
 334
 335 void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 336 {
 337         struct drm_i915_private *dev_priv =
 338                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 339
 340         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
 341                          sizeof(intel_dp->psr_dpcd));
 342
 343         if (!intel_dp->psr_dpcd[0])
 344                 return;
 345         drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
 346                     intel_dp->psr_dpcd[0]);
 347
 348         if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
 349                 drm_dbg_kms(&dev_priv->drm,
 350                             "PSR support not currently available for this panel\n");
 351                 return;
 352         }
 353
 354         if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
 355                 drm_dbg_kms(&dev_priv->drm,
 356                             "Panel lacks power state control, PSR cannot be enabled\n");
 357                 return;
 358         }
 359
 360         intel_dp->psr.sink_support = true;
 361         intel_dp->psr.sink_sync_latency =
 362                 intel_dp_get_sink_sync_latency(intel_dp);
 363
 364         if (DISPLAY_VER(dev_priv) >= 9 &&
 365             (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
 366                 bool y_req = intel_dp->psr_dpcd[1] &
 367                              DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 368                 bool alpm = intel_dp_get_alpm_status(intel_dp);
 369
 370                 /*
 371                  * All panels that supports PSR version 03h (PSR2 +
 372                  * Y-coordinate) can handle Y-coordinates in VSC but we are
 373                  * only sure that it is going to be used when required by the
 374                  * panel. This way panel is capable to do selective update
 375                  * without a aux frame sync.
 376                  *
 377                  * To support PSR version 02h and PSR version 03h without
 378                  * Y-coordinate requirement panels we would need to enable
 379                  * GTC first.
 380                  */
 381                 intel_dp->psr.sink_psr2_support = y_req && alpm;
 382                 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
 383                             intel_dp->psr.sink_psr2_support ? "" : "not ");
 384
 385                 if (intel_dp->psr.sink_psr2_support) {
 386                         intel_dp->psr.colorimetry_support =
 387                                 intel_dp_get_colorimetry_status(intel_dp);
 388                         intel_dp_get_su_granularity(intel_dp);
 389                 }
 390         }
 391 }
 392
 393 static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 394 {
 395         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 396         u8 dpcd_val = DP_PSR_ENABLE;
 397
 398         /* Enable ALPM at sink for psr2 */
 399         if (intel_dp->psr.psr2_enabled) {
 400                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 401                                    DP_ALPM_ENABLE |
 402                                    DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
 403
 404                 dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS;
 405         } else {
 406                 if (intel_dp->psr.link_standby)
 407                         dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
 408
 409                 if (DISPLAY_VER(dev_priv) >= 8)
 410                         dpcd_val |= DP_PSR_CRC_VERIFICATION;
 411         }
 412
 413         if (intel_dp->psr.req_psr2_sdp_prior_scanline)
 414                 dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE;
 415
 416         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
 417
 418         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
 419 }
 420
 421 static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 422 {
 423         struct intel_connector *connector = intel_dp->attached_connector;
 424         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 425         u32 val = 0;
 426
 427         if (DISPLAY_VER(dev_priv) >= 11)
 428                 val |= EDP_PSR_TP4_TIME_0US;
 429
 430         if (dev_priv->params.psr_safest_params) {
 431                 val |= EDP_PSR_TP1_TIME_2500us;
 432                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 433                 goto check_tp3_sel;
 434         }
 435
 436         if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)
 437                 val |= EDP_PSR_TP1_TIME_0us;
 438         else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)
 439                 val |= EDP_PSR_TP1_TIME_100us;
 440         else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)
 441                 val |= EDP_PSR_TP1_TIME_500us;
 442         else
 443                 val |= EDP_PSR_TP1_TIME_2500us;
 444
 445         if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)
 446                 val |= EDP_PSR_TP2_TP3_TIME_0us;
 447         else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)
 448                 val |= EDP_PSR_TP2_TP3_TIME_100us;
 449         else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)
 450                 val |= EDP_PSR_TP2_TP3_TIME_500us;
 451         else
 452                 val |= EDP_PSR_TP2_TP3_TIME_2500us;
 453
 454 check_tp3_sel:
 455         if (intel_dp_source_supports_tps3(dev_priv) &&
 456             drm_dp_tps3_supported(intel_dp->dpcd))
 457                 val |= EDP_PSR_TP1_TP3_SEL;
 458         else
 459                 val |= EDP_PSR_TP1_TP2_SEL;
 460
 461         return val;
 462 }
 463
 464 static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
 465 {
 466         struct intel_connector *connector = intel_dp->attached_connector;
 467         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 468         int idle_frames;
 469
 470         /* Let's use 6 as the minimum to cover all known cases including the
 471          * off-by-one issue that HW has in some cases.
 472          */
 473         idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
 474         idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
 475
 476         if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf))
 477                 idle_frames = 0xf;
 478
 479         return idle_frames;
 480 }
 481
 482 static void hsw_activate_psr1(struct intel_dp *intel_dp)
 483 {
 484         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 485         u32 max_sleep_time = 0x1f;
 486         u32 val = EDP_PSR_ENABLE;
 487
 488         val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT;
 489
 490         val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
 491         if (IS_HASWELL(dev_priv))
 492                 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
 493
 494         if (intel_dp->psr.link_standby)
 495                 val |= EDP_PSR_LINK_STANDBY;
 496
 497         val |= intel_psr1_get_tp_time(intel_dp);
 498
 499         if (DISPLAY_VER(dev_priv) >= 8)
 500                 val |= EDP_PSR_CRC_ENABLE;
 501
 502         val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
 503                 EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
 504         intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
 505 }
 506
 507 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 508 {
 509         struct intel_connector *connector = intel_dp->attached_connector;
 510         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 511         u32 val = 0;
 512
 513         if (dev_priv->params.psr_safest_params)
 514                 return EDP_PSR2_TP2_TIME_2500us;
 515
 516         if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
 517             connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
 518                 val |= EDP_PSR2_TP2_TIME_50us;
 519         else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
 520                 val |= EDP_PSR2_TP2_TIME_100us;
 521         else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
 522                 val |= EDP_PSR2_TP2_TIME_500us;
 523         else
 524                 val |= EDP_PSR2_TP2_TIME_2500us;
 525
 526         return val;
 527 }
 528
 529 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 530 {
 531         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 532         u32 val = EDP_PSR2_ENABLE;
 533
 534         val |= psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;
 535
 536         if (!IS_ALDERLAKE_P(dev_priv))
 537                 val |= EDP_SU_TRACK_ENABLE;
 538
 539         if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
 540                 val |= EDP_Y_COORDINATE_ENABLE;
 541
 542         val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));
 543         val |= intel_psr2_get_tp_time(intel_dp);
 544
 545         /* Wa_22012278275:adl-p */
 546         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_E0)) {
 547                 static const u8 map[] = {
 548                         2, /* 5 lines */
 549                         1, /* 6 lines */
 550                         0, /* 7 lines */
 551                         3, /* 8 lines */
 552                         6, /* 9 lines */
 553                         5, /* 10 lines */
 554                         4, /* 11 lines */
 555                         7, /* 12 lines */
 556                 };
 557                 /*
 558                  * Still using the default IO_BUFFER_WAKE and FAST_WAKE, see
 559                  * comments bellow for more information
 560                  */
 561                 u32 tmp, lines = 7;
 562
 563                 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 564
 565                 tmp = map[lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES];
 566                 tmp = tmp << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT;
 567                 val |= tmp;
 568
 569                 tmp = map[lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
 570                 tmp = tmp << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT;
 571                 val |= tmp;
 572         } else if (DISPLAY_VER(dev_priv) >= 12) {
 573                 /*
 574                  * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
 575                  * values from BSpec. In order to setting an optimal power
 576                  * consumption, lower than 4k resolution mode needs to decrease
 577                  * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
 578                  * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
 579                  */
 580                 val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
 581                 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
 582                 val |= TGL_EDP_PSR2_FAST_WAKE(7);
 583         } else if (DISPLAY_VER(dev_priv) >= 9) {
 584                 val |= EDP_PSR2_IO_BUFFER_WAKE(7);
 585                 val |= EDP_PSR2_FAST_WAKE(7);
 586         }
 587
 588         if (intel_dp->psr.req_psr2_sdp_prior_scanline)
 589                 val |= EDP_PSR2_SU_SDP_SCANLINE;
 590
 591         if (intel_dp->psr.psr2_sel_fetch_enabled) {
 592                 u32 tmp;
 593
 594                 /* Wa_1408330847 */
 595                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 596                         intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
 597                                      DIS_RAM_BYPASS_PSR2_MAN_TRACK,
 598                                      DIS_RAM_BYPASS_PSR2_MAN_TRACK);
 599
 600                 tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
 601                 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
 602         } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 603                 intel_de_write(dev_priv,
 604                                PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
 605         }
 606
 607         /*
 608          * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
 609          * recommending keep this bit unset while PSR2 is enabled.
 610          */
 611         intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), 0);
 612
 613         intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
 614 }
 615
 616 static bool
 617 transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
 618 {
 619         if (IS_ALDERLAKE_P(dev_priv))
 620                 return trans == TRANSCODER_A || trans == TRANSCODER_B;
 621         else if (DISPLAY_VER(dev_priv) >= 12)
 622                 return trans == TRANSCODER_A;
 623         else
 624                 return trans == TRANSCODER_EDP;
 625 }
 626
 627 static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
 628 {
 629         if (!cstate || !cstate->hw.active)
 630                 return 0;
 631
 632         return DIV_ROUND_UP(1000 * 1000,
 633                             drm_mode_vrefresh(&cstate->hw.adjusted_mode));
 634 }
 635
 636 static void psr2_program_idle_frames(struct intel_dp *intel_dp,
 637                                      u32 idle_frames)
 638 {
 639         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 640         u32 val;
 641
 642         idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT;
 643         val = intel_de_read(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder));
 644         val &= ~EDP_PSR2_IDLE_FRAME_MASK;
 645         val |= idle_frames;
 646         intel_de_write(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
 647 }
 648
 649 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
 650 {
 651         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 652
 653         psr2_program_idle_frames(intel_dp, 0);
 654         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
 655 }
 656
 657 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
 658 {
 659         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 660
 661         intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 662         psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
 663 }
 664
 665 static void tgl_dc3co_disable_work(struct work_struct *work)
 666 {
 667         struct intel_dp *intel_dp =
 668                 container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
 669
 670         mutex_lock(&intel_dp->psr.lock);
 671         /* If delayed work is pending, it is not idle */
 672         if (delayed_work_pending(&intel_dp->psr.dc3co_work))
 673                 goto unlock;
 674
 675         tgl_psr2_disable_dc3co(intel_dp);
 676 unlock:
 677         mutex_unlock(&intel_dp->psr.lock);
 678 }
 679
 680 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
 681 {
 682         if (!intel_dp->psr.dc3co_exitline)
 683                 return;
 684
 685         cancel_delayed_work(&intel_dp->psr.dc3co_work);
 686         /* Before PSR2 exit disallow dc3co*/
 687         tgl_psr2_disable_dc3co(intel_dp);
 688 }
 689
 690 static bool
 691 dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
 692                               struct intel_crtc_state *crtc_state)
 693 {
 694         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 695         enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
 696         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 697         enum port port = dig_port->base.port;
 698
 699         if (IS_ALDERLAKE_P(dev_priv))
 700                 return pipe <= PIPE_B && port <= PORT_B;
 701         else
 702                 return pipe == PIPE_A && port == PORT_A;
 703 }
 704
 705 static void
 706 tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
 707                                   struct intel_crtc_state *crtc_state)
 708 {
 709         const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
 710         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 711         u32 exit_scanlines;
 712
 713         /*
 714          * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
 715          * disable DC3CO until the changed dc3co activating/deactivating sequence
 716          * is applied. B.Specs:49196
 717          */
 718         return;
 719
 720         /*
 721          * DMC's DC3CO exit mechanism has an issue with Selective Fecth
 722          * TODO: when the issue is addressed, this restriction should be removed.
 723          */
 724         if (crtc_state->enable_psr2_sel_fetch)
 725                 return;
 726
 727         if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
 728                 return;
 729
 730         if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
 731                 return;
 732
 733         /* Wa_16011303918:adl-p */
 734         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 735                 return;
 736
 737         /*
 738          * DC3CO Exit time 200us B.Spec 49196
 739          * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
 740          */
 741         exit_scanlines =
 742                 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
 743
 744         if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay))
 745                 return;
 746
 747         crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
 748 }
 749
 750 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 751                                               struct intel_crtc_state *crtc_state)
 752 {
 753         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 754
 755         if (!dev_priv->params.enable_psr2_sel_fetch &&
 756             intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
 757                 drm_dbg_kms(&dev_priv->drm,
 758                             "PSR2 sel fetch not enabled, disabled by parameter\n");
 759                 return false;
 760         }
 761
 762         if (crtc_state->uapi.async_flip) {
 763                 drm_dbg_kms(&dev_priv->drm,
 764                             "PSR2 sel fetch not enabled, async flip enabled\n");
 765                 return false;
 766         }
 767
 768         /* Wa_14010254185 Wa_14010103792 */
 769         if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
 770                 drm_dbg_kms(&dev_priv->drm,
 771                             "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
 772                 return false;
 773         }
 774
 775         return crtc_state->enable_psr2_sel_fetch = true;
 776 }
 777
 778 static bool psr2_granularity_check(struct intel_dp *intel_dp,
 779                                    struct intel_crtc_state *crtc_state)
 780 {
 781         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 782         const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 783         const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 784         u16 y_granularity = 0;
 785
 786         /* PSR2 HW only send full lines so we only need to validate the width */
 787         if (crtc_hdisplay % intel_dp->psr.su_w_granularity)
 788                 return false;
 789
 790         if (crtc_vdisplay % intel_dp->psr.su_y_granularity)
 791                 return false;
 792
 793         /* HW tracking is only aligned to 4 lines */
 794         if (!crtc_state->enable_psr2_sel_fetch)
 795                 return intel_dp->psr.su_y_granularity == 4;
 796
 797         /*
 798          * adl_p has 1 line granularity. For other platforms with SW tracking we
 799          * can adjust the y coordinates to match sink requirement if multiple of
 800          * 4.
 801          */
 802         if (IS_ALDERLAKE_P(dev_priv))
 803                 y_granularity = intel_dp->psr.su_y_granularity;
 804         else if (intel_dp->psr.su_y_granularity <= 2)
 805                 y_granularity = 4;
 806         else if ((intel_dp->psr.su_y_granularity % 4) == 0)
 807                 y_granularity = intel_dp->psr.su_y_granularity;
 808
 809         if (y_granularity == 0 || crtc_vdisplay % y_granularity)
 810                 return false;
 811
 812         crtc_state->su_y_granularity = y_granularity;
 813         return true;
 814 }
 815
 816 static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dp,
 817                                                         struct intel_crtc_state *crtc_state)
 818 {
 819         const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;
 820         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 821         u32 hblank_total, hblank_ns, req_ns;
 822
 823         hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
 824         hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock);
 825
 826         /* From spec: ((60 / number of lanes) + 11) * 1000 / symbol clock frequency MHz */
 827         req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000);
 828
 829         if ((hblank_ns - req_ns) > 100)
 830                 return true;
 831
 832         /* Not supported <13 / Wa_22012279113:adl-p */
 833         if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b)
 834                 return false;
 835
 836         crtc_state->req_psr2_sdp_prior_scanline = true;
 837         return true;
 838 }
 839
 840 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 841                                     struct intel_crtc_state *crtc_state)
 842 {
 843         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 844         int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay;
 845         int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 846         int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 847
 848         if (!intel_dp->psr.sink_psr2_support)
 849                 return false;
 850
 851         /* JSL and EHL only supports eDP 1.3 */
 852         if (IS_JSL_EHL(dev_priv)) {
 853                 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n");
 854                 return false;
 855         }
 856
 857         /* Wa_16011181250 */
 858         if (IS_ROCKETLAKE(dev_priv) || IS_ALDERLAKE_S(dev_priv) ||
 859             IS_DG2(dev_priv)) {
 860                 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n");
 861                 return false;
 862         }
 863
 864         if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 865                 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n");
 866                 return false;
 867         }
 868
 869         if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) {
 870                 drm_dbg_kms(&dev_priv->drm,
 871                             "PSR2 not supported in transcoder %s\n",
 872                             transcoder_name(crtc_state->cpu_transcoder));
 873                 return false;
 874         }
 875
 876         if (!psr2_global_enabled(intel_dp)) {
 877                 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n");
 878                 return false;
 879         }
 880
 881         /*
 882          * DSC and PSR2 cannot be enabled simultaneously. If a requested
 883          * resolution requires DSC to be enabled, priority is given to DSC
 884          * over PSR2.
 885          */
 886         if (crtc_state->dsc.compression_enable) {
 887                 drm_dbg_kms(&dev_priv->drm,
 888                             "PSR2 cannot be enabled since DSC is enabled\n");
 889                 return false;
 890         }
 891
 892         if (crtc_state->crc_enabled) {
 893                 drm_dbg_kms(&dev_priv->drm,
 894                             "PSR2 not enabled because it would inhibit pipe CRC calculation\n");
 895                 return false;
 896         }
 897
 898         if (DISPLAY_VER(dev_priv) >= 12) {
 899                 psr_max_h = 5120;
 900                 psr_max_v = 3200;
 901                 max_bpp = 30;
 902         } else if (DISPLAY_VER(dev_priv) >= 10) {
 903                 psr_max_h = 4096;
 904                 psr_max_v = 2304;
 905                 max_bpp = 24;
 906         } else if (DISPLAY_VER(dev_priv) == 9) {
 907                 psr_max_h = 3640;
 908                 psr_max_v = 2304;
 909                 max_bpp = 24;
 910         }
 911
 912         if (crtc_state->pipe_bpp > max_bpp) {
 913                 drm_dbg_kms(&dev_priv->drm,
 914                             "PSR2 not enabled, pipe bpp %d > max supported %d\n",
 915                             crtc_state->pipe_bpp, max_bpp);
 916                 return false;
 917         }
 918
 919         /* Wa_16011303918:adl-p */
 920         if (crtc_state->vrr.enable &&
 921             IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
 922                 drm_dbg_kms(&dev_priv->drm,
 923                             "PSR2 not enabled, not compatible with HW stepping + VRR\n");
 924                 return false;
 925         }
 926
 927         if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {
 928                 drm_dbg_kms(&dev_priv->drm,
 929                             "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");
 930                 return false;
 931         }
 932
 933         if (HAS_PSR2_SEL_FETCH(dev_priv)) {
 934                 if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&
 935                     !HAS_PSR_HW_TRACKING(dev_priv)) {
 936                         drm_dbg_kms(&dev_priv->drm,
 937                                     "PSR2 not enabled, selective fetch not valid and no HW tracking available\n");
 938                         return false;
 939                 }
 940         }
 941
 942         /* Wa_2209313811 */
 943         if (!crtc_state->enable_psr2_sel_fetch &&
 944             IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
 945                 drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
 946                 goto unsupported;
 947         }
 948
 949         if (!psr2_granularity_check(intel_dp, crtc_state)) {
 950                 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
 951                 goto unsupported;
 952         }
 953
 954         if (!crtc_state->enable_psr2_sel_fetch &&
 955             (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) {
 956                 drm_dbg_kms(&dev_priv->drm,
 957                             "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",
 958                             crtc_hdisplay, crtc_vdisplay,
 959                             psr_max_h, psr_max_v);
 960                 goto unsupported;
 961         }
 962
 963         tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
 964         return true;
 965
 966 unsupported:
 967         crtc_state->enable_psr2_sel_fetch = false;
 968         return false;
 969 }
 970
 971 void intel_psr_compute_config(struct intel_dp *intel_dp,
 972                               struct intel_crtc_state *crtc_state,
 973                               struct drm_connector_state *conn_state)
 974 {
 975         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 976         const struct drm_display_mode *adjusted_mode =
 977                 &crtc_state->hw.adjusted_mode;
 978         int psr_setup_time;
 979
 980         /*
 981          * Current PSR panels don't work reliably with VRR enabled
 982          * So if VRR is enabled, do not enable PSR.
 983          */
 984         if (crtc_state->vrr.enable)
 985                 return;
 986
 987         if (!CAN_PSR(intel_dp))
 988                 return;
 989
 990         if (!psr_global_enabled(intel_dp)) {
 991                 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n");
 992                 return;
 993         }
 994
 995         if (intel_dp->psr.sink_not_reliable) {
 996                 drm_dbg_kms(&dev_priv->drm,
 997                             "PSR sink implementation is not reliable\n");
 998                 return;
 999         }
1000
1001         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
1002                 drm_dbg_kms(&dev_priv->drm,
1003                             "PSR condition failed: Interlaced mode enabled\n");
1004                 return;
1005         }
1006
1007         psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd);
1008         if (psr_setup_time < 0) {
1009                 drm_dbg_kms(&dev_priv->drm,
1010                             "PSR condition failed: Invalid PSR setup time (0x%02x)\n",
1011                             intel_dp->psr_dpcd[1]);
1012                 return;
1013         }
1014
1015         if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) >
1016             adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) {
1017                 drm_dbg_kms(&dev_priv->drm,
1018                             "PSR condition failed: PSR setup time (%d us) too long\n",
1019                             psr_setup_time);
1020                 return;
1021         }
1022
1023         crtc_state->has_psr = true;
1024         crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
1025
1026         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1027         intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
1028                                      &crtc_state->psr_vsc);
1029 }
1030
1031 void intel_psr_get_config(struct intel_encoder *encoder,
1032                           struct intel_crtc_state *pipe_config)
1033 {
1034         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1035         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1036         struct intel_dp *intel_dp;
1037         u32 val;
1038
1039         if (!dig_port)
1040                 return;
1041
1042         intel_dp = &dig_port->dp;
1043         if (!CAN_PSR(intel_dp))
1044                 return;
1045
1046         mutex_lock(&intel_dp->psr.lock);
1047         if (!intel_dp->psr.enabled)
1048                 goto unlock;
1049
1050         /*
1051          * Not possible to read EDP_PSR/PSR2_CTL registers as it is
1052          * enabled/disabled because of frontbuffer tracking and others.
1053          */
1054         pipe_config->has_psr = true;
1055         pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
1056         pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
1057
1058         if (!intel_dp->psr.psr2_enabled)
1059                 goto unlock;
1060
1061         if (HAS_PSR2_SEL_FETCH(dev_priv)) {
1062                 val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
1063                 if (val & PSR2_MAN_TRK_CTL_ENABLE)
1064                         pipe_config->enable_psr2_sel_fetch = true;
1065         }
1066
1067         if (DISPLAY_VER(dev_priv) >= 12) {
1068                 val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
1069                 val &= EXITLINE_MASK;
1070                 pipe_config->dc3co_exitline = val;
1071         }
1072 unlock:
1073         mutex_unlock(&intel_dp->psr.lock);
1074 }
1075
1076 static void intel_psr_activate(struct intel_dp *intel_dp)
1077 {
1078         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1079         enum transcoder transcoder = intel_dp->psr.transcoder;
1080
1081         if (transcoder_has_psr2(dev_priv, transcoder))
1082                 drm_WARN_ON(&dev_priv->drm,
1083                             intel_de_read(dev_priv, EDP_PSR2_CTL(transcoder)) & EDP_PSR2_ENABLE);
1084
1085         drm_WARN_ON(&dev_priv->drm,
1086                     intel_de_read(dev_priv, EDP_PSR_CTL(transcoder)) & EDP_PSR_ENABLE);
1087         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
1088         lockdep_assert_held(&intel_dp->psr.lock);
1089
1090         /* psr1 and psr2 are mutually exclusive.*/
1091         if (intel_dp->psr.psr2_enabled)
1092                 hsw_activate_psr2(intel_dp);
1093         else
1094                 hsw_activate_psr1(intel_dp);
1095
1096         intel_dp->psr.active = true;
1097 }
1098
1099 static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp)
1100 {
1101         switch (intel_dp->psr.pipe) {
1102         case PIPE_A:
1103                 return LATENCY_REPORTING_REMOVED_PIPE_A;
1104         case PIPE_B:
1105                 return LATENCY_REPORTING_REMOVED_PIPE_B;
1106         case PIPE_C:
1107                 return LATENCY_REPORTING_REMOVED_PIPE_C;
1108         default:
1109                 MISSING_CASE(intel_dp->psr.pipe);
1110                 return 0;
1111         }
1112 }
1113
1114 static void intel_psr_enable_source(struct intel_dp *intel_dp,
1115                                     const struct intel_crtc_state *crtc_state)
1116 {
1117         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1118         enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
1119         u32 mask;
1120
1121         /*
1122          * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
1123          * mask LPSP to avoid dependency on other drivers that might block
1124          * runtime_pm besides preventing  other hw tracking issues now we
1125          * can rely on frontbuffer tracking.
1126          */
1127         mask = EDP_PSR_DEBUG_MASK_MEMUP |
1128                EDP_PSR_DEBUG_MASK_HPD |
1129                EDP_PSR_DEBUG_MASK_LPSP |
1130                EDP_PSR_DEBUG_MASK_MAX_SLEEP;
1131
1132         if (DISPLAY_VER(dev_priv) < 11)
1133                 mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
1134
1135         intel_de_write(dev_priv, EDP_PSR_DEBUG(intel_dp->psr.transcoder),
1136                        mask);
1137
1138         psr_irq_control(intel_dp);
1139
1140         if (intel_dp->psr.dc3co_exitline) {
1141                 u32 val;
1142
1143                 /*
1144                  * TODO: if future platforms supports DC3CO in more than one
1145                  * transcoder, EXITLINE will need to be unset when disabling PSR
1146                  */
1147                 val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
1148                 val &= ~EXITLINE_MASK;
1149                 val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
1150                 val |= EXITLINE_ENABLE;
1151                 intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
1152         }
1153
1154         if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
1155                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
1156                              intel_dp->psr.psr2_sel_fetch_enabled ?
1157                              IGNORE_PSR2_HW_TRACKING : 0);
1158
1159         if (intel_dp->psr.psr2_enabled) {
1160                 if (DISPLAY_VER(dev_priv) == 9)
1161                         intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
1162                                      PSR2_VSC_ENABLE_PROG_HEADER |
1163                                      PSR2_ADD_VERTICAL_LINE_COUNT);
1164
1165                 /*
1166                  * Wa_16014451276:adlp
1167                  * All supported adlp panels have 1-based X granularity, this may
1168                  * cause issues if non-supported panels are used.
1169                  */
1170                 if (IS_ALDERLAKE_P(dev_priv))
1171                         intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
1172                                      ADLP_1_BASED_X_GRANULARITY);
1173
1174                 /* Wa_16011168373:adl-p */
1175                 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1176                         intel_de_rmw(dev_priv,
1177                                      TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1178                                      TRANS_SET_CONTEXT_LATENCY_MASK,
1179                                      TRANS_SET_CONTEXT_LATENCY_VALUE(1));
1180
1181                 /* Wa_16012604467:adlp */
1182                 if (IS_ALDERLAKE_P(dev_priv))
1183                         intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0,
1184                                      CLKGATE_DIS_MISC_DMASC_GATING_DIS);
1185
1186                 /* Wa_16013835468:tgl[b0+], dg1 */
1187                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
1188                     IS_DG1(dev_priv)) {
1189                         u16 vtotal, vblank;
1190
1191                         vtotal = crtc_state->uapi.adjusted_mode.crtc_vtotal -
1192                                  crtc_state->uapi.adjusted_mode.crtc_vdisplay;
1193                         vblank = crtc_state->uapi.adjusted_mode.crtc_vblank_end -
1194                                  crtc_state->uapi.adjusted_mode.crtc_vblank_start;
1195                         if (vblank > vtotal)
1196                                 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
1197                                              wa_16013835468_bit_get(intel_dp));
1198                 }
1199         }
1200 }
1201
1202 static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
1203 {
1204         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1205         u32 val;
1206
1207         /*
1208          * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
1209          * will still keep the error set even after the reset done in the
1210          * irq_preinstall and irq_uninstall hooks.
1211          * And enabling in this situation cause the screen to freeze in the
1212          * first time that PSR HW tries to activate so lets keep PSR disabled
1213          * to avoid any rendering problems.
1214          */
1215         if (DISPLAY_VER(dev_priv) >= 12)
1216                 val = intel_de_read(dev_priv,
1217                                     TRANS_PSR_IIR(intel_dp->psr.transcoder));
1218         else
1219                 val = intel_de_read(dev_priv, EDP_PSR_IIR);
1220         val &= psr_irq_psr_error_bit_get(intel_dp);
1221         if (val) {
1222                 intel_dp->psr.sink_not_reliable = true;
1223                 drm_dbg_kms(&dev_priv->drm,
1224                             "PSR interruption error set, not enabling PSR\n");
1225                 return false;
1226         }
1227
1228         return true;
1229 }
1230
1231 static void intel_psr_enable_locked(struct intel_dp *intel_dp,
1232                                     const struct intel_crtc_state *crtc_state)
1233 {
1234         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1235         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1236         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
1237         struct intel_encoder *encoder = &dig_port->base;
1238         u32 val;
1239
1240         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
1241
1242         intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
1243         intel_dp->psr.busy_frontbuffer_bits = 0;
1244         intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
1245         intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
1246         /* DC5/DC6 requires at least 6 idle frames */
1247         val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
1248         intel_dp->psr.dc3co_exit_delay = val;
1249         intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
1250         intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
1251         intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1252         intel_dp->psr.req_psr2_sdp_prior_scanline =
1253                 crtc_state->req_psr2_sdp_prior_scanline;
1254
1255         if (!psr_interrupt_error_check(intel_dp))
1256                 return;
1257
1258         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
1259                     intel_dp->psr.psr2_enabled ? "2" : "1");
1260         intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc);
1261         intel_snps_phy_update_psr_power_state(dev_priv, phy, true);
1262         intel_psr_enable_sink(intel_dp);
1263         intel_psr_enable_source(intel_dp, crtc_state);
1264         intel_dp->psr.enabled = true;
1265         intel_dp->psr.paused = false;
1266
1267         intel_psr_activate(intel_dp);
1268 }
1269
1270 static void intel_psr_exit(struct intel_dp *intel_dp)
1271 {
1272         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1273         u32 val;
1274
1275         if (!intel_dp->psr.active) {
1276                 if (transcoder_has_psr2(dev_priv, intel_dp->psr.transcoder)) {
1277                         val = intel_de_read(dev_priv,
1278                                             EDP_PSR2_CTL(intel_dp->psr.transcoder));
1279                         drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE);
1280                 }
1281
1282                 val = intel_de_read(dev_priv,
1283                                     EDP_PSR_CTL(intel_dp->psr.transcoder));
1284                 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE);
1285
1286                 return;
1287         }
1288
1289         if (intel_dp->psr.psr2_enabled) {
1290                 tgl_disallow_dc3co_on_psr2_exit(intel_dp);
1291                 val = intel_de_read(dev_priv,
1292                                     EDP_PSR2_CTL(intel_dp->psr.transcoder));
1293                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
1294                 val &= ~EDP_PSR2_ENABLE;
1295                 intel_de_write(dev_priv,
1296                                EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
1297         } else {
1298                 val = intel_de_read(dev_priv,
1299                                     EDP_PSR_CTL(intel_dp->psr.transcoder));
1300                 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
1301                 val &= ~EDP_PSR_ENABLE;
1302                 intel_de_write(dev_priv,
1303                                EDP_PSR_CTL(intel_dp->psr.transcoder), val);
1304         }
1305         intel_dp->psr.active = false;
1306 }
1307
1308 static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp)
1309 {
1310         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1311         i915_reg_t psr_status;
1312         u32 psr_status_mask;
1313
1314         if (intel_dp->psr.psr2_enabled) {
1315                 psr_status = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
1316                 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
1317         } else {
1318                 psr_status = EDP_PSR_STATUS(intel_dp->psr.transcoder);
1319                 psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
1320         }
1321
1322         /* Wait till PSR is idle */
1323         if (intel_de_wait_for_clear(dev_priv, psr_status,
1324                                     psr_status_mask, 2000))
1325                 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n");
1326 }
1327
1328 static void intel_psr_disable_locked(struct intel_dp *intel_dp)
1329 {
1330         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1331         enum phy phy = intel_port_to_phy(dev_priv,
1332                                          dp_to_dig_port(intel_dp)->base.port);
1333
1334         lockdep_assert_held(&intel_dp->psr.lock);
1335
1336         if (!intel_dp->psr.enabled)
1337                 return;
1338
1339         drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n",
1340                     intel_dp->psr.psr2_enabled ? "2" : "1");
1341
1342         intel_psr_exit(intel_dp);
1343         intel_psr_wait_exit_locked(intel_dp);
1344
1345         /* Wa_1408330847 */
1346         if (intel_dp->psr.psr2_sel_fetch_enabled &&
1347             IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1348                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1349                              DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
1350
1351         if (intel_dp->psr.psr2_enabled) {
1352                 /* Wa_16011168373:adl-p */
1353                 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
1354                         intel_de_rmw(dev_priv,
1355                                      TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
1356                                      TRANS_SET_CONTEXT_LATENCY_MASK, 0);
1357
1358                 /* Wa_16012604467:adlp */
1359                 if (IS_ALDERLAKE_P(dev_priv))
1360                         intel_de_rmw(dev_priv, CLKGATE_DIS_MISC,
1361                                      CLKGATE_DIS_MISC_DMASC_GATING_DIS, 0);
1362
1363                 /* Wa_16013835468:tgl[b0+], dg1 */
1364                 if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER) ||
1365                     IS_DG1(dev_priv))
1366                         intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
1367                                      wa_16013835468_bit_get(intel_dp), 0);
1368         }
1369
1370         intel_snps_phy_update_psr_power_state(dev_priv, phy, false);
1371
1372         /* Disable PSR on Sink */
1373         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);
1374
1375         if (intel_dp->psr.psr2_enabled)
1376                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0);
1377
1378         intel_dp->psr.enabled = false;
1379         intel_dp->psr.psr2_enabled = false;
1380         intel_dp->psr.psr2_sel_fetch_enabled = false;
1381         intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
1382 }
1383
1384 /**
1385  * intel_psr_disable - Disable PSR
1386  * @intel_dp: Intel DP
1387  * @old_crtc_state: old CRTC state
1388  *
1389  * This function needs to be called before disabling pipe.
1390  */
1391 void intel_psr_disable(struct intel_dp *intel_dp,
1392                        const struct intel_crtc_state *old_crtc_state)
1393 {
1394         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1395
1396         if (!old_crtc_state->has_psr)
1397                 return;
1398
1399         if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp)))
1400                 return;
1401
1402         mutex_lock(&intel_dp->psr.lock);
1403
1404         intel_psr_disable_locked(intel_dp);
1405
1406         mutex_unlock(&intel_dp->psr.lock);
1407         cancel_work_sync(&intel_dp->psr.work);
1408         cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
1409 }
1410
1411 /**
1412  * intel_psr_pause - Pause PSR
1413  * @intel_dp: Intel DP
1414  *
1415  * This function need to be called after enabling psr.
1416  */
1417 void intel_psr_pause(struct intel_dp *intel_dp)
1418 {
1419         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1420         struct intel_psr *psr = &intel_dp->psr;
1421
1422         if (!CAN_PSR(intel_dp))
1423                 return;
1424
1425         mutex_lock(&psr->lock);
1426
1427         if (!psr->enabled) {
1428                 mutex_unlock(&psr->lock);
1429                 return;
1430         }
1431
1432         /* If we ever hit this, we will need to add refcount to pause/resume */
1433         drm_WARN_ON(&dev_priv->drm, psr->paused);
1434
1435         intel_psr_exit(intel_dp);
1436         intel_psr_wait_exit_locked(intel_dp);
1437         psr->paused = true;
1438
1439         mutex_unlock(&psr->lock);
1440
1441         cancel_work_sync(&psr->work);
1442         cancel_delayed_work_sync(&psr->dc3co_work);
1443 }
1444
1445 /**
1446  * intel_psr_resume - Resume PSR
1447  * @intel_dp: Intel DP
1448  *
1449  * This function need to be called after pausing psr.
1450  */
1451 void intel_psr_resume(struct intel_dp *intel_dp)
1452 {
1453         struct intel_psr *psr = &intel_dp->psr;
1454
1455         if (!CAN_PSR(intel_dp))
1456                 return;
1457
1458         mutex_lock(&psr->lock);
1459
1460         if (!psr->paused)
1461                 goto unlock;
1462
1463         psr->paused = false;
1464         intel_psr_activate(intel_dp);
1465
1466 unlock:
1467         mutex_unlock(&psr->lock);
1468 }
1469
1470 static u32 man_trk_ctl_enable_bit_get(struct drm_i915_private *dev_priv)
1471 {
1472         return IS_ALDERLAKE_P(dev_priv) ? 0 : PSR2_MAN_TRK_CTL_ENABLE;
1473 }
1474
1475 static u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
1476 {
1477         return IS_ALDERLAKE_P(dev_priv) ?
1478                ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
1479                PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
1480 }
1481
1482 static u32 man_trk_ctl_partial_frame_bit_get(struct drm_i915_private *dev_priv)
1483 {
1484         return IS_ALDERLAKE_P(dev_priv) ?
1485                ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE :
1486                PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE;
1487 }
1488
1489 static u32 man_trk_ctl_continuos_full_frame(struct drm_i915_private *dev_priv)
1490 {
1491         return IS_ALDERLAKE_P(dev_priv) ?
1492                ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME :
1493                PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
1494 }
1495
1496 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
1497 {
1498         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1499
1500         if (intel_dp->psr.psr2_sel_fetch_enabled)
1501                 intel_de_write(dev_priv,
1502                                PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
1503                                man_trk_ctl_enable_bit_get(dev_priv) |
1504                                man_trk_ctl_partial_frame_bit_get(dev_priv) |
1505                                man_trk_ctl_single_full_frame_bit_get(dev_priv));
1506
1507         /*
1508          * Display WA #0884: skl+
1509          * This documented WA for bxt can be safely applied
1510          * broadly so we can force HW tracking to exit PSR
1511          * instead of disabling and re-enabling.
1512          * Workaround tells us to write 0 to CUR_SURFLIVE_A,
1513          * but it makes more sense write to the current active
1514          * pipe.
1515          *
1516          * This workaround do not exist for platforms with display 10 or newer
1517          * but testing proved that it works for up display 13, for newer
1518          * than that testing will be needed.
1519          */
1520         intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
1521 }
1522
1523 void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
1524                                         const struct intel_crtc_state *crtc_state)
1525 {
1526         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1527         enum pipe pipe = plane->pipe;
1528
1529         if (!crtc_state->enable_psr2_sel_fetch)
1530                 return;
1531
1532         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
1533 }
1534
1535 void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
1536                                         const struct intel_crtc_state *crtc_state,
1537                                         const struct intel_plane_state *plane_state,
1538                                         int color_plane)
1539 {
1540         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1541         enum pipe pipe = plane->pipe;
1542         const struct drm_rect *clip;
1543         u32 val;
1544         int x, y;
1545
1546         if (!crtc_state->enable_psr2_sel_fetch)
1547                 return;
1548
1549         if (plane->id == PLANE_CURSOR) {
1550                 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1551                                   plane_state->ctl);
1552                 return;
1553         }
1554
1555         clip = &plane_state->psr2_sel_fetch_area;
1556
1557         val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
1558         val |= plane_state->uapi.dst.x1;
1559         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
1560
1561         x = plane_state->view.color_plane[color_plane].x;
1562
1563         /*
1564          * From Bspec: UV surface Start Y Position = half of Y plane Y
1565          * start position.
1566          */
1567         if (!color_plane)
1568                 y = plane_state->view.color_plane[color_plane].y + clip->y1;
1569         else
1570                 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2;
1571
1572         val = y << 16 | x;
1573
1574         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
1575                           val);
1576
1577         /* Sizes are 0 based */
1578         val = (drm_rect_height(clip) - 1) << 16;
1579         val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
1580         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
1581
1582         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
1583                           PLANE_SEL_FETCH_CTL_ENABLE);
1584 }
1585
1586 void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
1587 {
1588         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1589         struct intel_encoder *encoder;
1590
1591         if (!crtc_state->enable_psr2_sel_fetch)
1592                 return;
1593
1594         for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
1595                                              crtc_state->uapi.encoder_mask) {
1596                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1597
1598                 lockdep_assert_held(&intel_dp->psr.lock);
1599                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled)
1600                         return;
1601                 break;
1602         }
1603
1604         intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
1605                        crtc_state->psr2_man_track_ctl);
1606 }
1607
1608 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
1609                                   struct drm_rect *clip, bool full_update)
1610 {
1611         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1612         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1613         u32 val = man_trk_ctl_enable_bit_get(dev_priv);
1614
1615         /* SF partial frame enable has to be set even on full update */
1616         val |= man_trk_ctl_partial_frame_bit_get(dev_priv);
1617
1618         if (full_update) {
1619                 /*
1620                  * Not applying Wa_14014971508:adlp as we do not support the
1621                  * feature that requires this workaround.
1622                  */
1623                 val |= man_trk_ctl_single_full_frame_bit_get(dev_priv);
1624                 goto exit;
1625         }
1626
1627         if (clip->y1 == -1)
1628                 goto exit;
1629
1630         if (IS_ALDERLAKE_P(dev_priv)) {
1631                 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1);
1632                 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1);
1633         } else {
1634                 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4);
1635
1636                 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1);
1637                 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1);
1638         }
1639 exit:
1640         crtc_state->psr2_man_track_ctl = val;
1641 }
1642
1643 static void clip_area_update(struct drm_rect *overlap_damage_area,
1644                              struct drm_rect *damage_area,
1645                              struct drm_rect *pipe_src)
1646 {
1647         if (!drm_rect_intersect(damage_area, pipe_src))
1648                 return;
1649
1650         if (overlap_damage_area->y1 == -1) {
1651                 overlap_damage_area->y1 = damage_area->y1;
1652                 overlap_damage_area->y2 = damage_area->y2;
1653                 return;
1654         }
1655
1656         if (damage_area->y1 < overlap_damage_area->y1)
1657                 overlap_damage_area->y1 = damage_area->y1;
1658
1659         if (damage_area->y2 > overlap_damage_area->y2)
1660                 overlap_damage_area->y2 = damage_area->y2;
1661 }
1662
1663 static void intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state *crtc_state,
1664                                                 struct drm_rect *pipe_clip)
1665 {
1666         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1667         const u16 y_alignment = crtc_state->su_y_granularity;
1668
1669         pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
1670         if (pipe_clip->y2 % y_alignment)
1671                 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment;
1672
1673         if (IS_ALDERLAKE_P(dev_priv) && crtc_state->dsc.compression_enable)
1674                 drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch alignment with DSC\n");
1675 }
1676
1677 /*
1678  * TODO: Not clear how to handle planes with negative position,
1679  * also planes are not updated if they have a negative X
1680  * position so for now doing a full update in this cases
1681  *
1682  * Plane scaling and rotation is not supported by selective fetch and both
1683  * properties can change without a modeset, so need to be check at every
1684  * atomic commit.
1685  */
1686 static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
1687 {
1688         if (plane_state->uapi.dst.y1 < 0 ||
1689             plane_state->uapi.dst.x1 < 0 ||
1690             plane_state->scaler_id >= 0 ||
1691             plane_state->uapi.rotation != DRM_MODE_ROTATE_0)
1692                 return false;
1693
1694         return true;
1695 }
1696
1697 /*
1698  * Check for pipe properties that is not supported by selective fetch.
1699  *
1700  * TODO: pipe scaling causes a modeset but skl_update_scaler_crtc() is executed
1701  * after intel_psr_compute_config(), so for now keeping PSR2 selective fetch
1702  * enabled and going to the full update path.
1703  */
1704 static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
1705 {
1706         if (crtc_state->scaler_state.scaler_id >= 0)
1707                 return false;
1708
1709         return true;
1710 }
1711
1712 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
1713                                 struct intel_crtc *crtc)
1714 {
1715         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1716         struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1717         struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 };
1718         struct intel_plane_state *new_plane_state, *old_plane_state;
1719         struct intel_plane *plane;
1720         bool full_update = false;
1721         int i, ret;
1722
1723         if (!crtc_state->enable_psr2_sel_fetch)
1724                 return 0;
1725
1726         if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
1727                 full_update = true;
1728                 goto skip_sel_fetch_set_loop;
1729         }
1730
1731         /*
1732          * Calculate minimal selective fetch area of each plane and calculate
1733          * the pipe damaged area.
1734          * In the next loop the plane selective fetch area will actually be set
1735          * using whole pipe damaged area.
1736          */
1737         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1738                                              new_plane_state, i) {
1739                 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
1740                                                       .x2 = INT_MAX };
1741
1742                 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
1743                         continue;
1744
1745                 if (!new_plane_state->uapi.visible &&
1746                     !old_plane_state->uapi.visible)
1747                         continue;
1748
1749                 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
1750                         full_update = true;
1751                         break;
1752                 }
1753
1754                 /*
1755                  * If visibility or plane moved, mark the whole plane area as
1756                  * damaged as it needs to be complete redraw in the new and old
1757                  * position.
1758                  */
1759                 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible ||
1760                     !drm_rect_equals(&new_plane_state->uapi.dst,
1761                                      &old_plane_state->uapi.dst)) {
1762                         if (old_plane_state->uapi.visible) {
1763                                 damaged_area.y1 = old_plane_state->uapi.dst.y1;
1764                                 damaged_area.y2 = old_plane_state->uapi.dst.y2;
1765                                 clip_area_update(&pipe_clip, &damaged_area,
1766                                                  &crtc_state->pipe_src);
1767                         }
1768
1769                         if (new_plane_state->uapi.visible) {
1770                                 damaged_area.y1 = new_plane_state->uapi.dst.y1;
1771                                 damaged_area.y2 = new_plane_state->uapi.dst.y2;
1772                                 clip_area_update(&pipe_clip, &damaged_area,
1773                                                  &crtc_state->pipe_src);
1774                         }
1775                         continue;
1776                 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
1777                         /* If alpha changed mark the whole plane area as damaged */
1778                         damaged_area.y1 = new_plane_state->uapi.dst.y1;
1779                         damaged_area.y2 = new_plane_state->uapi.dst.y2;
1780                         clip_area_update(&pipe_clip, &damaged_area,
1781                                          &crtc_state->pipe_src);
1782                         continue;
1783                 }
1784
1785                 src = drm_plane_state_src(&new_plane_state->uapi);
1786                 drm_rect_fp_to_int(&src, &src);
1787
1788                 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi,
1789                                                      &new_plane_state->uapi, &damaged_area))
1790                         continue;
1791
1792                 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1;
1793                 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1;
1794                 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1;
1795                 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1;
1796
1797                 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src);
1798         }
1799
1800         /*
1801          * TODO: For now we are just using full update in case
1802          * selective fetch area calculation fails. To optimize this we
1803          * should identify cases where this happens and fix the area
1804          * calculation for those.
1805          */
1806         if (pipe_clip.y1 == -1) {
1807                 drm_info_once(&dev_priv->drm,
1808                               "Selective fetch area calculation failed in pipe %c\n",
1809                               pipe_name(crtc->pipe));
1810                 full_update = true;
1811         }
1812
1813         if (full_update)
1814                 goto skip_sel_fetch_set_loop;
1815
1816         ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
1817         if (ret)
1818                 return ret;
1819
1820         intel_psr2_sel_fetch_pipe_alignment(crtc_state, &pipe_clip);
1821
1822         /*
1823          * Now that we have the pipe damaged area check if it intersect with
1824          * every plane, if it does set the plane selective fetch area.
1825          */
1826         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
1827                                              new_plane_state, i) {
1828                 struct drm_rect *sel_fetch_area, inter;
1829                 struct intel_plane *linked = new_plane_state->planar_linked_plane;
1830
1831                 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc ||
1832                     !new_plane_state->uapi.visible)
1833                         continue;
1834
1835                 inter = pipe_clip;
1836                 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
1837                         continue;
1838
1839                 if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
1840                         full_update = true;
1841                         break;
1842                 }
1843
1844                 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
1845                 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
1846                 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
1847                 crtc_state->update_planes |= BIT(plane->id);
1848
1849                 /*
1850                  * Sel_fetch_area is calculated for UV plane. Use
1851                  * same area for Y plane as well.
1852                  */
1853                 if (linked) {
1854                         struct intel_plane_state *linked_new_plane_state;
1855                         struct drm_rect *linked_sel_fetch_area;
1856
1857                         linked_new_plane_state = intel_atomic_get_plane_state(state, linked);
1858                         if (IS_ERR(linked_new_plane_state))
1859                                 return PTR_ERR(linked_new_plane_state);
1860
1861                         linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area;
1862                         linked_sel_fetch_area->y1 = sel_fetch_area->y1;
1863                         linked_sel_fetch_area->y2 = sel_fetch_area->y2;
1864                         crtc_state->update_planes |= BIT(linked->id);
1865                 }
1866         }
1867
1868 skip_sel_fetch_set_loop:
1869         psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update);
1870         return 0;
1871 }
1872
1873 void intel_psr_pre_plane_update(struct intel_atomic_state *state,
1874                                 struct intel_crtc *crtc)
1875 {
1876         struct drm_i915_private *i915 = to_i915(state->base.dev);
1877         const struct intel_crtc_state *old_crtc_state =
1878                 intel_atomic_get_old_crtc_state(state, crtc);
1879         const struct intel_crtc_state *new_crtc_state =
1880                 intel_atomic_get_new_crtc_state(state, crtc);
1881         struct intel_encoder *encoder;
1882
1883         if (!HAS_PSR(i915))
1884                 return;
1885
1886         for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
1887                                              old_crtc_state->uapi.encoder_mask) {
1888                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1889                 struct intel_psr *psr = &intel_dp->psr;
1890                 bool needs_to_disable = false;
1891
1892                 mutex_lock(&psr->lock);
1893
1894                 /*
1895                  * Reasons to disable:
1896                  * - PSR disabled in new state
1897                  * - All planes will go inactive
1898                  * - Changing between PSR versions
1899                  */
1900                 needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
1901                 needs_to_disable |= !new_crtc_state->has_psr;
1902                 needs_to_disable |= !new_crtc_state->active_planes;
1903                 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
1904
1905                 if (psr->enabled && needs_to_disable)
1906                         intel_psr_disable_locked(intel_dp);
1907
1908                 mutex_unlock(&psr->lock);
1909         }
1910 }
1911
1912 static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
1913                                          const struct intel_crtc_state *crtc_state)
1914 {
1915         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1916         struct intel_encoder *encoder;
1917
1918         if (!crtc_state->has_psr)
1919                 return;
1920
1921         for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
1922                                              crtc_state->uapi.encoder_mask) {
1923                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1924                 struct intel_psr *psr = &intel_dp->psr;
1925
1926                 mutex_lock(&psr->lock);
1927
1928                 if (psr->sink_not_reliable)
1929                         goto exit;
1930
1931                 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes);
1932
1933                 /* Only enable if there is active planes */
1934                 if (!psr->enabled && crtc_state->active_planes)
1935                         intel_psr_enable_locked(intel_dp, crtc_state);
1936
1937                 /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
1938                 if (crtc_state->crc_enabled && psr->enabled)
1939                         psr_force_hw_tracking_exit(intel_dp);
1940
1941 exit:
1942                 mutex_unlock(&psr->lock);
1943         }
1944 }
1945
1946 void intel_psr_post_plane_update(const struct intel_atomic_state *state)
1947 {
1948         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1949         struct intel_crtc_state *crtc_state;
1950         struct intel_crtc *crtc;
1951         int i;
1952
1953         if (!HAS_PSR(dev_priv))
1954                 return;
1955
1956         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)
1957                 _intel_psr_post_plane_update(state, crtc_state);
1958 }
1959
1960 static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
1961 {
1962         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1963
1964         /*
1965          * Any state lower than EDP_PSR2_STATUS_STATE_DEEP_SLEEP is enough.
1966          * As all higher states has bit 4 of PSR2 state set we can just wait for
1967          * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared.
1968          */
1969         return intel_de_wait_for_clear(dev_priv,
1970                                        EDP_PSR2_STATUS(intel_dp->psr.transcoder),
1971                                        EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50);
1972 }
1973
1974 static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
1975 {
1976         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1977
1978         /*
1979          * From bspec: Panel Self Refresh (BDW+)
1980          * Max. time for PSR to idle = Inverse of the refresh rate + 6 ms of
1981          * exit training time + 1.5 ms of aux channel handshake. 50 ms is
1982          * defensive enough to cover everything.
1983          */
1984         return intel_de_wait_for_clear(dev_priv,
1985                                        EDP_PSR_STATUS(intel_dp->psr.transcoder),
1986                                        EDP_PSR_STATUS_STATE_MASK, 50);
1987 }
1988
1989 /**
1990  * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
1991  * @new_crtc_state: new CRTC state
1992  *
1993  * This function is expected to be called from pipe_update_start() where it is
1994  * not expected to race with PSR enable or disable.
1995  */
1996 void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)
1997 {
1998         struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
1999         struct intel_encoder *encoder;
2000
2001         if (!new_crtc_state->has_psr)
2002                 return;
2003
2004         for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
2005                                              new_crtc_state->uapi.encoder_mask) {
2006                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2007                 int ret;
2008
2009                 lockdep_assert_held(&intel_dp->psr.lock);
2010
2011                 if (!intel_dp->psr.enabled)
2012                         continue;
2013
2014                 if (intel_dp->psr.psr2_enabled)
2015                         ret = _psr2_ready_for_pipe_update_locked(intel_dp);
2016                 else
2017                         ret = _psr1_ready_for_pipe_update_locked(intel_dp);
2018
2019                 if (ret)
2020                         drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
2021         }
2022 }
2023
2024 static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp)
2025 {
2026         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2027         i915_reg_t reg;
2028         u32 mask;
2029         int err;
2030
2031         if (!intel_dp->psr.enabled)
2032                 return false;
2033
2034         if (intel_dp->psr.psr2_enabled) {
2035                 reg = EDP_PSR2_STATUS(intel_dp->psr.transcoder);
2036                 mask = EDP_PSR2_STATUS_STATE_MASK;
2037         } else {
2038                 reg = EDP_PSR_STATUS(intel_dp->psr.transcoder);
2039                 mask = EDP_PSR_STATUS_STATE_MASK;
2040         }
2041
2042         mutex_unlock(&intel_dp->psr.lock);
2043
2044         err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
2045         if (err)
2046                 drm_err(&dev_priv->drm,
2047                         "Timed out waiting for PSR Idle for re-enable\n");
2048
2049         /* After the unlocked wait, verify that PSR is still wanted! */
2050         mutex_lock(&intel_dp->psr.lock);
2051         return err == 0 && intel_dp->psr.enabled;
2052 }
2053
2054 static int intel_psr_fastset_force(struct drm_i915_private *dev_priv)
2055 {
2056         struct drm_connector_list_iter conn_iter;
2057         struct drm_device *dev = &dev_priv->drm;
2058         struct drm_modeset_acquire_ctx ctx;
2059         struct drm_atomic_state *state;
2060         struct drm_connector *conn;
2061         int err = 0;
2062
2063         state = drm_atomic_state_alloc(dev);
2064         if (!state)
2065                 return -ENOMEM;
2066
2067         drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
2068         state->acquire_ctx = &ctx;
2069
2070 retry:
2071
2072         drm_connector_list_iter_begin(dev, &conn_iter);
2073         drm_for_each_connector_iter(conn, &conn_iter) {
2074                 struct drm_connector_state *conn_state;
2075                 struct drm_crtc_state *crtc_state;
2076
2077                 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP)
2078                         continue;
2079
2080                 conn_state = drm_atomic_get_connector_state(state, conn);
2081                 if (IS_ERR(conn_state)) {
2082                         err = PTR_ERR(conn_state);
2083                         break;
2084                 }
2085
2086                 if (!conn_state->crtc)
2087                         continue;
2088
2089                 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc);
2090                 if (IS_ERR(crtc_state)) {
2091                         err = PTR_ERR(crtc_state);
2092                         break;
2093                 }
2094
2095                 /* Mark mode as changed to trigger a pipe->update() */
2096                 crtc_state->mode_changed = true;
2097         }
2098         drm_connector_list_iter_end(&conn_iter);
2099
2100         if (err == 0)
2101                 err = drm_atomic_commit(state);
2102
2103         if (err == -EDEADLK) {
2104                 drm_atomic_state_clear(state);
2105                 err = drm_modeset_backoff(&ctx);
2106                 if (!err)
2107                         goto retry;
2108         }
2109
2110         drm_modeset_drop_locks(&ctx);
2111         drm_modeset_acquire_fini(&ctx);
2112         drm_atomic_state_put(state);
2113
2114         return err;
2115 }
2116
2117 int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val)
2118 {
2119         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2120         const u32 mode = val & I915_PSR_DEBUG_MODE_MASK;
2121         u32 old_mode;
2122         int ret;
2123
2124         if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
2125             mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
2126                 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val);
2127                 return -EINVAL;
2128         }
2129
2130         ret = mutex_lock_interruptible(&intel_dp->psr.lock);
2131         if (ret)
2132                 return ret;
2133
2134         old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;
2135         intel_dp->psr.debug = val;
2136
2137         /*
2138          * Do it right away if it's already enabled, otherwise it will be done
2139          * when enabling the source.
2140          */
2141         if (intel_dp->psr.enabled)
2142                 psr_irq_control(intel_dp);
2143
2144         mutex_unlock(&intel_dp->psr.lock);
2145
2146         if (old_mode != mode)
2147                 ret = intel_psr_fastset_force(dev_priv);
2148
2149         return ret;
2150 }
2151
2152 static void intel_psr_handle_irq(struct intel_dp *intel_dp)
2153 {
2154         struct intel_psr *psr = &intel_dp->psr;
2155
2156         intel_psr_disable_locked(intel_dp);
2157         psr->sink_not_reliable = true;
2158         /* let's make sure that sink is awaken */
2159         drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
2160 }
2161
2162 static void intel_psr_work(struct work_struct *work)
2163 {
2164         struct intel_dp *intel_dp =
2165                 container_of(work, typeof(*intel_dp), psr.work);
2166
2167         mutex_lock(&intel_dp->psr.lock);
2168
2169         if (!intel_dp->psr.enabled)
2170                 goto unlock;
2171
2172         if (READ_ONCE(intel_dp->psr.irq_aux_error))
2173                 intel_psr_handle_irq(intel_dp);
2174
2175         /*
2176          * We have to make sure PSR is ready for re-enable
2177          * otherwise it keeps disabled until next full enable/disable cycle.
2178          * PSR might take some time to get fully disabled
2179          * and be ready for re-enable.
2180          */
2181         if (!__psr_wait_for_idle_locked(intel_dp))
2182                 goto unlock;
2183
2184         /*
2185          * The delayed work can race with an invalidate hence we need to
2186          * recheck. Since psr_flush first clears this and then reschedules we
2187          * won't ever miss a flush when bailing out here.
2188          */
2189         if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)
2190                 goto unlock;
2191
2192         intel_psr_activate(intel_dp);
2193 unlock:
2194         mutex_unlock(&intel_dp->psr.lock);
2195 }
2196
2197 static void _psr_invalidate_handle(struct intel_dp *intel_dp)
2198 {
2199         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2200
2201         if (intel_dp->psr.psr2_sel_fetch_enabled) {
2202                 u32 val;
2203
2204                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
2205                         /* Send one update otherwise lag is observed in screen */
2206                         intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2207                         return;
2208                 }
2209
2210                 val = man_trk_ctl_enable_bit_get(dev_priv) |
2211                       man_trk_ctl_partial_frame_bit_get(dev_priv) |
2212                       man_trk_ctl_continuos_full_frame(dev_priv);
2213                 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), val);
2214                 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2215                 intel_dp->psr.psr2_sel_fetch_cff_enabled = true;
2216         } else {
2217                 intel_psr_exit(intel_dp);
2218         }
2219 }
2220
2221 /**
2222  * intel_psr_invalidate - Invalidate PSR
2223  * @dev_priv: i915 device
2224  * @frontbuffer_bits: frontbuffer plane tracking bits
2225  * @origin: which operation caused the invalidate
2226  *
2227  * Since the hardware frontbuffer tracking has gaps we need to integrate
2228  * with the software frontbuffer tracking. This function gets called every
2229  * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
2230  * disabled if the frontbuffer mask contains a buffer relevant to PSR.
2231  *
2232  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
2233  */
2234 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
2235                           unsigned frontbuffer_bits, enum fb_op_origin origin)
2236 {
2237         struct intel_encoder *encoder;
2238
2239         if (origin == ORIGIN_FLIP)
2240                 return;
2241
2242         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2243                 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2244                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2245
2246                 mutex_lock(&intel_dp->psr.lock);
2247                 if (!intel_dp->psr.enabled) {
2248                         mutex_unlock(&intel_dp->psr.lock);
2249                         continue;
2250                 }
2251
2252                 pipe_frontbuffer_bits &=
2253                         INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2254                 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;
2255
2256                 if (pipe_frontbuffer_bits)
2257                         _psr_invalidate_handle(intel_dp);
2258
2259                 mutex_unlock(&intel_dp->psr.lock);
2260         }
2261 }
2262 /*
2263  * When we will be completely rely on PSR2 S/W tracking in future,
2264  * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
2265  * event also therefore tgl_dc3co_flush_locked() require to be changed
2266  * accordingly in future.
2267  */
2268 static void
2269 tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
2270                        enum fb_op_origin origin)
2271 {
2272         if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||
2273             !intel_dp->psr.active)
2274                 return;
2275
2276         /*
2277          * At every frontbuffer flush flip event modified delay of delayed work,
2278          * when delayed work schedules that means display has been idle.
2279          */
2280         if (!(frontbuffer_bits &
2281             INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
2282                 return;
2283
2284         tgl_psr2_enable_dc3co(intel_dp);
2285         mod_delayed_work(system_wq, &intel_dp->psr.dc3co_work,
2286                          intel_dp->psr.dc3co_exit_delay);
2287 }
2288
2289 static void _psr_flush_handle(struct intel_dp *intel_dp)
2290 {
2291         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2292
2293         if (intel_dp->psr.psr2_sel_fetch_enabled) {
2294                 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {
2295                         /* can we turn CFF off? */
2296                         if (intel_dp->psr.busy_frontbuffer_bits == 0) {
2297                                 u32 val = man_trk_ctl_enable_bit_get(dev_priv) |
2298                                           man_trk_ctl_partial_frame_bit_get(dev_priv) |
2299                                           man_trk_ctl_single_full_frame_bit_get(dev_priv);
2300
2301                                 /*
2302                                  * turn continuous full frame off and do a single
2303                                  * full frame
2304                                  */
2305                                 intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
2306                                                val);
2307                                 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);
2308                                 intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
2309                         }
2310                 } else {
2311                         /*
2312                          * continuous full frame is disabled, only a single full
2313                          * frame is required
2314                          */
2315                         psr_force_hw_tracking_exit(intel_dp);
2316                 }
2317         } else {
2318                 psr_force_hw_tracking_exit(intel_dp);
2319
2320                 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)
2321                         schedule_work(&intel_dp->psr.work);
2322         }
2323 }
2324
2325 /**
2326  * intel_psr_flush - Flush PSR
2327  * @dev_priv: i915 device
2328  * @frontbuffer_bits: frontbuffer plane tracking bits
2329  * @origin: which operation caused the flush
2330  *
2331  * Since the hardware frontbuffer tracking has gaps we need to integrate
2332  * with the software frontbuffer tracking. This function gets called every
2333  * time frontbuffer rendering has completed and flushed out to memory. PSR
2334  * can be enabled again if no other frontbuffer relevant to PSR is dirty.
2335  *
2336  * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
2337  */
2338 void intel_psr_flush(struct drm_i915_private *dev_priv,
2339                      unsigned frontbuffer_bits, enum fb_op_origin origin)
2340 {
2341         struct intel_encoder *encoder;
2342
2343         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2344                 unsigned int pipe_frontbuffer_bits = frontbuffer_bits;
2345                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2346
2347                 mutex_lock(&intel_dp->psr.lock);
2348                 if (!intel_dp->psr.enabled) {
2349                         mutex_unlock(&intel_dp->psr.lock);
2350                         continue;
2351                 }
2352
2353                 pipe_frontbuffer_bits &=
2354                         INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);
2355                 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;
2356
2357                 /*
2358                  * If the PSR is paused by an explicit intel_psr_paused() call,
2359                  * we have to ensure that the PSR is not activated until
2360                  * intel_psr_resume() is called.
2361                  */
2362                 if (intel_dp->psr.paused)
2363                         goto unlock;
2364
2365                 if (origin == ORIGIN_FLIP ||
2366                     (origin == ORIGIN_CURSOR_UPDATE &&
2367                      !intel_dp->psr.psr2_sel_fetch_enabled)) {
2368                         tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
2369                         goto unlock;
2370                 }
2371
2372                 if (pipe_frontbuffer_bits == 0)
2373                         goto unlock;
2374
2375                 /* By definition flush = invalidate + flush */
2376                 _psr_flush_handle(intel_dp);
2377 unlock:
2378                 mutex_unlock(&intel_dp->psr.lock);
2379         }
2380 }
2381
2382 /**
2383  * intel_psr_init - Init basic PSR work and mutex.
2384  * @intel_dp: Intel DP
2385  *
2386  * This function is called after the initializing connector.
2387  * (the initializing of connector treats the handling of connector capabilities)
2388  * And it initializes basic PSR stuff for each DP Encoder.
2389  */
2390 void intel_psr_init(struct intel_dp *intel_dp)
2391 {
2392         struct intel_connector *connector = intel_dp->attached_connector;
2393         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2394         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2395
2396         if (!HAS_PSR(dev_priv))
2397                 return;
2398
2399         /*
2400          * HSW spec explicitly says PSR is tied to port A.
2401          * BDW+ platforms have a instance of PSR registers per transcoder but
2402          * BDW, GEN9 and GEN11 are not validated by HW team in other transcoder
2403          * than eDP one.
2404          * For now it only supports one instance of PSR for BDW, GEN9 and GEN11.
2405          * So lets keep it hardcoded to PORT_A for BDW, GEN9 and GEN11.
2406          * But GEN12 supports a instance of PSR registers per transcoder.
2407          */
2408         if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) {
2409                 drm_dbg_kms(&dev_priv->drm,
2410                             "PSR condition failed: Port not supported\n");
2411                 return;
2412         }
2413
2414         intel_dp->psr.source_support = true;
2415
2416         /* Set link_standby x link_off defaults */
2417         if (DISPLAY_VER(dev_priv) < 12)
2418                 /* For new platforms up to TGL let's respect VBT back again */
2419                 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
2420
2421         INIT_WORK(&intel_dp->psr.work, intel_psr_work);
2422         INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
2423         mutex_init(&intel_dp->psr.lock);
2424 }
2425
2426 static int psr_get_status_and_error_status(struct intel_dp *intel_dp,
2427                                            u8 *status, u8 *error_status)
2428 {
2429         struct drm_dp_aux *aux = &intel_dp->aux;
2430         int ret;
2431
2432         ret = drm_dp_dpcd_readb(aux, DP_PSR_STATUS, status);
2433         if (ret != 1)
2434                 return ret;
2435
2436         ret = drm_dp_dpcd_readb(aux, DP_PSR_ERROR_STATUS, error_status);
2437         if (ret != 1)
2438                 return ret;
2439
2440         *status = *status & DP_PSR_SINK_STATE_MASK;
2441
2442         return 0;
2443 }
2444
2445 static void psr_alpm_check(struct intel_dp *intel_dp)
2446 {
2447         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2448         struct drm_dp_aux *aux = &intel_dp->aux;
2449         struct intel_psr *psr = &intel_dp->psr;
2450         u8 val;
2451         int r;
2452
2453         if (!psr->psr2_enabled)
2454                 return;
2455
2456         r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);
2457         if (r != 1) {
2458                 drm_err(&dev_priv->drm, "Error reading ALPM status\n");
2459                 return;
2460         }
2461
2462         if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) {
2463                 intel_psr_disable_locked(intel_dp);
2464                 psr->sink_not_reliable = true;
2465                 drm_dbg_kms(&dev_priv->drm,
2466                             "ALPM lock timeout error, disabling PSR\n");
2467
2468                 /* Clearing error */
2469                 drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);
2470         }
2471 }
2472
2473 static void psr_capability_changed_check(struct intel_dp *intel_dp)
2474 {
2475         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2476         struct intel_psr *psr = &intel_dp->psr;
2477         u8 val;
2478         int r;
2479
2480         r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);
2481         if (r != 1) {
2482                 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n");
2483                 return;
2484         }
2485
2486         if (val & DP_PSR_CAPS_CHANGE) {
2487                 intel_psr_disable_locked(intel_dp);
2488                 psr->sink_not_reliable = true;
2489                 drm_dbg_kms(&dev_priv->drm,
2490                             "Sink PSR capability changed, disabling PSR\n");
2491
2492                 /* Clearing it */
2493                 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);
2494         }
2495 }
2496
2497 void intel_psr_short_pulse(struct intel_dp *intel_dp)
2498 {
2499         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2500         struct intel_psr *psr = &intel_dp->psr;
2501         u8 status, error_status;
2502         const u8 errors = DP_PSR_RFB_STORAGE_ERROR |
2503                           DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR |
2504                           DP_PSR_LINK_CRC_ERROR;
2505
2506         if (!CAN_PSR(intel_dp))
2507                 return;
2508
2509         mutex_lock(&psr->lock);
2510
2511         if (!psr->enabled)
2512                 goto exit;
2513
2514         if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) {
2515                 drm_err(&dev_priv->drm,
2516                         "Error reading PSR status or error status\n");
2517                 goto exit;
2518         }
2519
2520         if (status == DP_PSR_SINK_INTERNAL_ERROR || (error_status & errors)) {
2521                 intel_psr_disable_locked(intel_dp);
2522                 psr->sink_not_reliable = true;
2523         }
2524
2525         if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status)
2526                 drm_dbg_kms(&dev_priv->drm,
2527                             "PSR sink internal error, disabling PSR\n");
2528         if (error_status & DP_PSR_RFB_STORAGE_ERROR)
2529                 drm_dbg_kms(&dev_priv->drm,
2530                             "PSR RFB storage error, disabling PSR\n");
2531         if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
2532                 drm_dbg_kms(&dev_priv->drm,
2533                             "PSR VSC SDP uncorrectable error, disabling PSR\n");
2534         if (error_status & DP_PSR_LINK_CRC_ERROR)
2535                 drm_dbg_kms(&dev_priv->drm,
2536                             "PSR Link CRC error, disabling PSR\n");
2537
2538         if (error_status & ~errors)
2539                 drm_err(&dev_priv->drm,
2540                         "PSR_ERROR_STATUS unhandled errors %x\n",
2541                         error_status & ~errors);
2542         /* clear status register */
2543         drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);
2544
2545         psr_alpm_check(intel_dp);
2546         psr_capability_changed_check(intel_dp);
2547
2548 exit:
2549         mutex_unlock(&psr->lock);
2550 }
2551
2552 bool intel_psr_enabled(struct intel_dp *intel_dp)
2553 {
2554         bool ret;
2555
2556         if (!CAN_PSR(intel_dp))
2557                 return false;
2558
2559         mutex_lock(&intel_dp->psr.lock);
2560         ret = intel_dp->psr.enabled;
2561         mutex_unlock(&intel_dp->psr.lock);
2562
2563         return ret;
2564 }
2565
2566 /**
2567  * intel_psr_lock - grab PSR lock
2568  * @crtc_state: the crtc state
2569  *
2570  * This is initially meant to be used by around CRTC update, when
2571  * vblank sensitive registers are updated and we need grab the lock
2572  * before it to avoid vblank evasion.
2573  */
2574 void intel_psr_lock(const struct intel_crtc_state *crtc_state)
2575 {
2576         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2577         struct intel_encoder *encoder;
2578
2579         if (!crtc_state->has_psr)
2580                 return;
2581
2582         for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
2583                                              crtc_state->uapi.encoder_mask) {
2584                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2585
2586                 mutex_lock(&intel_dp->psr.lock);
2587                 break;
2588         }
2589 }
2590
2591 /**
2592  * intel_psr_unlock - release PSR lock
2593  * @crtc_state: the crtc state
2594  *
2595  * Release the PSR lock that was held during pipe update.
2596  */
2597 void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
2598 {
2599         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2600         struct intel_encoder *encoder;
2601
2602         if (!crtc_state->has_psr)
2603                 return;
2604
2605         for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
2606                                              crtc_state->uapi.encoder_mask) {
2607                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2608
2609                 mutex_unlock(&intel_dp->psr.lock);
2610                 break;
2611         }
2612 }