drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <[email protected]>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Jesse Barnes <[email protected]>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_hdcp_helper.h>
  36 #include <drm/display/drm_hdmi_helper.h>
  37 #include <drm/display/drm_scdc_helper.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_crtc.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/intel_lpe_audio.h>
  42
  43 #include "i915_debugfs.h"
  44 #include "i915_drv.h"
  45 #include "intel_atomic.h"
  46 #include "intel_connector.h"
  47 #include "intel_ddi.h"
  48 #include "intel_de.h"
  49 #include "intel_display_types.h"
  50 #include "intel_dp.h"
  51 #include "intel_gmbus.h"
  52 #include "intel_hdcp.h"
  53 #include "intel_hdcp_regs.h"
  54 #include "intel_hdmi.h"
  55 #include "intel_lspcon.h"
  56 #include "intel_panel.h"
  57 #include "intel_snps_phy.h"
  58
  59 static struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
  60 {
  61         return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
  62 }
  63
  64 static void
  65 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  66 {
  67         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
  68         u32 enabled_bits;
  69
  70         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  71
  72         drm_WARN(&dev_priv->drm,
  73                  intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
  74                  "HDMI port enabled, expecting disabled\n");
  75 }
  76
  77 static void
  78 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  79                                      enum transcoder cpu_transcoder)
  80 {
  81         drm_WARN(&dev_priv->drm,
  82                  intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  83                  TRANS_DDI_FUNC_ENABLE,
  84                  "HDMI transcoder function enabled, expecting disabled\n");
  85 }
  86
  87 static u32 g4x_infoframe_index(unsigned int type)
  88 {
  89         switch (type) {
  90         case HDMI_PACKET_TYPE_GAMUT_METADATA:
  91                 return VIDEO_DIP_SELECT_GAMUT;
  92         case HDMI_INFOFRAME_TYPE_AVI:
  93                 return VIDEO_DIP_SELECT_AVI;
  94         case HDMI_INFOFRAME_TYPE_SPD:
  95                 return VIDEO_DIP_SELECT_SPD;
  96         case HDMI_INFOFRAME_TYPE_VENDOR:
  97                 return VIDEO_DIP_SELECT_VENDOR;
  98         default:
  99                 MISSING_CASE(type);
 100                 return 0;
 101         }
 102 }
 103
 104 static u32 g4x_infoframe_enable(unsigned int type)
 105 {
 106         switch (type) {
 107         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 108                 return VIDEO_DIP_ENABLE_GCP;
 109         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 110                 return VIDEO_DIP_ENABLE_GAMUT;
 111         case DP_SDP_VSC:
 112                 return 0;
 113         case HDMI_INFOFRAME_TYPE_AVI:
 114                 return VIDEO_DIP_ENABLE_AVI;
 115         case HDMI_INFOFRAME_TYPE_SPD:
 116                 return VIDEO_DIP_ENABLE_SPD;
 117         case HDMI_INFOFRAME_TYPE_VENDOR:
 118                 return VIDEO_DIP_ENABLE_VENDOR;
 119         case HDMI_INFOFRAME_TYPE_DRM:
 120                 return 0;
 121         default:
 122                 MISSING_CASE(type);
 123                 return 0;
 124         }
 125 }
 126
 127 static u32 hsw_infoframe_enable(unsigned int type)
 128 {
 129         switch (type) {
 130         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 131                 return VIDEO_DIP_ENABLE_GCP_HSW;
 132         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 133                 return VIDEO_DIP_ENABLE_GMP_HSW;
 134         case DP_SDP_VSC:
 135                 return VIDEO_DIP_ENABLE_VSC_HSW;
 136         case DP_SDP_PPS:
 137                 return VDIP_ENABLE_PPS;
 138         case HDMI_INFOFRAME_TYPE_AVI:
 139                 return VIDEO_DIP_ENABLE_AVI_HSW;
 140         case HDMI_INFOFRAME_TYPE_SPD:
 141                 return VIDEO_DIP_ENABLE_SPD_HSW;
 142         case HDMI_INFOFRAME_TYPE_VENDOR:
 143                 return VIDEO_DIP_ENABLE_VS_HSW;
 144         case HDMI_INFOFRAME_TYPE_DRM:
 145                 return VIDEO_DIP_ENABLE_DRM_GLK;
 146         default:
 147                 MISSING_CASE(type);
 148                 return 0;
 149         }
 150 }
 151
 152 static i915_reg_t
 153 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 154                  enum transcoder cpu_transcoder,
 155                  unsigned int type,
 156                  int i)
 157 {
 158         switch (type) {
 159         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 160                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 161         case DP_SDP_VSC:
 162                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 163         case DP_SDP_PPS:
 164                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 165         case HDMI_INFOFRAME_TYPE_AVI:
 166                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 167         case HDMI_INFOFRAME_TYPE_SPD:
 168                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 169         case HDMI_INFOFRAME_TYPE_VENDOR:
 170                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 171         case HDMI_INFOFRAME_TYPE_DRM:
 172                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 173         default:
 174                 MISSING_CASE(type);
 175                 return INVALID_MMIO_REG;
 176         }
 177 }
 178
 179 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
 180                              unsigned int type)
 181 {
 182         switch (type) {
 183         case DP_SDP_VSC:
 184                 return VIDEO_DIP_VSC_DATA_SIZE;
 185         case DP_SDP_PPS:
 186                 return VIDEO_DIP_PPS_DATA_SIZE;
 187         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 188                 if (DISPLAY_VER(dev_priv) >= 11)
 189                         return VIDEO_DIP_GMP_DATA_SIZE;
 190                 else
 191                         return VIDEO_DIP_DATA_SIZE;
 192         default:
 193                 return VIDEO_DIP_DATA_SIZE;
 194         }
 195 }
 196
 197 static void g4x_write_infoframe(struct intel_encoder *encoder,
 198                                 const struct intel_crtc_state *crtc_state,
 199                                 unsigned int type,
 200                                 const void *frame, ssize_t len)
 201 {
 202         const u32 *data = frame;
 203         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 204         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 205         int i;
 206
 207         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 208                  "Writing DIP with CTL reg disabled\n");
 209
 210         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 211         val |= g4x_infoframe_index(type);
 212
 213         val &= ~g4x_infoframe_enable(type);
 214
 215         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 216
 217         for (i = 0; i < len; i += 4) {
 218                 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
 219                 data++;
 220         }
 221         /* Write every possible data byte to force correct ECC calculation. */
 222         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 223                 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
 224
 225         val |= g4x_infoframe_enable(type);
 226         val &= ~VIDEO_DIP_FREQ_MASK;
 227         val |= VIDEO_DIP_FREQ_VSYNC;
 228
 229         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 230         intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
 231 }
 232
 233 static void g4x_read_infoframe(struct intel_encoder *encoder,
 234                                const struct intel_crtc_state *crtc_state,
 235                                unsigned int type,
 236                                void *frame, ssize_t len)
 237 {
 238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 239         u32 val, *data = frame;
 240         int i;
 241
 242         val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 243
 244         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 245         val |= g4x_infoframe_index(type);
 246
 247         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 248
 249         for (i = 0; i < len; i += 4)
 250                 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
 251 }
 252
 253 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 254                                   const struct intel_crtc_state *pipe_config)
 255 {
 256         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 257         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 258
 259         if ((val & VIDEO_DIP_ENABLE) == 0)
 260                 return 0;
 261
 262         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 263                 return 0;
 264
 265         return val & (VIDEO_DIP_ENABLE_AVI |
 266                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 267 }
 268
 269 static void ibx_write_infoframe(struct intel_encoder *encoder,
 270                                 const struct intel_crtc_state *crtc_state,
 271                                 unsigned int type,
 272                                 const void *frame, ssize_t len)
 273 {
 274         const u32 *data = frame;
 275         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 276         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 277         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 278         u32 val = intel_de_read(dev_priv, reg);
 279         int i;
 280
 281         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 282                  "Writing DIP with CTL reg disabled\n");
 283
 284         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 285         val |= g4x_infoframe_index(type);
 286
 287         val &= ~g4x_infoframe_enable(type);
 288
 289         intel_de_write(dev_priv, reg, val);
 290
 291         for (i = 0; i < len; i += 4) {
 292                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 293                                *data);
 294                 data++;
 295         }
 296         /* Write every possible data byte to force correct ECC calculation. */
 297         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 298                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 299
 300         val |= g4x_infoframe_enable(type);
 301         val &= ~VIDEO_DIP_FREQ_MASK;
 302         val |= VIDEO_DIP_FREQ_VSYNC;
 303
 304         intel_de_write(dev_priv, reg, val);
 305         intel_de_posting_read(dev_priv, reg);
 306 }
 307
 308 static void ibx_read_infoframe(struct intel_encoder *encoder,
 309                                const struct intel_crtc_state *crtc_state,
 310                                unsigned int type,
 311                                void *frame, ssize_t len)
 312 {
 313         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 314         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 315         u32 val, *data = frame;
 316         int i;
 317
 318         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 319
 320         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 321         val |= g4x_infoframe_index(type);
 322
 323         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 324
 325         for (i = 0; i < len; i += 4)
 326                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 327 }
 328
 329 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 330                                   const struct intel_crtc_state *pipe_config)
 331 {
 332         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 333         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 334         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 335         u32 val = intel_de_read(dev_priv, reg);
 336
 337         if ((val & VIDEO_DIP_ENABLE) == 0)
 338                 return 0;
 339
 340         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 341                 return 0;
 342
 343         return val & (VIDEO_DIP_ENABLE_AVI |
 344                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 345                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 346 }
 347
 348 static void cpt_write_infoframe(struct intel_encoder *encoder,
 349                                 const struct intel_crtc_state *crtc_state,
 350                                 unsigned int type,
 351                                 const void *frame, ssize_t len)
 352 {
 353         const u32 *data = frame;
 354         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 355         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 356         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 357         u32 val = intel_de_read(dev_priv, reg);
 358         int i;
 359
 360         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 361                  "Writing DIP with CTL reg disabled\n");
 362
 363         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 364         val |= g4x_infoframe_index(type);
 365
 366         /* The DIP control register spec says that we need to update the AVI
 367          * infoframe without clearing its enable bit */
 368         if (type != HDMI_INFOFRAME_TYPE_AVI)
 369                 val &= ~g4x_infoframe_enable(type);
 370
 371         intel_de_write(dev_priv, reg, val);
 372
 373         for (i = 0; i < len; i += 4) {
 374                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 375                                *data);
 376                 data++;
 377         }
 378         /* Write every possible data byte to force correct ECC calculation. */
 379         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 380                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 381
 382         val |= g4x_infoframe_enable(type);
 383         val &= ~VIDEO_DIP_FREQ_MASK;
 384         val |= VIDEO_DIP_FREQ_VSYNC;
 385
 386         intel_de_write(dev_priv, reg, val);
 387         intel_de_posting_read(dev_priv, reg);
 388 }
 389
 390 static void cpt_read_infoframe(struct intel_encoder *encoder,
 391                                const struct intel_crtc_state *crtc_state,
 392                                unsigned int type,
 393                                void *frame, ssize_t len)
 394 {
 395         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 396         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 397         u32 val, *data = frame;
 398         int i;
 399
 400         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 401
 402         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 403         val |= g4x_infoframe_index(type);
 404
 405         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 406
 407         for (i = 0; i < len; i += 4)
 408                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 409 }
 410
 411 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 412                                   const struct intel_crtc_state *pipe_config)
 413 {
 414         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 415         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 416         u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
 417
 418         if ((val & VIDEO_DIP_ENABLE) == 0)
 419                 return 0;
 420
 421         return val & (VIDEO_DIP_ENABLE_AVI |
 422                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 423                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 424 }
 425
 426 static void vlv_write_infoframe(struct intel_encoder *encoder,
 427                                 const struct intel_crtc_state *crtc_state,
 428                                 unsigned int type,
 429                                 const void *frame, ssize_t len)
 430 {
 431         const u32 *data = frame;
 432         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 433         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 434         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 435         u32 val = intel_de_read(dev_priv, reg);
 436         int i;
 437
 438         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 439                  "Writing DIP with CTL reg disabled\n");
 440
 441         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 442         val |= g4x_infoframe_index(type);
 443
 444         val &= ~g4x_infoframe_enable(type);
 445
 446         intel_de_write(dev_priv, reg, val);
 447
 448         for (i = 0; i < len; i += 4) {
 449                 intel_de_write(dev_priv,
 450                                VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
 451                 data++;
 452         }
 453         /* Write every possible data byte to force correct ECC calculation. */
 454         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 455                 intel_de_write(dev_priv,
 456                                VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
 457
 458         val |= g4x_infoframe_enable(type);
 459         val &= ~VIDEO_DIP_FREQ_MASK;
 460         val |= VIDEO_DIP_FREQ_VSYNC;
 461
 462         intel_de_write(dev_priv, reg, val);
 463         intel_de_posting_read(dev_priv, reg);
 464 }
 465
 466 static void vlv_read_infoframe(struct intel_encoder *encoder,
 467                                const struct intel_crtc_state *crtc_state,
 468                                unsigned int type,
 469                                void *frame, ssize_t len)
 470 {
 471         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 472         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 473         u32 val, *data = frame;
 474         int i;
 475
 476         val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
 477
 478         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 479         val |= g4x_infoframe_index(type);
 480
 481         intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 482
 483         for (i = 0; i < len; i += 4)
 484                 *data++ = intel_de_read(dev_priv,
 485                                         VLV_TVIDEO_DIP_DATA(crtc->pipe));
 486 }
 487
 488 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 489                                   const struct intel_crtc_state *pipe_config)
 490 {
 491         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 492         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 493         u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
 494
 495         if ((val & VIDEO_DIP_ENABLE) == 0)
 496                 return 0;
 497
 498         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 499                 return 0;
 500
 501         return val & (VIDEO_DIP_ENABLE_AVI |
 502                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 503                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 504 }
 505
 506 void hsw_write_infoframe(struct intel_encoder *encoder,
 507                          const struct intel_crtc_state *crtc_state,
 508                          unsigned int type,
 509                          const void *frame, ssize_t len)
 510 {
 511         const u32 *data = frame;
 512         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 513         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 514         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 515         int data_size;
 516         int i;
 517         u32 val = intel_de_read(dev_priv, ctl_reg);
 518
 519         data_size = hsw_dip_data_size(dev_priv, type);
 520
 521         drm_WARN_ON(&dev_priv->drm, len > data_size);
 522
 523         val &= ~hsw_infoframe_enable(type);
 524         intel_de_write(dev_priv, ctl_reg, val);
 525
 526         for (i = 0; i < len; i += 4) {
 527                 intel_de_write(dev_priv,
 528                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 529                                *data);
 530                 data++;
 531         }
 532         /* Write every possible data byte to force correct ECC calculation. */
 533         for (; i < data_size; i += 4)
 534                 intel_de_write(dev_priv,
 535                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 536                                0);
 537
 538         /* Wa_14013475917 */
 539         if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr &&
 540             type == DP_SDP_VSC)
 541                 return;
 542
 543         val |= hsw_infoframe_enable(type);
 544         intel_de_write(dev_priv, ctl_reg, val);
 545         intel_de_posting_read(dev_priv, ctl_reg);
 546 }
 547
 548 void hsw_read_infoframe(struct intel_encoder *encoder,
 549                         const struct intel_crtc_state *crtc_state,
 550                         unsigned int type, void *frame, ssize_t len)
 551 {
 552         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 553         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 554         u32 *data = frame;
 555         int i;
 556
 557         for (i = 0; i < len; i += 4)
 558                 *data++ = intel_de_read(dev_priv,
 559                                         hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
 560 }
 561
 562 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 563                                   const struct intel_crtc_state *pipe_config)
 564 {
 565         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 566         u32 val = intel_de_read(dev_priv,
 567                                 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 568         u32 mask;
 569
 570         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 571                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 572                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 573
 574         if (DISPLAY_VER(dev_priv) >= 10)
 575                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 576
 577         return val & mask;
 578 }
 579
 580 static const u8 infoframe_type_to_idx[] = {
 581         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 582         HDMI_PACKET_TYPE_GAMUT_METADATA,
 583         DP_SDP_VSC,
 584         HDMI_INFOFRAME_TYPE_AVI,
 585         HDMI_INFOFRAME_TYPE_SPD,
 586         HDMI_INFOFRAME_TYPE_VENDOR,
 587         HDMI_INFOFRAME_TYPE_DRM,
 588 };
 589
 590 u32 intel_hdmi_infoframe_enable(unsigned int type)
 591 {
 592         int i;
 593
 594         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 595                 if (infoframe_type_to_idx[i] == type)
 596                         return BIT(i);
 597         }
 598
 599         return 0;
 600 }
 601
 602 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 603                                   const struct intel_crtc_state *crtc_state)
 604 {
 605         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 606         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 607         u32 val, ret = 0;
 608         int i;
 609
 610         val = dig_port->infoframes_enabled(encoder, crtc_state);
 611
 612         /* map from hardware bits to dip idx */
 613         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 614                 unsigned int type = infoframe_type_to_idx[i];
 615
 616                 if (HAS_DDI(dev_priv)) {
 617                         if (val & hsw_infoframe_enable(type))
 618                                 ret |= BIT(i);
 619                 } else {
 620                         if (val & g4x_infoframe_enable(type))
 621                                 ret |= BIT(i);
 622                 }
 623         }
 624
 625         return ret;
 626 }
 627
 628 /*
 629  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 630  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 631  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 632  * used for both technologies.
 633  *
 634  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 635  * DW1:       DB3       | DB2 | DB1 | DB0
 636  * DW2:       DB7       | DB6 | DB5 | DB4
 637  * DW3: ...
 638  *
 639  * (HB is Header Byte, DB is Data Byte)
 640  *
 641  * The hdmi pack() functions don't know about that hardware specific hole so we
 642  * trick them by giving an offset into the buffer and moving back the header
 643  * bytes by one.
 644  */
 645 static void intel_write_infoframe(struct intel_encoder *encoder,
 646                                   const struct intel_crtc_state *crtc_state,
 647                                   enum hdmi_infoframe_type type,
 648                                   const union hdmi_infoframe *frame)
 649 {
 650         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 651         u8 buffer[VIDEO_DIP_DATA_SIZE];
 652         ssize_t len;
 653
 654         if ((crtc_state->infoframes.enable &
 655              intel_hdmi_infoframe_enable(type)) == 0)
 656                 return;
 657
 658         if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
 659                 return;
 660
 661         /* see comment above for the reason for this offset */
 662         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 663         if (drm_WARN_ON(encoder->base.dev, len < 0))
 664                 return;
 665
 666         /* Insert the 'hole' (see big comment above) at position 3 */
 667         memmove(&buffer[0], &buffer[1], 3);
 668         buffer[3] = 0;
 669         len++;
 670
 671         dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 672 }
 673
 674 void intel_read_infoframe(struct intel_encoder *encoder,
 675                           const struct intel_crtc_state *crtc_state,
 676                           enum hdmi_infoframe_type type,
 677                           union hdmi_infoframe *frame)
 678 {
 679         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 680         u8 buffer[VIDEO_DIP_DATA_SIZE];
 681         int ret;
 682
 683         if ((crtc_state->infoframes.enable &
 684              intel_hdmi_infoframe_enable(type)) == 0)
 685                 return;
 686
 687         dig_port->read_infoframe(encoder, crtc_state,
 688                                        type, buffer, sizeof(buffer));
 689
 690         /* Fill the 'hole' (see big comment above) at position 3 */
 691         memmove(&buffer[1], &buffer[0], 3);
 692
 693         /* see comment above for the reason for this offset */
 694         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 695         if (ret) {
 696                 drm_dbg_kms(encoder->base.dev,
 697                             "Failed to unpack infoframe type 0x%02x\n", type);
 698                 return;
 699         }
 700
 701         if (frame->any.type != type)
 702                 drm_dbg_kms(encoder->base.dev,
 703                             "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 704                             frame->any.type, type);
 705 }
 706
 707 static bool
 708 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 709                                  struct intel_crtc_state *crtc_state,
 710                                  struct drm_connector_state *conn_state)
 711 {
 712         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 713         const struct drm_display_mode *adjusted_mode =
 714                 &crtc_state->hw.adjusted_mode;
 715         struct drm_connector *connector = conn_state->connector;
 716         int ret;
 717
 718         if (!crtc_state->has_infoframe)
 719                 return true;
 720
 721         crtc_state->infoframes.enable |=
 722                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 723
 724         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 725                                                        adjusted_mode);
 726         if (ret)
 727                 return false;
 728
 729         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 730                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 731         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 732                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 733         else
 734                 frame->colorspace = HDMI_COLORSPACE_RGB;
 735
 736         drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
 737
 738         /* nonsense combination */
 739         drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
 740                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 741
 742         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 743                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 744                                                    adjusted_mode,
 745                                                    crtc_state->limited_color_range ?
 746                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 747                                                    HDMI_QUANTIZATION_RANGE_FULL);
 748         } else {
 749                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 750                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 751         }
 752
 753         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 754
 755         /* TODO: handle pixel repetition for YCBCR420 outputs */
 756
 757         ret = hdmi_avi_infoframe_check(frame);
 758         if (drm_WARN_ON(encoder->base.dev, ret))
 759                 return false;
 760
 761         return true;
 762 }
 763
 764 static bool
 765 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 766                                  struct intel_crtc_state *crtc_state,
 767                                  struct drm_connector_state *conn_state)
 768 {
 769         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 770         int ret;
 771
 772         if (!crtc_state->has_infoframe)
 773                 return true;
 774
 775         crtc_state->infoframes.enable |=
 776                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 777
 778         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 779         if (drm_WARN_ON(encoder->base.dev, ret))
 780                 return false;
 781
 782         frame->sdi = HDMI_SPD_SDI_PC;
 783
 784         ret = hdmi_spd_infoframe_check(frame);
 785         if (drm_WARN_ON(encoder->base.dev, ret))
 786                 return false;
 787
 788         return true;
 789 }
 790
 791 static bool
 792 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 793                                   struct intel_crtc_state *crtc_state,
 794                                   struct drm_connector_state *conn_state)
 795 {
 796         struct hdmi_vendor_infoframe *frame =
 797                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 798         const struct drm_display_info *info =
 799                 &conn_state->connector->display_info;
 800         int ret;
 801
 802         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 803                 return true;
 804
 805         crtc_state->infoframes.enable |=
 806                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 807
 808         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 809                                                           conn_state->connector,
 810                                                           &crtc_state->hw.adjusted_mode);
 811         if (drm_WARN_ON(encoder->base.dev, ret))
 812                 return false;
 813
 814         ret = hdmi_vendor_infoframe_check(frame);
 815         if (drm_WARN_ON(encoder->base.dev, ret))
 816                 return false;
 817
 818         return true;
 819 }
 820
 821 static bool
 822 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 823                                  struct intel_crtc_state *crtc_state,
 824                                  struct drm_connector_state *conn_state)
 825 {
 826         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 827         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 828         int ret;
 829
 830         if (DISPLAY_VER(dev_priv) < 10)
 831                 return true;
 832
 833         if (!crtc_state->has_infoframe)
 834                 return true;
 835
 836         if (!conn_state->hdr_output_metadata)
 837                 return true;
 838
 839         crtc_state->infoframes.enable |=
 840                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 841
 842         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 843         if (ret < 0) {
 844                 drm_dbg_kms(&dev_priv->drm,
 845                             "couldn't set HDR metadata in infoframe\n");
 846                 return false;
 847         }
 848
 849         ret = hdmi_drm_infoframe_check(frame);
 850         if (drm_WARN_ON(&dev_priv->drm, ret))
 851                 return false;
 852
 853         return true;
 854 }
 855
 856 static void g4x_set_infoframes(struct intel_encoder *encoder,
 857                                bool enable,
 858                                const struct intel_crtc_state *crtc_state,
 859                                const struct drm_connector_state *conn_state)
 860 {
 861         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 862         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 863         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 864         i915_reg_t reg = VIDEO_DIP_CTL;
 865         u32 val = intel_de_read(dev_priv, reg);
 866         u32 port = VIDEO_DIP_PORT(encoder->port);
 867
 868         assert_hdmi_port_disabled(intel_hdmi);
 869
 870         /* If the registers were not initialized yet, they might be zeroes,
 871          * which means we're selecting the AVI DIP and we're setting its
 872          * frequency to once. This seems to really confuse the HW and make
 873          * things stop working (the register spec says the AVI always needs to
 874          * be sent every VSync). So here we avoid writing to the register more
 875          * than we need and also explicitly select the AVI DIP and explicitly
 876          * set its frequency to every VSync. Avoiding to write it twice seems to
 877          * be enough to solve the problem, but being defensive shouldn't hurt us
 878          * either. */
 879         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 880
 881         if (!enable) {
 882                 if (!(val & VIDEO_DIP_ENABLE))
 883                         return;
 884                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 885                         drm_dbg_kms(&dev_priv->drm,
 886                                     "video DIP still enabled on port %c\n",
 887                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 888                         return;
 889                 }
 890                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 891                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 892                 intel_de_write(dev_priv, reg, val);
 893                 intel_de_posting_read(dev_priv, reg);
 894                 return;
 895         }
 896
 897         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 898                 if (val & VIDEO_DIP_ENABLE) {
 899                         drm_dbg_kms(&dev_priv->drm,
 900                                     "video DIP already enabled on port %c\n",
 901                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 902                         return;
 903                 }
 904                 val &= ~VIDEO_DIP_PORT_MASK;
 905                 val |= port;
 906         }
 907
 908         val |= VIDEO_DIP_ENABLE;
 909         val &= ~(VIDEO_DIP_ENABLE_AVI |
 910                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 911
 912         intel_de_write(dev_priv, reg, val);
 913         intel_de_posting_read(dev_priv, reg);
 914
 915         intel_write_infoframe(encoder, crtc_state,
 916                               HDMI_INFOFRAME_TYPE_AVI,
 917                               &crtc_state->infoframes.avi);
 918         intel_write_infoframe(encoder, crtc_state,
 919                               HDMI_INFOFRAME_TYPE_SPD,
 920                               &crtc_state->infoframes.spd);
 921         intel_write_infoframe(encoder, crtc_state,
 922                               HDMI_INFOFRAME_TYPE_VENDOR,
 923                               &crtc_state->infoframes.hdmi);
 924 }
 925
 926 /*
 927  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 928  *
 929  * From HDMI specification 1.4a:
 930  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 931  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 932  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 933  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 934  *   phase of 0
 935  */
 936 static bool gcp_default_phase_possible(int pipe_bpp,
 937                                        const struct drm_display_mode *mode)
 938 {
 939         unsigned int pixels_per_group;
 940
 941         switch (pipe_bpp) {
 942         case 30:
 943                 /* 4 pixels in 5 clocks */
 944                 pixels_per_group = 4;
 945                 break;
 946         case 36:
 947                 /* 2 pixels in 3 clocks */
 948                 pixels_per_group = 2;
 949                 break;
 950         case 48:
 951                 /* 1 pixel in 2 clocks */
 952                 pixels_per_group = 1;
 953                 break;
 954         default:
 955                 /* phase information not relevant for 8bpc */
 956                 return false;
 957         }
 958
 959         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 960                 mode->crtc_htotal % pixels_per_group == 0 &&
 961                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 962                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 963                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 964                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 965                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 966                  mode->crtc_htotal/2 % pixels_per_group == 0);
 967 }
 968
 969 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 970                                          const struct intel_crtc_state *crtc_state,
 971                                          const struct drm_connector_state *conn_state)
 972 {
 973         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 974         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 975         i915_reg_t reg;
 976
 977         if ((crtc_state->infoframes.enable &
 978              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 979                 return false;
 980
 981         if (HAS_DDI(dev_priv))
 982                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 983         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 984                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 985         else if (HAS_PCH_SPLIT(dev_priv))
 986                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 987         else
 988                 return false;
 989
 990         intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
 991
 992         return true;
 993 }
 994
 995 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 996                                    struct intel_crtc_state *crtc_state)
 997 {
 998         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 999         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1000         i915_reg_t reg;
1001
1002         if ((crtc_state->infoframes.enable &
1003              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1004                 return;
1005
1006         if (HAS_DDI(dev_priv))
1007                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1008         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1009                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1010         else if (HAS_PCH_SPLIT(dev_priv))
1011                 reg = TVIDEO_DIP_GCP(crtc->pipe);
1012         else
1013                 return;
1014
1015         crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1016 }
1017
1018 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1019                                              struct intel_crtc_state *crtc_state,
1020                                              struct drm_connector_state *conn_state)
1021 {
1022         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1023
1024         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1025                 return;
1026
1027         crtc_state->infoframes.enable |=
1028                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1029
1030         /* Indicate color indication for deep color mode */
1031         if (crtc_state->pipe_bpp > 24)
1032                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1033
1034         /* Enable default_phase whenever the display mode is suitably aligned */
1035         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1036                                        &crtc_state->hw.adjusted_mode))
1037                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1038 }
1039
1040 static void ibx_set_infoframes(struct intel_encoder *encoder,
1041                                bool enable,
1042                                const struct intel_crtc_state *crtc_state,
1043                                const struct drm_connector_state *conn_state)
1044 {
1045         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1046         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1047         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1048         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1049         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1050         u32 val = intel_de_read(dev_priv, reg);
1051         u32 port = VIDEO_DIP_PORT(encoder->port);
1052
1053         assert_hdmi_port_disabled(intel_hdmi);
1054
1055         /* See the big comment in g4x_set_infoframes() */
1056         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1057
1058         if (!enable) {
1059                 if (!(val & VIDEO_DIP_ENABLE))
1060                         return;
1061                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1062                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1063                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1064                 intel_de_write(dev_priv, reg, val);
1065                 intel_de_posting_read(dev_priv, reg);
1066                 return;
1067         }
1068
1069         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1070                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1071                          "DIP already enabled on port %c\n",
1072                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1073                 val &= ~VIDEO_DIP_PORT_MASK;
1074                 val |= port;
1075         }
1076
1077         val |= VIDEO_DIP_ENABLE;
1078         val &= ~(VIDEO_DIP_ENABLE_AVI |
1079                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1080                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1081
1082         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1083                 val |= VIDEO_DIP_ENABLE_GCP;
1084
1085         intel_de_write(dev_priv, reg, val);
1086         intel_de_posting_read(dev_priv, reg);
1087
1088         intel_write_infoframe(encoder, crtc_state,
1089                               HDMI_INFOFRAME_TYPE_AVI,
1090                               &crtc_state->infoframes.avi);
1091         intel_write_infoframe(encoder, crtc_state,
1092                               HDMI_INFOFRAME_TYPE_SPD,
1093                               &crtc_state->infoframes.spd);
1094         intel_write_infoframe(encoder, crtc_state,
1095                               HDMI_INFOFRAME_TYPE_VENDOR,
1096                               &crtc_state->infoframes.hdmi);
1097 }
1098
1099 static void cpt_set_infoframes(struct intel_encoder *encoder,
1100                                bool enable,
1101                                const struct intel_crtc_state *crtc_state,
1102                                const struct drm_connector_state *conn_state)
1103 {
1104         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1105         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1106         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1107         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1108         u32 val = intel_de_read(dev_priv, reg);
1109
1110         assert_hdmi_port_disabled(intel_hdmi);
1111
1112         /* See the big comment in g4x_set_infoframes() */
1113         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1114
1115         if (!enable) {
1116                 if (!(val & VIDEO_DIP_ENABLE))
1117                         return;
1118                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1119                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1120                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1121                 intel_de_write(dev_priv, reg, val);
1122                 intel_de_posting_read(dev_priv, reg);
1123                 return;
1124         }
1125
1126         /* Set both together, unset both together: see the spec. */
1127         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1128         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1129                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1130
1131         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1132                 val |= VIDEO_DIP_ENABLE_GCP;
1133
1134         intel_de_write(dev_priv, reg, val);
1135         intel_de_posting_read(dev_priv, reg);
1136
1137         intel_write_infoframe(encoder, crtc_state,
1138                               HDMI_INFOFRAME_TYPE_AVI,
1139                               &crtc_state->infoframes.avi);
1140         intel_write_infoframe(encoder, crtc_state,
1141                               HDMI_INFOFRAME_TYPE_SPD,
1142                               &crtc_state->infoframes.spd);
1143         intel_write_infoframe(encoder, crtc_state,
1144                               HDMI_INFOFRAME_TYPE_VENDOR,
1145                               &crtc_state->infoframes.hdmi);
1146 }
1147
1148 static void vlv_set_infoframes(struct intel_encoder *encoder,
1149                                bool enable,
1150                                const struct intel_crtc_state *crtc_state,
1151                                const struct drm_connector_state *conn_state)
1152 {
1153         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1154         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1155         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1156         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1157         u32 val = intel_de_read(dev_priv, reg);
1158         u32 port = VIDEO_DIP_PORT(encoder->port);
1159
1160         assert_hdmi_port_disabled(intel_hdmi);
1161
1162         /* See the big comment in g4x_set_infoframes() */
1163         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1164
1165         if (!enable) {
1166                 if (!(val & VIDEO_DIP_ENABLE))
1167                         return;
1168                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1169                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1170                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1171                 intel_de_write(dev_priv, reg, val);
1172                 intel_de_posting_read(dev_priv, reg);
1173                 return;
1174         }
1175
1176         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1177                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1178                          "DIP already enabled on port %c\n",
1179                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1180                 val &= ~VIDEO_DIP_PORT_MASK;
1181                 val |= port;
1182         }
1183
1184         val |= VIDEO_DIP_ENABLE;
1185         val &= ~(VIDEO_DIP_ENABLE_AVI |
1186                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1187                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1188
1189         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1190                 val |= VIDEO_DIP_ENABLE_GCP;
1191
1192         intel_de_write(dev_priv, reg, val);
1193         intel_de_posting_read(dev_priv, reg);
1194
1195         intel_write_infoframe(encoder, crtc_state,
1196                               HDMI_INFOFRAME_TYPE_AVI,
1197                               &crtc_state->infoframes.avi);
1198         intel_write_infoframe(encoder, crtc_state,
1199                               HDMI_INFOFRAME_TYPE_SPD,
1200                               &crtc_state->infoframes.spd);
1201         intel_write_infoframe(encoder, crtc_state,
1202                               HDMI_INFOFRAME_TYPE_VENDOR,
1203                               &crtc_state->infoframes.hdmi);
1204 }
1205
1206 static void hsw_set_infoframes(struct intel_encoder *encoder,
1207                                bool enable,
1208                                const struct intel_crtc_state *crtc_state,
1209                                const struct drm_connector_state *conn_state)
1210 {
1211         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1212         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1213         u32 val = intel_de_read(dev_priv, reg);
1214
1215         assert_hdmi_transcoder_func_disabled(dev_priv,
1216                                              crtc_state->cpu_transcoder);
1217
1218         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1219                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1220                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1221                  VIDEO_DIP_ENABLE_DRM_GLK);
1222
1223         if (!enable) {
1224                 intel_de_write(dev_priv, reg, val);
1225                 intel_de_posting_read(dev_priv, reg);
1226                 return;
1227         }
1228
1229         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1230                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1231
1232         intel_de_write(dev_priv, reg, val);
1233         intel_de_posting_read(dev_priv, reg);
1234
1235         intel_write_infoframe(encoder, crtc_state,
1236                               HDMI_INFOFRAME_TYPE_AVI,
1237                               &crtc_state->infoframes.avi);
1238         intel_write_infoframe(encoder, crtc_state,
1239                               HDMI_INFOFRAME_TYPE_SPD,
1240                               &crtc_state->infoframes.spd);
1241         intel_write_infoframe(encoder, crtc_state,
1242                               HDMI_INFOFRAME_TYPE_VENDOR,
1243                               &crtc_state->infoframes.hdmi);
1244         intel_write_infoframe(encoder, crtc_state,
1245                               HDMI_INFOFRAME_TYPE_DRM,
1246                               &crtc_state->infoframes.drm);
1247 }
1248
1249 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1250 {
1251         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1252         struct i2c_adapter *adapter;
1253
1254         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1255                 return;
1256
1257         adapter = intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1258
1259         drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1260                     enable ? "Enabling" : "Disabling");
1261
1262         drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable);
1263 }
1264
1265 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1266                                 unsigned int offset, void *buffer, size_t size)
1267 {
1268         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1269         struct intel_hdmi *hdmi = &dig_port->hdmi;
1270         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1271                                                               hdmi->ddc_bus);
1272         int ret;
1273         u8 start = offset & 0xff;
1274         struct i2c_msg msgs[] = {
1275                 {
1276                         .addr = DRM_HDCP_DDC_ADDR,
1277                         .flags = 0,
1278                         .len = 1,
1279                         .buf = &start,
1280                 },
1281                 {
1282                         .addr = DRM_HDCP_DDC_ADDR,
1283                         .flags = I2C_M_RD,
1284                         .len = size,
1285                         .buf = buffer
1286                 }
1287         };
1288         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1289         if (ret == ARRAY_SIZE(msgs))
1290                 return 0;
1291         return ret >= 0 ? -EIO : ret;
1292 }
1293
1294 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1295                                  unsigned int offset, void *buffer, size_t size)
1296 {
1297         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1298         struct intel_hdmi *hdmi = &dig_port->hdmi;
1299         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1300                                                               hdmi->ddc_bus);
1301         int ret;
1302         u8 *write_buf;
1303         struct i2c_msg msg;
1304
1305         write_buf = kzalloc(size + 1, GFP_KERNEL);
1306         if (!write_buf)
1307                 return -ENOMEM;
1308
1309         write_buf[0] = offset & 0xff;
1310         memcpy(&write_buf[1], buffer, size);
1311
1312         msg.addr = DRM_HDCP_DDC_ADDR;
1313         msg.flags = 0,
1314         msg.len = size + 1,
1315         msg.buf = write_buf;
1316
1317         ret = i2c_transfer(adapter, &msg, 1);
1318         if (ret == 1)
1319                 ret = 0;
1320         else if (ret >= 0)
1321                 ret = -EIO;
1322
1323         kfree(write_buf);
1324         return ret;
1325 }
1326
1327 static
1328 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1329                                   u8 *an)
1330 {
1331         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1332         struct intel_hdmi *hdmi = &dig_port->hdmi;
1333         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1334                                                               hdmi->ddc_bus);
1335         int ret;
1336
1337         ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1338                                     DRM_HDCP_AN_LEN);
1339         if (ret) {
1340                 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1341                             ret);
1342                 return ret;
1343         }
1344
1345         ret = intel_gmbus_output_aksv(adapter);
1346         if (ret < 0) {
1347                 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1348                 return ret;
1349         }
1350         return 0;
1351 }
1352
1353 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1354                                      u8 *bksv)
1355 {
1356         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1357
1358         int ret;
1359         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1360                                    DRM_HDCP_KSV_LEN);
1361         if (ret)
1362                 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1363                             ret);
1364         return ret;
1365 }
1366
1367 static
1368 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1369                                  u8 *bstatus)
1370 {
1371         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1372
1373         int ret;
1374         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1375                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1376         if (ret)
1377                 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1378                             ret);
1379         return ret;
1380 }
1381
1382 static
1383 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1384                                      bool *repeater_present)
1385 {
1386         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1387         int ret;
1388         u8 val;
1389
1390         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1391         if (ret) {
1392                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1393                             ret);
1394                 return ret;
1395         }
1396         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1397         return 0;
1398 }
1399
1400 static
1401 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1402                                   u8 *ri_prime)
1403 {
1404         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1405
1406         int ret;
1407         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1408                                    ri_prime, DRM_HDCP_RI_LEN);
1409         if (ret)
1410                 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1411                             ret);
1412         return ret;
1413 }
1414
1415 static
1416 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1417                                    bool *ksv_ready)
1418 {
1419         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1420         int ret;
1421         u8 val;
1422
1423         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1424         if (ret) {
1425                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1426                             ret);
1427                 return ret;
1428         }
1429         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1430         return 0;
1431 }
1432
1433 static
1434 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1435                                   int num_downstream, u8 *ksv_fifo)
1436 {
1437         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1438         int ret;
1439         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1440                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1441         if (ret) {
1442                 drm_dbg_kms(&i915->drm,
1443                             "Read ksv fifo over DDC failed (%d)\n", ret);
1444                 return ret;
1445         }
1446         return 0;
1447 }
1448
1449 static
1450 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1451                                       int i, u32 *part)
1452 {
1453         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1454         int ret;
1455
1456         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1457                 return -EINVAL;
1458
1459         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1460                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1461         if (ret)
1462                 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1463                             i, ret);
1464         return ret;
1465 }
1466
1467 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1468                                            enum transcoder cpu_transcoder)
1469 {
1470         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1471         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1472         struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1473         u32 scanline;
1474         int ret;
1475
1476         for (;;) {
1477                 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1478                 if (scanline > 100 && scanline < 200)
1479                         break;
1480                 usleep_range(25, 50);
1481         }
1482
1483         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1484                                          false, TRANS_DDI_HDCP_SIGNALLING);
1485         if (ret) {
1486                 drm_err(&dev_priv->drm,
1487                         "Disable HDCP signalling failed (%d)\n", ret);
1488                 return ret;
1489         }
1490
1491         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1492                                          true, TRANS_DDI_HDCP_SIGNALLING);
1493         if (ret) {
1494                 drm_err(&dev_priv->drm,
1495                         "Enable HDCP signalling failed (%d)\n", ret);
1496                 return ret;
1497         }
1498
1499         return 0;
1500 }
1501
1502 static
1503 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1504                                       enum transcoder cpu_transcoder,
1505                                       bool enable)
1506 {
1507         struct intel_hdmi *hdmi = &dig_port->hdmi;
1508         struct intel_connector *connector = hdmi->attached_connector;
1509         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1510         int ret;
1511
1512         if (!enable)
1513                 usleep_range(6, 60); /* Bspec says >= 6us */
1514
1515         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1516                                          cpu_transcoder, enable,
1517                                          TRANS_DDI_HDCP_SIGNALLING);
1518         if (ret) {
1519                 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1520                         enable ? "Enable" : "Disable", ret);
1521                 return ret;
1522         }
1523
1524         /*
1525          * WA: To fix incorrect positioning of the window of
1526          * opportunity and enc_en signalling in KABYLAKE.
1527          */
1528         if (IS_KABYLAKE(dev_priv) && enable)
1529                 return kbl_repositioning_enc_en_signal(connector,
1530                                                        cpu_transcoder);
1531
1532         return 0;
1533 }
1534
1535 static
1536 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1537                                      struct intel_connector *connector)
1538 {
1539         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1540         enum port port = dig_port->base.port;
1541         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1542         int ret;
1543         union {
1544                 u32 reg;
1545                 u8 shim[DRM_HDCP_RI_LEN];
1546         } ri;
1547
1548         ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1549         if (ret)
1550                 return false;
1551
1552         intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1553
1554         /* Wait for Ri prime match */
1555         if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1556                       (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1557                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1558                 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1559                         intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1560                                                         port)));
1561                 return false;
1562         }
1563         return true;
1564 }
1565
1566 static
1567 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1568                                 struct intel_connector *connector)
1569 {
1570         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1571         int retry;
1572
1573         for (retry = 0; retry < 3; retry++)
1574                 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1575                         return true;
1576
1577         drm_err(&i915->drm, "Link check failed\n");
1578         return false;
1579 }
1580
1581 struct hdcp2_hdmi_msg_timeout {
1582         u8 msg_id;
1583         u16 timeout;
1584 };
1585
1586 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1587         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1588         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1589         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1590         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1591         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1592 };
1593
1594 static
1595 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1596                                     u8 *rx_status)
1597 {
1598         return intel_hdmi_hdcp_read(dig_port,
1599                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1600                                     rx_status,
1601                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1602 }
1603
1604 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1605 {
1606         int i;
1607
1608         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1609                 if (is_paired)
1610                         return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1611                 else
1612                         return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1613         }
1614
1615         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1616                 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1617                         return hdcp2_msg_timeout[i].timeout;
1618         }
1619
1620         return -EINVAL;
1621 }
1622
1623 static int
1624 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1625                               u8 msg_id, bool *msg_ready,
1626                               ssize_t *msg_sz)
1627 {
1628         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1629         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1630         int ret;
1631
1632         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1633         if (ret < 0) {
1634                 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1635                             ret);
1636                 return ret;
1637         }
1638
1639         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1640                   rx_status[0]);
1641
1642         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1643                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1644                              *msg_sz);
1645         else
1646                 *msg_ready = *msg_sz;
1647
1648         return 0;
1649 }
1650
1651 static ssize_t
1652 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1653                               u8 msg_id, bool paired)
1654 {
1655         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1656         bool msg_ready = false;
1657         int timeout, ret;
1658         ssize_t msg_sz = 0;
1659
1660         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1661         if (timeout < 0)
1662                 return timeout;
1663
1664         ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1665                                                              msg_id, &msg_ready,
1666                                                              &msg_sz),
1667                          !ret && msg_ready && msg_sz, timeout * 1000,
1668                          1000, 5 * 1000);
1669         if (ret)
1670                 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1671                             msg_id, ret, timeout);
1672
1673         return ret ? ret : msg_sz;
1674 }
1675
1676 static
1677 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1678                                void *buf, size_t size)
1679 {
1680         unsigned int offset;
1681
1682         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1683         return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1684 }
1685
1686 static
1687 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1688                               u8 msg_id, void *buf, size_t size)
1689 {
1690         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1691         struct intel_hdmi *hdmi = &dig_port->hdmi;
1692         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1693         unsigned int offset;
1694         ssize_t ret;
1695
1696         ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1697                                             hdcp->is_paired);
1698         if (ret < 0)
1699                 return ret;
1700
1701         /*
1702          * Available msg size should be equal to or lesser than the
1703          * available buffer.
1704          */
1705         if (ret > size) {
1706                 drm_dbg_kms(&i915->drm,
1707                             "msg_sz(%zd) is more than exp size(%zu)\n",
1708                             ret, size);
1709                 return -EINVAL;
1710         }
1711
1712         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1713         ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1714         if (ret)
1715                 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1716                             msg_id, ret);
1717
1718         return ret;
1719 }
1720
1721 static
1722 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1723                                 struct intel_connector *connector)
1724 {
1725         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1726         int ret;
1727
1728         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1729         if (ret)
1730                 return ret;
1731
1732         /*
1733          * Re-auth request and Link Integrity Failures are represented by
1734          * same bit. i.e reauth_req.
1735          */
1736         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1737                 ret = HDCP_REAUTH_REQUEST;
1738         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1739                 ret = HDCP_TOPOLOGY_CHANGE;
1740
1741         return ret;
1742 }
1743
1744 static
1745 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1746                              bool *capable)
1747 {
1748         u8 hdcp2_version;
1749         int ret;
1750
1751         *capable = false;
1752         ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1753                                    &hdcp2_version, sizeof(hdcp2_version));
1754         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1755                 *capable = true;
1756
1757         return ret;
1758 }
1759
1760 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1761         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1762         .read_bksv = intel_hdmi_hdcp_read_bksv,
1763         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1764         .repeater_present = intel_hdmi_hdcp_repeater_present,
1765         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1766         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1767         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1768         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1769         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1770         .check_link = intel_hdmi_hdcp_check_link,
1771         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1772         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1773         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1774         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1775         .protocol = HDCP_PROTOCOL_HDMI,
1776 };
1777
1778 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1779 {
1780         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1781         int max_tmds_clock, vbt_max_tmds_clock;
1782
1783         if (DISPLAY_VER(dev_priv) >= 10)
1784                 max_tmds_clock = 594000;
1785         else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1786                 max_tmds_clock = 300000;
1787         else if (DISPLAY_VER(dev_priv) >= 5)
1788                 max_tmds_clock = 225000;
1789         else
1790                 max_tmds_clock = 165000;
1791
1792         vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
1793         if (vbt_max_tmds_clock)
1794                 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1795
1796         return max_tmds_clock;
1797 }
1798
1799 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1800                                 const struct drm_connector_state *conn_state)
1801 {
1802         return hdmi->has_hdmi_sink &&
1803                 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1804 }
1805
1806 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1807 {
1808         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1809 }
1810
1811 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1812                                  bool respect_downstream_limits,
1813                                  bool has_hdmi_sink)
1814 {
1815         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1816         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1817
1818         if (respect_downstream_limits) {
1819                 struct intel_connector *connector = hdmi->attached_connector;
1820                 const struct drm_display_info *info = &connector->base.display_info;
1821
1822                 if (hdmi->dp_dual_mode.max_tmds_clock)
1823                         max_tmds_clock = min(max_tmds_clock,
1824                                              hdmi->dp_dual_mode.max_tmds_clock);
1825
1826                 if (info->max_tmds_clock)
1827                         max_tmds_clock = min(max_tmds_clock,
1828                                              info->max_tmds_clock);
1829                 else if (!has_hdmi_sink)
1830                         max_tmds_clock = min(max_tmds_clock, 165000);
1831         }
1832
1833         return max_tmds_clock;
1834 }
1835
1836 static enum drm_mode_status
1837 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1838                       int clock, bool respect_downstream_limits,
1839                       bool has_hdmi_sink)
1840 {
1841         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1842         enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1843
1844         if (clock < 25000)
1845                 return MODE_CLOCK_LOW;
1846         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1847                                           has_hdmi_sink))
1848                 return MODE_CLOCK_HIGH;
1849
1850         /* GLK DPLL can't generate 446-480 MHz */
1851         if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1852                 return MODE_CLOCK_RANGE;
1853
1854         /* BXT/GLK DPLL can't generate 223-240 MHz */
1855         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1856             clock > 223333 && clock < 240000)
1857                 return MODE_CLOCK_RANGE;
1858
1859         /* CHV DPLL can't generate 216-240 MHz */
1860         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1861                 return MODE_CLOCK_RANGE;
1862
1863         /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1864         if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1865                 return MODE_CLOCK_RANGE;
1866
1867         /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1868         if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1869                 return MODE_CLOCK_RANGE;
1870
1871         /*
1872          * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1873          * set of link rates.
1874          *
1875          * FIXME: We will hopefully get an algorithmic way of programming
1876          * the MPLLB for HDMI in the future.
1877          */
1878         if (IS_DG2(dev_priv))
1879                 return intel_snps_phy_check_hdmi_link_rate(clock);
1880
1881         return MODE_OK;
1882 }
1883
1884 int intel_hdmi_tmds_clock(int clock, int bpc, bool ycbcr420_output)
1885 {
1886         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1887         if (ycbcr420_output)
1888                 clock /= 2;
1889
1890         /*
1891          * Need to adjust the port link by:
1892          *  1.5x for 12bpc
1893          *  1.25x for 10bpc
1894          */
1895         return DIV_ROUND_CLOSEST(clock * bpc, 8);
1896 }
1897
1898 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1899 {
1900         switch (bpc) {
1901         case 12:
1902                 return !HAS_GMCH(i915);
1903         case 10:
1904                 return DISPLAY_VER(i915) >= 11;
1905         case 8:
1906                 return true;
1907         default:
1908                 MISSING_CASE(bpc);
1909                 return false;
1910         }
1911 }
1912
1913 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1914                                          int bpc, bool has_hdmi_sink, bool ycbcr420_output)
1915 {
1916         const struct drm_display_info *info = &connector->display_info;
1917         const struct drm_hdmi_info *hdmi = &info->hdmi;
1918
1919         switch (bpc) {
1920         case 12:
1921                 if (!has_hdmi_sink)
1922                         return false;
1923
1924                 if (ycbcr420_output)
1925                         return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1926                 else
1927                         return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1928         case 10:
1929                 if (!has_hdmi_sink)
1930                         return false;
1931
1932                 if (ycbcr420_output)
1933                         return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1934                 else
1935                         return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1936         case 8:
1937                 return true;
1938         default:
1939                 MISSING_CASE(bpc);
1940                 return false;
1941         }
1942 }
1943
1944 static enum drm_mode_status
1945 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1946                             bool has_hdmi_sink, bool ycbcr420_output)
1947 {
1948         struct drm_i915_private *i915 = to_i915(connector->dev);
1949         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1950         enum drm_mode_status status = MODE_OK;
1951         int bpc;
1952
1953         /*
1954          * Try all color depths since valid port clock range
1955          * can have holes. Any mode that can be used with at
1956          * least one color depth is accepted.
1957          */
1958         for (bpc = 12; bpc >= 8; bpc -= 2) {
1959                 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
1960
1961                 if (!intel_hdmi_source_bpc_possible(i915, bpc))
1962                         continue;
1963
1964                 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
1965                         continue;
1966
1967                 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1968                 if (status == MODE_OK)
1969                         return MODE_OK;
1970         }
1971
1972         /* can never happen */
1973         drm_WARN_ON(&i915->drm, status == MODE_OK);
1974
1975         return status;
1976 }
1977
1978 static enum drm_mode_status
1979 intel_hdmi_mode_valid(struct drm_connector *connector,
1980                       struct drm_display_mode *mode)
1981 {
1982         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1983         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1984         enum drm_mode_status status;
1985         int clock = mode->clock;
1986         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1987         bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1988         bool ycbcr_420_only;
1989
1990         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1991                 return MODE_NO_DBLESCAN;
1992
1993         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1994                 clock *= 2;
1995
1996         if (clock > max_dotclk)
1997                 return MODE_CLOCK_HIGH;
1998
1999         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2000                 if (!has_hdmi_sink)
2001                         return MODE_CLOCK_LOW;
2002                 clock *= 2;
2003         }
2004
2005         /*
2006          * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2007          * enumerated only if FRL is supported. Current platforms do not support
2008          * FRL so prune the higher resolution modes that require doctclock more
2009          * than 600MHz.
2010          */
2011         if (clock > 600000)
2012                 return MODE_CLOCK_HIGH;
2013
2014         ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2015
2016         status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only);
2017         if (status != MODE_OK) {
2018                 if (ycbcr_420_only ||
2019                     !connector->ycbcr_420_allowed ||
2020                     !drm_mode_is_420_also(&connector->display_info, mode))
2021                         return status;
2022
2023                 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true);
2024                 if (status != MODE_OK)
2025                         return status;
2026         }
2027
2028         return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2029 }
2030
2031 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2032                              int bpc, bool has_hdmi_sink, bool ycbcr420_output)
2033 {
2034         struct drm_atomic_state *state = crtc_state->uapi.state;
2035         struct drm_connector_state *connector_state;
2036         struct drm_connector *connector;
2037         int i;
2038
2039         for_each_new_connector_in_state(state, connector, connector_state, i) {
2040                 if (connector_state->crtc != crtc_state->uapi.crtc)
2041                         continue;
2042
2043                 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output))
2044                         return false;
2045         }
2046
2047         return true;
2048 }
2049
2050 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2051 {
2052         struct drm_i915_private *dev_priv =
2053                 to_i915(crtc_state->uapi.crtc->dev);
2054         const struct drm_display_mode *adjusted_mode =
2055                 &crtc_state->hw.adjusted_mode;
2056
2057         if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2058                 return false;
2059
2060         /*
2061          * HDMI deep color affects the clocks, so it's only possible
2062          * when not cloning with other encoder types.
2063          */
2064         if (bpc > 8 && crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI))
2065                 return false;
2066
2067         /* Display Wa_1405510057:icl,ehl */
2068         if (intel_hdmi_is_ycbcr420(crtc_state) &&
2069             bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2070             (adjusted_mode->crtc_hblank_end -
2071              adjusted_mode->crtc_hblank_start) % 8 == 2)
2072                 return false;
2073
2074         return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink,
2075                                        intel_hdmi_is_ycbcr420(crtc_state));
2076 }
2077
2078 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2079                                   struct intel_crtc_state *crtc_state,
2080                                   int clock, bool respect_downstream_limits)
2081 {
2082         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2083         bool ycbcr420_output = intel_hdmi_is_ycbcr420(crtc_state);
2084         int bpc;
2085
2086         /*
2087          * pipe_bpp could already be below 8bpc due to FDI
2088          * bandwidth constraints. HDMI minimum is 8bpc however.
2089          */
2090         bpc = max(crtc_state->pipe_bpp / 3, 8);
2091
2092         /*
2093          * We will never exceed downstream TMDS clock limits while
2094          * attempting deep color. If the user insists on forcing an
2095          * out of spec mode they will have to be satisfied with 8bpc.
2096          */
2097         if (!respect_downstream_limits)
2098                 bpc = 8;
2099
2100         for (; bpc >= 8; bpc -= 2) {
2101                 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, ycbcr420_output);
2102
2103                 if (hdmi_bpc_possible(crtc_state, bpc) &&
2104                     hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2105                                           respect_downstream_limits,
2106                                           crtc_state->has_hdmi_sink) == MODE_OK)
2107                         return bpc;
2108         }
2109
2110         return -EINVAL;
2111 }
2112
2113 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2114                                     struct intel_crtc_state *crtc_state,
2115                                     bool respect_downstream_limits)
2116 {
2117         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2118         const struct drm_display_mode *adjusted_mode =
2119                 &crtc_state->hw.adjusted_mode;
2120         int bpc, clock = adjusted_mode->crtc_clock;
2121
2122         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2123                 clock *= 2;
2124
2125         bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2126                                      respect_downstream_limits);
2127         if (bpc < 0)
2128                 return bpc;
2129
2130         crtc_state->port_clock =
2131                 intel_hdmi_tmds_clock(clock, bpc, intel_hdmi_is_ycbcr420(crtc_state));
2132
2133         /*
2134          * pipe_bpp could already be below 8bpc due to
2135          * FDI bandwidth constraints. We shouldn't bump it
2136          * back up to the HDMI minimum 8bpc in that case.
2137          */
2138         crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2139
2140         drm_dbg_kms(&i915->drm,
2141                     "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2142                     bpc, crtc_state->pipe_bpp);
2143
2144         return 0;
2145 }
2146
2147 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2148                                     const struct drm_connector_state *conn_state)
2149 {
2150         const struct intel_digital_connector_state *intel_conn_state =
2151                 to_intel_digital_connector_state(conn_state);
2152         const struct drm_display_mode *adjusted_mode =
2153                 &crtc_state->hw.adjusted_mode;
2154
2155         /*
2156          * Our YCbCr output is always limited range.
2157          * crtc_state->limited_color_range only applies to RGB,
2158          * and it must never be set for YCbCr or we risk setting
2159          * some conflicting bits in PIPECONF which will mess up
2160          * the colors on the monitor.
2161          */
2162         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2163                 return false;
2164
2165         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2166                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2167                 return crtc_state->has_hdmi_sink &&
2168                         drm_default_rgb_quant_range(adjusted_mode) ==
2169                         HDMI_QUANTIZATION_RANGE_LIMITED;
2170         } else {
2171                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2172         }
2173 }
2174
2175 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2176                                  const struct intel_crtc_state *crtc_state,
2177                                  const struct drm_connector_state *conn_state)
2178 {
2179         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2180         const struct intel_digital_connector_state *intel_conn_state =
2181                 to_intel_digital_connector_state(conn_state);
2182
2183         if (!crtc_state->has_hdmi_sink)
2184                 return false;
2185
2186         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2187                 return intel_hdmi->has_audio;
2188         else
2189                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2190 }
2191
2192 static enum intel_output_format
2193 intel_hdmi_output_format(struct intel_connector *connector,
2194                          bool ycbcr_420_output)
2195 {
2196         if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2197                 return INTEL_OUTPUT_FORMAT_YCBCR420;
2198         else
2199                 return INTEL_OUTPUT_FORMAT_RGB;
2200 }
2201
2202 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2203                                             struct intel_crtc_state *crtc_state,
2204                                             const struct drm_connector_state *conn_state,
2205                                             bool respect_downstream_limits)
2206 {
2207         struct intel_connector *connector = to_intel_connector(conn_state->connector);
2208         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2209         const struct drm_display_info *info = &connector->base.display_info;
2210         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2211         bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2212         int ret;
2213
2214         crtc_state->output_format = intel_hdmi_output_format(connector, ycbcr_420_only);
2215
2216         if (ycbcr_420_only && !intel_hdmi_is_ycbcr420(crtc_state)) {
2217                 drm_dbg_kms(&i915->drm,
2218                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2219                 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
2220         }
2221
2222         ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2223         if (ret) {
2224                 if (intel_hdmi_is_ycbcr420(crtc_state) ||
2225                     !connector->base.ycbcr_420_allowed ||
2226                     !drm_mode_is_420_also(info, adjusted_mode))
2227                         return ret;
2228
2229                 crtc_state->output_format = intel_hdmi_output_format(connector, true);
2230                 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2231         }
2232
2233         return ret;
2234 }
2235
2236 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2237                               struct intel_crtc_state *pipe_config,
2238                               struct drm_connector_state *conn_state)
2239 {
2240         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2241         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2242         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2243         struct drm_connector *connector = conn_state->connector;
2244         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2245         int ret;
2246
2247         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2248                 return -EINVAL;
2249
2250         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2251         pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2252                                                          conn_state);
2253
2254         if (pipe_config->has_hdmi_sink)
2255                 pipe_config->has_infoframe = true;
2256
2257         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2258                 pipe_config->pixel_multiplier = 2;
2259
2260         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2261                 pipe_config->has_pch_encoder = true;
2262
2263         pipe_config->has_audio =
2264                 intel_hdmi_has_audio(encoder, pipe_config, conn_state);
2265
2266         /*
2267          * Try to respect downstream TMDS clock limits first, if
2268          * that fails assume the user might know something we don't.
2269          */
2270         ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2271         if (ret)
2272                 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2273         if (ret) {
2274                 drm_dbg_kms(&dev_priv->drm,
2275                             "unsupported HDMI clock (%d kHz), rejecting mode\n",
2276                             pipe_config->hw.adjusted_mode.crtc_clock);
2277                 return ret;
2278         }
2279
2280         if (intel_hdmi_is_ycbcr420(pipe_config)) {
2281                 ret = intel_panel_fitting(pipe_config, conn_state);
2282                 if (ret)
2283                         return ret;
2284         }
2285
2286         pipe_config->limited_color_range =
2287                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2288
2289         if (conn_state->picture_aspect_ratio)
2290                 adjusted_mode->picture_aspect_ratio =
2291                         conn_state->picture_aspect_ratio;
2292
2293         pipe_config->lane_count = 4;
2294
2295         if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) {
2296                 if (scdc->scrambling.low_rates)
2297                         pipe_config->hdmi_scrambling = true;
2298
2299                 if (pipe_config->port_clock > 340000) {
2300                         pipe_config->hdmi_scrambling = true;
2301                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2302                 }
2303         }
2304
2305         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2306                                          conn_state);
2307
2308         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2309                 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2310                 return -EINVAL;
2311         }
2312
2313         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2314                 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2315                 return -EINVAL;
2316         }
2317
2318         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2319                 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2320                 return -EINVAL;
2321         }
2322
2323         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2324                 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2325                 return -EINVAL;
2326         }
2327
2328         return 0;
2329 }
2330
2331 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2332 {
2333         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2334
2335         /*
2336          * Give a hand to buggy BIOSen which forget to turn
2337          * the TMDS output buffers back on after a reboot.
2338          */
2339         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2340 }
2341
2342 static void
2343 intel_hdmi_unset_edid(struct drm_connector *connector)
2344 {
2345         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2346
2347         intel_hdmi->has_hdmi_sink = false;
2348         intel_hdmi->has_audio = false;
2349
2350         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2351         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2352
2353         kfree(to_intel_connector(connector)->detect_edid);
2354         to_intel_connector(connector)->detect_edid = NULL;
2355 }
2356
2357 static void
2358 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2359 {
2360         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2361         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2362         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2363         struct i2c_adapter *adapter =
2364                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2365         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter);
2366
2367         /*
2368          * Type 1 DVI adaptors are not required to implement any
2369          * registers, so we can't always detect their presence.
2370          * Ideally we should be able to check the state of the
2371          * CONFIG1 pin, but no such luck on our hardware.
2372          *
2373          * The only method left to us is to check the VBT to see
2374          * if the port is a dual mode capable DP port. But let's
2375          * only do that when we sucesfully read the EDID, to avoid
2376          * confusing log messages about DP dual mode adaptors when
2377          * there's nothing connected to the port.
2378          */
2379         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2380                 /* An overridden EDID imply that we want this port for testing.
2381                  * Make sure not to set limits for that port.
2382                  */
2383                 if (has_edid && !connector->override_edid &&
2384                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2385                         drm_dbg_kms(&dev_priv->drm,
2386                                     "Assuming DP dual mode adaptor presence based on VBT\n");
2387                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2388                 } else {
2389                         type = DRM_DP_DUAL_MODE_NONE;
2390                 }
2391         }
2392
2393         if (type == DRM_DP_DUAL_MODE_NONE)
2394                 return;
2395
2396         hdmi->dp_dual_mode.type = type;
2397         hdmi->dp_dual_mode.max_tmds_clock =
2398                 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter);
2399
2400         drm_dbg_kms(&dev_priv->drm,
2401                     "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2402                     drm_dp_get_dual_mode_type_name(type),
2403                     hdmi->dp_dual_mode.max_tmds_clock);
2404
2405         /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2406         if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2407             !intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2408                 drm_dbg_kms(&dev_priv->drm,
2409                             "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2410                 hdmi->dp_dual_mode.max_tmds_clock = 0;
2411         }
2412 }
2413
2414 static bool
2415 intel_hdmi_set_edid(struct drm_connector *connector)
2416 {
2417         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2418         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2419         intel_wakeref_t wakeref;
2420         struct edid *edid;
2421         bool connected = false;
2422         struct i2c_adapter *i2c;
2423
2424         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2425
2426         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2427
2428         edid = drm_get_edid(connector, i2c);
2429
2430         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2431                 drm_dbg_kms(&dev_priv->drm,
2432                             "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2433                 intel_gmbus_force_bit(i2c, true);
2434                 edid = drm_get_edid(connector, i2c);
2435                 intel_gmbus_force_bit(i2c, false);
2436         }
2437
2438         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2439
2440         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2441
2442         to_intel_connector(connector)->detect_edid = edid;
2443         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2444                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2445                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2446
2447                 connected = true;
2448         }
2449
2450         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2451
2452         return connected;
2453 }
2454
2455 static enum drm_connector_status
2456 intel_hdmi_detect(struct drm_connector *connector, bool force)
2457 {
2458         enum drm_connector_status status = connector_status_disconnected;
2459         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2460         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2461         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2462         intel_wakeref_t wakeref;
2463
2464         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2465                     connector->base.id, connector->name);
2466
2467         if (!INTEL_DISPLAY_ENABLED(dev_priv))
2468                 return connector_status_disconnected;
2469
2470         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2471
2472         if (DISPLAY_VER(dev_priv) >= 11 &&
2473             !intel_digital_port_connected(encoder))
2474                 goto out;
2475
2476         intel_hdmi_unset_edid(connector);
2477
2478         if (intel_hdmi_set_edid(connector))
2479                 status = connector_status_connected;
2480
2481 out:
2482         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2483
2484         if (status != connector_status_connected)
2485                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2486
2487         /*
2488          * Make sure the refs for power wells enabled during detect are
2489          * dropped to avoid a new detect cycle triggered by HPD polling.
2490          */
2491         intel_display_power_flush_work(dev_priv);
2492
2493         return status;
2494 }
2495
2496 static void
2497 intel_hdmi_force(struct drm_connector *connector)
2498 {
2499         struct drm_i915_private *i915 = to_i915(connector->dev);
2500
2501         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2502                     connector->base.id, connector->name);
2503
2504         intel_hdmi_unset_edid(connector);
2505
2506         if (connector->status != connector_status_connected)
2507                 return;
2508
2509         intel_hdmi_set_edid(connector);
2510 }
2511
2512 static int intel_hdmi_get_modes(struct drm_connector *connector)
2513 {
2514         struct edid *edid;
2515
2516         edid = to_intel_connector(connector)->detect_edid;
2517         if (edid == NULL)
2518                 return 0;
2519
2520         return intel_connector_update_modes(connector, edid);
2521 }
2522
2523 static struct i2c_adapter *
2524 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2525 {
2526         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2527         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2528
2529         return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2530 }
2531
2532 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2533 {
2534         struct drm_i915_private *i915 = to_i915(connector->dev);
2535         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2536         struct kobject *i2c_kobj = &adapter->dev.kobj;
2537         struct kobject *connector_kobj = &connector->kdev->kobj;
2538         int ret;
2539
2540         ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2541         if (ret)
2542                 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2543 }
2544
2545 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2546 {
2547         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2548         struct kobject *i2c_kobj = &adapter->dev.kobj;
2549         struct kobject *connector_kobj = &connector->kdev->kobj;
2550
2551         sysfs_remove_link(connector_kobj, i2c_kobj->name);
2552 }
2553
2554 static int
2555 intel_hdmi_connector_register(struct drm_connector *connector)
2556 {
2557         int ret;
2558
2559         ret = intel_connector_register(connector);
2560         if (ret)
2561                 return ret;
2562
2563         intel_hdmi_create_i2c_symlink(connector);
2564
2565         return ret;
2566 }
2567
2568 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2569 {
2570         struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2571
2572         cec_notifier_conn_unregister(n);
2573
2574         intel_hdmi_remove_i2c_symlink(connector);
2575         intel_connector_unregister(connector);
2576 }
2577
2578 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2579         .detect = intel_hdmi_detect,
2580         .force = intel_hdmi_force,
2581         .fill_modes = drm_helper_probe_single_connector_modes,
2582         .atomic_get_property = intel_digital_connector_atomic_get_property,
2583         .atomic_set_property = intel_digital_connector_atomic_set_property,
2584         .late_register = intel_hdmi_connector_register,
2585         .early_unregister = intel_hdmi_connector_unregister,
2586         .destroy = intel_connector_destroy,
2587         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2588         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2589 };
2590
2591 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2592         .get_modes = intel_hdmi_get_modes,
2593         .mode_valid = intel_hdmi_mode_valid,
2594         .atomic_check = intel_digital_connector_atomic_check,
2595 };
2596
2597 static void
2598 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2599 {
2600         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2601
2602         intel_attach_force_audio_property(connector);
2603         intel_attach_broadcast_rgb_property(connector);
2604         intel_attach_aspect_ratio_property(connector);
2605
2606         intel_attach_hdmi_colorspace_property(connector);
2607         drm_connector_attach_content_type_property(connector);
2608
2609         if (DISPLAY_VER(dev_priv) >= 10)
2610                 drm_connector_attach_hdr_output_metadata_property(connector);
2611
2612         if (!HAS_GMCH(dev_priv))
2613                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2614 }
2615
2616 /*
2617  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2618  * @encoder: intel_encoder
2619  * @connector: drm_connector
2620  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2621  *  or reset the high tmds clock ratio for scrambling
2622  * @scrambling: bool to Indicate if the function needs to set or reset
2623  *  sink scrambling
2624  *
2625  * This function handles scrambling on HDMI 2.0 capable sinks.
2626  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2627  * it enables scrambling. This should be called before enabling the HDMI
2628  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2629  * detect a scrambled clock within 100 ms.
2630  *
2631  * Returns:
2632  * True on success, false on failure.
2633  */
2634 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2635                                        struct drm_connector *connector,
2636                                        bool high_tmds_clock_ratio,
2637                                        bool scrambling)
2638 {
2639         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2640         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2641         struct drm_scrambling *sink_scrambling =
2642                 &connector->display_info.hdmi.scdc.scrambling;
2643         struct i2c_adapter *adapter =
2644                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2645
2646         if (!sink_scrambling->supported)
2647                 return true;
2648
2649         drm_dbg_kms(&dev_priv->drm,
2650                     "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2651                     connector->base.id, connector->name,
2652                     str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2653
2654         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2655         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2656                                                   high_tmds_clock_ratio) &&
2657                 drm_scdc_set_scrambling(adapter, scrambling);
2658 }
2659
2660 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2661 {
2662         u8 ddc_pin;
2663
2664         switch (port) {
2665         case PORT_B:
2666                 ddc_pin = GMBUS_PIN_DPB;
2667                 break;
2668         case PORT_C:
2669                 ddc_pin = GMBUS_PIN_DPC;
2670                 break;
2671         case PORT_D:
2672                 ddc_pin = GMBUS_PIN_DPD_CHV;
2673                 break;
2674         default:
2675                 MISSING_CASE(port);
2676                 ddc_pin = GMBUS_PIN_DPB;
2677                 break;
2678         }
2679         return ddc_pin;
2680 }
2681
2682 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2683 {
2684         u8 ddc_pin;
2685
2686         switch (port) {
2687         case PORT_B:
2688                 ddc_pin = GMBUS_PIN_1_BXT;
2689                 break;
2690         case PORT_C:
2691                 ddc_pin = GMBUS_PIN_2_BXT;
2692                 break;
2693         default:
2694                 MISSING_CASE(port);
2695                 ddc_pin = GMBUS_PIN_1_BXT;
2696                 break;
2697         }
2698         return ddc_pin;
2699 }
2700
2701 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2702                               enum port port)
2703 {
2704         u8 ddc_pin;
2705
2706         switch (port) {
2707         case PORT_B:
2708                 ddc_pin = GMBUS_PIN_1_BXT;
2709                 break;
2710         case PORT_C:
2711                 ddc_pin = GMBUS_PIN_2_BXT;
2712                 break;
2713         case PORT_D:
2714                 ddc_pin = GMBUS_PIN_4_CNP;
2715                 break;
2716         case PORT_F:
2717                 ddc_pin = GMBUS_PIN_3_BXT;
2718                 break;
2719         default:
2720                 MISSING_CASE(port);
2721                 ddc_pin = GMBUS_PIN_1_BXT;
2722                 break;
2723         }
2724         return ddc_pin;
2725 }
2726
2727 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2728 {
2729         enum phy phy = intel_port_to_phy(dev_priv, port);
2730
2731         if (intel_phy_is_combo(dev_priv, phy))
2732                 return GMBUS_PIN_1_BXT + port;
2733         else if (intel_phy_is_tc(dev_priv, phy))
2734                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2735
2736         drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2737         return GMBUS_PIN_2_BXT;
2738 }
2739
2740 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2741 {
2742         enum phy phy = intel_port_to_phy(dev_priv, port);
2743         u8 ddc_pin;
2744
2745         switch (phy) {
2746         case PHY_A:
2747                 ddc_pin = GMBUS_PIN_1_BXT;
2748                 break;
2749         case PHY_B:
2750                 ddc_pin = GMBUS_PIN_2_BXT;
2751                 break;
2752         case PHY_C:
2753                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2754                 break;
2755         default:
2756                 MISSING_CASE(phy);
2757                 ddc_pin = GMBUS_PIN_1_BXT;
2758                 break;
2759         }
2760         return ddc_pin;
2761 }
2762
2763 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2764 {
2765         enum phy phy = intel_port_to_phy(dev_priv, port);
2766
2767         WARN_ON(port == PORT_C);
2768
2769         /*
2770          * Pin mapping for RKL depends on which PCH is present.  With TGP, the
2771          * final two outputs use type-c pins, even though they're actually
2772          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2773          * all outputs.
2774          */
2775         if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2776                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2777
2778         return GMBUS_PIN_1_BXT + phy;
2779 }
2780
2781 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2782 {
2783         enum phy phy = intel_port_to_phy(i915, port);
2784
2785         drm_WARN_ON(&i915->drm, port == PORT_A);
2786
2787         /*
2788          * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
2789          * final two outputs use type-c pins, even though they're actually
2790          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2791          * all outputs.
2792          */
2793         if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2794                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2795
2796         return GMBUS_PIN_1_BXT + phy;
2797 }
2798
2799 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2800 {
2801         return intel_port_to_phy(dev_priv, port) + 1;
2802 }
2803
2804 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2805 {
2806         enum phy phy = intel_port_to_phy(dev_priv, port);
2807
2808         WARN_ON(port == PORT_B || port == PORT_C);
2809
2810         /*
2811          * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2812          * except first combo output.
2813          */
2814         if (phy == PHY_A)
2815                 return GMBUS_PIN_1_BXT;
2816
2817         return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2818 }
2819
2820 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2821                               enum port port)
2822 {
2823         u8 ddc_pin;
2824
2825         switch (port) {
2826         case PORT_B:
2827                 ddc_pin = GMBUS_PIN_DPB;
2828                 break;
2829         case PORT_C:
2830                 ddc_pin = GMBUS_PIN_DPC;
2831                 break;
2832         case PORT_D:
2833                 ddc_pin = GMBUS_PIN_DPD;
2834                 break;
2835         default:
2836                 MISSING_CASE(port);
2837                 ddc_pin = GMBUS_PIN_DPB;
2838                 break;
2839         }
2840         return ddc_pin;
2841 }
2842
2843 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2844 {
2845         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2846         enum port port = encoder->port;
2847         u8 ddc_pin;
2848
2849         ddc_pin = intel_bios_alternate_ddc_pin(encoder);
2850         if (ddc_pin) {
2851                 drm_dbg_kms(&dev_priv->drm,
2852                             "Using DDC pin 0x%x for port %c (VBT)\n",
2853                             ddc_pin, port_name(port));
2854                 return ddc_pin;
2855         }
2856
2857         if (IS_ALDERLAKE_S(dev_priv))
2858                 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2859         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2860                 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2861         else if (IS_ROCKETLAKE(dev_priv))
2862                 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2863         else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2864                 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2865         else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
2866                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2867         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2868                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2869         else if (HAS_PCH_CNP(dev_priv))
2870                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2871         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2872                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2873         else if (IS_CHERRYVIEW(dev_priv))
2874                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2875         else
2876                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2877
2878         drm_dbg_kms(&dev_priv->drm,
2879                     "Using DDC pin 0x%x for port %c (platform default)\n",
2880                     ddc_pin, port_name(port));
2881
2882         return ddc_pin;
2883 }
2884
2885 void intel_infoframe_init(struct intel_digital_port *dig_port)
2886 {
2887         struct drm_i915_private *dev_priv =
2888                 to_i915(dig_port->base.base.dev);
2889
2890         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2891                 dig_port->write_infoframe = vlv_write_infoframe;
2892                 dig_port->read_infoframe = vlv_read_infoframe;
2893                 dig_port->set_infoframes = vlv_set_infoframes;
2894                 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2895         } else if (IS_G4X(dev_priv)) {
2896                 dig_port->write_infoframe = g4x_write_infoframe;
2897                 dig_port->read_infoframe = g4x_read_infoframe;
2898                 dig_port->set_infoframes = g4x_set_infoframes;
2899                 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2900         } else if (HAS_DDI(dev_priv)) {
2901                 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) {
2902                         dig_port->write_infoframe = lspcon_write_infoframe;
2903                         dig_port->read_infoframe = lspcon_read_infoframe;
2904                         dig_port->set_infoframes = lspcon_set_infoframes;
2905                         dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2906                 } else {
2907                         dig_port->write_infoframe = hsw_write_infoframe;
2908                         dig_port->read_infoframe = hsw_read_infoframe;
2909                         dig_port->set_infoframes = hsw_set_infoframes;
2910                         dig_port->infoframes_enabled = hsw_infoframes_enabled;
2911                 }
2912         } else if (HAS_PCH_IBX(dev_priv)) {
2913                 dig_port->write_infoframe = ibx_write_infoframe;
2914                 dig_port->read_infoframe = ibx_read_infoframe;
2915                 dig_port->set_infoframes = ibx_set_infoframes;
2916                 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2917         } else {
2918                 dig_port->write_infoframe = cpt_write_infoframe;
2919                 dig_port->read_infoframe = cpt_read_infoframe;
2920                 dig_port->set_infoframes = cpt_set_infoframes;
2921                 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2922         }
2923 }
2924
2925 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2926                                struct intel_connector *intel_connector)
2927 {
2928         struct drm_connector *connector = &intel_connector->base;
2929         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2930         struct intel_encoder *intel_encoder = &dig_port->base;
2931         struct drm_device *dev = intel_encoder->base.dev;
2932         struct drm_i915_private *dev_priv = to_i915(dev);
2933         struct i2c_adapter *ddc;
2934         enum port port = intel_encoder->port;
2935         struct cec_connector_info conn_info;
2936
2937         drm_dbg_kms(&dev_priv->drm,
2938                     "Adding HDMI connector on [ENCODER:%d:%s]\n",
2939                     intel_encoder->base.base.id, intel_encoder->base.name);
2940
2941         if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2942                 return;
2943
2944         if (drm_WARN(dev, dig_port->max_lanes < 4,
2945                      "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2946                      dig_port->max_lanes, intel_encoder->base.base.id,
2947                      intel_encoder->base.name))
2948                 return;
2949
2950         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
2951         ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2952
2953         drm_connector_init_with_ddc(dev, connector,
2954                                     &intel_hdmi_connector_funcs,
2955                                     DRM_MODE_CONNECTOR_HDMIA,
2956                                     ddc);
2957         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2958
2959         connector->interlace_allowed = 1;
2960         connector->doublescan_allowed = 0;
2961         connector->stereo_allowed = 1;
2962
2963         if (DISPLAY_VER(dev_priv) >= 10)
2964                 connector->ycbcr_420_allowed = true;
2965
2966         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2967
2968         if (HAS_DDI(dev_priv))
2969                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2970         else
2971                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2972
2973         intel_hdmi_add_properties(intel_hdmi, connector);
2974
2975         intel_connector_attach_encoder(intel_connector, intel_encoder);
2976         intel_hdmi->attached_connector = intel_connector;
2977
2978         if (is_hdcp_supported(dev_priv, port)) {
2979                 int ret = intel_hdcp_init(intel_connector, dig_port,
2980                                           &intel_hdmi_hdcp_shim);
2981                 if (ret)
2982                         drm_dbg_kms(&dev_priv->drm,
2983                                     "HDCP init failed, skipping.\n");
2984         }
2985
2986         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2987          * 0xd.  Failure to do so will result in spurious interrupts being
2988          * generated on the port when a cable is not attached.
2989          */
2990         if (IS_G45(dev_priv)) {
2991                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
2992                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
2993                                (temp & ~0xf) | 0xd);
2994         }
2995
2996         cec_fill_conn_info_from_drm(&conn_info, connector);
2997
2998         intel_hdmi->cec_notifier =
2999                 cec_notifier_conn_register(dev->dev, port_identifier(port),
3000                                            &conn_info);
3001         if (!intel_hdmi->cec_notifier)
3002                 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3003 }
3004
3005 /*
3006  * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3007  * @vactive: Vactive of a display mode
3008  *
3009  * @return: appropriate dsc slice height for a given mode.
3010  */
3011 int intel_hdmi_dsc_get_slice_height(int vactive)
3012 {
3013         int slice_height;
3014
3015         /*
3016          * Slice Height determination : HDMI2.1 Section 7.7.5.2
3017          * Select smallest slice height >=96, that results in a valid PPS and
3018          * requires minimum padding lines required for final slice.
3019          *
3020          * Assumption : Vactive is even.
3021          */
3022         for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3023                 if (vactive % slice_height == 0)
3024                         return slice_height;
3025
3026         return 0;
3027 }
3028
3029 /*
3030  * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3031  * and dsc decoder capabilities
3032  *
3033  * @crtc_state: intel crtc_state
3034  * @src_max_slices: maximum slices supported by the DSC encoder
3035  * @src_max_slice_width: maximum slice width supported by DSC encoder
3036  * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3037  * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3038  *
3039  * @return: num of dsc slices that can be supported by the dsc encoder
3040  * and decoder.
3041  */
3042 int
3043 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3044                               int src_max_slices, int src_max_slice_width,
3045                               int hdmi_max_slices, int hdmi_throughput)
3046 {
3047 /* Pixel rates in KPixels/sec */
3048 #define HDMI_DSC_PEAK_PIXEL_RATE                2720000
3049 /*
3050  * Rates at which the source and sink are required to process pixels in each
3051  * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3052  */
3053 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0           340000
3054 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1           400000
3055
3056 /* Spec limits the slice width to 2720 pixels */
3057 #define MAX_HDMI_SLICE_WIDTH                    2720
3058         int kslice_adjust;
3059         int adjusted_clk_khz;
3060         int min_slices;
3061         int target_slices;
3062         int max_throughput; /* max clock freq. in khz per slice */
3063         int max_slice_width;
3064         int slice_width;
3065         int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3066
3067         if (!hdmi_throughput)
3068                 return 0;
3069
3070         /*
3071          * Slice Width determination : HDMI2.1 Section 7.7.5.1
3072          * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3073          * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3074          * dividing adjusted clock value by 10.
3075          */
3076         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3077             crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3078                 kslice_adjust = 10;
3079         else
3080                 kslice_adjust = 5;
3081
3082         /*
3083          * As per spec, the rate at which the source and the sink process
3084          * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3085          * This depends upon the pixel clock rate and output formats
3086          * (kslice adjust).
3087          * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3088          * at max 340MHz, otherwise they can be processed at max 400MHz.
3089          */
3090
3091         adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3092
3093         if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3094                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3095         else
3096                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3097
3098         /*
3099          * Taking into account the sink's capability for maximum
3100          * clock per slice (in MHz) as read from HF-VSDB.
3101          */
3102         max_throughput = min(max_throughput, hdmi_throughput * 1000);
3103
3104         min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3105         max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3106
3107         /*
3108          * Keep on increasing the num of slices/line, starting from min_slices
3109          * per line till we get such a number, for which the slice_width is
3110          * just less than max_slice_width. The slices/line selected should be
3111          * less than or equal to the max horizontal slices that the combination
3112          * of PCON encoder and HDMI decoder can support.
3113          */
3114         slice_width = max_slice_width;
3115
3116         do {
3117                 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3118                         target_slices = 1;
3119                 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3120                         target_slices = 2;
3121                 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3122                         target_slices = 4;
3123                 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3124                         target_slices = 8;
3125                 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3126                         target_slices = 12;
3127                 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3128                         target_slices = 16;
3129                 else
3130                         return 0;
3131
3132                 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3133                 if (slice_width >= max_slice_width)
3134                         min_slices = target_slices + 1;
3135         } while (slice_width >= max_slice_width);
3136
3137         return target_slices;
3138 }
3139
3140 /*
3141  * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3142  * source and sink capabilities.
3143  *
3144  * @src_fraction_bpp: fractional bpp supported by the source
3145  * @slice_width: dsc slice width supported by the source and sink
3146  * @num_slices: num of slices supported by the source and sink
3147  * @output_format: video output format
3148  * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3149  * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3150  *
3151  * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3152  */
3153 int
3154 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3155                        int output_format, bool hdmi_all_bpp,
3156                        int hdmi_max_chunk_bytes)
3157 {
3158         int max_dsc_bpp, min_dsc_bpp;
3159         int target_bytes;
3160         bool bpp_found = false;
3161         int bpp_decrement_x16;
3162         int bpp_target;
3163         int bpp_target_x16;
3164
3165         /*
3166          * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3167          * Start with the max bpp and keep on decrementing with
3168          * fractional bpp, if supported by PCON DSC encoder
3169          *
3170          * for each bpp we check if no of bytes can be supported by HDMI sink
3171          */
3172
3173         /* Assuming: bpc as 8*/
3174         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3175                 min_dsc_bpp = 6;
3176                 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3177         } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3178                    output_format == INTEL_OUTPUT_FORMAT_RGB) {
3179                 min_dsc_bpp = 8;
3180                 max_dsc_bpp = 3 * 8; /* 3*bpc */
3181         } else {
3182                 /* Assuming 4:2:2 encoding */
3183                 min_dsc_bpp = 7;
3184                 max_dsc_bpp = 2 * 8; /* 2*bpc */
3185         }
3186
3187         /*
3188          * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3189          * Section 7.7.34 : Source shall not enable compressed Video
3190          * Transport with bpp_target settings above 12 bpp unless
3191          * DSC_all_bpp is set to 1.
3192          */
3193         if (!hdmi_all_bpp)
3194                 max_dsc_bpp = min(max_dsc_bpp, 12);
3195
3196         /*
3197          * The Sink has a limit of compressed data in bytes for a scanline,
3198          * as described in max_chunk_bytes field in HFVSDB block of edid.
3199          * The no. of bytes depend on the target bits per pixel that the
3200          * source configures. So we start with the max_bpp and calculate
3201          * the target_chunk_bytes. We keep on decrementing the target_bpp,
3202          * till we get the target_chunk_bytes just less than what the sink's
3203          * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3204          *
3205          * The decrement is according to the fractional support from PCON DSC
3206          * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3207          *
3208          * bpp_target_x16 = bpp_target * 16
3209          * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3210          * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3211          */
3212
3213         bpp_target = max_dsc_bpp;
3214
3215         /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3216         if (!src_fractional_bpp)
3217                 src_fractional_bpp = 1;
3218         bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3219         bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3220
3221         while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3222                 int bpp;
3223
3224                 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3225                 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3226                 if (target_bytes <= hdmi_max_chunk_bytes) {
3227                         bpp_found = true;
3228                         break;
3229                 }
3230                 bpp_target_x16 -= bpp_decrement_x16;
3231         }
3232         if (bpp_found)
3233                 return bpp_target_x16;
3234
3235         return 0;
3236 }