drivers/gpu/drm/i915/display/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include <linux/string_helpers.h>
  42
  43 #include <drm/drm_blend.h>
  44 #include <drm/drm_fourcc.h>
  45
  46 #include "i915_drv.h"
  47 #include "i915_utils.h"
  48 #include "i915_vgpu.h"
  49 #include "intel_cdclk.h"
  50 #include "intel_de.h"
  51 #include "intel_display_trace.h"
  52 #include "intel_display_types.h"
  53 #include "intel_fbc.h"
  54 #include "intel_frontbuffer.h"
  55
  56 #define for_each_fbc_id(__dev_priv, __fbc_id) \
  57         for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
  58                 for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
  59
  60 #define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
  61         for_each_fbc_id((__dev_priv), (__fbc_id)) \
  62                 for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)])
  63
  64 struct intel_fbc_funcs {
  65         void (*activate)(struct intel_fbc *fbc);
  66         void (*deactivate)(struct intel_fbc *fbc);
  67         bool (*is_active)(struct intel_fbc *fbc);
  68         bool (*is_compressing)(struct intel_fbc *fbc);
  69         void (*nuke)(struct intel_fbc *fbc);
  70         void (*program_cfb)(struct intel_fbc *fbc);
  71         void (*set_false_color)(struct intel_fbc *fbc, bool enable);
  72 };
  73
  74 struct intel_fbc_state {
  75         struct intel_plane *plane;
  76         unsigned int cfb_stride;
  77         unsigned int cfb_size;
  78         unsigned int fence_y_offset;
  79         u16 override_cfb_stride;
  80         u16 interval;
  81         s8 fence_id;
  82 };
  83
  84 struct intel_fbc {
  85         struct drm_i915_private *i915;
  86         const struct intel_fbc_funcs *funcs;
  87
  88         /*
  89          * This is always the inner lock when overlapping with
  90          * struct_mutex and it's the outer lock when overlapping
  91          * with stolen_lock.
  92          */
  93         struct mutex lock;
  94         unsigned int busy_bits;
  95
  96         struct drm_mm_node compressed_fb;
  97         struct drm_mm_node compressed_llb;
  98
  99         enum intel_fbc_id id;
 100
 101         u8 limit;
 102
 103         bool false_color;
 104
 105         bool active;
 106         bool activated;
 107         bool flip_pending;
 108
 109         bool underrun_detected;
 110         struct work_struct underrun_work;
 111
 112         /*
 113          * This structure contains everything that's relevant to program the
 114          * hardware registers. When we want to figure out if we need to disable
 115          * and re-enable FBC for a new configuration we just check if there's
 116          * something different in the struct. The genx_fbc_activate functions
 117          * are supposed to read from it in order to program the registers.
 118          */
 119         struct intel_fbc_state state;
 120         const char *no_fbc_reason;
 121 };
 122
 123 /* plane stride in pixels */
 124 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
 125 {
 126         const struct drm_framebuffer *fb = plane_state->hw.fb;
 127         unsigned int stride;
 128
 129         stride = plane_state->view.color_plane[0].mapping_stride;
 130         if (!drm_rotation_90_or_270(plane_state->hw.rotation))
 131                 stride /= fb->format->cpp[0];
 132
 133         return stride;
 134 }
 135
 136 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
 137 static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
 138 {
 139         unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
 140
 141         return intel_fbc_plane_stride(plane_state) * cpp;
 142 }
 143
 144 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
 145 static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state)
 146 {
 147         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 148         unsigned int limit = 4; /* 1:4 compression limit is the worst case */
 149         unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
 150         unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
 151         unsigned int height = 4; /* FBC segment is 4 lines */
 152         unsigned int stride;
 153
 154         /* minimum segment stride we can use */
 155         stride = width * cpp * height / limit;
 156
 157         /*
 158          * Wa_16011863758: icl+
 159          * Avoid some hardware segment address miscalculation.
 160          */
 161         if (DISPLAY_VER(i915) >= 11)
 162                 stride += 64;
 163
 164         /*
 165          * At least some of the platforms require each 4 line segment to
 166          * be 512 byte aligned. Just do it always for simplicity.
 167          */
 168         stride = ALIGN(stride, 512);
 169
 170         /* convert back to single line equivalent with 1:1 compression limit */
 171         return stride * limit / height;
 172 }
 173
 174 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
 175 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
 176 {
 177         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 178         unsigned int stride = _intel_fbc_cfb_stride(plane_state);
 179
 180         /*
 181          * At least some of the platforms require each 4 line segment to
 182          * be 512 byte aligned. Aligning each line to 512 bytes guarantees
 183          * that regardless of the compression limit we choose later.
 184          */
 185         if (DISPLAY_VER(i915) >= 9)
 186                 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state));
 187         else
 188                 return stride;
 189 }
 190
 191 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)
 192 {
 193         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 194         int lines = drm_rect_height(&plane_state->uapi.src) >> 16;
 195
 196         if (DISPLAY_VER(i915) == 7)
 197                 lines = min(lines, 2048);
 198         else if (DISPLAY_VER(i915) >= 8)
 199                 lines = min(lines, 2560);
 200
 201         return lines * intel_fbc_cfb_stride(plane_state);
 202 }
 203
 204 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)
 205 {
 206         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 207         unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
 208         unsigned int stride = _intel_fbc_cfb_stride(plane_state);
 209         const struct drm_framebuffer *fb = plane_state->hw.fb;
 210
 211         /*
 212          * Override stride in 64 byte units per 4 line segment.
 213          *
 214          * Gen9 hw miscalculates cfb stride for linear as
 215          * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
 216          * we always need to use the override there.
 217          */
 218         if (stride != stride_aligned ||
 219             (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR))
 220                 return stride_aligned * 4 / 64;
 221
 222         return 0;
 223 }
 224
 225 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
 226 {
 227         const struct intel_fbc_state *fbc_state = &fbc->state;
 228         struct drm_i915_private *i915 = fbc->i915;
 229         unsigned int cfb_stride;
 230         u32 fbc_ctl;
 231
 232         cfb_stride = fbc_state->cfb_stride / fbc->limit;
 233
 234         /* FBC_CTL wants 32B or 64B units */
 235         if (DISPLAY_VER(i915) == 2)
 236                 cfb_stride = (cfb_stride / 32) - 1;
 237         else
 238                 cfb_stride = (cfb_stride / 64) - 1;
 239
 240         fbc_ctl = FBC_CTL_PERIODIC |
 241                 FBC_CTL_INTERVAL(fbc_state->interval) |
 242                 FBC_CTL_STRIDE(cfb_stride);
 243
 244         if (IS_I945GM(i915))
 245                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 246
 247         if (fbc_state->fence_id >= 0)
 248                 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
 249
 250         return fbc_ctl;
 251 }
 252
 253 static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
 254 {
 255         const struct intel_fbc_state *fbc_state = &fbc->state;
 256         u32 fbc_ctl2;
 257
 258         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
 259                 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
 260
 261         if (fbc_state->fence_id >= 0)
 262                 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
 263
 264         return fbc_ctl2;
 265 }
 266
 267 static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
 268 {
 269         struct drm_i915_private *i915 = fbc->i915;
 270         u32 fbc_ctl;
 271
 272         /* Disable compression */
 273         fbc_ctl = intel_de_read(i915, FBC_CONTROL);
 274         if ((fbc_ctl & FBC_CTL_EN) == 0)
 275                 return;
 276
 277         fbc_ctl &= ~FBC_CTL_EN;
 278         intel_de_write(i915, FBC_CONTROL, fbc_ctl);
 279
 280         /* Wait for compressing bit to clear */
 281         if (intel_de_wait_for_clear(i915, FBC_STATUS,
 282                                     FBC_STAT_COMPRESSING, 10)) {
 283                 drm_dbg_kms(&i915->drm, "FBC idle timed out\n");
 284                 return;
 285         }
 286 }
 287
 288 static void i8xx_fbc_activate(struct intel_fbc *fbc)
 289 {
 290         const struct intel_fbc_state *fbc_state = &fbc->state;
 291         struct drm_i915_private *i915 = fbc->i915;
 292         int i;
 293
 294         /* Clear old tags */
 295         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 296                 intel_de_write(i915, FBC_TAG(i), 0);
 297
 298         if (DISPLAY_VER(i915) == 4) {
 299                 intel_de_write(i915, FBC_CONTROL2,
 300                                i965_fbc_ctl2(fbc));
 301                 intel_de_write(i915, FBC_FENCE_OFF,
 302                                fbc_state->fence_y_offset);
 303         }
 304
 305         intel_de_write(i915, FBC_CONTROL,
 306                        FBC_CTL_EN | i8xx_fbc_ctl(fbc));
 307 }
 308
 309 static bool i8xx_fbc_is_active(struct intel_fbc *fbc)
 310 {
 311         return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN;
 312 }
 313
 314 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
 315 {
 316         return intel_de_read(fbc->i915, FBC_STATUS) &
 317                 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
 318 }
 319
 320 static void i8xx_fbc_nuke(struct intel_fbc *fbc)
 321 {
 322         struct intel_fbc_state *fbc_state = &fbc->state;
 323         enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
 324         struct drm_i915_private *dev_priv = fbc->i915;
 325
 326         spin_lock_irq(&dev_priv->uncore.lock);
 327         intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
 328                           intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
 329         spin_unlock_irq(&dev_priv->uncore.lock);
 330 }
 331
 332 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
 333 {
 334         struct drm_i915_private *i915 = fbc->i915;
 335
 336         GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
 337                                          fbc->compressed_fb.start, U32_MAX));
 338         GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
 339                                          fbc->compressed_llb.start, U32_MAX));
 340
 341         intel_de_write(i915, FBC_CFB_BASE,
 342                        i915->dsm.start + fbc->compressed_fb.start);
 343         intel_de_write(i915, FBC_LL_BASE,
 344                        i915->dsm.start + fbc->compressed_llb.start);
 345 }
 346
 347 static const struct intel_fbc_funcs i8xx_fbc_funcs = {
 348         .activate = i8xx_fbc_activate,
 349         .deactivate = i8xx_fbc_deactivate,
 350         .is_active = i8xx_fbc_is_active,
 351         .is_compressing = i8xx_fbc_is_compressing,
 352         .nuke = i8xx_fbc_nuke,
 353         .program_cfb = i8xx_fbc_program_cfb,
 354 };
 355
 356 static void i965_fbc_nuke(struct intel_fbc *fbc)
 357 {
 358         struct intel_fbc_state *fbc_state = &fbc->state;
 359         enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
 360         struct drm_i915_private *dev_priv = fbc->i915;
 361
 362         spin_lock_irq(&dev_priv->uncore.lock);
 363         intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
 364                           intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
 365         spin_unlock_irq(&dev_priv->uncore.lock);
 366 }
 367
 368 static const struct intel_fbc_funcs i965_fbc_funcs = {
 369         .activate = i8xx_fbc_activate,
 370         .deactivate = i8xx_fbc_deactivate,
 371         .is_active = i8xx_fbc_is_active,
 372         .is_compressing = i8xx_fbc_is_compressing,
 373         .nuke = i965_fbc_nuke,
 374         .program_cfb = i8xx_fbc_program_cfb,
 375 };
 376
 377 static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
 378 {
 379         switch (fbc->limit) {
 380         default:
 381                 MISSING_CASE(fbc->limit);
 382                 fallthrough;
 383         case 1:
 384                 return DPFC_CTL_LIMIT_1X;
 385         case 2:
 386                 return DPFC_CTL_LIMIT_2X;
 387         case 4:
 388                 return DPFC_CTL_LIMIT_4X;
 389         }
 390 }
 391
 392 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
 393 {
 394         const struct intel_fbc_state *fbc_state = &fbc->state;
 395         struct drm_i915_private *i915 = fbc->i915;
 396         u32 dpfc_ctl;
 397
 398         dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
 399                 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
 400
 401         if (IS_G4X(i915))
 402                 dpfc_ctl |= DPFC_CTL_SR_EN;
 403
 404         if (fbc_state->fence_id >= 0) {
 405                 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
 406
 407                 if (DISPLAY_VER(i915) < 6)
 408                         dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
 409         }
 410
 411         return dpfc_ctl;
 412 }
 413
 414 static void g4x_fbc_activate(struct intel_fbc *fbc)
 415 {
 416         const struct intel_fbc_state *fbc_state = &fbc->state;
 417         struct drm_i915_private *i915 = fbc->i915;
 418
 419         intel_de_write(i915, DPFC_FENCE_YOFF,
 420                        fbc_state->fence_y_offset);
 421
 422         intel_de_write(i915, DPFC_CONTROL,
 423                        DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
 424 }
 425
 426 static void g4x_fbc_deactivate(struct intel_fbc *fbc)
 427 {
 428         struct drm_i915_private *i915 = fbc->i915;
 429         u32 dpfc_ctl;
 430
 431         /* Disable compression */
 432         dpfc_ctl = intel_de_read(i915, DPFC_CONTROL);
 433         if (dpfc_ctl & DPFC_CTL_EN) {
 434                 dpfc_ctl &= ~DPFC_CTL_EN;
 435                 intel_de_write(i915, DPFC_CONTROL, dpfc_ctl);
 436         }
 437 }
 438
 439 static bool g4x_fbc_is_active(struct intel_fbc *fbc)
 440 {
 441         return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN;
 442 }
 443
 444 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
 445 {
 446         return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
 447 }
 448
 449 static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
 450 {
 451         struct drm_i915_private *i915 = fbc->i915;
 452
 453         intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start);
 454 }
 455
 456 static const struct intel_fbc_funcs g4x_fbc_funcs = {
 457         .activate = g4x_fbc_activate,
 458         .deactivate = g4x_fbc_deactivate,
 459         .is_active = g4x_fbc_is_active,
 460         .is_compressing = g4x_fbc_is_compressing,
 461         .nuke = i965_fbc_nuke,
 462         .program_cfb = g4x_fbc_program_cfb,
 463 };
 464
 465 static void ilk_fbc_activate(struct intel_fbc *fbc)
 466 {
 467         struct intel_fbc_state *fbc_state = &fbc->state;
 468         struct drm_i915_private *i915 = fbc->i915;
 469
 470         intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
 471                        fbc_state->fence_y_offset);
 472
 473         intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
 474                        DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
 475 }
 476
 477 static void ilk_fbc_deactivate(struct intel_fbc *fbc)
 478 {
 479         struct drm_i915_private *i915 = fbc->i915;
 480         u32 dpfc_ctl;
 481
 482         /* Disable compression */
 483         dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
 484         if (dpfc_ctl & DPFC_CTL_EN) {
 485                 dpfc_ctl &= ~DPFC_CTL_EN;
 486                 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
 487         }
 488 }
 489
 490 static bool ilk_fbc_is_active(struct intel_fbc *fbc)
 491 {
 492         return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
 493 }
 494
 495 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
 496 {
 497         return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
 498 }
 499
 500 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 501 {
 502         struct drm_i915_private *i915 = fbc->i915;
 503
 504         intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
 505 }
 506
 507 static const struct intel_fbc_funcs ilk_fbc_funcs = {
 508         .activate = ilk_fbc_activate,
 509         .deactivate = ilk_fbc_deactivate,
 510         .is_active = ilk_fbc_is_active,
 511         .is_compressing = ilk_fbc_is_compressing,
 512         .nuke = i965_fbc_nuke,
 513         .program_cfb = ilk_fbc_program_cfb,
 514 };
 515
 516 static void snb_fbc_program_fence(struct intel_fbc *fbc)
 517 {
 518         const struct intel_fbc_state *fbc_state = &fbc->state;
 519         struct drm_i915_private *i915 = fbc->i915;
 520         u32 ctl = 0;
 521
 522         if (fbc_state->fence_id >= 0)
 523                 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id);
 524
 525         intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
 526         intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);
 527 }
 528
 529 static void snb_fbc_activate(struct intel_fbc *fbc)
 530 {
 531         snb_fbc_program_fence(fbc);
 532
 533         ilk_fbc_activate(fbc);
 534 }
 535
 536 static void snb_fbc_nuke(struct intel_fbc *fbc)
 537 {
 538         struct drm_i915_private *i915 = fbc->i915;
 539
 540         intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
 541         intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
 542 }
 543
 544 static const struct intel_fbc_funcs snb_fbc_funcs = {
 545         .activate = snb_fbc_activate,
 546         .deactivate = ilk_fbc_deactivate,
 547         .is_active = ilk_fbc_is_active,
 548         .is_compressing = ilk_fbc_is_compressing,
 549         .nuke = snb_fbc_nuke,
 550         .program_cfb = ilk_fbc_program_cfb,
 551 };
 552
 553 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
 554 {
 555         const struct intel_fbc_state *fbc_state = &fbc->state;
 556         struct drm_i915_private *i915 = fbc->i915;
 557         u32 val = 0;
 558
 559         if (fbc_state->override_cfb_stride)
 560                 val |= FBC_STRIDE_OVERRIDE |
 561                         FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
 562
 563         intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
 564 }
 565
 566 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
 567 {
 568         const struct intel_fbc_state *fbc_state = &fbc->state;
 569         struct drm_i915_private *i915 = fbc->i915;
 570         u32 val = 0;
 571
 572         /* Display WA #0529: skl, kbl, bxt. */
 573         if (fbc_state->override_cfb_stride)
 574                 val |= CHICKEN_FBC_STRIDE_OVERRIDE |
 575                         CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
 576
 577         intel_de_rmw(i915, CHICKEN_MISC_4,
 578                      CHICKEN_FBC_STRIDE_OVERRIDE |
 579                      CHICKEN_FBC_STRIDE_MASK, val);
 580 }
 581
 582 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
 583 {
 584         const struct intel_fbc_state *fbc_state = &fbc->state;
 585         struct drm_i915_private *i915 = fbc->i915;
 586         u32 dpfc_ctl;
 587
 588         dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
 589
 590         if (IS_IVYBRIDGE(i915))
 591                 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);
 592
 593         if (fbc_state->fence_id >= 0)
 594                 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
 595
 596         if (fbc->false_color)
 597                 dpfc_ctl |= DPFC_CTL_FALSE_COLOR;
 598
 599         return dpfc_ctl;
 600 }
 601
 602 static void ivb_fbc_activate(struct intel_fbc *fbc)
 603 {
 604         struct drm_i915_private *i915 = fbc->i915;
 605
 606         if (DISPLAY_VER(i915) >= 10)
 607                 glk_fbc_program_cfb_stride(fbc);
 608         else if (DISPLAY_VER(i915) == 9)
 609                 skl_fbc_program_cfb_stride(fbc);
 610
 611         if (to_gt(i915)->ggtt->num_fences)
 612                 snb_fbc_program_fence(fbc);
 613
 614         intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
 615                        DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
 616 }
 617
 618 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
 619 {
 620         return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
 621 }
 622
 623 static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
 624                                     bool enable)
 625 {
 626         intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
 627                      DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
 628 }
 629
 630 static const struct intel_fbc_funcs ivb_fbc_funcs = {
 631         .activate = ivb_fbc_activate,
 632         .deactivate = ilk_fbc_deactivate,
 633         .is_active = ilk_fbc_is_active,
 634         .is_compressing = ivb_fbc_is_compressing,
 635         .nuke = snb_fbc_nuke,
 636         .program_cfb = ilk_fbc_program_cfb,
 637         .set_false_color = ivb_fbc_set_false_color,
 638 };
 639
 640 static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
 641 {
 642         return fbc->funcs->is_active(fbc);
 643 }
 644
 645 static void intel_fbc_hw_activate(struct intel_fbc *fbc)
 646 {
 647         trace_intel_fbc_activate(fbc->state.plane);
 648
 649         fbc->active = true;
 650         fbc->activated = true;
 651
 652         fbc->funcs->activate(fbc);
 653 }
 654
 655 static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
 656 {
 657         trace_intel_fbc_deactivate(fbc->state.plane);
 658
 659         fbc->active = false;
 660
 661         fbc->funcs->deactivate(fbc);
 662 }
 663
 664 static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
 665 {
 666         return fbc->funcs->is_compressing(fbc);
 667 }
 668
 669 static void intel_fbc_nuke(struct intel_fbc *fbc)
 670 {
 671         struct drm_i915_private *i915 = fbc->i915;
 672
 673         drm_WARN_ON(&i915->drm, fbc->flip_pending);
 674
 675         trace_intel_fbc_nuke(fbc->state.plane);
 676
 677         fbc->funcs->nuke(fbc);
 678 }
 679
 680 static void intel_fbc_activate(struct intel_fbc *fbc)
 681 {
 682         intel_fbc_hw_activate(fbc);
 683         intel_fbc_nuke(fbc);
 684
 685         fbc->no_fbc_reason = NULL;
 686 }
 687
 688 static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason)
 689 {
 690         struct drm_i915_private *i915 = fbc->i915;
 691
 692         drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
 693
 694         if (fbc->active)
 695                 intel_fbc_hw_deactivate(fbc);
 696
 697         fbc->no_fbc_reason = reason;
 698 }
 699
 700 static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
 701 {
 702         if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
 703                 return BIT_ULL(28);
 704         else
 705                 return BIT_ULL(32);
 706 }
 707
 708 static u64 intel_fbc_stolen_end(struct drm_i915_private *i915)
 709 {
 710         u64 end;
 711
 712         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 713          * reserved range size, so it always assumes the maximum (8mb) is used.
 714          * If we enable FBC using a CFB on that memory range we'll get FIFO
 715          * underruns, even if that range is not reserved by the BIOS. */
 716         if (IS_BROADWELL(i915) ||
 717             (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)))
 718                 end = resource_size(&i915->dsm) - 8 * 1024 * 1024;
 719         else
 720                 end = U64_MAX;
 721
 722         return min(end, intel_fbc_cfb_base_max(i915));
 723 }
 724
 725 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
 726 {
 727         return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
 728 }
 729
 730 static int intel_fbc_max_limit(struct drm_i915_private *i915)
 731 {
 732         /* WaFbcOnly1to1Ratio:ctg */
 733         if (IS_G4X(i915))
 734                 return 1;
 735
 736         /*
 737          * FBC2 can only do 1:1, 1:2, 1:4, we limit
 738          * FBC1 to the same out of convenience.
 739          */
 740         return 4;
 741 }
 742
 743 static int find_compression_limit(struct intel_fbc *fbc,
 744                                   unsigned int size, int min_limit)
 745 {
 746         struct drm_i915_private *i915 = fbc->i915;
 747         u64 end = intel_fbc_stolen_end(i915);
 748         int ret, limit = min_limit;
 749
 750         size /= limit;
 751
 752         /* Try to over-allocate to reduce reallocations and fragmentation. */
 753         ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
 754                                                    size <<= 1, 4096, 0, end);
 755         if (ret == 0)
 756                 return limit;
 757
 758         for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) {
 759                 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
 760                                                            size >>= 1, 4096, 0, end);
 761                 if (ret == 0)
 762                         return limit;
 763         }
 764
 765         return 0;
 766 }
 767
 768 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
 769                                unsigned int size, int min_limit)
 770 {
 771         struct drm_i915_private *i915 = fbc->i915;
 772         int ret;
 773
 774         drm_WARN_ON(&i915->drm,
 775                     drm_mm_node_allocated(&fbc->compressed_fb));
 776         drm_WARN_ON(&i915->drm,
 777                     drm_mm_node_allocated(&fbc->compressed_llb));
 778
 779         if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) {
 780                 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb,
 781                                                   4096, 4096);
 782                 if (ret)
 783                         goto err;
 784         }
 785
 786         ret = find_compression_limit(fbc, size, min_limit);
 787         if (!ret)
 788                 goto err_llb;
 789         else if (ret > min_limit)
 790                 drm_info_once(&i915->drm,
 791                               "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 792
 793         fbc->limit = ret;
 794
 795         drm_dbg_kms(&i915->drm,
 796                     "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
 797                     fbc->compressed_fb.size, fbc->limit);
 798
 799         return 0;
 800
 801 err_llb:
 802         if (drm_mm_node_allocated(&fbc->compressed_llb))
 803                 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
 804 err:
 805         if (drm_mm_initialized(&i915->mm.stolen))
 806                 drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 807         return -ENOSPC;
 808 }
 809
 810 static void intel_fbc_program_cfb(struct intel_fbc *fbc)
 811 {
 812         fbc->funcs->program_cfb(fbc);
 813 }
 814
 815 static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
 816 {
 817         /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp */
 818         if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915))
 819                 intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
 820                              DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
 821 }
 822
 823 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 824 {
 825         struct drm_i915_private *i915 = fbc->i915;
 826
 827         if (WARN_ON(intel_fbc_hw_is_active(fbc)))
 828                 return;
 829
 830         if (drm_mm_node_allocated(&fbc->compressed_llb))
 831                 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
 832         if (drm_mm_node_allocated(&fbc->compressed_fb))
 833                 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb);
 834 }
 835
 836 void intel_fbc_cleanup(struct drm_i915_private *i915)
 837 {
 838         struct intel_fbc *fbc;
 839         enum intel_fbc_id fbc_id;
 840
 841         for_each_intel_fbc(i915, fbc, fbc_id) {
 842                 mutex_lock(&fbc->lock);
 843                 __intel_fbc_cleanup_cfb(fbc);
 844                 mutex_unlock(&fbc->lock);
 845
 846                 kfree(fbc);
 847         }
 848 }
 849
 850 static bool stride_is_valid(const struct intel_plane_state *plane_state)
 851 {
 852         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 853         const struct drm_framebuffer *fb = plane_state->hw.fb;
 854         unsigned int stride = intel_fbc_plane_stride(plane_state) *
 855                 fb->format->cpp[0];
 856
 857         /* This should have been caught earlier. */
 858         if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0))
 859                 return false;
 860
 861         /* Below are the additional FBC restrictions. */
 862         if (stride < 512)
 863                 return false;
 864
 865         if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3)
 866                 return stride == 4096 || stride == 8192;
 867
 868         if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048)
 869                 return false;
 870
 871         /* Display WA #1105: skl,bxt,kbl,cfl,glk */
 872         if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) &&
 873             fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
 874                 return false;
 875
 876         if (stride > 16384)
 877                 return false;
 878
 879         return true;
 880 }
 881
 882 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
 883 {
 884         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 885         const struct drm_framebuffer *fb = plane_state->hw.fb;
 886
 887         switch (fb->format->format) {
 888         case DRM_FORMAT_XRGB8888:
 889         case DRM_FORMAT_XBGR8888:
 890                 return true;
 891         case DRM_FORMAT_XRGB1555:
 892         case DRM_FORMAT_RGB565:
 893                 /* 16bpp not supported on gen2 */
 894                 if (DISPLAY_VER(i915) == 2)
 895                         return false;
 896                 /* WaFbcOnly1to1Ratio:ctg */
 897                 if (IS_G4X(i915))
 898                         return false;
 899                 return true;
 900         default:
 901                 return false;
 902         }
 903 }
 904
 905 static bool rotation_is_valid(const struct intel_plane_state *plane_state)
 906 {
 907         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 908         const struct drm_framebuffer *fb = plane_state->hw.fb;
 909         unsigned int rotation = plane_state->hw.rotation;
 910
 911         if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 &&
 912             drm_rotation_90_or_270(rotation))
 913                 return false;
 914         else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) &&
 915                  rotation != DRM_MODE_ROTATE_0)
 916                 return false;
 917
 918         return true;
 919 }
 920
 921 /*
 922  * For some reason, the hardware tracking starts looking at whatever we
 923  * programmed as the display plane base address register. It does not look at
 924  * the X and Y offset registers. That's why we include the src x/y offsets
 925  * instead of just looking at the plane size.
 926  */
 927 static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state)
 928 {
 929         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 930         unsigned int effective_w, effective_h, max_w, max_h;
 931
 932         if (DISPLAY_VER(i915) >= 10) {
 933                 max_w = 5120;
 934                 max_h = 4096;
 935         } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) {
 936                 max_w = 4096;
 937                 max_h = 4096;
 938         } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) {
 939                 max_w = 4096;
 940                 max_h = 2048;
 941         } else {
 942                 max_w = 2048;
 943                 max_h = 1536;
 944         }
 945
 946         effective_w = plane_state->view.color_plane[0].x +
 947                 (drm_rect_width(&plane_state->uapi.src) >> 16);
 948         effective_h = plane_state->view.color_plane[0].y +
 949                 (drm_rect_height(&plane_state->uapi.src) >> 16);
 950
 951         return effective_w <= max_w && effective_h <= max_h;
 952 }
 953
 954 static bool tiling_is_valid(const struct intel_plane_state *plane_state)
 955 {
 956         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 957         const struct drm_framebuffer *fb = plane_state->hw.fb;
 958
 959         switch (fb->modifier) {
 960         case DRM_FORMAT_MOD_LINEAR:
 961         case I915_FORMAT_MOD_Y_TILED:
 962         case I915_FORMAT_MOD_Yf_TILED:
 963                 return DISPLAY_VER(i915) >= 9;
 964         case I915_FORMAT_MOD_4_TILED:
 965         case I915_FORMAT_MOD_X_TILED:
 966                 return true;
 967         default:
 968                 return false;
 969         }
 970 }
 971
 972 static void intel_fbc_update_state(struct intel_atomic_state *state,
 973                                    struct intel_crtc *crtc,
 974                                    struct intel_plane *plane)
 975 {
 976         struct drm_i915_private *i915 = to_i915(state->base.dev);
 977         const struct intel_crtc_state *crtc_state =
 978                 intel_atomic_get_new_crtc_state(state, crtc);
 979         const struct intel_plane_state *plane_state =
 980                 intel_atomic_get_new_plane_state(state, plane);
 981         struct intel_fbc *fbc = plane->fbc;
 982         struct intel_fbc_state *fbc_state = &fbc->state;
 983
 984         WARN_ON(plane_state->no_fbc_reason);
 985         WARN_ON(fbc_state->plane && fbc_state->plane != plane);
 986
 987         fbc_state->plane = plane;
 988
 989         /* FBC1 compression interval: arbitrary choice of 1 second */
 990         fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
 991
 992         fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
 993
 994         drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE &&
 995                     !plane_state->ggtt_vma->fence);
 996
 997         if (plane_state->flags & PLANE_HAS_FENCE &&
 998             plane_state->ggtt_vma->fence)
 999                 fbc_state->fence_id = plane_state->ggtt_vma->fence->id;
1000         else
1001                 fbc_state->fence_id = -1;
1002
1003         fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
1004         fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
1005         fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
1006 }
1007
1008 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
1009 {
1010         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1011
1012         /* The use of a CPU fence is one of two ways to detect writes by the
1013          * CPU to the scanout and trigger updates to the FBC.
1014          *
1015          * The other method is by software tracking (see
1016          * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
1017          * the current compressed buffer and recompress it.
1018          *
1019          * Note that is possible for a tiled surface to be unmappable (and
1020          * so have no fence associated with it) due to aperture constraints
1021          * at the time of pinning.
1022          *
1023          * FIXME with 90/270 degree rotation we should use the fence on
1024          * the normal GTT view (the rotated view doesn't even have a
1025          * fence). Would need changes to the FBC fence Y offset as well.
1026          * For now this will effectively disable FBC with 90/270 degree
1027          * rotation.
1028          */
1029         return DISPLAY_VER(i915) >= 9 ||
1030                 (plane_state->flags & PLANE_HAS_FENCE &&
1031                  plane_state->ggtt_vma->fence);
1032 }
1033
1034 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
1035 {
1036         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1037         struct intel_fbc *fbc = plane->fbc;
1038
1039         return intel_fbc_min_limit(plane_state) <= fbc->limit &&
1040                 intel_fbc_cfb_size(plane_state) <= fbc->compressed_fb.size * fbc->limit;
1041 }
1042
1043 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
1044 {
1045         return !plane_state->no_fbc_reason &&
1046                 intel_fbc_is_fence_ok(plane_state) &&
1047                 intel_fbc_is_cfb_ok(plane_state);
1048 }
1049
1050 static int intel_fbc_check_plane(struct intel_atomic_state *state,
1051                                  struct intel_plane *plane)
1052 {
1053         struct drm_i915_private *i915 = to_i915(state->base.dev);
1054         struct intel_plane_state *plane_state =
1055                 intel_atomic_get_new_plane_state(state, plane);
1056         const struct drm_framebuffer *fb = plane_state->hw.fb;
1057         struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1058         const struct intel_crtc_state *crtc_state;
1059         struct intel_fbc *fbc = plane->fbc;
1060
1061         if (!fbc)
1062                 return 0;
1063
1064         if (intel_vgpu_active(i915)) {
1065                 plane_state->no_fbc_reason = "VGPU active";
1066                 return 0;
1067         }
1068
1069         if (!i915->params.enable_fbc) {
1070                 plane_state->no_fbc_reason = "disabled per module param or by default";
1071                 return 0;
1072         }
1073
1074         if (!plane_state->uapi.visible) {
1075                 plane_state->no_fbc_reason = "plane not visible";
1076                 return 0;
1077         }
1078
1079         crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1080
1081         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1082                 plane_state->no_fbc_reason = "interlaced mode not supported";
1083                 return 0;
1084         }
1085
1086         if (crtc_state->double_wide) {
1087                 plane_state->no_fbc_reason = "double wide pipe not supported";
1088                 return 0;
1089         }
1090
1091         /*
1092          * Display 12+ is not supporting FBC with PSR2.
1093          * Recommendation is to keep this combination disabled
1094          * Bspec: 50422 HSD: 14010260002
1095          */
1096         if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
1097                 plane_state->no_fbc_reason = "PSR2 enabled";
1098                 return 0;
1099         }
1100
1101         /* Wa_14016291713 */
1102         if (IS_DISPLAY_VER(i915, 12, 13) && crtc_state->has_psr) {
1103                 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
1104                 return 0;
1105         }
1106
1107         if (!pixel_format_is_valid(plane_state)) {
1108                 plane_state->no_fbc_reason = "pixel format not supported";
1109                 return 0;
1110         }
1111
1112         if (!tiling_is_valid(plane_state)) {
1113                 plane_state->no_fbc_reason = "tiling not supported";
1114                 return 0;
1115         }
1116
1117         if (!rotation_is_valid(plane_state)) {
1118                 plane_state->no_fbc_reason = "rotation not supported";
1119                 return 0;
1120         }
1121
1122         if (!stride_is_valid(plane_state)) {
1123                 plane_state->no_fbc_reason = "stride not supported";
1124                 return 0;
1125         }
1126
1127         if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
1128             fb->format->has_alpha) {
1129                 plane_state->no_fbc_reason = "per-pixel alpha not supported";
1130                 return 0;
1131         }
1132
1133         if (!intel_fbc_hw_tracking_covers_screen(plane_state)) {
1134                 plane_state->no_fbc_reason = "plane size too big";
1135                 return 0;
1136         }
1137
1138         /*
1139          * Work around a problem on GEN9+ HW, where enabling FBC on a plane
1140          * having a Y offset that isn't divisible by 4 causes FIFO underrun
1141          * and screen flicker.
1142          */
1143         if (DISPLAY_VER(i915) >= 9 &&
1144             plane_state->view.color_plane[0].y & 3) {
1145                 plane_state->no_fbc_reason = "plane start Y offset misaligned";
1146                 return 0;
1147         }
1148
1149         /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
1150         if (DISPLAY_VER(i915) >= 11 &&
1151             (plane_state->view.color_plane[0].y +
1152              (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
1153                 plane_state->no_fbc_reason = "plane end Y offset misaligned";
1154                 return 0;
1155         }
1156
1157         /* WaFbcExceedCdClockThreshold:hsw,bdw */
1158         if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1159                 const struct intel_cdclk_state *cdclk_state;
1160
1161                 cdclk_state = intel_atomic_get_cdclk_state(state);
1162                 if (IS_ERR(cdclk_state))
1163                         return PTR_ERR(cdclk_state);
1164
1165                 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
1166                         plane_state->no_fbc_reason = "pixel rate too high";
1167                         return 0;
1168                 }
1169         }
1170
1171         plane_state->no_fbc_reason = NULL;
1172
1173         return 0;
1174 }
1175
1176
1177 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
1178                                     struct intel_crtc *crtc,
1179                                     struct intel_plane *plane)
1180 {
1181         const struct intel_crtc_state *new_crtc_state =
1182                 intel_atomic_get_new_crtc_state(state, crtc);
1183         const struct intel_plane_state *old_plane_state =
1184                 intel_atomic_get_old_plane_state(state, plane);
1185         const struct intel_plane_state *new_plane_state =
1186                 intel_atomic_get_new_plane_state(state, plane);
1187         const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
1188         const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
1189
1190         if (drm_atomic_crtc_needs_modeset(&new_crtc_state->uapi))
1191                 return false;
1192
1193         if (!intel_fbc_is_ok(old_plane_state) ||
1194             !intel_fbc_is_ok(new_plane_state))
1195                 return false;
1196
1197         if (old_fb->format->format != new_fb->format->format)
1198                 return false;
1199
1200         if (old_fb->modifier != new_fb->modifier)
1201                 return false;
1202
1203         if (intel_fbc_plane_stride(old_plane_state) !=
1204             intel_fbc_plane_stride(new_plane_state))
1205                 return false;
1206
1207         if (intel_fbc_cfb_stride(old_plane_state) !=
1208             intel_fbc_cfb_stride(new_plane_state))
1209                 return false;
1210
1211         if (intel_fbc_cfb_size(old_plane_state) !=
1212             intel_fbc_cfb_size(new_plane_state))
1213                 return false;
1214
1215         if (intel_fbc_override_cfb_stride(old_plane_state) !=
1216             intel_fbc_override_cfb_stride(new_plane_state))
1217                 return false;
1218
1219         return true;
1220 }
1221
1222 static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
1223                                    struct intel_crtc *crtc,
1224                                    struct intel_plane *plane)
1225 {
1226         struct drm_i915_private *i915 = to_i915(state->base.dev);
1227         struct intel_fbc *fbc = plane->fbc;
1228         bool need_vblank_wait = false;
1229
1230         fbc->flip_pending = true;
1231
1232         if (intel_fbc_can_flip_nuke(state, crtc, plane))
1233                 return need_vblank_wait;
1234
1235         intel_fbc_deactivate(fbc, "update pending");
1236
1237         /*
1238          * Display WA #1198: glk+
1239          * Need an extra vblank wait between FBC disable and most plane
1240          * updates. Bspec says this is only needed for plane disable, but
1241          * that is not true. Touching most plane registers will cause the
1242          * corruption to appear. Also SKL/derivatives do not seem to be
1243          * affected.
1244          *
1245          * TODO: could optimize this a bit by sampling the frame
1246          * counter when we disable FBC (if it was already done earlier)
1247          * and skipping the extra vblank wait before the plane update
1248          * if at least one frame has already passed.
1249          */
1250         if (fbc->activated && DISPLAY_VER(i915) >= 10)
1251                 need_vblank_wait = true;
1252         fbc->activated = false;
1253
1254         return need_vblank_wait;
1255 }
1256
1257 bool intel_fbc_pre_update(struct intel_atomic_state *state,
1258                           struct intel_crtc *crtc)
1259 {
1260         const struct intel_plane_state *plane_state;
1261         bool need_vblank_wait = false;
1262         struct intel_plane *plane;
1263         int i;
1264
1265         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1266                 struct intel_fbc *fbc = plane->fbc;
1267
1268                 if (!fbc || plane->pipe != crtc->pipe)
1269                         continue;
1270
1271                 mutex_lock(&fbc->lock);
1272
1273                 if (fbc->state.plane == plane)
1274                         need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
1275
1276                 mutex_unlock(&fbc->lock);
1277         }
1278
1279         return need_vblank_wait;
1280 }
1281
1282 static void __intel_fbc_disable(struct intel_fbc *fbc)
1283 {
1284         struct drm_i915_private *i915 = fbc->i915;
1285         struct intel_plane *plane = fbc->state.plane;
1286
1287         drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
1288         drm_WARN_ON(&i915->drm, fbc->active);
1289
1290         drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
1291                     plane->base.base.id, plane->base.name);
1292
1293         __intel_fbc_cleanup_cfb(fbc);
1294
1295         fbc->state.plane = NULL;
1296         fbc->flip_pending = false;
1297         fbc->busy_bits = 0;
1298 }
1299
1300 static void __intel_fbc_post_update(struct intel_fbc *fbc)
1301 {
1302         struct drm_i915_private *i915 = fbc->i915;
1303
1304         drm_WARN_ON(&i915->drm, !mutex_is_locked(&fbc->lock));
1305
1306         if (!fbc->busy_bits)
1307                 intel_fbc_activate(fbc);
1308         else
1309                 intel_fbc_deactivate(fbc, "frontbuffer write");
1310 }
1311
1312 void intel_fbc_post_update(struct intel_atomic_state *state,
1313                            struct intel_crtc *crtc)
1314 {
1315         const struct intel_plane_state *plane_state;
1316         struct intel_plane *plane;
1317         int i;
1318
1319         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1320                 struct intel_fbc *fbc = plane->fbc;
1321
1322                 if (!fbc || plane->pipe != crtc->pipe)
1323                         continue;
1324
1325                 mutex_lock(&fbc->lock);
1326
1327                 if (fbc->state.plane == plane) {
1328                         fbc->flip_pending = false;
1329                         __intel_fbc_post_update(fbc);
1330                 }
1331
1332                 mutex_unlock(&fbc->lock);
1333         }
1334 }
1335
1336 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1337 {
1338         if (fbc->state.plane)
1339                 return fbc->state.plane->frontbuffer_bit;
1340         else
1341                 return 0;
1342 }
1343
1344 static void __intel_fbc_invalidate(struct intel_fbc *fbc,
1345                                    unsigned int frontbuffer_bits,
1346                                    enum fb_op_origin origin)
1347 {
1348         if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1349                 return;
1350
1351         mutex_lock(&fbc->lock);
1352
1353         frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1354         if (!frontbuffer_bits)
1355                 goto out;
1356
1357         fbc->busy_bits |= frontbuffer_bits;
1358         intel_fbc_deactivate(fbc, "frontbuffer write");
1359
1360 out:
1361         mutex_unlock(&fbc->lock);
1362 }
1363
1364 void intel_fbc_invalidate(struct drm_i915_private *i915,
1365                           unsigned int frontbuffer_bits,
1366                           enum fb_op_origin origin)
1367 {
1368         struct intel_fbc *fbc;
1369         enum intel_fbc_id fbc_id;
1370
1371         for_each_intel_fbc(i915, fbc, fbc_id)
1372                 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
1373
1374 }
1375
1376 static void __intel_fbc_flush(struct intel_fbc *fbc,
1377                               unsigned int frontbuffer_bits,
1378                               enum fb_op_origin origin)
1379 {
1380         mutex_lock(&fbc->lock);
1381
1382         frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1383         if (!frontbuffer_bits)
1384                 goto out;
1385
1386         fbc->busy_bits &= ~frontbuffer_bits;
1387
1388         if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1389                 goto out;
1390
1391         if (fbc->busy_bits || fbc->flip_pending)
1392                 goto out;
1393
1394         if (fbc->active)
1395                 intel_fbc_nuke(fbc);
1396         else
1397                 intel_fbc_activate(fbc);
1398
1399 out:
1400         mutex_unlock(&fbc->lock);
1401 }
1402
1403 void intel_fbc_flush(struct drm_i915_private *i915,
1404                      unsigned int frontbuffer_bits,
1405                      enum fb_op_origin origin)
1406 {
1407         struct intel_fbc *fbc;
1408         enum intel_fbc_id fbc_id;
1409
1410         for_each_intel_fbc(i915, fbc, fbc_id)
1411                 __intel_fbc_flush(fbc, frontbuffer_bits, origin);
1412 }
1413
1414 int intel_fbc_atomic_check(struct intel_atomic_state *state)
1415 {
1416         struct intel_plane_state *plane_state;
1417         struct intel_plane *plane;
1418         int i;
1419
1420         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1421                 int ret;
1422
1423                 ret = intel_fbc_check_plane(state, plane);
1424                 if (ret)
1425                         return ret;
1426         }
1427
1428         return 0;
1429 }
1430
1431 static void __intel_fbc_enable(struct intel_atomic_state *state,
1432                                struct intel_crtc *crtc,
1433                                struct intel_plane *plane)
1434 {
1435         struct drm_i915_private *i915 = to_i915(state->base.dev);
1436         const struct intel_plane_state *plane_state =
1437                 intel_atomic_get_new_plane_state(state, plane);
1438         struct intel_fbc *fbc = plane->fbc;
1439
1440         if (fbc->state.plane) {
1441                 if (fbc->state.plane != plane)
1442                         return;
1443
1444                 if (intel_fbc_is_ok(plane_state)) {
1445                         intel_fbc_update_state(state, crtc, plane);
1446                         return;
1447                 }
1448
1449                 __intel_fbc_disable(fbc);
1450         }
1451
1452         drm_WARN_ON(&i915->drm, fbc->active);
1453
1454         fbc->no_fbc_reason = plane_state->no_fbc_reason;
1455         if (fbc->no_fbc_reason)
1456                 return;
1457
1458         if (!intel_fbc_is_fence_ok(plane_state)) {
1459                 fbc->no_fbc_reason = "framebuffer not fenced";
1460                 return;
1461         }
1462
1463         if (fbc->underrun_detected) {
1464                 fbc->no_fbc_reason = "FIFO underrun";
1465                 return;
1466         }
1467
1468         if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
1469                                 intel_fbc_min_limit(plane_state))) {
1470                 fbc->no_fbc_reason = "not enough stolen memory";
1471                 return;
1472         }
1473
1474         drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n",
1475                     plane->base.base.id, plane->base.name);
1476         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1477
1478         intel_fbc_update_state(state, crtc, plane);
1479
1480         intel_fbc_program_workarounds(fbc);
1481         intel_fbc_program_cfb(fbc);
1482 }
1483
1484 /**
1485  * intel_fbc_disable - disable FBC if it's associated with crtc
1486  * @crtc: the CRTC
1487  *
1488  * This function disables FBC if it's associated with the provided CRTC.
1489  */
1490 void intel_fbc_disable(struct intel_crtc *crtc)
1491 {
1492         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1493         struct intel_plane *plane;
1494
1495         for_each_intel_plane(&i915->drm, plane) {
1496                 struct intel_fbc *fbc = plane->fbc;
1497
1498                 if (!fbc || plane->pipe != crtc->pipe)
1499                         continue;
1500
1501                 mutex_lock(&fbc->lock);
1502                 if (fbc->state.plane == plane)
1503                         __intel_fbc_disable(fbc);
1504                 mutex_unlock(&fbc->lock);
1505         }
1506 }
1507
1508 void intel_fbc_update(struct intel_atomic_state *state,
1509                       struct intel_crtc *crtc)
1510 {
1511         const struct intel_crtc_state *crtc_state =
1512                 intel_atomic_get_new_crtc_state(state, crtc);
1513         const struct intel_plane_state *plane_state;
1514         struct intel_plane *plane;
1515         int i;
1516
1517         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1518                 struct intel_fbc *fbc = plane->fbc;
1519
1520                 if (!fbc || plane->pipe != crtc->pipe)
1521                         continue;
1522
1523                 mutex_lock(&fbc->lock);
1524
1525                 if (crtc_state->update_pipe && plane_state->no_fbc_reason) {
1526                         if (fbc->state.plane == plane)
1527                                 __intel_fbc_disable(fbc);
1528                 } else {
1529                         __intel_fbc_enable(state, crtc, plane);
1530                 }
1531
1532                 mutex_unlock(&fbc->lock);
1533         }
1534 }
1535
1536 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1537 {
1538         struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work);
1539         struct drm_i915_private *i915 = fbc->i915;
1540
1541         mutex_lock(&fbc->lock);
1542
1543         /* Maybe we were scheduled twice. */
1544         if (fbc->underrun_detected || !fbc->state.plane)
1545                 goto out;
1546
1547         drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
1548         fbc->underrun_detected = true;
1549
1550         intel_fbc_deactivate(fbc, "FIFO underrun");
1551         if (!fbc->flip_pending)
1552                 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, fbc->state.plane->pipe));
1553         __intel_fbc_disable(fbc);
1554 out:
1555         mutex_unlock(&fbc->lock);
1556 }
1557
1558 static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
1559 {
1560         struct drm_i915_private *i915 = fbc->i915;
1561
1562         cancel_work_sync(&fbc->underrun_work);
1563
1564         mutex_lock(&fbc->lock);
1565
1566         if (fbc->underrun_detected) {
1567                 drm_dbg_kms(&i915->drm,
1568                             "Re-allowing FBC after fifo underrun\n");
1569                 fbc->no_fbc_reason = "FIFO underrun cleared";
1570         }
1571
1572         fbc->underrun_detected = false;
1573         mutex_unlock(&fbc->lock);
1574 }
1575
1576 /*
1577  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1578  * @i915: the i915 device
1579  *
1580  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1581  * want to re-enable FBC after an underrun to increase test coverage.
1582  */
1583 void intel_fbc_reset_underrun(struct drm_i915_private *i915)
1584 {
1585         struct intel_fbc *fbc;
1586         enum intel_fbc_id fbc_id;
1587
1588         for_each_intel_fbc(i915, fbc, fbc_id)
1589                 __intel_fbc_reset_underrun(fbc);
1590 }
1591
1592 static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
1593 {
1594         /*
1595          * There's no guarantee that underrun_detected won't be set to true
1596          * right after this check and before the work is scheduled, but that's
1597          * not a problem since we'll check it again under the work function
1598          * while FBC is locked. This check here is just to prevent us from
1599          * unnecessarily scheduling the work, and it relies on the fact that we
1600          * never switch underrun_detect back to false after it's true.
1601          */
1602         if (READ_ONCE(fbc->underrun_detected))
1603                 return;
1604
1605         schedule_work(&fbc->underrun_work);
1606 }
1607
1608 /**
1609  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1610  * @i915: i915 device
1611  *
1612  * Without FBC, most underruns are harmless and don't really cause too many
1613  * problems, except for an annoying message on dmesg. With FBC, underruns can
1614  * become black screens or even worse, especially when paired with bad
1615  * watermarks. So in order for us to be on the safe side, completely disable FBC
1616  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1617  * already suggests that watermarks may be bad, so try to be as safe as
1618  * possible.
1619  *
1620  * This function is called from the IRQ handler.
1621  */
1622 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
1623 {
1624         struct intel_fbc *fbc;
1625         enum intel_fbc_id fbc_id;
1626
1627         for_each_intel_fbc(i915, fbc, fbc_id)
1628                 __intel_fbc_handle_fifo_underrun_irq(fbc);
1629 }
1630
1631 /*
1632  * The DDX driver changes its behavior depending on the value it reads from
1633  * i915.enable_fbc, so sanitize it by translating the default value into either
1634  * 0 or 1 in order to allow it to know what's going on.
1635  *
1636  * Notice that this is done at driver initialization and we still allow user
1637  * space to change the value during runtime without sanitizing it again. IGT
1638  * relies on being able to change i915.enable_fbc at runtime.
1639  */
1640 static int intel_sanitize_fbc_option(struct drm_i915_private *i915)
1641 {
1642         if (i915->params.enable_fbc >= 0)
1643                 return !!i915->params.enable_fbc;
1644
1645         if (!HAS_FBC(i915))
1646                 return 0;
1647
1648         if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9)
1649                 return 1;
1650
1651         return 0;
1652 }
1653
1654 static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
1655 {
1656         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1657         if (i915_vtd_active(i915) &&
1658             (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
1659                 drm_info(&i915->drm,
1660                          "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1661                 return true;
1662         }
1663
1664         return false;
1665 }
1666
1667 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
1668 {
1669         plane->fbc = fbc;
1670 }
1671
1672 static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
1673                                           enum intel_fbc_id fbc_id)
1674 {
1675         struct intel_fbc *fbc;
1676
1677         fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
1678         if (!fbc)
1679                 return NULL;
1680
1681         fbc->id = fbc_id;
1682         fbc->i915 = i915;
1683         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1684         mutex_init(&fbc->lock);
1685
1686         if (DISPLAY_VER(i915) >= 7)
1687                 fbc->funcs = &ivb_fbc_funcs;
1688         else if (DISPLAY_VER(i915) == 6)
1689                 fbc->funcs = &snb_fbc_funcs;
1690         else if (DISPLAY_VER(i915) == 5)
1691                 fbc->funcs = &ilk_fbc_funcs;
1692         else if (IS_G4X(i915))
1693                 fbc->funcs = &g4x_fbc_funcs;
1694         else if (DISPLAY_VER(i915) == 4)
1695                 fbc->funcs = &i965_fbc_funcs;
1696         else
1697                 fbc->funcs = &i8xx_fbc_funcs;
1698
1699         return fbc;
1700 }
1701
1702 /**
1703  * intel_fbc_init - Initialize FBC
1704  * @i915: the i915 device
1705  *
1706  * This function might be called during PM init process.
1707  */
1708 void intel_fbc_init(struct drm_i915_private *i915)
1709 {
1710         enum intel_fbc_id fbc_id;
1711
1712         if (!drm_mm_initialized(&i915->mm.stolen))
1713                 RUNTIME_INFO(i915)->fbc_mask = 0;
1714
1715         if (need_fbc_vtd_wa(i915))
1716                 RUNTIME_INFO(i915)->fbc_mask = 0;
1717
1718         i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
1719         drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
1720                     i915->params.enable_fbc);
1721
1722         for_each_fbc_id(i915, fbc_id)
1723                 i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
1724 }
1725
1726 /**
1727  * intel_fbc_sanitize - Sanitize FBC
1728  * @i915: the i915 device
1729  *
1730  * Make sure FBC is initially disabled since we have no
1731  * idea eg. into which parts of stolen it might be scribbling
1732  * into.
1733  */
1734 void intel_fbc_sanitize(struct drm_i915_private *i915)
1735 {
1736         struct intel_fbc *fbc;
1737         enum intel_fbc_id fbc_id;
1738
1739         for_each_intel_fbc(i915, fbc, fbc_id) {
1740                 if (intel_fbc_hw_is_active(fbc))
1741                         intel_fbc_hw_deactivate(fbc);
1742         }
1743 }
1744
1745 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
1746 {
1747         struct intel_fbc *fbc = m->private;
1748         struct drm_i915_private *i915 = fbc->i915;
1749         struct intel_plane *plane;
1750         intel_wakeref_t wakeref;
1751
1752         drm_modeset_lock_all(&i915->drm);
1753
1754         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1755         mutex_lock(&fbc->lock);
1756
1757         if (fbc->active) {
1758                 seq_puts(m, "FBC enabled\n");
1759                 seq_printf(m, "Compressing: %s\n",
1760                            str_yes_no(intel_fbc_is_compressing(fbc)));
1761         } else {
1762                 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1763         }
1764
1765         for_each_intel_plane(&i915->drm, plane) {
1766                 const struct intel_plane_state *plane_state =
1767                         to_intel_plane_state(plane->base.state);
1768
1769                 if (plane->fbc != fbc)
1770                         continue;
1771
1772                 seq_printf(m, "%c [PLANE:%d:%s]: %s\n",
1773                            fbc->state.plane == plane ? '*' : ' ',
1774                            plane->base.base.id, plane->base.name,
1775                            plane_state->no_fbc_reason ?: "FBC possible");
1776         }
1777
1778         mutex_unlock(&fbc->lock);
1779         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1780
1781         drm_modeset_unlock_all(&i915->drm);
1782
1783         return 0;
1784 }
1785
1786 DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
1787
1788 static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
1789 {
1790         struct intel_fbc *fbc = data;
1791
1792         *val = fbc->false_color;
1793
1794         return 0;
1795 }
1796
1797 static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
1798 {
1799         struct intel_fbc *fbc = data;
1800
1801         mutex_lock(&fbc->lock);
1802
1803         fbc->false_color = val;
1804
1805         if (fbc->active)
1806                 fbc->funcs->set_false_color(fbc, fbc->false_color);
1807
1808         mutex_unlock(&fbc->lock);
1809
1810         return 0;
1811 }
1812
1813 DEFINE_SIMPLE_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
1814                         intel_fbc_debugfs_false_color_get,
1815                         intel_fbc_debugfs_false_color_set,
1816                         "%llu\n");
1817
1818 static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
1819                                   struct dentry *parent)
1820 {
1821         debugfs_create_file("i915_fbc_status", 0444, parent,
1822                             fbc, &intel_fbc_debugfs_status_fops);
1823
1824         if (fbc->funcs->set_false_color)
1825                 debugfs_create_file("i915_fbc_false_color", 0644, parent,
1826                                     fbc, &intel_fbc_debugfs_false_color_fops);
1827 }
1828
1829 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
1830 {
1831         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1832
1833         if (plane->fbc)
1834                 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
1835 }
1836
1837 /* FIXME: remove this once igt is on board with per-crtc stuff */
1838 void intel_fbc_debugfs_register(struct drm_i915_private *i915)
1839 {
1840         struct drm_minor *minor = i915->drm.primary;
1841         struct intel_fbc *fbc;
1842
1843         fbc = i915->display.fbc[INTEL_FBC_A];
1844         if (fbc)
1845                 intel_fbc_debugfs_add(fbc, minor->debugfs_root);
1846 }