drivers/gpu/drm/i915/display/intel_atomic_plane.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic plane helpers
  26  *
  27  * The functions here are used by the atomic plane helper functions to
  28  * implement legacy plane updates (i.e., drm_plane->update_plane() and
  29  * drm_plane->disable_plane()).  This allows plane updates to use the
  30  * atomic state infrastructure and perform plane updates as separate
  31  * prepare/check/commit/cleanup steps.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_fourcc.h>
  36
  37 #include "gt/intel_rps.h"
  38
  39 #include "intel_atomic_plane.h"
  40 #include "intel_cdclk.h"
  41 #include "intel_display_trace.h"
  42 #include "intel_display_types.h"
  43 #include "intel_fb.h"
  44 #include "intel_fb_pin.h"
  45 #include "intel_sprite.h"
  46 #include "skl_scaler.h"
  47 #include "skl_watermark.h"
  48
  49 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
  50                                     struct intel_plane *plane)
  51 {
  52         memset(plane_state, 0, sizeof(*plane_state));
  53
  54         __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
  55
  56         plane_state->scaler_id = -1;
  57 }
  58
  59 struct intel_plane *intel_plane_alloc(void)
  60 {
  61         struct intel_plane_state *plane_state;
  62         struct intel_plane *plane;
  63
  64         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
  65         if (!plane)
  66                 return ERR_PTR(-ENOMEM);
  67
  68         plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
  69         if (!plane_state) {
  70                 kfree(plane);
  71                 return ERR_PTR(-ENOMEM);
  72         }
  73
  74         intel_plane_state_reset(plane_state, plane);
  75
  76         plane->base.state = &plane_state->uapi;
  77
  78         return plane;
  79 }
  80
  81 void intel_plane_free(struct intel_plane *plane)
  82 {
  83         intel_plane_destroy_state(&plane->base, plane->base.state);
  84         kfree(plane);
  85 }
  86
  87 /**
  88  * intel_plane_duplicate_state - duplicate plane state
  89  * @plane: drm plane
  90  *
  91  * Allocates and returns a copy of the plane state (both common and
  92  * Intel-specific) for the specified plane.
  93  *
  94  * Returns: The newly allocated plane state, or NULL on failure.
  95  */
  96 struct drm_plane_state *
  97 intel_plane_duplicate_state(struct drm_plane *plane)
  98 {
  99         struct intel_plane_state *intel_state;
 100
 101         intel_state = to_intel_plane_state(plane->state);
 102         intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
 103
 104         if (!intel_state)
 105                 return NULL;
 106
 107         __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
 108
 109         intel_state->ggtt_vma = NULL;
 110         intel_state->dpt_vma = NULL;
 111         intel_state->flags = 0;
 112
 113         /* add reference to fb */
 114         if (intel_state->hw.fb)
 115                 drm_framebuffer_get(intel_state->hw.fb);
 116
 117         return &intel_state->uapi;
 118 }
 119
 120 /**
 121  * intel_plane_destroy_state - destroy plane state
 122  * @plane: drm plane
 123  * @state: state object to destroy
 124  *
 125  * Destroys the plane state (both common and Intel-specific) for the
 126  * specified plane.
 127  */
 128 void
 129 intel_plane_destroy_state(struct drm_plane *plane,
 130                           struct drm_plane_state *state)
 131 {
 132         struct intel_plane_state *plane_state = to_intel_plane_state(state);
 133
 134         drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
 135         drm_WARN_ON(plane->dev, plane_state->dpt_vma);
 136
 137         __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
 138         if (plane_state->hw.fb)
 139                 drm_framebuffer_put(plane_state->hw.fb);
 140         kfree(plane_state);
 141 }
 142
 143 unsigned int intel_adjusted_rate(const struct drm_rect *src,
 144                                  const struct drm_rect *dst,
 145                                  unsigned int rate)
 146 {
 147         unsigned int src_w, src_h, dst_w, dst_h;
 148
 149         src_w = drm_rect_width(src) >> 16;
 150         src_h = drm_rect_height(src) >> 16;
 151         dst_w = drm_rect_width(dst);
 152         dst_h = drm_rect_height(dst);
 153
 154         /* Downscaling limits the maximum pixel rate */
 155         dst_w = min(src_w, dst_w);
 156         dst_h = min(src_h, dst_h);
 157
 158         return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
 159                                 dst_w * dst_h);
 160 }
 161
 162 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
 163                                     const struct intel_plane_state *plane_state)
 164 {
 165         /*
 166          * Note we don't check for plane visibility here as
 167          * we want to use this when calculating the cursor
 168          * watermarks even if the cursor is fully offscreen.
 169          * That depends on the src/dst rectangles being
 170          * correctly populated whenever the watermark code
 171          * considers the cursor to be visible, whether or not
 172          * it is actually visible.
 173          *
 174          * See: intel_wm_plane_visible() and intel_check_cursor()
 175          */
 176
 177         return intel_adjusted_rate(&plane_state->uapi.src,
 178                                    &plane_state->uapi.dst,
 179                                    crtc_state->pixel_rate);
 180 }
 181
 182 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 183                                    const struct intel_plane_state *plane_state,
 184                                    int color_plane)
 185 {
 186         const struct drm_framebuffer *fb = plane_state->hw.fb;
 187
 188         if (!plane_state->uapi.visible)
 189                 return 0;
 190
 191         return intel_plane_pixel_rate(crtc_state, plane_state) *
 192                 fb->format->cpp[color_plane];
 193 }
 194
 195 static bool
 196 use_min_ddb(const struct intel_crtc_state *crtc_state,
 197             struct intel_plane *plane)
 198 {
 199         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 200
 201         return DISPLAY_VER(i915) >= 13 &&
 202                crtc_state->uapi.async_flip &&
 203                plane->async_flip;
 204 }
 205
 206 static unsigned int
 207 intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 208                                const struct intel_plane_state *plane_state,
 209                                int color_plane)
 210 {
 211         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 212         const struct drm_framebuffer *fb = plane_state->hw.fb;
 213         int width, height;
 214
 215         if (plane->id == PLANE_CURSOR)
 216                 return 0;
 217
 218         if (!plane_state->uapi.visible)
 219                 return 0;
 220
 221         /*
 222          * We calculate extra ddb based on ratio plane rate/total data rate
 223          * in case, in some cases we should not allocate extra ddb for the plane,
 224          * so do not count its data rate, if this is the case.
 225          */
 226         if (use_min_ddb(crtc_state, plane))
 227                 return 0;
 228
 229         /*
 230          * Src coordinates are already rotated by 270 degrees for
 231          * the 90/270 degree plane rotation cases (to match the
 232          * GTT mapping), hence no need to account for rotation here.
 233          */
 234         width = drm_rect_width(&plane_state->uapi.src) >> 16;
 235         height = drm_rect_height(&plane_state->uapi.src) >> 16;
 236
 237         /* UV plane does 1/2 pixel sub-sampling */
 238         if (color_plane == 1) {
 239                 width /= 2;
 240                 height /= 2;
 241         }
 242
 243         return width * height * fb->format->cpp[color_plane];
 244 }
 245
 246 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 247                                struct intel_plane *plane,
 248                                bool *need_cdclk_calc)
 249 {
 250         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 251         const struct intel_plane_state *plane_state =
 252                 intel_atomic_get_new_plane_state(state, plane);
 253         struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
 254         const struct intel_cdclk_state *cdclk_state;
 255         const struct intel_crtc_state *old_crtc_state;
 256         struct intel_crtc_state *new_crtc_state;
 257
 258         if (!plane_state->uapi.visible || !plane->min_cdclk)
 259                 return 0;
 260
 261         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
 262         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 263
 264         new_crtc_state->min_cdclk[plane->id] =
 265                 plane->min_cdclk(new_crtc_state, plane_state);
 266
 267         /*
 268          * No need to check against the cdclk state if
 269          * the min cdclk for the plane doesn't increase.
 270          *
 271          * Ie. we only ever increase the cdclk due to plane
 272          * requirements. This can reduce back and forth
 273          * display blinking due to constant cdclk changes.
 274          */
 275         if (new_crtc_state->min_cdclk[plane->id] <=
 276             old_crtc_state->min_cdclk[plane->id])
 277                 return 0;
 278
 279         cdclk_state = intel_atomic_get_cdclk_state(state);
 280         if (IS_ERR(cdclk_state))
 281                 return PTR_ERR(cdclk_state);
 282
 283         /*
 284          * No need to recalculate the cdclk state if
 285          * the min cdclk for the pipe doesn't increase.
 286          *
 287          * Ie. we only ever increase the cdclk due to plane
 288          * requirements. This can reduce back and forth
 289          * display blinking due to constant cdclk changes.
 290          */
 291         if (new_crtc_state->min_cdclk[plane->id] <=
 292             cdclk_state->min_cdclk[crtc->pipe])
 293                 return 0;
 294
 295         drm_dbg_kms(&dev_priv->drm,
 296                     "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
 297                     plane->base.base.id, plane->base.name,
 298                     new_crtc_state->min_cdclk[plane->id],
 299                     crtc->base.base.id, crtc->base.name,
 300                     cdclk_state->min_cdclk[crtc->pipe]);
 301         *need_cdclk_calc = true;
 302
 303         return 0;
 304 }
 305
 306 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
 307 {
 308         if (plane_state->hw.fb)
 309                 drm_framebuffer_put(plane_state->hw.fb);
 310
 311         memset(&plane_state->hw, 0, sizeof(plane_state->hw));
 312 }
 313
 314 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 315                                        const struct intel_plane_state *from_plane_state,
 316                                        struct intel_crtc *crtc)
 317 {
 318         intel_plane_clear_hw_state(plane_state);
 319
 320         /*
 321          * For the bigjoiner slave uapi.crtc will point at
 322          * the master crtc. So we explicitly assign the right
 323          * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
 324          * the plane is logically enabled on the uapi level.
 325          */
 326         plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
 327
 328         plane_state->hw.fb = from_plane_state->uapi.fb;
 329         if (plane_state->hw.fb)
 330                 drm_framebuffer_get(plane_state->hw.fb);
 331
 332         plane_state->hw.alpha = from_plane_state->uapi.alpha;
 333         plane_state->hw.pixel_blend_mode =
 334                 from_plane_state->uapi.pixel_blend_mode;
 335         plane_state->hw.rotation = from_plane_state->uapi.rotation;
 336         plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
 337         plane_state->hw.color_range = from_plane_state->uapi.color_range;
 338         plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
 339
 340         plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
 341         plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
 342 }
 343
 344 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
 345                                const struct intel_plane_state *from_plane_state)
 346 {
 347         intel_plane_clear_hw_state(plane_state);
 348
 349         memcpy(&plane_state->hw, &from_plane_state->hw,
 350                sizeof(plane_state->hw));
 351
 352         if (plane_state->hw.fb)
 353                 drm_framebuffer_get(plane_state->hw.fb);
 354 }
 355
 356 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 357                                struct intel_plane_state *plane_state)
 358 {
 359         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 360
 361         crtc_state->active_planes &= ~BIT(plane->id);
 362         crtc_state->scaled_planes &= ~BIT(plane->id);
 363         crtc_state->nv12_planes &= ~BIT(plane->id);
 364         crtc_state->c8_planes &= ~BIT(plane->id);
 365         crtc_state->data_rate[plane->id] = 0;
 366         crtc_state->data_rate_y[plane->id] = 0;
 367         crtc_state->rel_data_rate[plane->id] = 0;
 368         crtc_state->rel_data_rate_y[plane->id] = 0;
 369         crtc_state->min_cdclk[plane->id] = 0;
 370
 371         plane_state->uapi.visible = false;
 372 }
 373
 374 /* FIXME nuke when all wm code is atomic */
 375 static bool intel_wm_need_update(const struct intel_plane_state *cur,
 376                                  struct intel_plane_state *new)
 377 {
 378         /* Update watermarks on tiling or size changes. */
 379         if (new->uapi.visible != cur->uapi.visible)
 380                 return true;
 381
 382         if (!cur->hw.fb || !new->hw.fb)
 383                 return false;
 384
 385         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
 386             cur->hw.rotation != new->hw.rotation ||
 387             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
 388             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
 389             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
 390             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
 391                 return true;
 392
 393         return false;
 394 }
 395
 396 static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
 397 {
 398         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 399         int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 400         int dst_w = drm_rect_width(&plane_state->uapi.dst);
 401         int dst_h = drm_rect_height(&plane_state->uapi.dst);
 402
 403         return src_w != dst_w || src_h != dst_h;
 404 }
 405
 406 static bool intel_plane_do_async_flip(struct intel_plane *plane,
 407                                       const struct intel_crtc_state *old_crtc_state,
 408                                       const struct intel_crtc_state *new_crtc_state)
 409 {
 410         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 411
 412         if (!plane->async_flip)
 413                 return false;
 414
 415         if (!new_crtc_state->uapi.async_flip)
 416                 return false;
 417
 418         /*
 419          * In platforms after DISPLAY13, we might need to override
 420          * first async flip in order to change watermark levels
 421          * as part of optimization.
 422          * So for those, we are checking if this is a first async flip.
 423          * For platforms earlier than DISPLAY13 we always do async flip.
 424          */
 425         return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
 426 }
 427
 428 static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
 429                                            struct intel_crtc_state *new_crtc_state,
 430                                            const struct intel_plane_state *old_plane_state,
 431                                            struct intel_plane_state *new_plane_state)
 432 {
 433         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 434         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 435         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 436         bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
 437         bool was_crtc_enabled = old_crtc_state->hw.active;
 438         bool is_crtc_enabled = new_crtc_state->hw.active;
 439         bool turn_off, turn_on, visible, was_visible;
 440         int ret;
 441
 442         if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
 443                 ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
 444                 if (ret)
 445                         return ret;
 446         }
 447
 448         was_visible = old_plane_state->uapi.visible;
 449         visible = new_plane_state->uapi.visible;
 450
 451         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
 452                 was_visible = false;
 453
 454         /*
 455          * Visibility is calculated as if the crtc was on, but
 456          * after scaler setup everything depends on it being off
 457          * when the crtc isn't active.
 458          *
 459          * FIXME this is wrong for watermarks. Watermarks should also
 460          * be computed as if the pipe would be active. Perhaps move
 461          * per-plane wm computation to the .check_plane() hook, and
 462          * only combine the results from all planes in the current place?
 463          */
 464         if (!is_crtc_enabled) {
 465                 intel_plane_set_invisible(new_crtc_state, new_plane_state);
 466                 visible = false;
 467         }
 468
 469         if (!was_visible && !visible)
 470                 return 0;
 471
 472         turn_off = was_visible && (!visible || mode_changed);
 473         turn_on = visible && (!was_visible || mode_changed);
 474
 475         drm_dbg_atomic(&dev_priv->drm,
 476                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
 477                        crtc->base.base.id, crtc->base.name,
 478                        plane->base.base.id, plane->base.name,
 479                        was_visible, visible,
 480                        turn_off, turn_on, mode_changed);
 481
 482         if (turn_on) {
 483                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 484                         new_crtc_state->update_wm_pre = true;
 485
 486                 /* must disable cxsr around plane enable/disable */
 487                 if (plane->id != PLANE_CURSOR)
 488                         new_crtc_state->disable_cxsr = true;
 489         } else if (turn_off) {
 490                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 491                         new_crtc_state->update_wm_post = true;
 492
 493                 /* must disable cxsr around plane enable/disable */
 494                 if (plane->id != PLANE_CURSOR)
 495                         new_crtc_state->disable_cxsr = true;
 496         } else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
 497                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
 498                         /* FIXME bollocks */
 499                         new_crtc_state->update_wm_pre = true;
 500                         new_crtc_state->update_wm_post = true;
 501                 }
 502         }
 503
 504         if (visible || was_visible)
 505                 new_crtc_state->fb_bits |= plane->frontbuffer_bit;
 506
 507         /*
 508          * ILK/SNB DVSACNTR/Sprite Enable
 509          * IVB SPR_CTL/Sprite Enable
 510          * "When in Self Refresh Big FIFO mode, a write to enable the
 511          *  plane will be internally buffered and delayed while Big FIFO
 512          *  mode is exiting."
 513          *
 514          * Which means that enabling the sprite can take an extra frame
 515          * when we start in big FIFO mode (LP1+). Thus we need to drop
 516          * down to LP0 and wait for vblank in order to make sure the
 517          * sprite gets enabled on the next vblank after the register write.
 518          * Doing otherwise would risk enabling the sprite one frame after
 519          * we've already signalled flip completion. We can resume LP1+
 520          * once the sprite has been enabled.
 521          *
 522          *
 523          * WaCxSRDisabledForSpriteScaling:ivb
 524          * IVB SPR_SCALE/Scaling Enable
 525          * "Low Power watermarks must be disabled for at least one
 526          *  frame before enabling sprite scaling, and kept disabled
 527          *  until sprite scaling is disabled."
 528          *
 529          * ILK/SNB DVSASCALE/Scaling Enable
 530          * "When in Self Refresh Big FIFO mode, scaling enable will be
 531          *  masked off while Big FIFO mode is exiting."
 532          *
 533          * Despite the w/a only being listed for IVB we assume that
 534          * the ILK/SNB note has similar ramifications, hence we apply
 535          * the w/a on all three platforms.
 536          *
 537          * With experimental results seems this is needed also for primary
 538          * plane, not only sprite plane.
 539          */
 540         if (plane->id != PLANE_CURSOR &&
 541             (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
 542              IS_IVYBRIDGE(dev_priv)) &&
 543             (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
 544                          intel_plane_is_scaled(new_plane_state))))
 545                 new_crtc_state->disable_lp_wm = true;
 546
 547         if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state))
 548                 new_crtc_state->do_async_flip = true;
 549
 550         return 0;
 551 }
 552
 553 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 554                                         struct intel_crtc_state *new_crtc_state,
 555                                         const struct intel_plane_state *old_plane_state,
 556                                         struct intel_plane_state *new_plane_state)
 557 {
 558         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 559         const struct drm_framebuffer *fb = new_plane_state->hw.fb;
 560         int ret;
 561
 562         intel_plane_set_invisible(new_crtc_state, new_plane_state);
 563         new_crtc_state->enabled_planes &= ~BIT(plane->id);
 564
 565         if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
 566                 return 0;
 567
 568         ret = plane->check_plane(new_crtc_state, new_plane_state);
 569         if (ret)
 570                 return ret;
 571
 572         if (fb)
 573                 new_crtc_state->enabled_planes |= BIT(plane->id);
 574
 575         /* FIXME pre-g4x don't work like this */
 576         if (new_plane_state->uapi.visible)
 577                 new_crtc_state->active_planes |= BIT(plane->id);
 578
 579         if (new_plane_state->uapi.visible &&
 580             intel_plane_is_scaled(new_plane_state))
 581                 new_crtc_state->scaled_planes |= BIT(plane->id);
 582
 583         if (new_plane_state->uapi.visible &&
 584             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 585                 new_crtc_state->nv12_planes |= BIT(plane->id);
 586
 587         if (new_plane_state->uapi.visible &&
 588             fb->format->format == DRM_FORMAT_C8)
 589                 new_crtc_state->c8_planes |= BIT(plane->id);
 590
 591         if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
 592                 new_crtc_state->update_planes |= BIT(plane->id);
 593
 594         if (new_plane_state->uapi.visible &&
 595             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 596                 new_crtc_state->data_rate_y[plane->id] =
 597                         intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 598                 new_crtc_state->data_rate[plane->id] =
 599                         intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
 600
 601                 new_crtc_state->rel_data_rate_y[plane->id] =
 602                         intel_plane_relative_data_rate(new_crtc_state,
 603                                                        new_plane_state, 0);
 604                 new_crtc_state->rel_data_rate[plane->id] =
 605                         intel_plane_relative_data_rate(new_crtc_state,
 606                                                        new_plane_state, 1);
 607         } else if (new_plane_state->uapi.visible) {
 608                 new_crtc_state->data_rate[plane->id] =
 609                         intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 610
 611                 new_crtc_state->rel_data_rate[plane->id] =
 612                         intel_plane_relative_data_rate(new_crtc_state,
 613                                                        new_plane_state, 0);
 614         }
 615
 616         return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
 617                                                old_plane_state, new_plane_state);
 618 }
 619
 620 static struct intel_plane *
 621 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
 622 {
 623         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 624         struct intel_plane *plane;
 625
 626         for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 627                 if (plane->id == plane_id)
 628                         return plane;
 629         }
 630
 631         return NULL;
 632 }
 633
 634 int intel_plane_atomic_check(struct intel_atomic_state *state,
 635                              struct intel_plane *plane)
 636 {
 637         struct drm_i915_private *i915 = to_i915(state->base.dev);
 638         struct intel_plane_state *new_plane_state =
 639                 intel_atomic_get_new_plane_state(state, plane);
 640         const struct intel_plane_state *old_plane_state =
 641                 intel_atomic_get_old_plane_state(state, plane);
 642         const struct intel_plane_state *new_master_plane_state;
 643         struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
 644         const struct intel_crtc_state *old_crtc_state =
 645                 intel_atomic_get_old_crtc_state(state, crtc);
 646         struct intel_crtc_state *new_crtc_state =
 647                 intel_atomic_get_new_crtc_state(state, crtc);
 648
 649         if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
 650                 struct intel_crtc *master_crtc =
 651                         intel_master_crtc(new_crtc_state);
 652                 struct intel_plane *master_plane =
 653                         intel_crtc_get_plane(master_crtc, plane->id);
 654
 655                 new_master_plane_state =
 656                         intel_atomic_get_new_plane_state(state, master_plane);
 657         } else {
 658                 new_master_plane_state = new_plane_state;
 659         }
 660
 661         intel_plane_copy_uapi_to_hw_state(new_plane_state,
 662                                           new_master_plane_state,
 663                                           crtc);
 664
 665         new_plane_state->uapi.visible = false;
 666         if (!new_crtc_state)
 667                 return 0;
 668
 669         return intel_plane_atomic_check_with_state(old_crtc_state,
 670                                                    new_crtc_state,
 671                                                    old_plane_state,
 672                                                    new_plane_state);
 673 }
 674
 675 static struct intel_plane *
 676 skl_next_plane_to_commit(struct intel_atomic_state *state,
 677                          struct intel_crtc *crtc,
 678                          struct skl_ddb_entry ddb[I915_MAX_PLANES],
 679                          struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
 680                          unsigned int *update_mask)
 681 {
 682         struct intel_crtc_state *crtc_state =
 683                 intel_atomic_get_new_crtc_state(state, crtc);
 684         struct intel_plane_state *plane_state;
 685         struct intel_plane *plane;
 686         int i;
 687
 688         if (*update_mask == 0)
 689                 return NULL;
 690
 691         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 692                 enum plane_id plane_id = plane->id;
 693
 694                 if (crtc->pipe != plane->pipe ||
 695                     !(*update_mask & BIT(plane_id)))
 696                         continue;
 697
 698                 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
 699                                                 ddb, I915_MAX_PLANES, plane_id) ||
 700                     skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
 701                                                 ddb_y, I915_MAX_PLANES, plane_id))
 702                         continue;
 703
 704                 *update_mask &= ~BIT(plane_id);
 705                 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
 706                 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
 707
 708                 return plane;
 709         }
 710
 711         /* should never happen */
 712         drm_WARN_ON(state->base.dev, 1);
 713
 714         return NULL;
 715 }
 716
 717 void intel_plane_update_noarm(struct intel_plane *plane,
 718                               const struct intel_crtc_state *crtc_state,
 719                               const struct intel_plane_state *plane_state)
 720 {
 721         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 722
 723         trace_intel_plane_update_noarm(&plane->base, crtc);
 724
 725         if (plane->update_noarm)
 726                 plane->update_noarm(plane, crtc_state, plane_state);
 727 }
 728
 729 void intel_plane_update_arm(struct intel_plane *plane,
 730                             const struct intel_crtc_state *crtc_state,
 731                             const struct intel_plane_state *plane_state)
 732 {
 733         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 734
 735         trace_intel_plane_update_arm(&plane->base, crtc);
 736
 737         if (crtc_state->do_async_flip && plane->async_flip)
 738                 plane->async_flip(plane, crtc_state, plane_state, true);
 739         else
 740                 plane->update_arm(plane, crtc_state, plane_state);
 741 }
 742
 743 void intel_plane_disable_arm(struct intel_plane *plane,
 744                              const struct intel_crtc_state *crtc_state)
 745 {
 746         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 747
 748         trace_intel_plane_disable_arm(&plane->base, crtc);
 749         plane->disable_arm(plane, crtc_state);
 750 }
 751
 752 void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
 753                                     struct intel_crtc *crtc)
 754 {
 755         struct intel_crtc_state *new_crtc_state =
 756                 intel_atomic_get_new_crtc_state(state, crtc);
 757         u32 update_mask = new_crtc_state->update_planes;
 758         struct intel_plane_state *new_plane_state;
 759         struct intel_plane *plane;
 760         int i;
 761
 762         if (new_crtc_state->do_async_flip)
 763                 return;
 764
 765         /*
 766          * Since we only write non-arming registers here,
 767          * the order does not matter even for skl+.
 768          */
 769         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 770                 if (crtc->pipe != plane->pipe ||
 771                     !(update_mask & BIT(plane->id)))
 772                         continue;
 773
 774                 /* TODO: for mailbox updates this should be skipped */
 775                 if (new_plane_state->uapi.visible ||
 776                     new_plane_state->planar_slave)
 777                         intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
 778         }
 779 }
 780
 781 static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
 782                                        struct intel_crtc *crtc)
 783 {
 784         struct intel_crtc_state *old_crtc_state =
 785                 intel_atomic_get_old_crtc_state(state, crtc);
 786         struct intel_crtc_state *new_crtc_state =
 787                 intel_atomic_get_new_crtc_state(state, crtc);
 788         struct skl_ddb_entry ddb[I915_MAX_PLANES];
 789         struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
 790         u32 update_mask = new_crtc_state->update_planes;
 791         struct intel_plane *plane;
 792
 793         memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
 794                sizeof(old_crtc_state->wm.skl.plane_ddb));
 795         memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
 796                sizeof(old_crtc_state->wm.skl.plane_ddb_y));
 797
 798         while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
 799                 struct intel_plane_state *new_plane_state =
 800                         intel_atomic_get_new_plane_state(state, plane);
 801
 802                 /*
 803                  * TODO: for mailbox updates intel_plane_update_noarm()
 804                  * would have to be called here as well.
 805                  */
 806                 if (new_plane_state->uapi.visible ||
 807                     new_plane_state->planar_slave)
 808                         intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
 809                 else
 810                         intel_plane_disable_arm(plane, new_crtc_state);
 811         }
 812 }
 813
 814 static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
 815                                         struct intel_crtc *crtc)
 816 {
 817         struct intel_crtc_state *new_crtc_state =
 818                 intel_atomic_get_new_crtc_state(state, crtc);
 819         u32 update_mask = new_crtc_state->update_planes;
 820         struct intel_plane_state *new_plane_state;
 821         struct intel_plane *plane;
 822         int i;
 823
 824         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 825                 if (crtc->pipe != plane->pipe ||
 826                     !(update_mask & BIT(plane->id)))
 827                         continue;
 828
 829                 /*
 830                  * TODO: for mailbox updates intel_plane_update_noarm()
 831                  * would have to be called here as well.
 832                  */
 833                 if (new_plane_state->uapi.visible)
 834                         intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
 835                 else
 836                         intel_plane_disable_arm(plane, new_crtc_state);
 837         }
 838 }
 839
 840 void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
 841                                   struct intel_crtc *crtc)
 842 {
 843         struct drm_i915_private *i915 = to_i915(state->base.dev);
 844
 845         if (DISPLAY_VER(i915) >= 9)
 846                 skl_crtc_planes_update_arm(state, crtc);
 847         else
 848                 i9xx_crtc_planes_update_arm(state, crtc);
 849 }
 850
 851 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
 852                                       struct intel_crtc_state *crtc_state,
 853                                       int min_scale, int max_scale,
 854                                       bool can_position)
 855 {
 856         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 857         struct drm_framebuffer *fb = plane_state->hw.fb;
 858         struct drm_rect *src = &plane_state->uapi.src;
 859         struct drm_rect *dst = &plane_state->uapi.dst;
 860         const struct drm_rect *clip = &crtc_state->pipe_src;
 861         unsigned int rotation = plane_state->hw.rotation;
 862         int hscale, vscale;
 863
 864         if (!fb) {
 865                 plane_state->uapi.visible = false;
 866                 return 0;
 867         }
 868
 869         drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
 870
 871         /* Check scaling */
 872         hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 873         vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 874         if (hscale < 0 || vscale < 0) {
 875                 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
 876                 drm_rect_debug_print("src: ", src, true);
 877                 drm_rect_debug_print("dst: ", dst, false);
 878                 return -ERANGE;
 879         }
 880
 881         /*
 882          * FIXME: This might need further adjustment for seamless scaling
 883          * with phase information, for the 2p2 and 2p1 scenarios.
 884          */
 885         plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
 886
 887         drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
 888
 889         if (!can_position && plane_state->uapi.visible &&
 890             !drm_rect_equals(dst, clip)) {
 891                 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
 892                 drm_rect_debug_print("dst: ", dst, false);
 893                 drm_rect_debug_print("clip: ", clip, false);
 894                 return -EINVAL;
 895         }
 896
 897         /* final plane coordinates will be relative to the plane's pipe */
 898         drm_rect_translate(dst, -clip->x1, -clip->y1);
 899
 900         return 0;
 901 }
 902
 903 struct wait_rps_boost {
 904         struct wait_queue_entry wait;
 905
 906         struct drm_crtc *crtc;
 907         struct i915_request *request;
 908 };
 909
 910 static int do_rps_boost(struct wait_queue_entry *_wait,
 911                         unsigned mode, int sync, void *key)
 912 {
 913         struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
 914         struct i915_request *rq = wait->request;
 915
 916         /*
 917          * If we missed the vblank, but the request is already running it
 918          * is reasonable to assume that it will complete before the next
 919          * vblank without our intervention, so leave RPS alone.
 920          */
 921         if (!i915_request_started(rq))
 922                 intel_rps_boost(rq);
 923         i915_request_put(rq);
 924
 925         drm_crtc_vblank_put(wait->crtc);
 926
 927         list_del(&wait->wait.entry);
 928         kfree(wait);
 929         return 1;
 930 }
 931
 932 static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
 933                                        struct dma_fence *fence)
 934 {
 935         struct wait_rps_boost *wait;
 936
 937         if (!dma_fence_is_i915(fence))
 938                 return;
 939
 940         if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
 941                 return;
 942
 943         if (drm_crtc_vblank_get(crtc))
 944                 return;
 945
 946         wait = kmalloc(sizeof(*wait), GFP_KERNEL);
 947         if (!wait) {
 948                 drm_crtc_vblank_put(crtc);
 949                 return;
 950         }
 951
 952         wait->request = to_request(dma_fence_get(fence));
 953         wait->crtc = crtc;
 954
 955         wait->wait.func = do_rps_boost;
 956         wait->wait.flags = 0;
 957
 958         add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait);
 959 }
 960
 961 /**
 962  * intel_prepare_plane_fb - Prepare fb for usage on plane
 963  * @_plane: drm plane to prepare for
 964  * @_new_plane_state: the plane state being prepared
 965  *
 966  * Prepares a framebuffer for usage on a display plane.  Generally this
 967  * involves pinning the underlying object and updating the frontbuffer tracking
 968  * bits.  Some older platforms need special physical address handling for
 969  * cursor planes.
 970  *
 971  * Returns 0 on success, negative error code on failure.
 972  */
 973 static int
 974 intel_prepare_plane_fb(struct drm_plane *_plane,
 975                        struct drm_plane_state *_new_plane_state)
 976 {
 977         struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
 978         struct intel_plane *plane = to_intel_plane(_plane);
 979         struct intel_plane_state *new_plane_state =
 980                 to_intel_plane_state(_new_plane_state);
 981         struct intel_atomic_state *state =
 982                 to_intel_atomic_state(new_plane_state->uapi.state);
 983         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 984         const struct intel_plane_state *old_plane_state =
 985                 intel_atomic_get_old_plane_state(state, plane);
 986         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
 987         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
 988         int ret;
 989
 990         if (old_obj) {
 991                 const struct intel_crtc_state *crtc_state =
 992                         intel_atomic_get_new_crtc_state(state,
 993                                                         to_intel_crtc(old_plane_state->hw.crtc));
 994
 995                 /* Big Hammer, we also need to ensure that any pending
 996                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
 997                  * current scanout is retired before unpinning the old
 998                  * framebuffer. Note that we rely on userspace rendering
 999                  * into the buffer attached to the pipe they are waiting
1000                  * on. If not, userspace generates a GPU hang with IPEHR
1001                  * point to the MI_WAIT_FOR_EVENT.
1002                  *
1003                  * This should only fail upon a hung GPU, in which case we
1004                  * can safely continue.
1005                  */
1006                 if (intel_crtc_needs_modeset(crtc_state)) {
1007                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
1008                                                               old_obj->base.resv, NULL,
1009                                                               false, 0,
1010                                                               GFP_KERNEL);
1011                         if (ret < 0)
1012                                 return ret;
1013                 }
1014         }
1015
1016         if (new_plane_state->uapi.fence) { /* explicit fencing */
1017                 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
1018                                              &attr);
1019                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
1020                                                     new_plane_state->uapi.fence,
1021                                                     i915_fence_timeout(dev_priv),
1022                                                     GFP_KERNEL);
1023                 if (ret < 0)
1024                         return ret;
1025         }
1026
1027         if (!obj)
1028                 return 0;
1029
1030
1031         ret = intel_plane_pin_fb(new_plane_state);
1032         if (ret)
1033                 return ret;
1034
1035         i915_gem_object_wait_priority(obj, 0, &attr);
1036
1037         if (!new_plane_state->uapi.fence) { /* implicit fencing */
1038                 struct dma_resv_iter cursor;
1039                 struct dma_fence *fence;
1040
1041                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
1042                                                       obj->base.resv, NULL,
1043                                                       false,
1044                                                       i915_fence_timeout(dev_priv),
1045                                                       GFP_KERNEL);
1046                 if (ret < 0)
1047                         goto unpin_fb;
1048
1049                 dma_resv_iter_begin(&cursor, obj->base.resv,
1050                                     DMA_RESV_USAGE_WRITE);
1051                 dma_resv_for_each_fence_unlocked(&cursor, fence) {
1052                         add_rps_boost_after_vblank(new_plane_state->hw.crtc,
1053                                                    fence);
1054                 }
1055                 dma_resv_iter_end(&cursor);
1056         } else {
1057                 add_rps_boost_after_vblank(new_plane_state->hw.crtc,
1058                                            new_plane_state->uapi.fence);
1059         }
1060
1061         /*
1062          * We declare pageflips to be interactive and so merit a small bias
1063          * towards upclocking to deliver the frame on time. By only changing
1064          * the RPS thresholds to sample more regularly and aim for higher
1065          * clocks we can hopefully deliver low power workloads (like kodi)
1066          * that are not quite steady state without resorting to forcing
1067          * maximum clocks following a vblank miss (see do_rps_boost()).
1068          */
1069         if (!state->rps_interactive) {
1070                 intel_rps_mark_interactive(&to_gt(dev_priv)->rps, true);
1071                 state->rps_interactive = true;
1072         }
1073
1074         return 0;
1075
1076 unpin_fb:
1077         intel_plane_unpin_fb(new_plane_state);
1078
1079         return ret;
1080 }
1081
1082 /**
1083  * intel_cleanup_plane_fb - Cleans up an fb after plane use
1084  * @plane: drm plane to clean up for
1085  * @_old_plane_state: the state from the previous modeset
1086  *
1087  * Cleans up a framebuffer that has just been removed from a plane.
1088  */
1089 static void
1090 intel_cleanup_plane_fb(struct drm_plane *plane,
1091                        struct drm_plane_state *_old_plane_state)
1092 {
1093         struct intel_plane_state *old_plane_state =
1094                 to_intel_plane_state(_old_plane_state);
1095         struct intel_atomic_state *state =
1096                 to_intel_atomic_state(old_plane_state->uapi.state);
1097         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1098         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
1099
1100         if (!obj)
1101                 return;
1102
1103         if (state->rps_interactive) {
1104                 intel_rps_mark_interactive(&to_gt(dev_priv)->rps, false);
1105                 state->rps_interactive = false;
1106         }
1107
1108         /* Should only be called after a successful intel_prepare_plane_fb()! */
1109         intel_plane_unpin_fb(old_plane_state);
1110 }
1111
1112 static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1113         .prepare_fb = intel_prepare_plane_fb,
1114         .cleanup_fb = intel_cleanup_plane_fb,
1115 };
1116
1117 void intel_plane_helper_add(struct intel_plane *plane)
1118 {
1119         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1120 }