1 // SPDX-License-Identifier: GPL-2.0
5 * Based on tc358764.c by
9 * Based on rpi_touchscreen.c by
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/of_graph.h>
16 #include <linux/regulator/consumer.h>
18 #include <video/mipi_display.h>
20 #include <drm/drm_atomic_helper.h>
21 #include <drm/drm_crtc.h>
22 #include <drm/drm_fb_helper.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
26 #include <drm/drm_print.h>
27 #include <drm/drm_probe_helper.h>
29 /* PPI layer registers */
30 #define PPI_STARTPPI 0x0104 /* START control bit */
31 #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */
32 #define PPI_D0S_ATMR 0x0144
33 #define PPI_D1S_ATMR 0x0148
34 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */
35 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */
36 #define PPI_START_FUNCTION 1
38 /* DSI layer registers */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
40 #define DSI_LANEENABLE 0x0210 /* Enables each lane */
41 #define DSI_RX_START 1
43 /* LCDC/DPI Host Registers */
44 #define LCDCTRL 0x0420
46 /* SPI Master Registers */
50 /* System Controller Registers */
51 #define SYSCTRL 0x0464
53 /* System registers */
56 /* Lane enable PPI and DSI register bits */
57 #define LANEENABLE_CLEN BIT(0)
58 #define LANEENABLE_L0EN BIT(1)
59 #define LANEENABLE_L1EN BIT(2)
63 struct drm_bridge bridge;
64 struct regulator *regulator;
65 struct drm_bridge *panel_bridge;
70 static int tc358762_clear_error(struct tc358762 *ctx)
78 static void tc358762_write(struct tc358762 *ctx, u16 addr, u32 val)
80 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
94 ret = mipi_dsi_generic_write(dsi, data, sizeof(data));
99 static inline struct tc358762 *bridge_to_tc358762(struct drm_bridge *bridge)
101 return container_of(bridge, struct tc358762, bridge);
104 static int tc358762_init(struct tc358762 *ctx)
106 tc358762_write(ctx, DSI_LANEENABLE,
107 LANEENABLE_L0EN | LANEENABLE_CLEN);
108 tc358762_write(ctx, PPI_D0S_CLRSIPOCOUNT, 5);
109 tc358762_write(ctx, PPI_D1S_CLRSIPOCOUNT, 5);
110 tc358762_write(ctx, PPI_D0S_ATMR, 0);
111 tc358762_write(ctx, PPI_D1S_ATMR, 0);
112 tc358762_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD);
114 tc358762_write(ctx, SPICMR, 0x00);
115 tc358762_write(ctx, LCDCTRL, 0x00100150);
116 tc358762_write(ctx, SYSCTRL, 0x040f);
119 tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION);
120 tc358762_write(ctx, DSI_STARTDSI, DSI_RX_START);
124 return tc358762_clear_error(ctx);
127 static void tc358762_post_disable(struct drm_bridge *bridge)
129 struct tc358762 *ctx = bridge_to_tc358762(bridge);
133 * The post_disable hook might be called multiple times.
134 * We want to avoid regulator imbalance below.
136 if (!ctx->pre_enabled)
139 ctx->pre_enabled = false;
141 ret = regulator_disable(ctx->regulator);
143 dev_err(ctx->dev, "error disabling regulators (%d)\n", ret);
146 static void tc358762_pre_enable(struct drm_bridge *bridge)
148 struct tc358762 *ctx = bridge_to_tc358762(bridge);
151 ret = regulator_enable(ctx->regulator);
153 dev_err(ctx->dev, "error enabling regulators (%d)\n", ret);
155 ret = tc358762_init(ctx);
157 dev_err(ctx->dev, "error initializing bridge (%d)\n", ret);
159 ctx->pre_enabled = true;
162 static int tc358762_attach(struct drm_bridge *bridge,
163 enum drm_bridge_attach_flags flags)
165 struct tc358762 *ctx = bridge_to_tc358762(bridge);
167 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge,
171 static const struct drm_bridge_funcs tc358762_bridge_funcs = {
172 .post_disable = tc358762_post_disable,
173 .pre_enable = tc358762_pre_enable,
174 .attach = tc358762_attach,
177 static int tc358762_parse_dt(struct tc358762 *ctx)
179 struct drm_bridge *panel_bridge;
180 struct device *dev = ctx->dev;
182 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
183 if (IS_ERR(panel_bridge))
184 return PTR_ERR(panel_bridge);
186 ctx->panel_bridge = panel_bridge;
191 static int tc358762_configure_regulators(struct tc358762 *ctx)
193 ctx->regulator = devm_regulator_get(ctx->dev, "vddc");
194 if (IS_ERR(ctx->regulator))
195 return PTR_ERR(ctx->regulator);
200 static int tc358762_probe(struct mipi_dsi_device *dsi)
202 struct device *dev = &dsi->dev;
203 struct tc358762 *ctx;
206 ctx = devm_kzalloc(dev, sizeof(struct tc358762), GFP_KERNEL);
210 mipi_dsi_set_drvdata(dsi, ctx);
213 ctx->pre_enabled = false;
215 /* TODO: Find out how to get dual-lane mode working */
217 dsi->format = MIPI_DSI_FMT_RGB888;
218 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
221 ret = tc358762_parse_dt(ctx);
225 ret = tc358762_configure_regulators(ctx);
229 ctx->bridge.funcs = &tc358762_bridge_funcs;
230 ctx->bridge.type = DRM_MODE_CONNECTOR_DPI;
231 ctx->bridge.of_node = dev->of_node;
233 drm_bridge_add(&ctx->bridge);
235 ret = mipi_dsi_attach(dsi);
237 drm_bridge_remove(&ctx->bridge);
238 dev_err(dev, "failed to attach dsi\n");
244 static void tc358762_remove(struct mipi_dsi_device *dsi)
246 struct tc358762 *ctx = mipi_dsi_get_drvdata(dsi);
248 mipi_dsi_detach(dsi);
249 drm_bridge_remove(&ctx->bridge);
252 static const struct of_device_id tc358762_of_match[] = {
253 { .compatible = "toshiba,tc358762" },
256 MODULE_DEVICE_TABLE(of, tc358762_of_match);
258 static struct mipi_dsi_driver tc358762_driver = {
259 .probe = tc358762_probe,
260 .remove = tc358762_remove,
263 .of_match_table = tc358762_of_match,
266 module_mipi_dsi_driver(tc358762_driver);
269 MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358762 DSI/DPI Bridge");
270 MODULE_LICENSE("GPL v2");