drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32 #include "vi.h"
  33 #include "vid.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "gmc/gmc_8_1_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44
  45 #include "bif/bif_5_0_d.h"
  46 #include "bif/bif_5_0_sh_mask.h"
  47
  48 #include "tonga_sdma_pkt_open.h"
  49
  50 #include "ivsrcid/ivsrcid_vislands30.h"
  51
  52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  56
  57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
  70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
  72
  73
  74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  75 {
  76         SDMA0_REGISTER_OFFSET,
  77         SDMA1_REGISTER_OFFSET
  78 };
  79
  80 static const u32 golden_settings_tonga_a11[] =
  81 {
  82         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  83         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  84         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  85         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  86         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  87         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  88         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  89         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  90         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  91         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  92 };
  93
  94 static const u32 tonga_mgcg_cgcg_init[] =
  95 {
  96         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  97         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  98 };
  99
 100 static const u32 golden_settings_fiji_a10[] =
 101 {
 102         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 103         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 104         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 105         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 106         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 107         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 108         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 109         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 110 };
 111
 112 static const u32 fiji_mgcg_cgcg_init[] =
 113 {
 114         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 115         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 116 };
 117
 118 static const u32 golden_settings_polaris11_a11[] =
 119 {
 120         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 121         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 122         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 123         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 124         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 125         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 126         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 127         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 128         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 129         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 130 };
 131
 132 static const u32 golden_settings_polaris10_a11[] =
 133 {
 134         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 135         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 136         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 137         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 138         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 139         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 140         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 141         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 142         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 143         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 144 };
 145
 146 static const u32 cz_golden_settings_a11[] =
 147 {
 148         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 149         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 150         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 151         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 152         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 153         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 154         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 155         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 156         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 157         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 158         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 159         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 160 };
 161
 162 static const u32 cz_mgcg_cgcg_init[] =
 163 {
 164         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 165         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 166 };
 167
 168 static const u32 stoney_golden_settings_a11[] =
 169 {
 170         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 171         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 172         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 173         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 174 };
 175
 176 static const u32 stoney_mgcg_cgcg_init[] =
 177 {
 178         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 179 };
 180
 181 /*
 182  * sDMA - System DMA
 183  * Starting with CIK, the GPU has new asynchronous
 184  * DMA engines.  These engines are used for compute
 185  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 186  * and each one supports 1 ring buffer used for gfx
 187  * and 2 queues used for compute.
 188  *
 189  * The programming model is very similar to the CP
 190  * (ring buffer, IBs, etc.), but sDMA has it's own
 191  * packet format that is different from the PM4 format
 192  * used by the CP. sDMA supports copying data, writing
 193  * embedded data, solid fills, and a number of other
 194  * things.  It also has support for tiling/detiling of
 195  * buffers.
 196  */
 197
 198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 199 {
 200         switch (adev->asic_type) {
 201         case CHIP_FIJI:
 202                 amdgpu_device_program_register_sequence(adev,
 203                                                         fiji_mgcg_cgcg_init,
 204                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 205                 amdgpu_device_program_register_sequence(adev,
 206                                                         golden_settings_fiji_a10,
 207                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 208                 break;
 209         case CHIP_TONGA:
 210                 amdgpu_device_program_register_sequence(adev,
 211                                                         tonga_mgcg_cgcg_init,
 212                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 213                 amdgpu_device_program_register_sequence(adev,
 214                                                         golden_settings_tonga_a11,
 215                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 216                 break;
 217         case CHIP_POLARIS11:
 218         case CHIP_POLARIS12:
 219         case CHIP_VEGAM:
 220                 amdgpu_device_program_register_sequence(adev,
 221                                                         golden_settings_polaris11_a11,
 222                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 223                 break;
 224         case CHIP_POLARIS10:
 225                 amdgpu_device_program_register_sequence(adev,
 226                                                         golden_settings_polaris10_a11,
 227                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 228                 break;
 229         case CHIP_CARRIZO:
 230                 amdgpu_device_program_register_sequence(adev,
 231                                                         cz_mgcg_cgcg_init,
 232                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 233                 amdgpu_device_program_register_sequence(adev,
 234                                                         cz_golden_settings_a11,
 235                                                         ARRAY_SIZE(cz_golden_settings_a11));
 236                 break;
 237         case CHIP_STONEY:
 238                 amdgpu_device_program_register_sequence(adev,
 239                                                         stoney_mgcg_cgcg_init,
 240                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 241                 amdgpu_device_program_register_sequence(adev,
 242                                                         stoney_golden_settings_a11,
 243                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 244                 break;
 245         default:
 246                 break;
 247         }
 248 }
 249
 250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 251 {
 252         int i;
 253         for (i = 0; i < adev->sdma.num_instances; i++) {
 254                 release_firmware(adev->sdma.instance[i].fw);
 255                 adev->sdma.instance[i].fw = NULL;
 256         }
 257 }
 258
 259 /**
 260  * sdma_v3_0_init_microcode - load ucode images from disk
 261  *
 262  * @adev: amdgpu_device pointer
 263  *
 264  * Use the firmware interface to load the ucode images into
 265  * the driver (not loaded into hw).
 266  * Returns 0 on success, error on failure.
 267  */
 268 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 269 {
 270         const char *chip_name;
 271         char fw_name[30];
 272         int err = 0, i;
 273         struct amdgpu_firmware_info *info = NULL;
 274         const struct common_firmware_header *header = NULL;
 275         const struct sdma_firmware_header_v1_0 *hdr;
 276
 277         DRM_DEBUG("\n");
 278
 279         switch (adev->asic_type) {
 280         case CHIP_TONGA:
 281                 chip_name = "tonga";
 282                 break;
 283         case CHIP_FIJI:
 284                 chip_name = "fiji";
 285                 break;
 286         case CHIP_POLARIS10:
 287                 chip_name = "polaris10";
 288                 break;
 289         case CHIP_POLARIS11:
 290                 chip_name = "polaris11";
 291                 break;
 292         case CHIP_POLARIS12:
 293                 chip_name = "polaris12";
 294                 break;
 295         case CHIP_VEGAM:
 296                 chip_name = "vegam";
 297                 break;
 298         case CHIP_CARRIZO:
 299                 chip_name = "carrizo";
 300                 break;
 301         case CHIP_STONEY:
 302                 chip_name = "stoney";
 303                 break;
 304         default: BUG();
 305         }
 306
 307         for (i = 0; i < adev->sdma.num_instances; i++) {
 308                 if (i == 0)
 309                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 310                 else
 311                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 312                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 313                 if (err)
 314                         goto out;
 315                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 316                 if (err)
 317                         goto out;
 318                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 319                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 320                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 321                 if (adev->sdma.instance[i].feature_version >= 20)
 322                         adev->sdma.instance[i].burst_nop = true;
 323
 324                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 325                 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 326                 info->fw = adev->sdma.instance[i].fw;
 327                 header = (const struct common_firmware_header *)info->fw->data;
 328                 adev->firmware.fw_size +=
 329                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 330
 331         }
 332 out:
 333         if (err) {
 334                 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
 335                 for (i = 0; i < adev->sdma.num_instances; i++) {
 336                         release_firmware(adev->sdma.instance[i].fw);
 337                         adev->sdma.instance[i].fw = NULL;
 338                 }
 339         }
 340         return err;
 341 }
 342
 343 /**
 344  * sdma_v3_0_ring_get_rptr - get the current read pointer
 345  *
 346  * @ring: amdgpu ring pointer
 347  *
 348  * Get the current rptr from the hardware (VI+).
 349  */
 350 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 351 {
 352         /* XXX check if swapping is necessary on BE */
 353         return *ring->rptr_cpu_addr >> 2;
 354 }
 355
 356 /**
 357  * sdma_v3_0_ring_get_wptr - get the current write pointer
 358  *
 359  * @ring: amdgpu ring pointer
 360  *
 361  * Get the current wptr from the hardware (VI+).
 362  */
 363 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 364 {
 365         struct amdgpu_device *adev = ring->adev;
 366         u32 wptr;
 367
 368         if (ring->use_doorbell || ring->use_pollmem) {
 369                 /* XXX check if swapping is necessary on BE */
 370                 wptr = *ring->wptr_cpu_addr >> 2;
 371         } else {
 372                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 373         }
 374
 375         return wptr;
 376 }
 377
 378 /**
 379  * sdma_v3_0_ring_set_wptr - commit the write pointer
 380  *
 381  * @ring: amdgpu ring pointer
 382  *
 383  * Write the wptr back to the hardware (VI+).
 384  */
 385 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 386 {
 387         struct amdgpu_device *adev = ring->adev;
 388
 389         if (ring->use_doorbell) {
 390                 u32 *wb = (u32 *)ring->wptr_cpu_addr;
 391                 /* XXX check if swapping is necessary on BE */
 392                 WRITE_ONCE(*wb, ring->wptr << 2);
 393                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 394         } else if (ring->use_pollmem) {
 395                 u32 *wb = (u32 *)ring->wptr_cpu_addr;
 396
 397                 WRITE_ONCE(*wb, ring->wptr << 2);
 398         } else {
 399                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
 400         }
 401 }
 402
 403 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 404 {
 405         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 406         int i;
 407
 408         for (i = 0; i < count; i++)
 409                 if (sdma && sdma->burst_nop && (i == 0))
 410                         amdgpu_ring_write(ring, ring->funcs->nop |
 411                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 412                 else
 413                         amdgpu_ring_write(ring, ring->funcs->nop);
 414 }
 415
 416 /**
 417  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 418  *
 419  * @ring: amdgpu ring pointer
 420  * @job: job to retrieve vmid from
 421  * @ib: IB object to schedule
 422  * @flags: unused
 423  *
 424  * Schedule an IB in the DMA ring (VI).
 425  */
 426 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 427                                    struct amdgpu_job *job,
 428                                    struct amdgpu_ib *ib,
 429                                    uint32_t flags)
 430 {
 431         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 432
 433         /* IB packet must end on a 8 DW boundary */
 434         sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 435
 436         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 437                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 438         /* base must be 32 byte aligned */
 439         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 440         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 441         amdgpu_ring_write(ring, ib->length_dw);
 442         amdgpu_ring_write(ring, 0);
 443         amdgpu_ring_write(ring, 0);
 444
 445 }
 446
 447 /**
 448  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 449  *
 450  * @ring: amdgpu ring pointer
 451  *
 452  * Emit an hdp flush packet on the requested DMA ring.
 453  */
 454 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 455 {
 456         u32 ref_and_mask = 0;
 457
 458         if (ring->me == 0)
 459                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 460         else
 461                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 462
 463         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 464                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 465                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 466         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 467         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 468         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 469         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 470         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 471                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 472 }
 473
 474 /**
 475  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 476  *
 477  * @ring: amdgpu ring pointer
 478  * @addr: address
 479  * @seq: sequence number
 480  * @flags: fence related flags
 481  *
 482  * Add a DMA fence packet to the ring to write
 483  * the fence seq number and DMA trap packet to generate
 484  * an interrupt if needed (VI).
 485  */
 486 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 487                                       unsigned flags)
 488 {
 489         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 490         /* write the fence */
 491         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 492         amdgpu_ring_write(ring, lower_32_bits(addr));
 493         amdgpu_ring_write(ring, upper_32_bits(addr));
 494         amdgpu_ring_write(ring, lower_32_bits(seq));
 495
 496         /* optionally write high bits as well */
 497         if (write64bit) {
 498                 addr += 4;
 499                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 500                 amdgpu_ring_write(ring, lower_32_bits(addr));
 501                 amdgpu_ring_write(ring, upper_32_bits(addr));
 502                 amdgpu_ring_write(ring, upper_32_bits(seq));
 503         }
 504
 505         /* generate an interrupt */
 506         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 507         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 508 }
 509
 510 /**
 511  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 512  *
 513  * @adev: amdgpu_device pointer
 514  *
 515  * Stop the gfx async dma ring buffers (VI).
 516  */
 517 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 518 {
 519         u32 rb_cntl, ib_cntl;
 520         int i;
 521
 522         amdgpu_sdma_unset_buffer_funcs_helper(adev);
 523
 524         for (i = 0; i < adev->sdma.num_instances; i++) {
 525                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 526                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 527                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 528                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 529                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 530                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 531         }
 532 }
 533
 534 /**
 535  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 536  *
 537  * @adev: amdgpu_device pointer
 538  *
 539  * Stop the compute async dma queues (VI).
 540  */
 541 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 542 {
 543         /* XXX todo */
 544 }
 545
 546 /**
 547  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 548  *
 549  * @adev: amdgpu_device pointer
 550  * @enable: enable/disable the DMA MEs context switch.
 551  *
 552  * Halt or unhalt the async dma engines context switch (VI).
 553  */
 554 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 555 {
 556         u32 f32_cntl, phase_quantum = 0;
 557         int i;
 558
 559         if (amdgpu_sdma_phase_quantum) {
 560                 unsigned value = amdgpu_sdma_phase_quantum;
 561                 unsigned unit = 0;
 562
 563                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 564                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 565                         value = (value + 1) >> 1;
 566                         unit++;
 567                 }
 568                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 569                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 570                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 571                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 572                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 573                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 574                         WARN_ONCE(1,
 575                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 576                                   value << unit);
 577                 }
 578                 phase_quantum =
 579                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 580                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 581         }
 582
 583         for (i = 0; i < adev->sdma.num_instances; i++) {
 584                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 585                 if (enable) {
 586                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 587                                         AUTO_CTXSW_ENABLE, 1);
 588                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 589                                         ATC_L1_ENABLE, 1);
 590                         if (amdgpu_sdma_phase_quantum) {
 591                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 592                                        phase_quantum);
 593                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 594                                        phase_quantum);
 595                         }
 596                 } else {
 597                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 598                                         AUTO_CTXSW_ENABLE, 0);
 599                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 600                                         ATC_L1_ENABLE, 1);
 601                 }
 602
 603                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 604         }
 605 }
 606
 607 /**
 608  * sdma_v3_0_enable - stop the async dma engines
 609  *
 610  * @adev: amdgpu_device pointer
 611  * @enable: enable/disable the DMA MEs.
 612  *
 613  * Halt or unhalt the async dma engines (VI).
 614  */
 615 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 616 {
 617         u32 f32_cntl;
 618         int i;
 619
 620         if (!enable) {
 621                 sdma_v3_0_gfx_stop(adev);
 622                 sdma_v3_0_rlc_stop(adev);
 623         }
 624
 625         for (i = 0; i < adev->sdma.num_instances; i++) {
 626                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 627                 if (enable)
 628                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 629                 else
 630                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 631                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 632         }
 633 }
 634
 635 /**
 636  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 637  *
 638  * @adev: amdgpu_device pointer
 639  *
 640  * Set up the gfx DMA ring buffers and enable them (VI).
 641  * Returns 0 for success, error for failure.
 642  */
 643 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 644 {
 645         struct amdgpu_ring *ring;
 646         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 647         u32 rb_bufsz;
 648         u32 doorbell;
 649         u64 wptr_gpu_addr;
 650         int i, j, r;
 651
 652         for (i = 0; i < adev->sdma.num_instances; i++) {
 653                 ring = &adev->sdma.instance[i].ring;
 654                 amdgpu_ring_clear_ring(ring);
 655
 656                 mutex_lock(&adev->srbm_mutex);
 657                 for (j = 0; j < 16; j++) {
 658                         vi_srbm_select(adev, 0, 0, 0, j);
 659                         /* SDMA GFX */
 660                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 661                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 662                 }
 663                 vi_srbm_select(adev, 0, 0, 0, 0);
 664                 mutex_unlock(&adev->srbm_mutex);
 665
 666                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 667                        adev->gfx.config.gb_addr_config & 0x70);
 668
 669                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 670
 671                 /* Set ring buffer size in dwords */
 672                 rb_bufsz = order_base_2(ring->ring_size / 4);
 673                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 674                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 675 #ifdef __BIG_ENDIAN
 676                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 677                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 678                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 679 #endif
 680                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 681
 682                 /* Initialize the ring buffer's read and write pointers */
 683                 ring->wptr = 0;
 684                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 685                 sdma_v3_0_ring_set_wptr(ring);
 686                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 687                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 688
 689                 /* set the wb address whether it's enabled or not */
 690                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 691                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 692                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 693                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 694
 695                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 696
 697                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 698                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 699
 700                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 701
 702                 if (ring->use_doorbell) {
 703                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 704                                                  OFFSET, ring->doorbell_index);
 705                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 706                 } else {
 707                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 708                 }
 709                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 710
 711                 /* setup the wptr shadow polling */
 712                 wptr_gpu_addr = ring->wptr_gpu_addr;
 713
 714                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
 715                        lower_32_bits(wptr_gpu_addr));
 716                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
 717                        upper_32_bits(wptr_gpu_addr));
 718                 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
 719                 if (ring->use_pollmem) {
 720                         /*wptr polling is not enogh fast, directly clean the wptr register */
 721                         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 722                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 723                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 724                                                        ENABLE, 1);
 725                 } else {
 726                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 727                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 728                                                        ENABLE, 0);
 729                 }
 730                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
 731
 732                 /* enable DMA RB */
 733                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 734                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 735
 736                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 737                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 738 #ifdef __BIG_ENDIAN
 739                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 740 #endif
 741                 /* enable DMA IBs */
 742                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 743
 744                 ring->sched.ready = true;
 745         }
 746
 747         /* unhalt the MEs */
 748         sdma_v3_0_enable(adev, true);
 749         /* enable sdma ring preemption */
 750         sdma_v3_0_ctx_switch_enable(adev, true);
 751
 752         for (i = 0; i < adev->sdma.num_instances; i++) {
 753                 ring = &adev->sdma.instance[i].ring;
 754                 r = amdgpu_ring_test_helper(ring);
 755                 if (r)
 756                         return r;
 757
 758                 if (adev->mman.buffer_funcs_ring == ring)
 759                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 760         }
 761
 762         return 0;
 763 }
 764
 765 /**
 766  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 767  *
 768  * @adev: amdgpu_device pointer
 769  *
 770  * Set up the compute DMA queues and enable them (VI).
 771  * Returns 0 for success, error for failure.
 772  */
 773 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 774 {
 775         /* XXX todo */
 776         return 0;
 777 }
 778
 779 /**
 780  * sdma_v3_0_start - setup and start the async dma engines
 781  *
 782  * @adev: amdgpu_device pointer
 783  *
 784  * Set up the DMA engines and enable them (VI).
 785  * Returns 0 for success, error for failure.
 786  */
 787 static int sdma_v3_0_start(struct amdgpu_device *adev)
 788 {
 789         int r;
 790
 791         /* disable sdma engine before programing it */
 792         sdma_v3_0_ctx_switch_enable(adev, false);
 793         sdma_v3_0_enable(adev, false);
 794
 795         /* start the gfx rings and rlc compute queues */
 796         r = sdma_v3_0_gfx_resume(adev);
 797         if (r)
 798                 return r;
 799         r = sdma_v3_0_rlc_resume(adev);
 800         if (r)
 801                 return r;
 802
 803         return 0;
 804 }
 805
 806 /**
 807  * sdma_v3_0_ring_test_ring - simple async dma engine test
 808  *
 809  * @ring: amdgpu_ring structure holding ring information
 810  *
 811  * Test the DMA engine by writing using it to write an
 812  * value to memory. (VI).
 813  * Returns 0 for success, error for failure.
 814  */
 815 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 816 {
 817         struct amdgpu_device *adev = ring->adev;
 818         unsigned i;
 819         unsigned index;
 820         int r;
 821         u32 tmp;
 822         u64 gpu_addr;
 823
 824         r = amdgpu_device_wb_get(adev, &index);
 825         if (r)
 826                 return r;
 827
 828         gpu_addr = adev->wb.gpu_addr + (index * 4);
 829         tmp = 0xCAFEDEAD;
 830         adev->wb.wb[index] = cpu_to_le32(tmp);
 831
 832         r = amdgpu_ring_alloc(ring, 5);
 833         if (r)
 834                 goto error_free_wb;
 835
 836         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 837                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 838         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 839         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 840         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 841         amdgpu_ring_write(ring, 0xDEADBEEF);
 842         amdgpu_ring_commit(ring);
 843
 844         for (i = 0; i < adev->usec_timeout; i++) {
 845                 tmp = le32_to_cpu(adev->wb.wb[index]);
 846                 if (tmp == 0xDEADBEEF)
 847                         break;
 848                 udelay(1);
 849         }
 850
 851         if (i >= adev->usec_timeout)
 852                 r = -ETIMEDOUT;
 853
 854 error_free_wb:
 855         amdgpu_device_wb_free(adev, index);
 856         return r;
 857 }
 858
 859 /**
 860  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 861  *
 862  * @ring: amdgpu_ring structure holding ring information
 863  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 864  *
 865  * Test a simple IB in the DMA ring (VI).
 866  * Returns 0 on success, error on failure.
 867  */
 868 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 869 {
 870         struct amdgpu_device *adev = ring->adev;
 871         struct amdgpu_ib ib;
 872         struct dma_fence *f = NULL;
 873         unsigned index;
 874         u32 tmp = 0;
 875         u64 gpu_addr;
 876         long r;
 877
 878         r = amdgpu_device_wb_get(adev, &index);
 879         if (r)
 880                 return r;
 881
 882         gpu_addr = adev->wb.gpu_addr + (index * 4);
 883         tmp = 0xCAFEDEAD;
 884         adev->wb.wb[index] = cpu_to_le32(tmp);
 885         memset(&ib, 0, sizeof(ib));
 886         r = amdgpu_ib_get(adev, NULL, 256,
 887                                         AMDGPU_IB_POOL_DIRECT, &ib);
 888         if (r)
 889                 goto err0;
 890
 891         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 892                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 893         ib.ptr[1] = lower_32_bits(gpu_addr);
 894         ib.ptr[2] = upper_32_bits(gpu_addr);
 895         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 896         ib.ptr[4] = 0xDEADBEEF;
 897         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 898         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 899         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 900         ib.length_dw = 8;
 901
 902         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 903         if (r)
 904                 goto err1;
 905
 906         r = dma_fence_wait_timeout(f, false, timeout);
 907         if (r == 0) {
 908                 r = -ETIMEDOUT;
 909                 goto err1;
 910         } else if (r < 0) {
 911                 goto err1;
 912         }
 913         tmp = le32_to_cpu(adev->wb.wb[index]);
 914         if (tmp == 0xDEADBEEF)
 915                 r = 0;
 916         else
 917                 r = -EINVAL;
 918 err1:
 919         amdgpu_ib_free(adev, &ib, NULL);
 920         dma_fence_put(f);
 921 err0:
 922         amdgpu_device_wb_free(adev, index);
 923         return r;
 924 }
 925
 926 /**
 927  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 928  *
 929  * @ib: indirect buffer to fill with commands
 930  * @pe: addr of the page entry
 931  * @src: src addr to copy from
 932  * @count: number of page entries to update
 933  *
 934  * Update PTEs by copying them from the GART using sDMA (CIK).
 935  */
 936 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 937                                   uint64_t pe, uint64_t src,
 938                                   unsigned count)
 939 {
 940         unsigned bytes = count * 8;
 941
 942         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 943                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 944         ib->ptr[ib->length_dw++] = bytes;
 945         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 946         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 947         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 948         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 949         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 950 }
 951
 952 /**
 953  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 954  *
 955  * @ib: indirect buffer to fill with commands
 956  * @pe: addr of the page entry
 957  * @value: dst addr to write into pe
 958  * @count: number of page entries to update
 959  * @incr: increase next addr by incr bytes
 960  *
 961  * Update PTEs by writing them manually using sDMA (CIK).
 962  */
 963 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 964                                    uint64_t value, unsigned count,
 965                                    uint32_t incr)
 966 {
 967         unsigned ndw = count * 2;
 968
 969         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 970                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 971         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 972         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 973         ib->ptr[ib->length_dw++] = ndw;
 974         for (; ndw > 0; ndw -= 2) {
 975                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 976                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 977                 value += incr;
 978         }
 979 }
 980
 981 /**
 982  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 983  *
 984  * @ib: indirect buffer to fill with commands
 985  * @pe: addr of the page entry
 986  * @addr: dst addr to write into pe
 987  * @count: number of page entries to update
 988  * @incr: increase next addr by incr bytes
 989  * @flags: access flags
 990  *
 991  * Update the page tables using sDMA (CIK).
 992  */
 993 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 994                                      uint64_t addr, unsigned count,
 995                                      uint32_t incr, uint64_t flags)
 996 {
 997         /* for physically contiguous pages (vram) */
 998         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 999         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1000         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1001         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1002         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1003         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1004         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1005         ib->ptr[ib->length_dw++] = incr; /* increment size */
1006         ib->ptr[ib->length_dw++] = 0;
1007         ib->ptr[ib->length_dw++] = count; /* number of entries */
1008 }
1009
1010 /**
1011  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1012  *
1013  * @ring: amdgpu_ring structure holding ring information
1014  * @ib: indirect buffer to fill with padding
1015  *
1016  */
1017 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1018 {
1019         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1020         u32 pad_count;
1021         int i;
1022
1023         pad_count = (-ib->length_dw) & 7;
1024         for (i = 0; i < pad_count; i++)
1025                 if (sdma && sdma->burst_nop && (i == 0))
1026                         ib->ptr[ib->length_dw++] =
1027                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1028                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1029                 else
1030                         ib->ptr[ib->length_dw++] =
1031                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1032 }
1033
1034 /**
1035  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1036  *
1037  * @ring: amdgpu_ring pointer
1038  *
1039  * Make sure all previous operations are completed (CIK).
1040  */
1041 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1042 {
1043         uint32_t seq = ring->fence_drv.sync_seq;
1044         uint64_t addr = ring->fence_drv.gpu_addr;
1045
1046         /* wait for idle */
1047         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1048                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1049                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1050                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1051         amdgpu_ring_write(ring, addr & 0xfffffffc);
1052         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1053         amdgpu_ring_write(ring, seq); /* reference */
1054         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1055         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1056                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1057 }
1058
1059 /**
1060  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1061  *
1062  * @ring: amdgpu_ring pointer
1063  * @vmid: vmid number to use
1064  * @pd_addr: address
1065  *
1066  * Update the page table base and flush the VM TLB
1067  * using sDMA (VI).
1068  */
1069 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1070                                          unsigned vmid, uint64_t pd_addr)
1071 {
1072         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1073
1074         /* wait for flush */
1075         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1076                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1077                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1078         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1079         amdgpu_ring_write(ring, 0);
1080         amdgpu_ring_write(ring, 0); /* reference */
1081         amdgpu_ring_write(ring, 0); /* mask */
1082         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1083                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1084 }
1085
1086 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1087                                      uint32_t reg, uint32_t val)
1088 {
1089         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1090                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1091         amdgpu_ring_write(ring, reg);
1092         amdgpu_ring_write(ring, val);
1093 }
1094
1095 static int sdma_v3_0_early_init(void *handle)
1096 {
1097         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1098
1099         switch (adev->asic_type) {
1100         case CHIP_STONEY:
1101                 adev->sdma.num_instances = 1;
1102                 break;
1103         default:
1104                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1105                 break;
1106         }
1107
1108         sdma_v3_0_set_ring_funcs(adev);
1109         sdma_v3_0_set_buffer_funcs(adev);
1110         sdma_v3_0_set_vm_pte_funcs(adev);
1111         sdma_v3_0_set_irq_funcs(adev);
1112
1113         return 0;
1114 }
1115
1116 static int sdma_v3_0_sw_init(void *handle)
1117 {
1118         struct amdgpu_ring *ring;
1119         int r, i;
1120         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122         /* SDMA trap event */
1123         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1124                               &adev->sdma.trap_irq);
1125         if (r)
1126                 return r;
1127
1128         /* SDMA Privileged inst */
1129         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
1130                               &adev->sdma.illegal_inst_irq);
1131         if (r)
1132                 return r;
1133
1134         /* SDMA Privileged inst */
1135         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1136                               &adev->sdma.illegal_inst_irq);
1137         if (r)
1138                 return r;
1139
1140         r = sdma_v3_0_init_microcode(adev);
1141         if (r) {
1142                 DRM_ERROR("Failed to load sdma firmware!\n");
1143                 return r;
1144         }
1145
1146         for (i = 0; i < adev->sdma.num_instances; i++) {
1147                 ring = &adev->sdma.instance[i].ring;
1148                 ring->ring_obj = NULL;
1149                 if (!amdgpu_sriov_vf(adev)) {
1150                         ring->use_doorbell = true;
1151                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
1152                 } else {
1153                         ring->use_pollmem = true;
1154                 }
1155
1156                 sprintf(ring->name, "sdma%d", i);
1157                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1158                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1159                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1160                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1161                 if (r)
1162                         return r;
1163         }
1164
1165         return r;
1166 }
1167
1168 static int sdma_v3_0_sw_fini(void *handle)
1169 {
1170         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171         int i;
1172
1173         for (i = 0; i < adev->sdma.num_instances; i++)
1174                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1175
1176         sdma_v3_0_free_microcode(adev);
1177         return 0;
1178 }
1179
1180 static int sdma_v3_0_hw_init(void *handle)
1181 {
1182         int r;
1183         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1184
1185         sdma_v3_0_init_golden_registers(adev);
1186
1187         r = sdma_v3_0_start(adev);
1188         if (r)
1189                 return r;
1190
1191         return r;
1192 }
1193
1194 static int sdma_v3_0_hw_fini(void *handle)
1195 {
1196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1197
1198         sdma_v3_0_ctx_switch_enable(adev, false);
1199         sdma_v3_0_enable(adev, false);
1200
1201         return 0;
1202 }
1203
1204 static int sdma_v3_0_suspend(void *handle)
1205 {
1206         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1207
1208         return sdma_v3_0_hw_fini(adev);
1209 }
1210
1211 static int sdma_v3_0_resume(void *handle)
1212 {
1213         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1214
1215         return sdma_v3_0_hw_init(adev);
1216 }
1217
1218 static bool sdma_v3_0_is_idle(void *handle)
1219 {
1220         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1221         u32 tmp = RREG32(mmSRBM_STATUS2);
1222
1223         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1224                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1225             return false;
1226
1227         return true;
1228 }
1229
1230 static int sdma_v3_0_wait_for_idle(void *handle)
1231 {
1232         unsigned i;
1233         u32 tmp;
1234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1235
1236         for (i = 0; i < adev->usec_timeout; i++) {
1237                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1238                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1239
1240                 if (!tmp)
1241                         return 0;
1242                 udelay(1);
1243         }
1244         return -ETIMEDOUT;
1245 }
1246
1247 static bool sdma_v3_0_check_soft_reset(void *handle)
1248 {
1249         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250         u32 srbm_soft_reset = 0;
1251         u32 tmp = RREG32(mmSRBM_STATUS2);
1252
1253         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1254             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1255                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1256                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1257         }
1258
1259         if (srbm_soft_reset) {
1260                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1261                 return true;
1262         } else {
1263                 adev->sdma.srbm_soft_reset = 0;
1264                 return false;
1265         }
1266 }
1267
1268 static int sdma_v3_0_pre_soft_reset(void *handle)
1269 {
1270         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1271         u32 srbm_soft_reset = 0;
1272
1273         if (!adev->sdma.srbm_soft_reset)
1274                 return 0;
1275
1276         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1277
1278         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1279             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1280                 sdma_v3_0_ctx_switch_enable(adev, false);
1281                 sdma_v3_0_enable(adev, false);
1282         }
1283
1284         return 0;
1285 }
1286
1287 static int sdma_v3_0_post_soft_reset(void *handle)
1288 {
1289         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290         u32 srbm_soft_reset = 0;
1291
1292         if (!adev->sdma.srbm_soft_reset)
1293                 return 0;
1294
1295         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1296
1297         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1298             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1299                 sdma_v3_0_gfx_resume(adev);
1300                 sdma_v3_0_rlc_resume(adev);
1301         }
1302
1303         return 0;
1304 }
1305
1306 static int sdma_v3_0_soft_reset(void *handle)
1307 {
1308         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1309         u32 srbm_soft_reset = 0;
1310         u32 tmp;
1311
1312         if (!adev->sdma.srbm_soft_reset)
1313                 return 0;
1314
1315         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1316
1317         if (srbm_soft_reset) {
1318                 tmp = RREG32(mmSRBM_SOFT_RESET);
1319                 tmp |= srbm_soft_reset;
1320                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1321                 WREG32(mmSRBM_SOFT_RESET, tmp);
1322                 tmp = RREG32(mmSRBM_SOFT_RESET);
1323
1324                 udelay(50);
1325
1326                 tmp &= ~srbm_soft_reset;
1327                 WREG32(mmSRBM_SOFT_RESET, tmp);
1328                 tmp = RREG32(mmSRBM_SOFT_RESET);
1329
1330                 /* Wait a little for things to settle down */
1331                 udelay(50);
1332         }
1333
1334         return 0;
1335 }
1336
1337 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1338                                         struct amdgpu_irq_src *source,
1339                                         unsigned type,
1340                                         enum amdgpu_interrupt_state state)
1341 {
1342         u32 sdma_cntl;
1343
1344         switch (type) {
1345         case AMDGPU_SDMA_IRQ_INSTANCE0:
1346                 switch (state) {
1347                 case AMDGPU_IRQ_STATE_DISABLE:
1348                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1349                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1350                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1351                         break;
1352                 case AMDGPU_IRQ_STATE_ENABLE:
1353                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1354                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1355                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1356                         break;
1357                 default:
1358                         break;
1359                 }
1360                 break;
1361         case AMDGPU_SDMA_IRQ_INSTANCE1:
1362                 switch (state) {
1363                 case AMDGPU_IRQ_STATE_DISABLE:
1364                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1365                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1366                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1367                         break;
1368                 case AMDGPU_IRQ_STATE_ENABLE:
1369                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1370                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1371                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1372                         break;
1373                 default:
1374                         break;
1375                 }
1376                 break;
1377         default:
1378                 break;
1379         }
1380         return 0;
1381 }
1382
1383 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1384                                       struct amdgpu_irq_src *source,
1385                                       struct amdgpu_iv_entry *entry)
1386 {
1387         u8 instance_id, queue_id;
1388
1389         instance_id = (entry->ring_id & 0x3) >> 0;
1390         queue_id = (entry->ring_id & 0xc) >> 2;
1391         DRM_DEBUG("IH: SDMA trap\n");
1392         switch (instance_id) {
1393         case 0:
1394                 switch (queue_id) {
1395                 case 0:
1396                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1397                         break;
1398                 case 1:
1399                         /* XXX compute */
1400                         break;
1401                 case 2:
1402                         /* XXX compute */
1403                         break;
1404                 }
1405                 break;
1406         case 1:
1407                 switch (queue_id) {
1408                 case 0:
1409                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1410                         break;
1411                 case 1:
1412                         /* XXX compute */
1413                         break;
1414                 case 2:
1415                         /* XXX compute */
1416                         break;
1417                 }
1418                 break;
1419         }
1420         return 0;
1421 }
1422
1423 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1424                                               struct amdgpu_irq_src *source,
1425                                               struct amdgpu_iv_entry *entry)
1426 {
1427         u8 instance_id, queue_id;
1428
1429         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1430         instance_id = (entry->ring_id & 0x3) >> 0;
1431         queue_id = (entry->ring_id & 0xc) >> 2;
1432
1433         if (instance_id <= 1 && queue_id == 0)
1434                 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1435         return 0;
1436 }
1437
1438 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1439                 struct amdgpu_device *adev,
1440                 bool enable)
1441 {
1442         uint32_t temp, data;
1443         int i;
1444
1445         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1446                 for (i = 0; i < adev->sdma.num_instances; i++) {
1447                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1448                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1449                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1450                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1451                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1452                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1453                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1454                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1455                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1456                         if (data != temp)
1457                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1458                 }
1459         } else {
1460                 for (i = 0; i < adev->sdma.num_instances; i++) {
1461                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1462                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1463                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1464                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1465                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1466                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1467                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1468                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1469                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1470
1471                         if (data != temp)
1472                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1473                 }
1474         }
1475 }
1476
1477 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1478                 struct amdgpu_device *adev,
1479                 bool enable)
1480 {
1481         uint32_t temp, data;
1482         int i;
1483
1484         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1485                 for (i = 0; i < adev->sdma.num_instances; i++) {
1486                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1487                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1488
1489                         if (temp != data)
1490                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1491                 }
1492         } else {
1493                 for (i = 0; i < adev->sdma.num_instances; i++) {
1494                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1495                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1496
1497                         if (temp != data)
1498                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1499                 }
1500         }
1501 }
1502
1503 static int sdma_v3_0_set_clockgating_state(void *handle,
1504                                           enum amd_clockgating_state state)
1505 {
1506         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1507
1508         if (amdgpu_sriov_vf(adev))
1509                 return 0;
1510
1511         switch (adev->asic_type) {
1512         case CHIP_FIJI:
1513         case CHIP_CARRIZO:
1514         case CHIP_STONEY:
1515                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1516                                 state == AMD_CG_STATE_GATE);
1517                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1518                                 state == AMD_CG_STATE_GATE);
1519                 break;
1520         default:
1521                 break;
1522         }
1523         return 0;
1524 }
1525
1526 static int sdma_v3_0_set_powergating_state(void *handle,
1527                                           enum amd_powergating_state state)
1528 {
1529         return 0;
1530 }
1531
1532 static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags)
1533 {
1534         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1535         int data;
1536
1537         if (amdgpu_sriov_vf(adev))
1538                 *flags = 0;
1539
1540         /* AMD_CG_SUPPORT_SDMA_MGCG */
1541         data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1542         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1543                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1544
1545         /* AMD_CG_SUPPORT_SDMA_LS */
1546         data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1547         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1548                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1549 }
1550
1551 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1552         .name = "sdma_v3_0",
1553         .early_init = sdma_v3_0_early_init,
1554         .late_init = NULL,
1555         .sw_init = sdma_v3_0_sw_init,
1556         .sw_fini = sdma_v3_0_sw_fini,
1557         .hw_init = sdma_v3_0_hw_init,
1558         .hw_fini = sdma_v3_0_hw_fini,
1559         .suspend = sdma_v3_0_suspend,
1560         .resume = sdma_v3_0_resume,
1561         .is_idle = sdma_v3_0_is_idle,
1562         .wait_for_idle = sdma_v3_0_wait_for_idle,
1563         .check_soft_reset = sdma_v3_0_check_soft_reset,
1564         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1565         .post_soft_reset = sdma_v3_0_post_soft_reset,
1566         .soft_reset = sdma_v3_0_soft_reset,
1567         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1568         .set_powergating_state = sdma_v3_0_set_powergating_state,
1569         .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1570 };
1571
1572 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1573         .type = AMDGPU_RING_TYPE_SDMA,
1574         .align_mask = 0xf,
1575         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1576         .support_64bit_ptrs = false,
1577         .secure_submission_supported = true,
1578         .get_rptr = sdma_v3_0_ring_get_rptr,
1579         .get_wptr = sdma_v3_0_ring_get_wptr,
1580         .set_wptr = sdma_v3_0_ring_set_wptr,
1581         .emit_frame_size =
1582                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1583                 3 + /* hdp invalidate */
1584                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1585                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1586                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1587         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1588         .emit_ib = sdma_v3_0_ring_emit_ib,
1589         .emit_fence = sdma_v3_0_ring_emit_fence,
1590         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1591         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1592         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1593         .test_ring = sdma_v3_0_ring_test_ring,
1594         .test_ib = sdma_v3_0_ring_test_ib,
1595         .insert_nop = sdma_v3_0_ring_insert_nop,
1596         .pad_ib = sdma_v3_0_ring_pad_ib,
1597         .emit_wreg = sdma_v3_0_ring_emit_wreg,
1598 };
1599
1600 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1601 {
1602         int i;
1603
1604         for (i = 0; i < adev->sdma.num_instances; i++) {
1605                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1606                 adev->sdma.instance[i].ring.me = i;
1607         }
1608 }
1609
1610 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1611         .set = sdma_v3_0_set_trap_irq_state,
1612         .process = sdma_v3_0_process_trap_irq,
1613 };
1614
1615 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1616         .process = sdma_v3_0_process_illegal_inst_irq,
1617 };
1618
1619 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1620 {
1621         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1622         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1623         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1624 }
1625
1626 /**
1627  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1628  *
1629  * @ib: indirect buffer to copy to
1630  * @src_offset: src GPU address
1631  * @dst_offset: dst GPU address
1632  * @byte_count: number of bytes to xfer
1633  * @tmz: unused
1634  *
1635  * Copy GPU buffers using the DMA engine (VI).
1636  * Used by the amdgpu ttm implementation to move pages if
1637  * registered as the asic copy callback.
1638  */
1639 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1640                                        uint64_t src_offset,
1641                                        uint64_t dst_offset,
1642                                        uint32_t byte_count,
1643                                        bool tmz)
1644 {
1645         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1646                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1647         ib->ptr[ib->length_dw++] = byte_count;
1648         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1649         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1650         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1651         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1652         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1653 }
1654
1655 /**
1656  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1657  *
1658  * @ib: indirect buffer to copy to
1659  * @src_data: value to write to buffer
1660  * @dst_offset: dst GPU address
1661  * @byte_count: number of bytes to xfer
1662  *
1663  * Fill GPU buffers using the DMA engine (VI).
1664  */
1665 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1666                                        uint32_t src_data,
1667                                        uint64_t dst_offset,
1668                                        uint32_t byte_count)
1669 {
1670         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1671         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1672         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1673         ib->ptr[ib->length_dw++] = src_data;
1674         ib->ptr[ib->length_dw++] = byte_count;
1675 }
1676
1677 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1678         .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1679         .copy_num_dw = 7,
1680         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1681
1682         .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1683         .fill_num_dw = 5,
1684         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1685 };
1686
1687 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1688 {
1689         adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1690         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1691 }
1692
1693 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1694         .copy_pte_num_dw = 7,
1695         .copy_pte = sdma_v3_0_vm_copy_pte,
1696
1697         .write_pte = sdma_v3_0_vm_write_pte,
1698         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1699 };
1700
1701 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1702 {
1703         unsigned i;
1704
1705         adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1706         for (i = 0; i < adev->sdma.num_instances; i++) {
1707                 adev->vm_manager.vm_pte_scheds[i] =
1708                          &adev->sdma.instance[i].ring.sched;
1709         }
1710         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1711 }
1712
1713 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1714 {
1715         .type = AMD_IP_BLOCK_TYPE_SDMA,
1716         .major = 3,
1717         .minor = 0,
1718         .rev = 0,
1719         .funcs = &sdma_v3_0_ip_funcs,
1720 };
1721
1722 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1723 {
1724         .type = AMD_IP_BLOCK_TYPE_SDMA,
1725         .major = 3,
1726         .minor = 1,
1727         .rev = 0,
1728         .funcs = &sdma_v3_0_ip_funcs,
1729 };