drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/module.h>
  26 #include "amdgpu.h"
  27 #include "soc15_common.h"
  28 #include "soc21.h"
  29 #include "gc/gc_11_0_0_offset.h"
  30 #include "gc/gc_11_0_0_sh_mask.h"
  31 #include "gc/gc_11_0_0_default.h"
  32 #include "v11_structs.h"
  33 #include "mes_v11_api_def.h"
  34
  35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin");
  36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin");
  37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin");
  38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin");
  39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin");
  40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin");
  41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin");
  42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin");
  43
  44 static int mes_v11_0_hw_fini(void *handle);
  45 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev);
  46 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev);
  47
  48 #define MES_EOP_SIZE   2048
  49
  50 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring)
  51 {
  52         struct amdgpu_device *adev = ring->adev;
  53
  54         if (ring->use_doorbell) {
  55                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
  56                              ring->wptr);
  57                 WDOORBELL64(ring->doorbell_index, ring->wptr);
  58         } else {
  59                 BUG();
  60         }
  61 }
  62
  63 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring)
  64 {
  65         return *ring->rptr_cpu_addr;
  66 }
  67
  68 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring)
  69 {
  70         u64 wptr;
  71
  72         if (ring->use_doorbell)
  73                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
  74         else
  75                 BUG();
  76         return wptr;
  77 }
  78
  79 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = {
  80         .type = AMDGPU_RING_TYPE_MES,
  81         .align_mask = 1,
  82         .nop = 0,
  83         .support_64bit_ptrs = true,
  84         .get_rptr = mes_v11_0_ring_get_rptr,
  85         .get_wptr = mes_v11_0_ring_get_wptr,
  86         .set_wptr = mes_v11_0_ring_set_wptr,
  87         .insert_nop = amdgpu_ring_insert_nop,
  88 };
  89
  90 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
  91                                                     void *pkt, int size,
  92                                                     int api_status_off)
  93 {
  94         int ndw = size / 4;
  95         signed long r;
  96         union MESAPI__ADD_QUEUE *x_pkt = pkt;
  97         struct MES_API_STATUS *api_status;
  98         struct amdgpu_device *adev = mes->adev;
  99         struct amdgpu_ring *ring = &mes->ring;
 100         unsigned long flags;
 101         signed long timeout = adev->usec_timeout;
 102
 103         if (amdgpu_emu_mode) {
 104                 timeout *= 100;
 105         } else if (amdgpu_sriov_vf(adev)) {
 106                 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
 107                 timeout = 15 * 600 * 1000;
 108         }
 109         BUG_ON(size % 4 != 0);
 110
 111         spin_lock_irqsave(&mes->ring_lock, flags);
 112         if (amdgpu_ring_alloc(ring, ndw)) {
 113                 spin_unlock_irqrestore(&mes->ring_lock, flags);
 114                 return -ENOMEM;
 115         }
 116
 117         api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off);
 118         api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr;
 119         api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq;
 120
 121         amdgpu_ring_write_multiple(ring, pkt, ndw);
 122         amdgpu_ring_commit(ring);
 123         spin_unlock_irqrestore(&mes->ring_lock, flags);
 124
 125         DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
 126
 127         r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
 128                       timeout);
 129         if (r < 1) {
 130                 DRM_ERROR("MES failed to response msg=%d\n",
 131                           x_pkt->header.opcode);
 132                 return -ETIMEDOUT;
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int convert_to_mes_queue_type(int queue_type)
 139 {
 140         if (queue_type == AMDGPU_RING_TYPE_GFX)
 141                 return MES_QUEUE_TYPE_GFX;
 142         else if (queue_type == AMDGPU_RING_TYPE_COMPUTE)
 143                 return MES_QUEUE_TYPE_COMPUTE;
 144         else if (queue_type == AMDGPU_RING_TYPE_SDMA)
 145                 return MES_QUEUE_TYPE_SDMA;
 146         else
 147                 BUG();
 148         return -1;
 149 }
 150
 151 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes,
 152                                   struct mes_add_queue_input *input)
 153 {
 154         struct amdgpu_device *adev = mes->adev;
 155         union MESAPI__ADD_QUEUE mes_add_queue_pkt;
 156         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 157         uint32_t vm_cntx_cntl = hub->vm_cntx_cntl;
 158
 159         memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt));
 160
 161         mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 162         mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE;
 163         mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 164
 165         mes_add_queue_pkt.process_id = input->process_id;
 166         mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr;
 167         mes_add_queue_pkt.process_va_start = input->process_va_start;
 168         mes_add_queue_pkt.process_va_end = input->process_va_end;
 169         mes_add_queue_pkt.process_quantum = input->process_quantum;
 170         mes_add_queue_pkt.process_context_addr = input->process_context_addr;
 171         mes_add_queue_pkt.gang_quantum = input->gang_quantum;
 172         mes_add_queue_pkt.gang_context_addr = input->gang_context_addr;
 173         mes_add_queue_pkt.inprocess_gang_priority =
 174                 input->inprocess_gang_priority;
 175         mes_add_queue_pkt.gang_global_priority_level =
 176                 input->gang_global_priority_level;
 177         mes_add_queue_pkt.doorbell_offset = input->doorbell_offset;
 178         mes_add_queue_pkt.mqd_addr = input->mqd_addr;
 179
 180         if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >>
 181                         AMDGPU_MES_API_VERSION_SHIFT) >= 2)
 182                 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr;
 183         else
 184                 mes_add_queue_pkt.wptr_addr = input->wptr_addr;
 185
 186         mes_add_queue_pkt.queue_type =
 187                 convert_to_mes_queue_type(input->queue_type);
 188         mes_add_queue_pkt.paging = input->paging;
 189         mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl;
 190         mes_add_queue_pkt.gws_base = input->gws_base;
 191         mes_add_queue_pkt.gws_size = input->gws_size;
 192         mes_add_queue_pkt.trap_handler_addr = input->tba_addr;
 193         mes_add_queue_pkt.tma_addr = input->tma_addr;
 194         mes_add_queue_pkt.is_kfd_process = input->is_kfd_process;
 195         mes_add_queue_pkt.trap_en = 1;
 196
 197         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 198         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 199         mes_add_queue_pkt.gds_size = input->queue_size;
 200
 201         if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) &&
 202                   (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) &&
 203                   (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3))))
 204                 mes_add_queue_pkt.trap_en = 1;
 205
 206         /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */
 207         mes_add_queue_pkt.is_aql_queue = input->is_aql_queue;
 208         mes_add_queue_pkt.gds_size = input->queue_size;
 209
 210         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 211                         &mes_add_queue_pkt, sizeof(mes_add_queue_pkt),
 212                         offsetof(union MESAPI__ADD_QUEUE, api_status));
 213 }
 214
 215 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes,
 216                                      struct mes_remove_queue_input *input)
 217 {
 218         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 219
 220         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 221
 222         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 223         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 224         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 225
 226         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 227         mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr;
 228
 229         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 230                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 231                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 232 }
 233
 234 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes,
 235                         struct mes_unmap_legacy_queue_input *input)
 236 {
 237         union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt;
 238
 239         memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt));
 240
 241         mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER;
 242         mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE;
 243         mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 244
 245         mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset;
 246         mes_remove_queue_pkt.gang_context_addr = 0;
 247
 248         mes_remove_queue_pkt.pipe_id = input->pipe_id;
 249         mes_remove_queue_pkt.queue_id = input->queue_id;
 250
 251         if (input->action == PREEMPT_QUEUES_NO_UNMAP) {
 252                 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1;
 253                 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr;
 254                 mes_remove_queue_pkt.tf_data =
 255                         lower_32_bits(input->trail_fence_data);
 256         } else {
 257                 mes_remove_queue_pkt.unmap_legacy_queue = 1;
 258                 mes_remove_queue_pkt.queue_type =
 259                         convert_to_mes_queue_type(input->queue_type);
 260         }
 261
 262         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 263                         &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt),
 264                         offsetof(union MESAPI__REMOVE_QUEUE, api_status));
 265 }
 266
 267 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes,
 268                                   struct mes_suspend_gang_input *input)
 269 {
 270         return 0;
 271 }
 272
 273 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes,
 274                                  struct mes_resume_gang_input *input)
 275 {
 276         return 0;
 277 }
 278
 279 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes)
 280 {
 281         union MESAPI__QUERY_MES_STATUS mes_status_pkt;
 282
 283         memset(&mes_status_pkt, 0, sizeof(mes_status_pkt));
 284
 285         mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER;
 286         mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS;
 287         mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 288
 289         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 290                         &mes_status_pkt, sizeof(mes_status_pkt),
 291                         offsetof(union MESAPI__QUERY_MES_STATUS, api_status));
 292 }
 293
 294 static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
 295                              struct mes_misc_op_input *input)
 296 {
 297         union MESAPI__MISC misc_pkt;
 298
 299         memset(&misc_pkt, 0, sizeof(misc_pkt));
 300
 301         misc_pkt.header.type = MES_API_TYPE_SCHEDULER;
 302         misc_pkt.header.opcode = MES_SCH_API_MISC;
 303         misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 304
 305         switch (input->op) {
 306         case MES_MISC_OP_READ_REG:
 307                 misc_pkt.opcode = MESAPI_MISC__READ_REG;
 308                 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset;
 309                 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr;
 310                 break;
 311         case MES_MISC_OP_WRITE_REG:
 312                 misc_pkt.opcode = MESAPI_MISC__WRITE_REG;
 313                 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset;
 314                 misc_pkt.write_reg.reg_value = input->write_reg.reg_value;
 315                 break;
 316         case MES_MISC_OP_WRM_REG_WAIT:
 317                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 318                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM;
 319                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 320                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 321                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 322                 misc_pkt.wait_reg_mem.reg_offset2 = 0;
 323                 break;
 324         case MES_MISC_OP_WRM_REG_WR_WAIT:
 325                 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM;
 326                 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG;
 327                 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref;
 328                 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask;
 329                 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0;
 330                 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1;
 331                 break;
 332         default:
 333                 DRM_ERROR("unsupported misc op (%d) \n", input->op);
 334                 return -EINVAL;
 335         }
 336
 337         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 338                         &misc_pkt, sizeof(misc_pkt),
 339                         offsetof(union MESAPI__MISC, api_status));
 340 }
 341
 342 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
 343 {
 344         int i;
 345         struct amdgpu_device *adev = mes->adev;
 346         union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 347
 348         memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt));
 349
 350         mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER;
 351         mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC;
 352         mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 353
 354         mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub;
 355         mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub;
 356         mes_set_hw_res_pkt.gds_size = adev->gds.gds_size;
 357         mes_set_hw_res_pkt.paging_vmid = 0;
 358         mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr;
 359         mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr =
 360                 mes->query_status_fence_gpu_addr;
 361
 362         for (i = 0; i < MAX_COMPUTE_PIPES; i++)
 363                 mes_set_hw_res_pkt.compute_hqd_mask[i] =
 364                         mes->compute_hqd_mask[i];
 365
 366         for (i = 0; i < MAX_GFX_PIPES; i++)
 367                 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i];
 368
 369         for (i = 0; i < MAX_SDMA_PIPES; i++)
 370                 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
 371
 372         for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++)
 373                 mes_set_hw_res_pkt.aggregated_doorbells[i] =
 374                         mes->aggregated_doorbells[i];
 375
 376         for (i = 0; i < 5; i++) {
 377                 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i];
 378                 mes_set_hw_res_pkt.mmhub_base[i] =
 379                                 adev->reg_offset[MMHUB_HWIP][0][i];
 380                 mes_set_hw_res_pkt.osssys_base[i] =
 381                 adev->reg_offset[OSSSYS_HWIP][0][i];
 382         }
 383
 384         mes_set_hw_res_pkt.disable_reset = 1;
 385         mes_set_hw_res_pkt.disable_mes_log = 1;
 386         mes_set_hw_res_pkt.use_different_vmid_compute = 1;
 387         mes_set_hw_res_pkt.oversubscription_timer = 50;
 388
 389         return mes_v11_0_submit_pkt_and_poll_completion(mes,
 390                         &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 391                         offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
 392 }
 393
 394 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes)
 395 {
 396         struct amdgpu_device *adev = mes->adev;
 397         uint32_t data;
 398
 399         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1);
 400         data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK |
 401                   CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK |
 402                   CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK);
 403         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] <<
 404                 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT;
 405         data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT;
 406         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data);
 407
 408         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2);
 409         data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK |
 410                   CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK |
 411                   CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK);
 412         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] <<
 413                 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT;
 414         data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT;
 415         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data);
 416
 417         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3);
 418         data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK |
 419                   CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK |
 420                   CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK);
 421         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] <<
 422                 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT;
 423         data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT;
 424         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data);
 425
 426         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4);
 427         data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK |
 428                   CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK |
 429                   CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK);
 430         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] <<
 431                 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT;
 432         data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT;
 433         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data);
 434
 435         data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5);
 436         data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK |
 437                   CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK |
 438                   CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK);
 439         data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] <<
 440                 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT;
 441         data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT;
 442         WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data);
 443
 444         data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT;
 445         WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data);
 446 }
 447
 448 static const struct amdgpu_mes_funcs mes_v11_0_funcs = {
 449         .add_hw_queue = mes_v11_0_add_hw_queue,
 450         .remove_hw_queue = mes_v11_0_remove_hw_queue,
 451         .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue,
 452         .suspend_gang = mes_v11_0_suspend_gang,
 453         .resume_gang = mes_v11_0_resume_gang,
 454         .misc_op = mes_v11_0_misc_op,
 455 };
 456
 457 static int mes_v11_0_init_microcode(struct amdgpu_device *adev,
 458                                     enum admgpu_mes_pipe pipe)
 459 {
 460         char fw_name[30];
 461         char ucode_prefix[30];
 462         int err;
 463         const struct mes_firmware_header_v1_0 *mes_hdr;
 464         struct amdgpu_firmware_info *info;
 465
 466         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 467
 468         if (pipe == AMDGPU_MES_SCHED_PIPE)
 469                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin",
 470                          ucode_prefix);
 471         else
 472                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin",
 473                          ucode_prefix);
 474
 475         err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev);
 476         if (err)
 477                 return err;
 478
 479         err = amdgpu_ucode_validate(adev->mes.fw[pipe]);
 480         if (err) {
 481                 release_firmware(adev->mes.fw[pipe]);
 482                 adev->mes.fw[pipe] = NULL;
 483                 return err;
 484         }
 485
 486         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 487                 adev->mes.fw[pipe]->data;
 488         adev->mes.ucode_fw_version[pipe] =
 489                 le32_to_cpu(mes_hdr->mes_ucode_version);
 490         adev->mes.ucode_fw_version[pipe] =
 491                 le32_to_cpu(mes_hdr->mes_ucode_data_version);
 492         adev->mes.uc_start_addr[pipe] =
 493                 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) |
 494                 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32);
 495         adev->mes.data_start_addr[pipe] =
 496                 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) |
 497                 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32);
 498
 499         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 500                 int ucode, ucode_data;
 501
 502                 if (pipe == AMDGPU_MES_SCHED_PIPE) {
 503                         ucode = AMDGPU_UCODE_ID_CP_MES;
 504                         ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA;
 505                 } else {
 506                         ucode = AMDGPU_UCODE_ID_CP_MES1;
 507                         ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA;
 508                 }
 509
 510                 info = &adev->firmware.ucode[ucode];
 511                 info->ucode_id = ucode;
 512                 info->fw = adev->mes.fw[pipe];
 513                 adev->firmware.fw_size +=
 514                         ALIGN(le32_to_cpu(mes_hdr->mes_ucode_size_bytes),
 515                               PAGE_SIZE);
 516
 517                 info = &adev->firmware.ucode[ucode_data];
 518                 info->ucode_id = ucode_data;
 519                 info->fw = adev->mes.fw[pipe];
 520                 adev->firmware.fw_size +=
 521                         ALIGN(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes),
 522                               PAGE_SIZE);
 523         }
 524
 525         return 0;
 526 }
 527
 528 static void mes_v11_0_free_microcode(struct amdgpu_device *adev,
 529                                      enum admgpu_mes_pipe pipe)
 530 {
 531         release_firmware(adev->mes.fw[pipe]);
 532         adev->mes.fw[pipe] = NULL;
 533 }
 534
 535 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev,
 536                                            enum admgpu_mes_pipe pipe)
 537 {
 538         int r;
 539         const struct mes_firmware_header_v1_0 *mes_hdr;
 540         const __le32 *fw_data;
 541         unsigned fw_size;
 542
 543         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 544                 adev->mes.fw[pipe]->data;
 545
 546         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 547                    le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
 548         fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 549
 550         r = amdgpu_bo_create_reserved(adev, fw_size,
 551                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 552                                       &adev->mes.ucode_fw_obj[pipe],
 553                                       &adev->mes.ucode_fw_gpu_addr[pipe],
 554                                       (void **)&adev->mes.ucode_fw_ptr[pipe]);
 555         if (r) {
 556                 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r);
 557                 return r;
 558         }
 559
 560         memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size);
 561
 562         amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]);
 563         amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]);
 564
 565         return 0;
 566 }
 567
 568 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev,
 569                                                 enum admgpu_mes_pipe pipe)
 570 {
 571         int r;
 572         const struct mes_firmware_header_v1_0 *mes_hdr;
 573         const __le32 *fw_data;
 574         unsigned fw_size;
 575
 576         mes_hdr = (const struct mes_firmware_header_v1_0 *)
 577                 adev->mes.fw[pipe]->data;
 578
 579         fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
 580                    le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
 581         fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 582
 583         r = amdgpu_bo_create_reserved(adev, fw_size,
 584                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
 585                                       &adev->mes.data_fw_obj[pipe],
 586                                       &adev->mes.data_fw_gpu_addr[pipe],
 587                                       (void **)&adev->mes.data_fw_ptr[pipe]);
 588         if (r) {
 589                 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r);
 590                 return r;
 591         }
 592
 593         memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size);
 594
 595         amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]);
 596         amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]);
 597
 598         return 0;
 599 }
 600
 601 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev,
 602                                          enum admgpu_mes_pipe pipe)
 603 {
 604         amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe],
 605                               &adev->mes.data_fw_gpu_addr[pipe],
 606                               (void **)&adev->mes.data_fw_ptr[pipe]);
 607
 608         amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe],
 609                               &adev->mes.ucode_fw_gpu_addr[pipe],
 610                               (void **)&adev->mes.ucode_fw_ptr[pipe]);
 611 }
 612
 613 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable)
 614 {
 615         uint64_t ucode_addr;
 616         uint32_t pipe, data = 0;
 617
 618         if (enable) {
 619                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 620                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 621                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 622                              MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0);
 623                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 624
 625                 mutex_lock(&adev->srbm_mutex);
 626                 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
 627                         if (!adev->enable_mes_kiq &&
 628                             pipe == AMDGPU_MES_KIQ_PIPE)
 629                                 continue;
 630
 631                         soc21_grbm_select(adev, 3, pipe, 0, 0);
 632
 633                         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 634                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 635                                      lower_32_bits(ucode_addr));
 636                         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 637                                      upper_32_bits(ucode_addr));
 638                 }
 639                 soc21_grbm_select(adev, 0, 0, 0, 0);
 640                 mutex_unlock(&adev->srbm_mutex);
 641
 642                 /* unhalt MES and activate pipe0 */
 643                 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1);
 644                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE,
 645                                      adev->enable_mes_kiq ? 1 : 0);
 646                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 647
 648                 if (amdgpu_emu_mode)
 649                         msleep(100);
 650                 else
 651                         udelay(50);
 652         } else {
 653                 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL);
 654                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0);
 655                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0);
 656                 data = REG_SET_FIELD(data, CP_MES_CNTL,
 657                                      MES_INVALIDATE_ICACHE, 1);
 658                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1);
 659                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET,
 660                                      adev->enable_mes_kiq ? 1 : 0);
 661                 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1);
 662                 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data);
 663         }
 664 }
 665
 666 /* This function is for backdoor MES firmware */
 667 static int mes_v11_0_load_microcode(struct amdgpu_device *adev,
 668                                     enum admgpu_mes_pipe pipe, bool prime_icache)
 669 {
 670         int r;
 671         uint32_t data;
 672         uint64_t ucode_addr;
 673
 674         mes_v11_0_enable(adev, false);
 675
 676         if (!adev->mes.fw[pipe])
 677                 return -EINVAL;
 678
 679         r = mes_v11_0_allocate_ucode_buffer(adev, pipe);
 680         if (r)
 681                 return r;
 682
 683         r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe);
 684         if (r) {
 685                 mes_v11_0_free_ucode_buffers(adev, pipe);
 686                 return r;
 687         }
 688
 689         mutex_lock(&adev->srbm_mutex);
 690         /* me=3, pipe=0, queue=0 */
 691         soc21_grbm_select(adev, 3, pipe, 0, 0);
 692
 693         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0);
 694
 695         /* set ucode start address */
 696         ucode_addr = adev->mes.uc_start_addr[pipe] >> 2;
 697         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START,
 698                      lower_32_bits(ucode_addr));
 699         WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI,
 700                      upper_32_bits(ucode_addr));
 701
 702         /* set ucode fimrware address */
 703         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO,
 704                      lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 705         WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI,
 706                      upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe]));
 707
 708         /* set ucode instruction cache boundary to 2M-1 */
 709         WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF);
 710
 711         /* set ucode data firmware address */
 712         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO,
 713                      lower_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 714         WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI,
 715                      upper_32_bits(adev->mes.data_fw_gpu_addr[pipe]));
 716
 717         /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */
 718         WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF);
 719
 720         if (prime_icache) {
 721                 /* invalidate ICACHE */
 722                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 723                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
 724                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
 725                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 726
 727                 /* prime the ICACHE. */
 728                 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL);
 729                 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
 730                 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data);
 731         }
 732
 733         soc21_grbm_select(adev, 0, 0, 0, 0);
 734         mutex_unlock(&adev->srbm_mutex);
 735
 736         return 0;
 737 }
 738
 739 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev,
 740                                       enum admgpu_mes_pipe pipe)
 741 {
 742         int r;
 743         u32 *eop;
 744
 745         r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE,
 746                               AMDGPU_GEM_DOMAIN_GTT,
 747                               &adev->mes.eop_gpu_obj[pipe],
 748                               &adev->mes.eop_gpu_addr[pipe],
 749                               (void **)&eop);
 750         if (r) {
 751                 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r);
 752                 return r;
 753         }
 754
 755         memset(eop, 0,
 756                adev->mes.eop_gpu_obj[pipe]->tbo.base.size);
 757
 758         amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]);
 759         amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]);
 760
 761         return 0;
 762 }
 763
 764 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring)
 765 {
 766         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 767         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
 768         uint32_t tmp;
 769
 770         mqd->header = 0xC0310800;
 771         mqd->compute_pipelinestat_enable = 0x00000001;
 772         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
 773         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
 774         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
 775         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
 776         mqd->compute_misc_reserved = 0x00000007;
 777
 778         eop_base_addr = ring->eop_gpu_addr >> 8;
 779
 780         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
 781         tmp = regCP_HQD_EOP_CONTROL_DEFAULT;
 782         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
 783                         (order_base_2(MES_EOP_SIZE / 4) - 1));
 784
 785         mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr);
 786         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
 787         mqd->cp_hqd_eop_control = tmp;
 788
 789         /* disable the queue if it's active */
 790         ring->wptr = 0;
 791         mqd->cp_hqd_pq_rptr = 0;
 792         mqd->cp_hqd_pq_wptr_lo = 0;
 793         mqd->cp_hqd_pq_wptr_hi = 0;
 794
 795         /* set the pointer to the MQD */
 796         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
 797         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
 798
 799         /* set MQD vmid to 0 */
 800         tmp = regCP_MQD_CONTROL_DEFAULT;
 801         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
 802         mqd->cp_mqd_control = tmp;
 803
 804         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
 805         hqd_gpu_addr = ring->gpu_addr >> 8;
 806         mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr);
 807         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
 808
 809         /* set the wb address whether it's enabled or not */
 810         wb_gpu_addr = ring->rptr_gpu_addr;
 811         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
 812         mqd->cp_hqd_pq_rptr_report_addr_hi =
 813                 upper_32_bits(wb_gpu_addr) & 0xffff;
 814
 815         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
 816         wb_gpu_addr = ring->wptr_gpu_addr;
 817         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8;
 818         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 819
 820         /* set up the HQD, this is similar to CP_RB0_CNTL */
 821         tmp = regCP_HQD_PQ_CONTROL_DEFAULT;
 822         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
 823                             (order_base_2(ring->ring_size / 4) - 1));
 824         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
 825                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
 826         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);
 827         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
 828         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
 829         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
 830         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1);
 831         mqd->cp_hqd_pq_control = tmp;
 832
 833         /* enable doorbell */
 834         tmp = 0;
 835         if (ring->use_doorbell) {
 836                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 837                                     DOORBELL_OFFSET, ring->doorbell_index);
 838                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 839                                     DOORBELL_EN, 1);
 840                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 841                                     DOORBELL_SOURCE, 0);
 842                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 843                                     DOORBELL_HIT, 0);
 844         }
 845         else
 846                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
 847                                     DOORBELL_EN, 0);
 848         mqd->cp_hqd_pq_doorbell_control = tmp;
 849
 850         mqd->cp_hqd_vmid = 0;
 851         /* activate the queue */
 852         mqd->cp_hqd_active = 1;
 853
 854         tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT;
 855         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE,
 856                             PRELOAD_SIZE, 0x55);
 857         mqd->cp_hqd_persistent_state = tmp;
 858
 859         mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT;
 860         mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT;
 861         mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT;
 862
 863         return 0;
 864 }
 865
 866 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring)
 867 {
 868         struct v11_compute_mqd *mqd = ring->mqd_ptr;
 869         struct amdgpu_device *adev = ring->adev;
 870         uint32_t data = 0;
 871
 872         mutex_lock(&adev->srbm_mutex);
 873         soc21_grbm_select(adev, 3, ring->pipe, 0, 0);
 874
 875         /* set CP_HQD_VMID.VMID = 0. */
 876         data = RREG32_SOC15(GC, 0, regCP_HQD_VMID);
 877         data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0);
 878         WREG32_SOC15(GC, 0, regCP_HQD_VMID, data);
 879
 880         /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */
 881         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
 882         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
 883                              DOORBELL_EN, 0);
 884         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
 885
 886         /* set CP_MQD_BASE_ADDR/HI with the MQD base address */
 887         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
 888         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
 889
 890         /* set CP_MQD_CONTROL.VMID=0 */
 891         data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
 892         data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0);
 893         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0);
 894
 895         /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */
 896         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
 897         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
 898
 899         /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */
 900         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
 901                      mqd->cp_hqd_pq_rptr_report_addr_lo);
 902         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
 903                      mqd->cp_hqd_pq_rptr_report_addr_hi);
 904
 905         /* set CP_HQD_PQ_CONTROL */
 906         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control);
 907
 908         /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */
 909         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
 910                      mqd->cp_hqd_pq_wptr_poll_addr_lo);
 911         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
 912                      mqd->cp_hqd_pq_wptr_poll_addr_hi);
 913
 914         /* set CP_HQD_PQ_DOORBELL_CONTROL */
 915         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
 916                      mqd->cp_hqd_pq_doorbell_control);
 917
 918         /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */
 919         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state);
 920
 921         /* set CP_HQD_ACTIVE.ACTIVE=1 */
 922         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active);
 923
 924         soc21_grbm_select(adev, 0, 0, 0, 0);
 925         mutex_unlock(&adev->srbm_mutex);
 926 }
 927
 928 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev)
 929 {
 930         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 931         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
 932         int r;
 933
 934         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
 935                 return -EINVAL;
 936
 937         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
 938         if (r) {
 939                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
 940                 return r;
 941         }
 942
 943         kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring);
 944
 945         r = amdgpu_ring_test_ring(kiq_ring);
 946         if (r) {
 947                 DRM_ERROR("kfq enable failed\n");
 948                 kiq_ring->sched.ready = false;
 949         }
 950         return r;
 951 }
 952
 953 static int mes_v11_0_queue_init(struct amdgpu_device *adev,
 954                                 enum admgpu_mes_pipe pipe)
 955 {
 956         struct amdgpu_ring *ring;
 957         int r;
 958
 959         if (pipe == AMDGPU_MES_KIQ_PIPE)
 960                 ring = &adev->gfx.kiq.ring;
 961         else if (pipe == AMDGPU_MES_SCHED_PIPE)
 962                 ring = &adev->mes.ring;
 963         else
 964                 BUG();
 965
 966         if ((pipe == AMDGPU_MES_SCHED_PIPE) &&
 967             (amdgpu_in_reset(adev) || adev->in_suspend)) {
 968                 *(ring->wptr_cpu_addr) = 0;
 969                 *(ring->rptr_cpu_addr) = 0;
 970                 amdgpu_ring_clear_ring(ring);
 971         }
 972
 973         r = mes_v11_0_mqd_init(ring);
 974         if (r)
 975                 return r;
 976
 977         if (pipe == AMDGPU_MES_SCHED_PIPE) {
 978                 r = mes_v11_0_kiq_enable_queue(adev);
 979                 if (r)
 980                         return r;
 981         } else {
 982                 mes_v11_0_queue_init_register(ring);
 983         }
 984
 985         /* get MES scheduler/KIQ versions */
 986         mutex_lock(&adev->srbm_mutex);
 987         soc21_grbm_select(adev, 3, pipe, 0, 0);
 988
 989         if (pipe == AMDGPU_MES_SCHED_PIPE)
 990                 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
 991         else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
 992                 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
 993
 994         soc21_grbm_select(adev, 0, 0, 0, 0);
 995         mutex_unlock(&adev->srbm_mutex);
 996
 997         return 0;
 998 }
 999
1000 static int mes_v11_0_ring_init(struct amdgpu_device *adev)
1001 {
1002         struct amdgpu_ring *ring;
1003
1004         ring = &adev->mes.ring;
1005
1006         ring->funcs = &mes_v11_0_ring_funcs;
1007
1008         ring->me = 3;
1009         ring->pipe = 0;
1010         ring->queue = 0;
1011
1012         ring->ring_obj = NULL;
1013         ring->use_doorbell = true;
1014         ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1;
1015         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE];
1016         ring->no_scheduler = true;
1017         sprintf(ring->name, "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1018
1019         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1020                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1021 }
1022
1023 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev)
1024 {
1025         struct amdgpu_ring *ring;
1026
1027         spin_lock_init(&adev->gfx.kiq.ring_lock);
1028
1029         ring = &adev->gfx.kiq.ring;
1030
1031         ring->me = 3;
1032         ring->pipe = 1;
1033         ring->queue = 0;
1034
1035         ring->adev = NULL;
1036         ring->ring_obj = NULL;
1037         ring->use_doorbell = true;
1038         ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1;
1039         ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE];
1040         ring->no_scheduler = true;
1041         sprintf(ring->name, "mes_kiq_%d.%d.%d",
1042                 ring->me, ring->pipe, ring->queue);
1043
1044         return amdgpu_ring_init(adev, ring, 1024, NULL, 0,
1045                                 AMDGPU_RING_PRIO_DEFAULT, NULL);
1046 }
1047
1048 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev,
1049                                  enum admgpu_mes_pipe pipe)
1050 {
1051         int r, mqd_size = sizeof(struct v11_compute_mqd);
1052         struct amdgpu_ring *ring;
1053
1054         if (pipe == AMDGPU_MES_KIQ_PIPE)
1055                 ring = &adev->gfx.kiq.ring;
1056         else if (pipe == AMDGPU_MES_SCHED_PIPE)
1057                 ring = &adev->mes.ring;
1058         else
1059                 BUG();
1060
1061         if (ring->mqd_obj)
1062                 return 0;
1063
1064         r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
1065                                     AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj,
1066                                     &ring->mqd_gpu_addr, &ring->mqd_ptr);
1067         if (r) {
1068                 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r);
1069                 return r;
1070         }
1071
1072         memset(ring->mqd_ptr, 0, mqd_size);
1073
1074         /* prepare MQD backup */
1075         adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL);
1076         if (!adev->mes.mqd_backup[pipe])
1077                 dev_warn(adev->dev,
1078                          "no memory to create MQD backup for ring %s\n",
1079                          ring->name);
1080
1081         return 0;
1082 }
1083
1084 static int mes_v11_0_sw_init(void *handle)
1085 {
1086         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1087         int pipe, r;
1088
1089         adev->mes.adev = adev;
1090         adev->mes.funcs = &mes_v11_0_funcs;
1091         adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
1092         adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
1093
1094         r = amdgpu_mes_init(adev);
1095         if (r)
1096                 return r;
1097
1098         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1099                 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE)
1100                         continue;
1101
1102                 r = mes_v11_0_init_microcode(adev, pipe);
1103                 if (r)
1104                         return r;
1105
1106                 r = mes_v11_0_allocate_eop_buf(adev, pipe);
1107                 if (r)
1108                         return r;
1109
1110                 r = mes_v11_0_mqd_sw_init(adev, pipe);
1111                 if (r)
1112                         return r;
1113         }
1114
1115         if (adev->enable_mes_kiq) {
1116                 r = mes_v11_0_kiq_ring_init(adev);
1117                 if (r)
1118                         return r;
1119         }
1120
1121         r = mes_v11_0_ring_init(adev);
1122         if (r)
1123                 return r;
1124
1125         return 0;
1126 }
1127
1128 static int mes_v11_0_sw_fini(void *handle)
1129 {
1130         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1131         int pipe;
1132
1133         amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);
1134         amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);
1135
1136         for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) {
1137                 kfree(adev->mes.mqd_backup[pipe]);
1138
1139                 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe],
1140                                       &adev->mes.eop_gpu_addr[pipe],
1141                                       NULL);
1142
1143                 mes_v11_0_free_microcode(adev, pipe);
1144         }
1145
1146         amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj,
1147                               &adev->gfx.kiq.ring.mqd_gpu_addr,
1148                               &adev->gfx.kiq.ring.mqd_ptr);
1149
1150         amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj,
1151                               &adev->mes.ring.mqd_gpu_addr,
1152                               &adev->mes.ring.mqd_ptr);
1153
1154         amdgpu_ring_fini(&adev->gfx.kiq.ring);
1155         amdgpu_ring_fini(&adev->mes.ring);
1156
1157         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1158                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE);
1159                 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE);
1160         }
1161
1162         amdgpu_mes_fini(adev);
1163         return 0;
1164 }
1165
1166 static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev)
1167 {
1168         uint32_t data;
1169         int i;
1170
1171         mutex_lock(&adev->srbm_mutex);
1172         soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);
1173
1174         /* disable the queue if it's active */
1175         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
1176                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
1177                 for (i = 0; i < adev->usec_timeout; i++) {
1178                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
1179                                 break;
1180                         udelay(1);
1181                 }
1182         }
1183         data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
1184         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1185                                 DOORBELL_EN, 0);
1186         data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,
1187                                 DOORBELL_HIT, 1);
1188         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);
1189
1190         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);
1191
1192         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);
1193         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);
1194         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);
1195
1196         soc21_grbm_select(adev, 0, 0, 0, 0);
1197         mutex_unlock(&adev->srbm_mutex);
1198
1199         adev->mes.ring.sched.ready = false;
1200 }
1201
1202 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
1203 {
1204         uint32_t tmp;
1205         struct amdgpu_device *adev = ring->adev;
1206
1207         /* tell RLC which is KIQ queue */
1208         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
1209         tmp &= 0xffffff00;
1210         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
1211         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1212         tmp |= 0x80;
1213         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
1214 }
1215
1216 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
1217 {
1218         int r = 0;
1219
1220         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1221
1222                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false);
1223                 if (r) {
1224                         DRM_ERROR("failed to load MES fw, r=%d\n", r);
1225                         return r;
1226                 }
1227
1228                 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true);
1229                 if (r) {
1230                         DRM_ERROR("failed to load MES kiq fw, r=%d\n", r);
1231                         return r;
1232                 }
1233
1234         }
1235
1236         mes_v11_0_enable(adev, true);
1237
1238         mes_v11_0_kiq_setting(&adev->gfx.kiq.ring);
1239
1240         r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE);
1241         if (r)
1242                 goto failure;
1243
1244         return r;
1245
1246 failure:
1247         mes_v11_0_hw_fini(adev);
1248         return r;
1249 }
1250
1251 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
1252 {
1253         if (adev->mes.ring.sched.ready)
1254                 mes_v11_0_kiq_dequeue_sched(adev);
1255
1256         mes_v11_0_enable(adev, false);
1257         return 0;
1258 }
1259
1260 static int mes_v11_0_hw_init(void *handle)
1261 {
1262         int r;
1263         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1264
1265         if (!adev->enable_mes_kiq) {
1266                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1267                         r = mes_v11_0_load_microcode(adev,
1268                                              AMDGPU_MES_SCHED_PIPE, true);
1269                         if (r) {
1270                                 DRM_ERROR("failed to MES fw, r=%d\n", r);
1271                                 return r;
1272                         }
1273                 }
1274
1275                 mes_v11_0_enable(adev, true);
1276         }
1277
1278         r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE);
1279         if (r)
1280                 goto failure;
1281
1282         r = mes_v11_0_set_hw_resources(&adev->mes);
1283         if (r)
1284                 goto failure;
1285
1286         mes_v11_0_init_aggregated_doorbell(&adev->mes);
1287
1288         r = mes_v11_0_query_sched_status(&adev->mes);
1289         if (r) {
1290                 DRM_ERROR("MES is busy\n");
1291                 goto failure;
1292         }
1293
1294         /*
1295          * Disable KIQ ring usage from the driver once MES is enabled.
1296          * MES uses KIQ ring exclusively so driver cannot access KIQ ring
1297          * with MES enabled.
1298          */
1299         adev->gfx.kiq.ring.sched.ready = false;
1300         adev->mes.ring.sched.ready = true;
1301
1302         return 0;
1303
1304 failure:
1305         mes_v11_0_hw_fini(adev);
1306         return r;
1307 }
1308
1309 static int mes_v11_0_hw_fini(void *handle)
1310 {
1311         return 0;
1312 }
1313
1314 static int mes_v11_0_suspend(void *handle)
1315 {
1316         int r;
1317         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1318
1319         r = amdgpu_mes_suspend(adev);
1320         if (r)
1321                 return r;
1322
1323         return mes_v11_0_hw_fini(adev);
1324 }
1325
1326 static int mes_v11_0_resume(void *handle)
1327 {
1328         int r;
1329         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330
1331         r = mes_v11_0_hw_init(adev);
1332         if (r)
1333                 return r;
1334
1335         return amdgpu_mes_resume(adev);
1336 }
1337
1338 static int mes_v11_0_late_init(void *handle)
1339 {
1340         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1341
1342         if (!amdgpu_in_reset(adev) &&
1343             (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3)))
1344                 amdgpu_mes_self_test(adev);
1345
1346         return 0;
1347 }
1348
1349 static const struct amd_ip_funcs mes_v11_0_ip_funcs = {
1350         .name = "mes_v11_0",
1351         .late_init = mes_v11_0_late_init,
1352         .sw_init = mes_v11_0_sw_init,
1353         .sw_fini = mes_v11_0_sw_fini,
1354         .hw_init = mes_v11_0_hw_init,
1355         .hw_fini = mes_v11_0_hw_fini,
1356         .suspend = mes_v11_0_suspend,
1357         .resume = mes_v11_0_resume,
1358 };
1359
1360 const struct amdgpu_ip_block_version mes_v11_0_ip_block = {
1361         .type = AMD_IP_BLOCK_TYPE_MES,
1362         .major = 11,
1363         .minor = 0,
1364         .rev = 0,
1365         .funcs = &mes_v11_0_ip_funcs,
1366 };