drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/delay.h>
  24 #include <linux/kernel.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_gfx.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_smu.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "imu_v11_0.h"
  34 #include "soc21.h"
  35 #include "nvd.h"
  36
  37 #include "gc/gc_11_0_0_offset.h"
  38 #include "gc/gc_11_0_0_sh_mask.h"
  39 #include "smuio/smuio_13_0_6_offset.h"
  40 #include "smuio/smuio_13_0_6_sh_mask.h"
  41 #include "navi10_enum.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "clearstate_gfx11.h"
  47 #include "v11_structs.h"
  48 #include "gfx_v11_0.h"
  49 #include "nbio_v4_3.h"
  50 #include "mes_v11_0.h"
  51
  52 #define GFX11_NUM_GFX_RINGS             1
  53 #define GFX11_MEC_HPD_SIZE      2048
  54
  55 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  56 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1        0x1388
  57
  58 #define regCGTT_WD_CLK_CTRL             0x5086
  59 #define regCGTT_WD_CLK_CTRL_BASE_IDX    1
  60 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1   0x4e7e
  61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX  1
  62
  63 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
  64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
  65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
  66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");
  67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");
  68 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");
  69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin");
  70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin");
  71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin");
  72 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin");
  73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
  74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
  75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
  76 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
  77 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
  78 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
  79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
  80
  81 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
  82 {
  83         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
  84         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
  85         SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
  86         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
  87         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
  88         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
  89         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
  90         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
  91         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
  92 };
  93
  94 #define DEFAULT_SH_MEM_CONFIG \
  95         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
  96          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
  97          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
  98
  99 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev);
 100 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev);
 101 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev);
 102 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev);
 103 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev);
 104 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev);
 105 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev);
 106 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
 107                                  struct amdgpu_cu_info *cu_info);
 108 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 109 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 110                                    u32 sh_num, u32 instance);
 111 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 112
 113 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 114 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
 115 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 116                                      uint32_t val);
 117 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 118 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 119                                            uint16_t pasid, uint32_t flush_type,
 120                                            bool all_hub, uint8_t dst_sel);
 121 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev);
 122 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);
 123 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
 124                                       bool enable);
 125
 126 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 127 {
 128         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 129         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 130                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 131         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 132         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 133         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 134         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 135         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 136         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 137 }
 138
 139 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 140                                  struct amdgpu_ring *ring)
 141 {
 142         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 143         uint64_t wptr_addr = ring->wptr_gpu_addr;
 144         uint32_t me = 0, eng_sel = 0;
 145
 146         switch (ring->funcs->type) {
 147         case AMDGPU_RING_TYPE_COMPUTE:
 148                 me = 1;
 149                 eng_sel = 0;
 150                 break;
 151         case AMDGPU_RING_TYPE_GFX:
 152                 me = 0;
 153                 eng_sel = 4;
 154                 break;
 155         case AMDGPU_RING_TYPE_MES:
 156                 me = 2;
 157                 eng_sel = 5;
 158                 break;
 159         default:
 160                 WARN_ON(1);
 161         }
 162
 163         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 164         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 165         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 166                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 167                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 168                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 169                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 170                           PACKET3_MAP_QUEUES_ME((me)) |
 171                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 172                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 173                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 174                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 175         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 176         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 177         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 178         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 179         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 180 }
 181
 182 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 183                                    struct amdgpu_ring *ring,
 184                                    enum amdgpu_unmap_queues_action action,
 185                                    u64 gpu_addr, u64 seq)
 186 {
 187         struct amdgpu_device *adev = kiq_ring->adev;
 188         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 189
 190         if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
 191                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
 192                 return;
 193         }
 194
 195         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 196         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 197                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 198                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 199                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 200                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 201         amdgpu_ring_write(kiq_ring,
 202                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 203
 204         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 205                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 206                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 207                 amdgpu_ring_write(kiq_ring, seq);
 208         } else {
 209                 amdgpu_ring_write(kiq_ring, 0);
 210                 amdgpu_ring_write(kiq_ring, 0);
 211                 amdgpu_ring_write(kiq_ring, 0);
 212         }
 213 }
 214
 215 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,
 216                                    struct amdgpu_ring *ring,
 217                                    u64 addr,
 218                                    u64 seq)
 219 {
 220         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 221
 222         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 223         amdgpu_ring_write(kiq_ring,
 224                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 225                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 226                           PACKET3_QUERY_STATUS_COMMAND(2));
 227         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 228                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 229                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 230         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 231         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 232         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 233         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 234 }
 235
 236 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 237                                 uint16_t pasid, uint32_t flush_type,
 238                                 bool all_hub)
 239 {
 240         gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
 241 }
 242
 243 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = {
 244         .kiq_set_resources = gfx11_kiq_set_resources,
 245         .kiq_map_queues = gfx11_kiq_map_queues,
 246         .kiq_unmap_queues = gfx11_kiq_unmap_queues,
 247         .kiq_query_status = gfx11_kiq_query_status,
 248         .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs,
 249         .set_resources_size = 8,
 250         .map_queues_size = 7,
 251         .unmap_queues_size = 6,
 252         .query_status_size = 7,
 253         .invalidate_tlbs_size = 2,
 254 };
 255
 256 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 257 {
 258         adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs;
 259 }
 260
 261 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
 262 {
 263         switch (adev->ip_versions[GC_HWIP][0]) {
 264         case IP_VERSION(11, 0, 1):
 265                 soc15_program_register_sequence(adev,
 266                                                 golden_settings_gc_11_0_1,
 267                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
 268                 break;
 269         default:
 270                 break;
 271         }
 272 }
 273
 274 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 275                                        bool wc, uint32_t reg, uint32_t val)
 276 {
 277         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 278         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 279                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 280         amdgpu_ring_write(ring, reg);
 281         amdgpu_ring_write(ring, 0);
 282         amdgpu_ring_write(ring, val);
 283 }
 284
 285 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 286                                   int mem_space, int opt, uint32_t addr0,
 287                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 288                                   uint32_t inv)
 289 {
 290         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 291         amdgpu_ring_write(ring,
 292                           /* memory (1) or register (0) */
 293                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 294                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 295                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 296                            WAIT_REG_MEM_ENGINE(eng_sel)));
 297
 298         if (mem_space)
 299                 BUG_ON(addr0 & 0x3); /* Dword align */
 300         amdgpu_ring_write(ring, addr0);
 301         amdgpu_ring_write(ring, addr1);
 302         amdgpu_ring_write(ring, ref);
 303         amdgpu_ring_write(ring, mask);
 304         amdgpu_ring_write(ring, inv); /* poll interval */
 305 }
 306
 307 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
 308 {
 309         struct amdgpu_device *adev = ring->adev;
 310         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 311         uint32_t tmp = 0;
 312         unsigned i;
 313         int r;
 314
 315         WREG32(scratch, 0xCAFEDEAD);
 316         r = amdgpu_ring_alloc(ring, 5);
 317         if (r) {
 318                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 319                           ring->idx, r);
 320                 return r;
 321         }
 322
 323         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
 324                 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
 325         } else {
 326                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 327                 amdgpu_ring_write(ring, scratch -
 328                                   PACKET3_SET_UCONFIG_REG_START);
 329                 amdgpu_ring_write(ring, 0xDEADBEEF);
 330         }
 331         amdgpu_ring_commit(ring);
 332
 333         for (i = 0; i < adev->usec_timeout; i++) {
 334                 tmp = RREG32(scratch);
 335                 if (tmp == 0xDEADBEEF)
 336                         break;
 337                 if (amdgpu_emu_mode == 1)
 338                         msleep(1);
 339                 else
 340                         udelay(1);
 341         }
 342
 343         if (i >= adev->usec_timeout)
 344                 r = -ETIMEDOUT;
 345         return r;
 346 }
 347
 348 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 349 {
 350         struct amdgpu_device *adev = ring->adev;
 351         struct amdgpu_ib ib;
 352         struct dma_fence *f = NULL;
 353         unsigned index;
 354         uint64_t gpu_addr;
 355         volatile uint32_t *cpu_ptr;
 356         long r;
 357
 358         /* MES KIQ fw hasn't indirect buffer support for now */
 359         if (adev->enable_mes_kiq &&
 360             ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 361                 return 0;
 362
 363         memset(&ib, 0, sizeof(ib));
 364
 365         if (ring->is_mes_queue) {
 366                 uint32_t padding, offset;
 367
 368                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 369                 padding = amdgpu_mes_ctx_get_offs(ring,
 370                                                   AMDGPU_MES_CTX_PADDING_OFFS);
 371
 372                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 373                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 374
 375                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
 376                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
 377                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
 378         } else {
 379                 r = amdgpu_device_wb_get(adev, &index);
 380                 if (r)
 381                         return r;
 382
 383                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 384                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 385                 cpu_ptr = &adev->wb.wb[index];
 386
 387                 r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
 388                 if (r) {
 389                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 390                         goto err1;
 391                 }
 392         }
 393
 394         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 395         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 396         ib.ptr[2] = lower_32_bits(gpu_addr);
 397         ib.ptr[3] = upper_32_bits(gpu_addr);
 398         ib.ptr[4] = 0xDEADBEEF;
 399         ib.length_dw = 5;
 400
 401         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 402         if (r)
 403                 goto err2;
 404
 405         r = dma_fence_wait_timeout(f, false, timeout);
 406         if (r == 0) {
 407                 r = -ETIMEDOUT;
 408                 goto err2;
 409         } else if (r < 0) {
 410                 goto err2;
 411         }
 412
 413         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
 414                 r = 0;
 415         else
 416                 r = -EINVAL;
 417 err2:
 418         if (!ring->is_mes_queue)
 419                 amdgpu_ib_free(adev, &ib, NULL);
 420         dma_fence_put(f);
 421 err1:
 422         if (!ring->is_mes_queue)
 423                 amdgpu_device_wb_free(adev, index);
 424         return r;
 425 }
 426
 427 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
 428 {
 429         release_firmware(adev->gfx.pfp_fw);
 430         adev->gfx.pfp_fw = NULL;
 431         release_firmware(adev->gfx.me_fw);
 432         adev->gfx.me_fw = NULL;
 433         release_firmware(adev->gfx.rlc_fw);
 434         adev->gfx.rlc_fw = NULL;
 435         release_firmware(adev->gfx.mec_fw);
 436         adev->gfx.mec_fw = NULL;
 437
 438         kfree(adev->gfx.rlc.register_list_format);
 439 }
 440
 441 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
 442 {
 443         char fw_name[40];
 444         char ucode_prefix[30];
 445         int err;
 446         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 447         uint16_t version_major;
 448         uint16_t version_minor;
 449
 450         DRM_DEBUG("\n");
 451
 452         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 453
 454         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix);
 455         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 456         if (err)
 457                 goto out;
 458         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 459         if (err)
 460                 goto out;
 461         /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/
 462         adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
 463                                 (union amdgpu_firmware_header *)
 464                                 adev->gfx.pfp_fw->data, 2, 0);
 465         if (adev->gfx.rs64_enable) {
 466                 dev_info(adev->dev, "CP RS64 enable\n");
 467                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
 468                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
 469                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK);
 470         } else {
 471                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 472         }
 473
 474         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);
 475         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 476         if (err)
 477                 goto out;
 478         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 479         if (err)
 480                 goto out;
 481         if (adev->gfx.rs64_enable) {
 482                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
 483                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
 484                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK);
 485         } else {
 486                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 487         }
 488
 489         if (!amdgpu_sriov_vf(adev)) {
 490                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
 491                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 492                 if (err)
 493                         goto out;
 494                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 495                 if (err)
 496                         goto out;
 497                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 498                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 499                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 500                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 501                 if (err)
 502                         goto out;
 503         }
 504
 505         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);
 506         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 507         if (err)
 508                 goto out;
 509         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 510         if (err)
 511                 goto out;
 512         if (adev->gfx.rs64_enable) {
 513                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
 514                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
 515                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
 516                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK);
 517                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK);
 518         } else {
 519                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 520                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 521         }
 522
 523         /* only one MEC for gfx 11.0.0. */
 524         adev->gfx.mec2_fw = NULL;
 525
 526 out:
 527         if (err) {
 528                 dev_err(adev->dev,
 529                         "gfx11: Failed to init firmware \"%s\"\n",
 530                         fw_name);
 531                 release_firmware(adev->gfx.pfp_fw);
 532                 adev->gfx.pfp_fw = NULL;
 533                 release_firmware(adev->gfx.me_fw);
 534                 adev->gfx.me_fw = NULL;
 535                 release_firmware(adev->gfx.rlc_fw);
 536                 adev->gfx.rlc_fw = NULL;
 537                 release_firmware(adev->gfx.mec_fw);
 538                 adev->gfx.mec_fw = NULL;
 539         }
 540
 541         return err;
 542 }
 543
 544 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev)
 545 {
 546         const struct psp_firmware_header_v1_0 *toc_hdr;
 547         int err = 0;
 548         char fw_name[40];
 549         char ucode_prefix[30];
 550
 551         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 552
 553         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix);
 554         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
 555         if (err)
 556                 goto out;
 557
 558         err = amdgpu_ucode_validate(adev->psp.toc_fw);
 559         if (err)
 560                 goto out;
 561
 562         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
 563         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
 564         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
 565         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
 566         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
 567                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
 568         return 0;
 569 out:
 570         dev_err(adev->dev, "Failed to load TOC microcode\n");
 571         release_firmware(adev->psp.toc_fw);
 572         adev->psp.toc_fw = NULL;
 573         return err;
 574 }
 575
 576 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)
 577 {
 578         u32 count = 0;
 579         const struct cs_section_def *sect = NULL;
 580         const struct cs_extent_def *ext = NULL;
 581
 582         /* begin clear state */
 583         count += 2;
 584         /* context control state */
 585         count += 3;
 586
 587         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
 588                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 589                         if (sect->id == SECT_CONTEXT)
 590                                 count += 2 + ext->reg_count;
 591                         else
 592                                 return 0;
 593                 }
 594         }
 595
 596         /* set PA_SC_TILE_STEERING_OVERRIDE */
 597         count += 3;
 598         /* end clear state */
 599         count += 2;
 600         /* clear state */
 601         count += 2;
 602
 603         return count;
 604 }
 605
 606 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,
 607                                     volatile u32 *buffer)
 608 {
 609         u32 count = 0, i;
 610         const struct cs_section_def *sect = NULL;
 611         const struct cs_extent_def *ext = NULL;
 612         int ctx_reg_offset;
 613
 614         if (adev->gfx.rlc.cs_data == NULL)
 615                 return;
 616         if (buffer == NULL)
 617                 return;
 618
 619         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 620         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 621
 622         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 623         buffer[count++] = cpu_to_le32(0x80000000);
 624         buffer[count++] = cpu_to_le32(0x80000000);
 625
 626         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 627                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 628                         if (sect->id == SECT_CONTEXT) {
 629                                 buffer[count++] =
 630                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 631                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 632                                                 PACKET3_SET_CONTEXT_REG_START);
 633                                 for (i = 0; i < ext->reg_count; i++)
 634                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 635                         } else {
 636                                 return;
 637                         }
 638                 }
 639         }
 640
 641         ctx_reg_offset =
 642                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 643         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 644         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 645         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 646
 647         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 648         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 649
 650         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 651         buffer[count++] = cpu_to_le32(0);
 652 }
 653
 654 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev)
 655 {
 656         /* clear state block */
 657         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 658                         &adev->gfx.rlc.clear_state_gpu_addr,
 659                         (void **)&adev->gfx.rlc.cs_ptr);
 660
 661         /* jump table block */
 662         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 663                         &adev->gfx.rlc.cp_table_gpu_addr,
 664                         (void **)&adev->gfx.rlc.cp_table_ptr);
 665 }
 666
 667 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
 668 {
 669         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 670
 671         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
 672         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 673         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
 674         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
 675         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
 676         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
 677         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
 678         reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
 679         adev->gfx.rlc.rlcg_reg_access_supported = true;
 680 }
 681
 682 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
 683 {
 684         const struct cs_section_def *cs_data;
 685         int r;
 686
 687         adev->gfx.rlc.cs_data = gfx11_cs_data;
 688
 689         cs_data = adev->gfx.rlc.cs_data;
 690
 691         if (cs_data) {
 692                 /* init clear state block */
 693                 r = amdgpu_gfx_rlc_init_csb(adev);
 694                 if (r)
 695                         return r;
 696         }
 697
 698         /* init spm vmid with 0xf */
 699         if (adev->gfx.rlc.funcs->update_spm_vmid)
 700                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
 701
 702         return 0;
 703 }
 704
 705 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev)
 706 {
 707         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 708         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 709         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
 710 }
 711
 712 static int gfx_v11_0_me_init(struct amdgpu_device *adev)
 713 {
 714         int r;
 715
 716         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 717
 718         amdgpu_gfx_graphics_queue_acquire(adev);
 719
 720         r = gfx_v11_0_init_microcode(adev);
 721         if (r)
 722                 DRM_ERROR("Failed to load gfx firmware!\n");
 723
 724         return r;
 725 }
 726
 727 static int gfx_v11_0_mec_init(struct amdgpu_device *adev)
 728 {
 729         int r;
 730         u32 *hpd;
 731         size_t mec_hpd_size;
 732
 733         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 734
 735         /* take ownership of the relevant compute queues */
 736         amdgpu_gfx_compute_queue_acquire(adev);
 737         mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE;
 738
 739         if (mec_hpd_size) {
 740                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 741                                               AMDGPU_GEM_DOMAIN_GTT,
 742                                               &adev->gfx.mec.hpd_eop_obj,
 743                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 744                                               (void **)&hpd);
 745                 if (r) {
 746                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 747                         gfx_v11_0_mec_fini(adev);
 748                         return r;
 749                 }
 750
 751                 memset(hpd, 0, mec_hpd_size);
 752
 753                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 754                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 755         }
 756
 757         return 0;
 758 }
 759
 760 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
 761 {
 762         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 763                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 764                 (address << SQ_IND_INDEX__INDEX__SHIFT));
 765         return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 766 }
 767
 768 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
 769                            uint32_t thread, uint32_t regno,
 770                            uint32_t num, uint32_t *out)
 771 {
 772         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 773                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 774                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 775                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
 776                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 777         while (num--)
 778                 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 779 }
 780
 781 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
 782 {
 783         /* in gfx11 the SIMD_ID is specified as part of the INSTANCE
 784          * field when performing a select_se_sh so it should be
 785          * zero here */
 786         WARN_ON(simd != 0);
 787
 788         /* type 2 wave data */
 789         dst[(*no_fields)++] = 2;
 790         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
 791         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
 792         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
 793         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
 794         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
 795         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
 796         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
 797         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
 798         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
 799         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
 800         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
 801         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
 802         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
 803         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
 804         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
 805 }
 806
 807 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
 808                                      uint32_t wave, uint32_t start,
 809                                      uint32_t size, uint32_t *dst)
 810 {
 811         WARN_ON(simd != 0);
 812
 813         wave_read_regs(
 814                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
 815                 dst);
 816 }
 817
 818 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
 819                                       uint32_t wave, uint32_t thread,
 820                                       uint32_t start, uint32_t size,
 821                                       uint32_t *dst)
 822 {
 823         wave_read_regs(
 824                 adev, wave, thread,
 825                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 826 }
 827
 828 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
 829                                                                           u32 me, u32 pipe, u32 q, u32 vm)
 830 {
 831         soc21_grbm_select(adev, me, pipe, q, vm);
 832 }
 833
 834 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
 835         .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
 836         .select_se_sh = &gfx_v11_0_select_se_sh,
 837         .read_wave_data = &gfx_v11_0_read_wave_data,
 838         .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
 839         .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
 840         .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
 841         .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
 842 };
 843
 844 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
 845 {
 846         adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
 847
 848         switch (adev->ip_versions[GC_HWIP][0]) {
 849         case IP_VERSION(11, 0, 0):
 850         case IP_VERSION(11, 0, 2):
 851         case IP_VERSION(11, 0, 3):
 852                 adev->gfx.config.max_hw_contexts = 8;
 853                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 854                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 855                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 856                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 857                 break;
 858         case IP_VERSION(11, 0, 1):
 859                 adev->gfx.config.max_hw_contexts = 8;
 860                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 861                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 862                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
 863                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;
 864                 break;
 865         default:
 866                 BUG();
 867                 break;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 874                                    int me, int pipe, int queue)
 875 {
 876         int r;
 877         struct amdgpu_ring *ring;
 878         unsigned int irq_type;
 879
 880         ring = &adev->gfx.gfx_ring[ring_id];
 881
 882         ring->me = me;
 883         ring->pipe = pipe;
 884         ring->queue = queue;
 885
 886         ring->ring_obj = NULL;
 887         ring->use_doorbell = true;
 888
 889         if (!ring_id)
 890                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
 891         else
 892                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
 893         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 894
 895         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
 896         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 897                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 898         if (r)
 899                 return r;
 900         return 0;
 901 }
 902
 903 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 904                                        int mec, int pipe, int queue)
 905 {
 906         int r;
 907         unsigned irq_type;
 908         struct amdgpu_ring *ring;
 909         unsigned int hw_prio;
 910
 911         ring = &adev->gfx.compute_ring[ring_id];
 912
 913         /* mec0 is me1 */
 914         ring->me = mec + 1;
 915         ring->pipe = pipe;
 916         ring->queue = queue;
 917
 918         ring->ring_obj = NULL;
 919         ring->use_doorbell = true;
 920         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
 921         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
 922                                 + (ring_id * GFX11_MEC_HPD_SIZE);
 923         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 924
 925         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
 926                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
 927                 + ring->pipe;
 928         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
 929                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
 930         /* type-2 packets are deprecated on MEC, use type-3 instead */
 931         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 932                              hw_prio, NULL);
 933         if (r)
 934                 return r;
 935
 936         return 0;
 937 }
 938
 939 static struct {
 940         SOC21_FIRMWARE_ID       id;
 941         unsigned int            offset;
 942         unsigned int            size;
 943 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX];
 944
 945 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
 946 {
 947         RLC_TABLE_OF_CONTENT *ucode = rlc_toc;
 948
 949         while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) &&
 950                         (ucode->id < SOC21_FIRMWARE_ID_MAX)) {
 951                 rlc_autoload_info[ucode->id].id = ucode->id;
 952                 rlc_autoload_info[ucode->id].offset = ucode->offset * 4;
 953                 rlc_autoload_info[ucode->id].size = ucode->size * 4;
 954
 955                 ucode++;
 956         }
 957 }
 958
 959 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev)
 960 {
 961         uint32_t total_size = 0;
 962         SOC21_FIRMWARE_ID id;
 963
 964         gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
 965
 966         for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++)
 967                 total_size += rlc_autoload_info[id].size;
 968
 969         /* In case the offset in rlc toc ucode is aligned */
 970         if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset)
 971                 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset +
 972                         rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size;
 973
 974         return total_size;
 975 }
 976
 977 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
 978 {
 979         int r;
 980         uint32_t total_size;
 981
 982         total_size = gfx_v11_0_calc_toc_total_size(adev);
 983
 984         r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
 985                         AMDGPU_GEM_DOMAIN_VRAM,
 986                         &adev->gfx.rlc.rlc_autoload_bo,
 987                         &adev->gfx.rlc.rlc_autoload_gpu_addr,
 988                         (void **)&adev->gfx.rlc.rlc_autoload_ptr);
 989
 990         if (r) {
 991                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
 992                 return r;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
 999                                               SOC21_FIRMWARE_ID id,
1000                                               const void *fw_data,
1001                                               uint32_t fw_size,
1002                                               uint32_t *fw_autoload_mask)
1003 {
1004         uint32_t toc_offset;
1005         uint32_t toc_fw_size;
1006         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1007
1008         if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX)
1009                 return;
1010
1011         toc_offset = rlc_autoload_info[id].offset;
1012         toc_fw_size = rlc_autoload_info[id].size;
1013
1014         if (fw_size == 0)
1015                 fw_size = toc_fw_size;
1016
1017         if (fw_size > toc_fw_size)
1018                 fw_size = toc_fw_size;
1019
1020         memcpy(ptr + toc_offset, fw_data, fw_size);
1021
1022         if (fw_size < toc_fw_size)
1023                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1024
1025         if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME))
1026                 *(uint64_t *)fw_autoload_mask |= 1ULL << id;
1027 }
1028
1029 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev,
1030                                                         uint32_t *fw_autoload_mask)
1031 {
1032         void *data;
1033         uint32_t size;
1034         uint64_t *toc_ptr;
1035
1036         *(uint64_t *)fw_autoload_mask |= 0x1;
1037
1038         DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);
1039
1040         data = adev->psp.toc.start_addr;
1041         size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size;
1042
1043         toc_ptr = (uint64_t *)data + size / 8 - 1;
1044         *toc_ptr = *(uint64_t *)fw_autoload_mask;
1045
1046         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC,
1047                                         data, size, fw_autoload_mask);
1048 }
1049
1050 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev,
1051                                                         uint32_t *fw_autoload_mask)
1052 {
1053         const __le32 *fw_data;
1054         uint32_t fw_size;
1055         const struct gfx_firmware_header_v1_0 *cp_hdr;
1056         const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1057         const struct rlc_firmware_header_v2_0 *rlc_hdr;
1058         const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1059         uint16_t version_major, version_minor;
1060
1061         if (adev->gfx.rs64_enable) {
1062                 /* pfp ucode */
1063                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1064                         adev->gfx.pfp_fw->data;
1065                 /* instruction */
1066                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1067                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1068                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1069                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP,
1070                                                 fw_data, fw_size, fw_autoload_mask);
1071                 /* data */
1072                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1073                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1074                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1075                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK,
1076                                                 fw_data, fw_size, fw_autoload_mask);
1077                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK,
1078                                                 fw_data, fw_size, fw_autoload_mask);
1079                 /* me ucode */
1080                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1081                         adev->gfx.me_fw->data;
1082                 /* instruction */
1083                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1084                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1085                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1086                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME,
1087                                                 fw_data, fw_size, fw_autoload_mask);
1088                 /* data */
1089                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1090                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1091                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1092                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK,
1093                                                 fw_data, fw_size, fw_autoload_mask);
1094                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK,
1095                                                 fw_data, fw_size, fw_autoload_mask);
1096                 /* mec ucode */
1097                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1098                         adev->gfx.mec_fw->data;
1099                 /* instruction */
1100                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1101                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1102                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1103                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC,
1104                                                 fw_data, fw_size, fw_autoload_mask);
1105                 /* data */
1106                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1107                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1108                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1109                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK,
1110                                                 fw_data, fw_size, fw_autoload_mask);
1111                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK,
1112                                                 fw_data, fw_size, fw_autoload_mask);
1113                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK,
1114                                                 fw_data, fw_size, fw_autoload_mask);
1115                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK,
1116                                                 fw_data, fw_size, fw_autoload_mask);
1117         } else {
1118                 /* pfp ucode */
1119                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1120                         adev->gfx.pfp_fw->data;
1121                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1122                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1123                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1124                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP,
1125                                                 fw_data, fw_size, fw_autoload_mask);
1126
1127                 /* me ucode */
1128                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1129                         adev->gfx.me_fw->data;
1130                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1131                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1132                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1133                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME,
1134                                                 fw_data, fw_size, fw_autoload_mask);
1135
1136                 /* mec ucode */
1137                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1138                         adev->gfx.mec_fw->data;
1139                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1140                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1141                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1142                         cp_hdr->jt_size * 4;
1143                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC,
1144                                                 fw_data, fw_size, fw_autoload_mask);
1145         }
1146
1147         /* rlc ucode */
1148         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1149                 adev->gfx.rlc_fw->data;
1150         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1151                         le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1152         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1153         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE,
1154                                         fw_data, fw_size, fw_autoload_mask);
1155
1156         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1157         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1158         if (version_major == 2) {
1159                 if (version_minor >= 2) {
1160                         rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1161
1162                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1163                                         le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1164                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1165                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE,
1166                                         fw_data, fw_size, fw_autoload_mask);
1167
1168                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1169                                         le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1170                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1171                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT,
1172                                         fw_data, fw_size, fw_autoload_mask);
1173                 }
1174         }
1175 }
1176
1177 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev,
1178                                                         uint32_t *fw_autoload_mask)
1179 {
1180         const __le32 *fw_data;
1181         uint32_t fw_size;
1182         const struct sdma_firmware_header_v2_0 *sdma_hdr;
1183
1184         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)
1185                 adev->sdma.instance[0].fw->data;
1186         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1187                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
1188         fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
1189
1190         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1191                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask);
1192
1193         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1194                         le32_to_cpu(sdma_hdr->ctl_ucode_offset));
1195         fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
1196
1197         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1198                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask);
1199 }
1200
1201 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev,
1202                                                         uint32_t *fw_autoload_mask)
1203 {
1204         const __le32 *fw_data;
1205         unsigned fw_size;
1206         const struct mes_firmware_header_v1_0 *mes_hdr;
1207         int pipe, ucode_id, data_id;
1208
1209         for (pipe = 0; pipe < 2; pipe++) {
1210                 if (pipe==0) {
1211                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0;
1212                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK;
1213                 } else {
1214                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1;
1215                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK;
1216                 }
1217
1218                 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1219                         adev->mes.fw[pipe]->data;
1220
1221                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1222                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1223                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1224
1225                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1226                                 ucode_id, fw_data, fw_size, fw_autoload_mask);
1227
1228                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1229                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1230                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1231
1232                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1233                                 data_id, fw_data, fw_size, fw_autoload_mask);
1234         }
1235 }
1236
1237 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1238 {
1239         uint32_t rlc_g_offset, rlc_g_size;
1240         uint64_t gpu_addr;
1241         uint32_t autoload_fw_id[2];
1242
1243         memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);
1244
1245         /* RLC autoload sequence 2: copy ucode */
1246         gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id);
1247         gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id);
1248         gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id);
1249         gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id);
1250
1251         rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset;
1252         rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size;
1253         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
1254
1255         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1256         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1257
1258         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1259
1260         /* RLC autoload sequence 3: load IMU fw */
1261         if (adev->gfx.imu.funcs->load_microcode)
1262                 adev->gfx.imu.funcs->load_microcode(adev);
1263         /* RLC autoload sequence 4 init IMU fw */
1264         if (adev->gfx.imu.funcs->setup_imu)
1265                 adev->gfx.imu.funcs->setup_imu(adev);
1266         if (adev->gfx.imu.funcs->start_imu)
1267                 adev->gfx.imu.funcs->start_imu(adev);
1268
1269         /* RLC autoload sequence 5 disable gpa mode */
1270         gfx_v11_0_disable_gpa_mode(adev);
1271
1272         return 0;
1273 }
1274
1275 static int gfx_v11_0_sw_init(void *handle)
1276 {
1277         int i, j, k, r, ring_id = 0;
1278         struct amdgpu_kiq *kiq;
1279         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1280
1281         adev->gfxhub.funcs->init(adev);
1282
1283         switch (adev->ip_versions[GC_HWIP][0]) {
1284         case IP_VERSION(11, 0, 0):
1285         case IP_VERSION(11, 0, 1):
1286         case IP_VERSION(11, 0, 2):
1287         case IP_VERSION(11, 0, 3):
1288                 adev->gfx.me.num_me = 1;
1289                 adev->gfx.me.num_pipe_per_me = 1;
1290                 adev->gfx.me.num_queue_per_pipe = 1;
1291                 adev->gfx.mec.num_mec = 2;
1292                 adev->gfx.mec.num_pipe_per_mec = 4;
1293                 adev->gfx.mec.num_queue_per_pipe = 4;
1294                 break;
1295         default:
1296                 adev->gfx.me.num_me = 1;
1297                 adev->gfx.me.num_pipe_per_me = 1;
1298                 adev->gfx.me.num_queue_per_pipe = 1;
1299                 adev->gfx.mec.num_mec = 1;
1300                 adev->gfx.mec.num_pipe_per_mec = 4;
1301                 adev->gfx.mec.num_queue_per_pipe = 8;
1302                 break;
1303         }
1304
1305         /* EOP Event */
1306         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1307                               GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1308                               &adev->gfx.eop_irq);
1309         if (r)
1310                 return r;
1311
1312         /* Privileged reg */
1313         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1314                               GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1315                               &adev->gfx.priv_reg_irq);
1316         if (r)
1317                 return r;
1318
1319         /* Privileged inst */
1320         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1321                               GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1322                               &adev->gfx.priv_inst_irq);
1323         if (r)
1324                 return r;
1325
1326         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1327
1328         if (adev->gfx.imu.funcs) {
1329                 if (adev->gfx.imu.funcs->init_microcode) {
1330                         r = adev->gfx.imu.funcs->init_microcode(adev);
1331                         if (r)
1332                                 DRM_ERROR("Failed to load imu firmware!\n");
1333                 }
1334         }
1335
1336         r = gfx_v11_0_me_init(adev);
1337         if (r)
1338                 return r;
1339
1340         r = gfx_v11_0_rlc_init(adev);
1341         if (r) {
1342                 DRM_ERROR("Failed to init rlc BOs!\n");
1343                 return r;
1344         }
1345
1346         r = gfx_v11_0_mec_init(adev);
1347         if (r) {
1348                 DRM_ERROR("Failed to init MEC BOs!\n");
1349                 return r;
1350         }
1351
1352         /* set up the gfx ring */
1353         for (i = 0; i < adev->gfx.me.num_me; i++) {
1354                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1355                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1356                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1357                                         continue;
1358
1359                                 r = gfx_v11_0_gfx_ring_init(adev, ring_id,
1360                                                             i, k, j);
1361                                 if (r)
1362                                         return r;
1363                                 ring_id++;
1364                         }
1365                 }
1366         }
1367
1368         ring_id = 0;
1369         /* set up the compute queues - allocate horizontally across pipes */
1370         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1371                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1372                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1373                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1374                                                                      j))
1375                                         continue;
1376
1377                                 r = gfx_v11_0_compute_ring_init(adev, ring_id,
1378                                                                 i, k, j);
1379                                 if (r)
1380                                         return r;
1381
1382                                 ring_id++;
1383                         }
1384                 }
1385         }
1386
1387         if (!adev->enable_mes_kiq) {
1388                 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE);
1389                 if (r) {
1390                         DRM_ERROR("Failed to init KIQ BOs!\n");
1391                         return r;
1392                 }
1393
1394                 kiq = &adev->gfx.kiq;
1395                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1396                 if (r)
1397                         return r;
1398         }
1399
1400         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd));
1401         if (r)
1402                 return r;
1403
1404         /* allocate visible FB for rlc auto-loading fw */
1405         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1406                 r = gfx_v11_0_init_toc_microcode(adev);
1407                 if (r)
1408                         dev_err(adev->dev, "Failed to load toc firmware!\n");
1409                 r = gfx_v11_0_rlc_autoload_buffer_init(adev);
1410                 if (r)
1411                         return r;
1412         }
1413
1414         r = gfx_v11_0_gpu_early_init(adev);
1415         if (r)
1416                 return r;
1417
1418         return 0;
1419 }
1420
1421 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev)
1422 {
1423         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1424                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1425                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1426
1427         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1428                               &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1429                               (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1430 }
1431
1432 static void gfx_v11_0_me_fini(struct amdgpu_device *adev)
1433 {
1434         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1435                               &adev->gfx.me.me_fw_gpu_addr,
1436                               (void **)&adev->gfx.me.me_fw_ptr);
1437
1438         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1439                                &adev->gfx.me.me_fw_data_gpu_addr,
1440                                (void **)&adev->gfx.me.me_fw_data_ptr);
1441 }
1442
1443 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1444 {
1445         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1446                         &adev->gfx.rlc.rlc_autoload_gpu_addr,
1447                         (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1448 }
1449
1450 static int gfx_v11_0_sw_fini(void *handle)
1451 {
1452         int i;
1453         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1454
1455         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1456                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1457         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1458                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1459
1460         amdgpu_gfx_mqd_sw_fini(adev);
1461
1462         if (!adev->enable_mes_kiq) {
1463                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1464                 amdgpu_gfx_kiq_fini(adev);
1465         }
1466
1467         gfx_v11_0_pfp_fini(adev);
1468         gfx_v11_0_me_fini(adev);
1469         gfx_v11_0_rlc_fini(adev);
1470         gfx_v11_0_mec_fini(adev);
1471
1472         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1473                 gfx_v11_0_rlc_autoload_buffer_fini(adev);
1474
1475         gfx_v11_0_free_microcode(adev);
1476
1477         return 0;
1478 }
1479
1480 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1481                                    u32 sh_num, u32 instance)
1482 {
1483         u32 data;
1484
1485         if (instance == 0xffffffff)
1486                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1487                                      INSTANCE_BROADCAST_WRITES, 1);
1488         else
1489                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1490                                      instance);
1491
1492         if (se_num == 0xffffffff)
1493                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1494                                      1);
1495         else
1496                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1497
1498         if (sh_num == 0xffffffff)
1499                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1500                                      1);
1501         else
1502                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1503
1504         WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1505 }
1506
1507 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1508 {
1509         u32 data, mask;
1510
1511         data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1512         data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1513
1514         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1515         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1516
1517         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1518                                          adev->gfx.config.max_sh_per_se);
1519
1520         return (~data) & mask;
1521 }
1522
1523 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
1524 {
1525         int i, j;
1526         u32 data;
1527         u32 active_rbs = 0;
1528         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1529                                         adev->gfx.config.max_sh_per_se;
1530
1531         mutex_lock(&adev->grbm_idx_mutex);
1532         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1533                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1534                         gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff);
1535                         data = gfx_v11_0_get_rb_active_bitmap(adev);
1536                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1537                                                rb_bitmap_width_per_sh);
1538                 }
1539         }
1540         gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1541         mutex_unlock(&adev->grbm_idx_mutex);
1542
1543         adev->gfx.config.backend_enable_mask = active_rbs;
1544         adev->gfx.config.num_rbs = hweight32(active_rbs);
1545 }
1546
1547 #define DEFAULT_SH_MEM_BASES    (0x6000)
1548 #define LDS_APP_BASE           0x1
1549 #define SCRATCH_APP_BASE       0x2
1550
1551 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
1552 {
1553         int i;
1554         uint32_t sh_mem_bases;
1555         uint32_t data;
1556
1557         /*
1558          * Configure apertures:
1559          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1560          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1561          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1562          */
1563         sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1564                         SCRATCH_APP_BASE;
1565
1566         mutex_lock(&adev->srbm_mutex);
1567         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1568                 soc21_grbm_select(adev, 0, 0, 0, i);
1569                 /* CP and shaders */
1570                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1571                 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1572
1573                 /* Enable trap for each kfd vmid. */
1574                 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1575                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1576         }
1577         soc21_grbm_select(adev, 0, 0, 0, 0);
1578         mutex_unlock(&adev->srbm_mutex);
1579
1580         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1581            acccess. These should be enabled by FW for target VMIDs. */
1582         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1583                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
1584                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
1585                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);
1586                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);
1587         }
1588 }
1589
1590 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev)
1591 {
1592         int vmid;
1593
1594         /*
1595          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1596          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1597          * the driver can enable them for graphics. VMID0 should maintain
1598          * access so that HWS firmware can save/restore entries.
1599          */
1600         for (vmid = 1; vmid < 16; vmid++) {
1601                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);
1602                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);
1603                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);
1604                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);
1605         }
1606 }
1607
1608 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev)
1609 {
1610         /* TODO: harvest feature to be added later. */
1611 }
1612
1613 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev)
1614 {
1615         /* TCCs are global (not instanced). */
1616         uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |
1617                                RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);
1618
1619         adev->gfx.config.tcc_disabled_mask =
1620                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1621                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1622 }
1623
1624 static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
1625 {
1626         u32 tmp;
1627         int i;
1628
1629         WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1630
1631         gfx_v11_0_setup_rb(adev);
1632         gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info);
1633         gfx_v11_0_get_tcc_info(adev);
1634         adev->gfx.config.pa_sc_tile_steering_override = 0;
1635
1636         /* XXX SH_MEM regs */
1637         /* where to put LDS, scratch, GPUVM in FSA64 space */
1638         mutex_lock(&adev->srbm_mutex);
1639         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1640                 soc21_grbm_select(adev, 0, 0, 0, i);
1641                 /* CP and shaders */
1642                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1643                 if (i != 0) {
1644                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1645                                 (adev->gmc.private_aperture_start >> 48));
1646                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1647                                 (adev->gmc.shared_aperture_start >> 48));
1648                         WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1649                 }
1650         }
1651         soc21_grbm_select(adev, 0, 0, 0, 0);
1652
1653         mutex_unlock(&adev->srbm_mutex);
1654
1655         gfx_v11_0_init_compute_vmid(adev);
1656         gfx_v11_0_init_gds_vmid(adev);
1657 }
1658
1659 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1660                                                bool enable)
1661 {
1662         u32 tmp;
1663
1664         if (amdgpu_sriov_vf(adev))
1665                 return;
1666
1667         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
1668
1669         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1670                             enable ? 1 : 0);
1671         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1672                             enable ? 1 : 0);
1673         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1674                             enable ? 1 : 0);
1675         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1676                             enable ? 1 : 0);
1677
1678         WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
1679 }
1680
1681 static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
1682 {
1683         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1684
1685         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1686                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1687         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1688                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1689         WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1690
1691         return 0;
1692 }
1693
1694 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev)
1695 {
1696         u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1697
1698         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1699         WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1700 }
1701
1702 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev)
1703 {
1704         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1705         udelay(50);
1706         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1707         udelay(50);
1708 }
1709
1710 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1711                                              bool enable)
1712 {
1713         uint32_t rlc_pg_cntl;
1714
1715         rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1716
1717         if (!enable) {
1718                 /* RLC_PG_CNTL[23] = 0 (default)
1719                  * RLC will wait for handshake acks with SMU
1720                  * GFXOFF will be enabled
1721                  * RLC_PG_CNTL[23] = 1
1722                  * RLC will not issue any message to SMU
1723                  * hence no handshake between SMU & RLC
1724                  * GFXOFF will be disabled
1725                  */
1726                 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1727         } else
1728                 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1729         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1730 }
1731
1732 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev)
1733 {
1734         /* TODO: enable rlc & smu handshake until smu
1735          * and gfxoff feature works as expected */
1736         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1737                 gfx_v11_0_rlc_smu_handshake_cntl(adev, false);
1738
1739         WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1740         udelay(50);
1741 }
1742
1743 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev)
1744 {
1745         uint32_t tmp;
1746
1747         /* enable Save Restore Machine */
1748         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1749         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1750         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1751         WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1752 }
1753
1754 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev)
1755 {
1756         const struct rlc_firmware_header_v2_0 *hdr;
1757         const __le32 *fw_data;
1758         unsigned i, fw_size;
1759
1760         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1761         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1762                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1763         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1764
1765         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1766                      RLCG_UCODE_LOADING_START_ADDRESS);
1767
1768         for (i = 0; i < fw_size; i++)
1769                 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1770                              le32_to_cpup(fw_data++));
1771
1772         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1773 }
1774
1775 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1776 {
1777         const struct rlc_firmware_header_v2_2 *hdr;
1778         const __le32 *fw_data;
1779         unsigned i, fw_size;
1780         u32 tmp;
1781
1782         hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1783
1784         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1785                         le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
1786         fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
1787
1788         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
1789
1790         for (i = 0; i < fw_size; i++) {
1791                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1792                         msleep(1);
1793                 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
1794                                 le32_to_cpup(fw_data++));
1795         }
1796
1797         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1798
1799         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1800                         le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
1801         fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
1802
1803         WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
1804         for (i = 0; i < fw_size; i++) {
1805                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1806                         msleep(1);
1807                 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
1808                                 le32_to_cpup(fw_data++));
1809         }
1810
1811         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1812
1813         tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
1814         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
1815         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
1816         WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
1817 }
1818
1819 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev)
1820 {
1821         const struct rlc_firmware_header_v2_3 *hdr;
1822         const __le32 *fw_data;
1823         unsigned i, fw_size;
1824         u32 tmp;
1825
1826         hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
1827
1828         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1829                         le32_to_cpu(hdr->rlcp_ucode_offset_bytes));
1830         fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4;
1831
1832         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);
1833
1834         for (i = 0; i < fw_size; i++) {
1835                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1836                         msleep(1);
1837                 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,
1838                                 le32_to_cpup(fw_data++));
1839         }
1840
1841         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);
1842
1843         tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1844         tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1845         WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);
1846
1847         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1848                         le32_to_cpu(hdr->rlcv_ucode_offset_bytes));
1849         fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4;
1850
1851         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);
1852
1853         for (i = 0; i < fw_size; i++) {
1854                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1855                         msleep(1);
1856                 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,
1857                                 le32_to_cpup(fw_data++));
1858         }
1859
1860         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);
1861
1862         tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);
1863         tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);
1864         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);
1865 }
1866
1867 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
1868 {
1869         const struct rlc_firmware_header_v2_0 *hdr;
1870         uint16_t version_major;
1871         uint16_t version_minor;
1872
1873         if (!adev->gfx.rlc_fw)
1874                 return -EINVAL;
1875
1876         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1877         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1878
1879         version_major = le16_to_cpu(hdr->header.header_version_major);
1880         version_minor = le16_to_cpu(hdr->header.header_version_minor);
1881
1882         if (version_major == 2) {
1883                 gfx_v11_0_load_rlcg_microcode(adev);
1884                 if (amdgpu_dpm == 1) {
1885                         if (version_minor >= 2)
1886                                 gfx_v11_0_load_rlc_iram_dram_microcode(adev);
1887                         if (version_minor == 3)
1888                                 gfx_v11_0_load_rlcp_rlcv_microcode(adev);
1889                 }
1890
1891                 return 0;
1892         }
1893
1894         return -EINVAL;
1895 }
1896
1897 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
1898 {
1899         int r;
1900
1901         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1902                 gfx_v11_0_init_csb(adev);
1903
1904                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1905                         gfx_v11_0_rlc_enable_srm(adev);
1906         } else {
1907                 if (amdgpu_sriov_vf(adev)) {
1908                         gfx_v11_0_init_csb(adev);
1909                         return 0;
1910                 }
1911
1912                 adev->gfx.rlc.funcs->stop(adev);
1913
1914                 /* disable CG */
1915                 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
1916
1917                 /* disable PG */
1918                 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
1919
1920                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1921                         /* legacy rlc firmware loading */
1922                         r = gfx_v11_0_rlc_load_microcode(adev);
1923                         if (r)
1924                                 return r;
1925                 }
1926
1927                 gfx_v11_0_init_csb(adev);
1928
1929                 adev->gfx.rlc.funcs->start(adev);
1930         }
1931         return 0;
1932 }
1933
1934 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
1935 {
1936         uint32_t usec_timeout = 50000;  /* wait for 50ms */
1937         uint32_t tmp;
1938         int i;
1939
1940         /* Trigger an invalidation of the L1 instruction caches */
1941         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
1942         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1943         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
1944
1945         /* Wait for invalidation complete */
1946         for (i = 0; i < usec_timeout; i++) {
1947                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
1948                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
1949                                         INVALIDATE_CACHE_COMPLETE))
1950                         break;
1951                 udelay(1);
1952         }
1953
1954         if (i >= usec_timeout) {
1955                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
1956                 return -EINVAL;
1957         }
1958
1959         if (amdgpu_emu_mode == 1)
1960                 adev->hdp.funcs->flush_hdp(adev, NULL);
1961
1962         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
1963         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
1964         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
1965         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
1966         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
1967         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
1968
1969         /* Program me ucode address into intruction cache address register */
1970         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
1971                         lower_32_bits(addr) & 0xFFFFF000);
1972         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
1973                         upper_32_bits(addr));
1974
1975         return 0;
1976 }
1977
1978 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
1979 {
1980         uint32_t usec_timeout = 50000;  /* wait for 50ms */
1981         uint32_t tmp;
1982         int i;
1983
1984         /* Trigger an invalidation of the L1 instruction caches */
1985         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
1986         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1987         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
1988
1989         /* Wait for invalidation complete */
1990         for (i = 0; i < usec_timeout; i++) {
1991                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
1992                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
1993                                         INVALIDATE_CACHE_COMPLETE))
1994                         break;
1995                 udelay(1);
1996         }
1997
1998         if (i >= usec_timeout) {
1999                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2000                 return -EINVAL;
2001         }
2002
2003         if (amdgpu_emu_mode == 1)
2004                 adev->hdp.funcs->flush_hdp(adev, NULL);
2005
2006         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2007         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2008         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2009         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2010         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2011         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2012
2013         /* Program pfp ucode address into intruction cache address register */
2014         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2015                         lower_32_bits(addr) & 0xFFFFF000);
2016         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2017                         upper_32_bits(addr));
2018
2019         return 0;
2020 }
2021
2022 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
2023 {
2024         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2025         uint32_t tmp;
2026         int i;
2027
2028         /* Trigger an invalidation of the L1 instruction caches */
2029         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2030         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2031
2032         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2033
2034         /* Wait for invalidation complete */
2035         for (i = 0; i < usec_timeout; i++) {
2036                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2037                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2038                                         INVALIDATE_CACHE_COMPLETE))
2039                         break;
2040                 udelay(1);
2041         }
2042
2043         if (i >= usec_timeout) {
2044                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2045                 return -EINVAL;
2046         }
2047
2048         if (amdgpu_emu_mode == 1)
2049                 adev->hdp.funcs->flush_hdp(adev, NULL);
2050
2051         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2052         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2053         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2054         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2055         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2056
2057         /* Program mec1 ucode address into intruction cache address register */
2058         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2059                         lower_32_bits(addr) & 0xFFFFF000);
2060         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2061                         upper_32_bits(addr));
2062
2063         return 0;
2064 }
2065
2066 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2067 {
2068         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2069         uint32_t tmp;
2070         unsigned i, pipe_id;
2071         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2072
2073         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2074                 adev->gfx.pfp_fw->data;
2075
2076         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2077                 lower_32_bits(addr));
2078         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2079                 upper_32_bits(addr));
2080
2081         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2082         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2083         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2084         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2085         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2086
2087         /*
2088          * Programming any of the CP_PFP_IC_BASE registers
2089          * forces invalidation of the ME L1 I$. Wait for the
2090          * invalidation complete
2091          */
2092         for (i = 0; i < usec_timeout; i++) {
2093                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2094                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2095                         INVALIDATE_CACHE_COMPLETE))
2096                         break;
2097                 udelay(1);
2098         }
2099
2100         if (i >= usec_timeout) {
2101                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2102                 return -EINVAL;
2103         }
2104
2105         /* Prime the L1 instruction caches */
2106         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2107         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2108         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2109         /* Waiting for cache primed*/
2110         for (i = 0; i < usec_timeout; i++) {
2111                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2112                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2113                         ICACHE_PRIMED))
2114                         break;
2115                 udelay(1);
2116         }
2117
2118         if (i >= usec_timeout) {
2119                 dev_err(adev->dev, "failed to prime instruction cache\n");
2120                 return -EINVAL;
2121         }
2122
2123         mutex_lock(&adev->srbm_mutex);
2124         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2125                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2126                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2127                         (pfp_hdr->ucode_start_addr_hi << 30) |
2128                         (pfp_hdr->ucode_start_addr_lo >> 2));
2129                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2130                         pfp_hdr->ucode_start_addr_hi >> 2);
2131
2132                 /*
2133                  * Program CP_ME_CNTL to reset given PIPE to take
2134                  * effect of CP_PFP_PRGRM_CNTR_START.
2135                  */
2136                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2137                 if (pipe_id == 0)
2138                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2139                                         PFP_PIPE0_RESET, 1);
2140                 else
2141                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2142                                         PFP_PIPE1_RESET, 1);
2143                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2144
2145                 /* Clear pfp pipe0 reset bit. */
2146                 if (pipe_id == 0)
2147                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2148                                         PFP_PIPE0_RESET, 0);
2149                 else
2150                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2151                                         PFP_PIPE1_RESET, 0);
2152                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2153
2154                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2155                         lower_32_bits(addr2));
2156                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2157                         upper_32_bits(addr2));
2158         }
2159         soc21_grbm_select(adev, 0, 0, 0, 0);
2160         mutex_unlock(&adev->srbm_mutex);
2161
2162         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2163         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2164         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2165         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2166
2167         /* Invalidate the data caches */
2168         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2169         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2170         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2171
2172         for (i = 0; i < usec_timeout; i++) {
2173                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2174                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2175                         INVALIDATE_DCACHE_COMPLETE))
2176                         break;
2177                 udelay(1);
2178         }
2179
2180         if (i >= usec_timeout) {
2181                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2182                 return -EINVAL;
2183         }
2184
2185         return 0;
2186 }
2187
2188 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2189 {
2190         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2191         uint32_t tmp;
2192         unsigned i, pipe_id;
2193         const struct gfx_firmware_header_v2_0 *me_hdr;
2194
2195         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2196                 adev->gfx.me_fw->data;
2197
2198         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2199                 lower_32_bits(addr));
2200         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2201                 upper_32_bits(addr));
2202
2203         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2204         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2205         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2206         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2207         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2208
2209         /*
2210          * Programming any of the CP_ME_IC_BASE registers
2211          * forces invalidation of the ME L1 I$. Wait for the
2212          * invalidation complete
2213          */
2214         for (i = 0; i < usec_timeout; i++) {
2215                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2216                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2217                         INVALIDATE_CACHE_COMPLETE))
2218                         break;
2219                 udelay(1);
2220         }
2221
2222         if (i >= usec_timeout) {
2223                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2224                 return -EINVAL;
2225         }
2226
2227         /* Prime the instruction caches */
2228         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2229         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2230         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2231
2232         /* Waiting for instruction cache primed*/
2233         for (i = 0; i < usec_timeout; i++) {
2234                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2235                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2236                         ICACHE_PRIMED))
2237                         break;
2238                 udelay(1);
2239         }
2240
2241         if (i >= usec_timeout) {
2242                 dev_err(adev->dev, "failed to prime instruction cache\n");
2243                 return -EINVAL;
2244         }
2245
2246         mutex_lock(&adev->srbm_mutex);
2247         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2248                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2249                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2250                         (me_hdr->ucode_start_addr_hi << 30) |
2251                         (me_hdr->ucode_start_addr_lo >> 2) );
2252                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2253                         me_hdr->ucode_start_addr_hi>>2);
2254
2255                 /*
2256                  * Program CP_ME_CNTL to reset given PIPE to take
2257                  * effect of CP_PFP_PRGRM_CNTR_START.
2258                  */
2259                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2260                 if (pipe_id == 0)
2261                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2262                                         ME_PIPE0_RESET, 1);
2263                 else
2264                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2265                                         ME_PIPE1_RESET, 1);
2266                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2267
2268                 /* Clear pfp pipe0 reset bit. */
2269                 if (pipe_id == 0)
2270                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2271                                         ME_PIPE0_RESET, 0);
2272                 else
2273                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2274                                         ME_PIPE1_RESET, 0);
2275                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2276
2277                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2278                         lower_32_bits(addr2));
2279                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2280                         upper_32_bits(addr2));
2281         }
2282         soc21_grbm_select(adev, 0, 0, 0, 0);
2283         mutex_unlock(&adev->srbm_mutex);
2284
2285         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2286         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2287         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2288         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2289
2290         /* Invalidate the data caches */
2291         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2292         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2293         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2294
2295         for (i = 0; i < usec_timeout; i++) {
2296                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2297                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2298                         INVALIDATE_DCACHE_COMPLETE))
2299                         break;
2300                 udelay(1);
2301         }
2302
2303         if (i >= usec_timeout) {
2304                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2305                 return -EINVAL;
2306         }
2307
2308         return 0;
2309 }
2310
2311 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2312 {
2313         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2314         uint32_t tmp;
2315         unsigned i;
2316         const struct gfx_firmware_header_v2_0 *mec_hdr;
2317
2318         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2319                 adev->gfx.mec_fw->data;
2320
2321         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2322         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2323         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2324         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2325         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2326
2327         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2328         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2329         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2330         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2331
2332         mutex_lock(&adev->srbm_mutex);
2333         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2334                 soc21_grbm_select(adev, 1, i, 0, 0);
2335
2336                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);
2337                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2338                      upper_32_bits(addr2));
2339
2340                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2341                                         mec_hdr->ucode_start_addr_lo >> 2 |
2342                                         mec_hdr->ucode_start_addr_hi << 30);
2343                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2344                                         mec_hdr->ucode_start_addr_hi >> 2);
2345
2346                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);
2347                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2348                      upper_32_bits(addr));
2349         }
2350         mutex_unlock(&adev->srbm_mutex);
2351         soc21_grbm_select(adev, 0, 0, 0, 0);
2352
2353         /* Trigger an invalidation of the L1 instruction caches */
2354         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2355         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2356         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2357
2358         /* Wait for invalidation complete */
2359         for (i = 0; i < usec_timeout; i++) {
2360                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2361                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2362                                        INVALIDATE_DCACHE_COMPLETE))
2363                         break;
2364                 udelay(1);
2365         }
2366
2367         if (i >= usec_timeout) {
2368                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2369                 return -EINVAL;
2370         }
2371
2372         /* Trigger an invalidation of the L1 instruction caches */
2373         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2374         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2375         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2376
2377         /* Wait for invalidation complete */
2378         for (i = 0; i < usec_timeout; i++) {
2379                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2380                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2381                                        INVALIDATE_CACHE_COMPLETE))
2382                         break;
2383                 udelay(1);
2384         }
2385
2386         if (i >= usec_timeout) {
2387                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2388                 return -EINVAL;
2389         }
2390
2391         return 0;
2392 }
2393
2394 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev)
2395 {
2396         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2397         const struct gfx_firmware_header_v2_0 *me_hdr;
2398         const struct gfx_firmware_header_v2_0 *mec_hdr;
2399         uint32_t pipe_id, tmp;
2400
2401         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2402                 adev->gfx.mec_fw->data;
2403         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2404                 adev->gfx.me_fw->data;
2405         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2406                 adev->gfx.pfp_fw->data;
2407
2408         /* config pfp program start addr */
2409         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2410                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2411                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2412                         (pfp_hdr->ucode_start_addr_hi << 30) |
2413                         (pfp_hdr->ucode_start_addr_lo >> 2));
2414                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2415                         pfp_hdr->ucode_start_addr_hi >> 2);
2416         }
2417         soc21_grbm_select(adev, 0, 0, 0, 0);
2418
2419         /* reset pfp pipe */
2420         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2421         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2422         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2423         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2424
2425         /* clear pfp pipe reset */
2426         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2427         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2428         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2429
2430         /* config me program start addr */
2431         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2432                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2433                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2434                         (me_hdr->ucode_start_addr_hi << 30) |
2435                         (me_hdr->ucode_start_addr_lo >> 2) );
2436                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2437                         me_hdr->ucode_start_addr_hi>>2);
2438         }
2439         soc21_grbm_select(adev, 0, 0, 0, 0);
2440
2441         /* reset me pipe */
2442         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2443         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2444         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2445         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2446
2447         /* clear me pipe reset */
2448         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2449         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2450         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2451
2452         /* config mec program start addr */
2453         for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2454                 soc21_grbm_select(adev, 1, pipe_id, 0, 0);
2455                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2456                                         mec_hdr->ucode_start_addr_lo >> 2 |
2457                                         mec_hdr->ucode_start_addr_hi << 30);
2458                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2459                                         mec_hdr->ucode_start_addr_hi >> 2);
2460         }
2461         soc21_grbm_select(adev, 0, 0, 0, 0);
2462
2463         /* reset mec pipe */
2464         tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2465         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2466         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2467         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2468         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2469         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2470
2471         /* clear mec pipe reset */
2472         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2473         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2474         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2475         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2476         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2477 }
2478
2479 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2480 {
2481         uint32_t cp_status;
2482         uint32_t bootload_status;
2483         int i, r;
2484         uint64_t addr, addr2;
2485
2486         for (i = 0; i < adev->usec_timeout; i++) {
2487                 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2488
2489                 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1))
2490                         bootload_status = RREG32_SOC15(GC, 0,
2491                                         regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
2492                 else
2493                         bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2494
2495                 if ((cp_status == 0) &&
2496                     (REG_GET_FIELD(bootload_status,
2497                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2498                         break;
2499                 }
2500                 udelay(1);
2501         }
2502
2503         if (i >= adev->usec_timeout) {
2504                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2505                 return -ETIMEDOUT;
2506         }
2507
2508         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2509                 if (adev->gfx.rs64_enable) {
2510                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2511                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset;
2512                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2513                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset;
2514                         r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2);
2515                         if (r)
2516                                 return r;
2517                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2518                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset;
2519                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2520                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset;
2521                         r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2);
2522                         if (r)
2523                                 return r;
2524                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2525                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset;
2526                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2527                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset;
2528                         r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2);
2529                         if (r)
2530                                 return r;
2531                 } else {
2532                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2533                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset;
2534                         r = gfx_v11_0_config_me_cache(adev, addr);
2535                         if (r)
2536                                 return r;
2537                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2538                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset;
2539                         r = gfx_v11_0_config_pfp_cache(adev, addr);
2540                         if (r)
2541                                 return r;
2542                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2543                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset;
2544                         r = gfx_v11_0_config_mec_cache(adev, addr);
2545                         if (r)
2546                                 return r;
2547                 }
2548         }
2549
2550         return 0;
2551 }
2552
2553 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2554 {
2555         int i;
2556         u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2557
2558         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2559         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2560         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2561
2562         for (i = 0; i < adev->usec_timeout; i++) {
2563                 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2564                         break;
2565                 udelay(1);
2566         }
2567
2568         if (i >= adev->usec_timeout)
2569                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2570
2571         return 0;
2572 }
2573
2574 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2575 {
2576         int r;
2577         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2578         const __le32 *fw_data;
2579         unsigned i, fw_size;
2580
2581         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2582                 adev->gfx.pfp_fw->data;
2583
2584         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2585
2586         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2587                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2588         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2589
2590         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2591                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2592                                       &adev->gfx.pfp.pfp_fw_obj,
2593                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2594                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2595         if (r) {
2596                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2597                 gfx_v11_0_pfp_fini(adev);
2598                 return r;
2599         }
2600
2601         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2602
2603         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2604         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2605
2606         gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr);
2607
2608         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);
2609
2610         for (i = 0; i < pfp_hdr->jt_size; i++)
2611                 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,
2612                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
2613
2614         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2615
2616         return 0;
2617 }
2618
2619 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2620 {
2621         int r;
2622         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2623         const __le32 *fw_ucode, *fw_data;
2624         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2625         uint32_t tmp;
2626         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2627
2628         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2629                 adev->gfx.pfp_fw->data;
2630
2631         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2632
2633         /* instruction */
2634         fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2635                 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2636         fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2637         /* data */
2638         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2639                 le32_to_cpu(pfp_hdr->data_offset_bytes));
2640         fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2641
2642         /* 64kb align */
2643         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2644                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2645                                       &adev->gfx.pfp.pfp_fw_obj,
2646                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2647                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2648         if (r) {
2649                 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2650                 gfx_v11_0_pfp_fini(adev);
2651                 return r;
2652         }
2653
2654         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2655                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2656                                       &adev->gfx.pfp.pfp_fw_data_obj,
2657                                       &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2658                                       (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2659         if (r) {
2660                 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2661                 gfx_v11_0_pfp_fini(adev);
2662                 return r;
2663         }
2664
2665         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2666         memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2667
2668         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2669         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2670         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2671         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2672
2673         if (amdgpu_emu_mode == 1)
2674                 adev->hdp.funcs->flush_hdp(adev, NULL);
2675
2676         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2677                 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2678         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2679                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2680
2681         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2682         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2683         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2684         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2685         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2686
2687         /*
2688          * Programming any of the CP_PFP_IC_BASE registers
2689          * forces invalidation of the ME L1 I$. Wait for the
2690          * invalidation complete
2691          */
2692         for (i = 0; i < usec_timeout; i++) {
2693                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2694                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2695                         INVALIDATE_CACHE_COMPLETE))
2696                         break;
2697                 udelay(1);
2698         }
2699
2700         if (i >= usec_timeout) {
2701                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2702                 return -EINVAL;
2703         }
2704
2705         /* Prime the L1 instruction caches */
2706         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2707         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2708         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2709         /* Waiting for cache primed*/
2710         for (i = 0; i < usec_timeout; i++) {
2711                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2712                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2713                         ICACHE_PRIMED))
2714                         break;
2715                 udelay(1);
2716         }
2717
2718         if (i >= usec_timeout) {
2719                 dev_err(adev->dev, "failed to prime instruction cache\n");
2720                 return -EINVAL;
2721         }
2722
2723         mutex_lock(&adev->srbm_mutex);
2724         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2725                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2726                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2727                         (pfp_hdr->ucode_start_addr_hi << 30) |
2728                         (pfp_hdr->ucode_start_addr_lo >> 2) );
2729                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2730                         pfp_hdr->ucode_start_addr_hi>>2);
2731
2732                 /*
2733                  * Program CP_ME_CNTL to reset given PIPE to take
2734                  * effect of CP_PFP_PRGRM_CNTR_START.
2735                  */
2736                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2737                 if (pipe_id == 0)
2738                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2739                                         PFP_PIPE0_RESET, 1);
2740                 else
2741                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2742                                         PFP_PIPE1_RESET, 1);
2743                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2744
2745                 /* Clear pfp pipe0 reset bit. */
2746                 if (pipe_id == 0)
2747                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2748                                         PFP_PIPE0_RESET, 0);
2749                 else
2750                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2751                                         PFP_PIPE1_RESET, 0);
2752                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2753
2754                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2755                         lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2756                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2757                         upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2758         }
2759         soc21_grbm_select(adev, 0, 0, 0, 0);
2760         mutex_unlock(&adev->srbm_mutex);
2761
2762         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2763         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2764         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2765         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2766
2767         /* Invalidate the data caches */
2768         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2769         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2770         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2771
2772         for (i = 0; i < usec_timeout; i++) {
2773                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2774                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2775                         INVALIDATE_DCACHE_COMPLETE))
2776                         break;
2777                 udelay(1);
2778         }
2779
2780         if (i >= usec_timeout) {
2781                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2782                 return -EINVAL;
2783         }
2784
2785         return 0;
2786 }
2787
2788 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2789 {
2790         int r;
2791         const struct gfx_firmware_header_v1_0 *me_hdr;
2792         const __le32 *fw_data;
2793         unsigned i, fw_size;
2794
2795         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2796                 adev->gfx.me_fw->data;
2797
2798         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2799
2800         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2801                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2802         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2803
2804         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2805                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2806                                       &adev->gfx.me.me_fw_obj,
2807                                       &adev->gfx.me.me_fw_gpu_addr,
2808                                       (void **)&adev->gfx.me.me_fw_ptr);
2809         if (r) {
2810                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2811                 gfx_v11_0_me_fini(adev);
2812                 return r;
2813         }
2814
2815         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2816
2817         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2818         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2819
2820         gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr);
2821
2822         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);
2823
2824         for (i = 0; i < me_hdr->jt_size; i++)
2825                 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,
2826                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
2827
2828         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
2829
2830         return 0;
2831 }
2832
2833 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2834 {
2835         int r;
2836         const struct gfx_firmware_header_v2_0 *me_hdr;
2837         const __le32 *fw_ucode, *fw_data;
2838         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2839         uint32_t tmp;
2840         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2841
2842         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2843                 adev->gfx.me_fw->data;
2844
2845         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2846
2847         /* instruction */
2848         fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2849                 le32_to_cpu(me_hdr->ucode_offset_bytes));
2850         fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2851         /* data */
2852         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2853                 le32_to_cpu(me_hdr->data_offset_bytes));
2854         fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2855
2856         /* 64kb align*/
2857         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2858                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2859                                       &adev->gfx.me.me_fw_obj,
2860                                       &adev->gfx.me.me_fw_gpu_addr,
2861                                       (void **)&adev->gfx.me.me_fw_ptr);
2862         if (r) {
2863                 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2864                 gfx_v11_0_me_fini(adev);
2865                 return r;
2866         }
2867
2868         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2869                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2870                                       &adev->gfx.me.me_fw_data_obj,
2871                                       &adev->gfx.me.me_fw_data_gpu_addr,
2872                                       (void **)&adev->gfx.me.me_fw_data_ptr);
2873         if (r) {
2874                 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2875                 gfx_v11_0_pfp_fini(adev);
2876                 return r;
2877         }
2878
2879         memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2880         memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2881
2882         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2883         amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2884         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2885         amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2886
2887         if (amdgpu_emu_mode == 1)
2888                 adev->hdp.funcs->flush_hdp(adev, NULL);
2889
2890         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2891                 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2892         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2893                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2894
2895         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2896         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2897         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2898         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2899         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2900
2901         /*
2902          * Programming any of the CP_ME_IC_BASE registers
2903          * forces invalidation of the ME L1 I$. Wait for the
2904          * invalidation complete
2905          */
2906         for (i = 0; i < usec_timeout; i++) {
2907                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2908                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2909                         INVALIDATE_CACHE_COMPLETE))
2910                         break;
2911                 udelay(1);
2912         }
2913
2914         if (i >= usec_timeout) {
2915                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2916                 return -EINVAL;
2917         }
2918
2919         /* Prime the instruction caches */
2920         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2921         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2922         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2923
2924         /* Waiting for instruction cache primed*/
2925         for (i = 0; i < usec_timeout; i++) {
2926                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2927                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2928                         ICACHE_PRIMED))
2929                         break;
2930                 udelay(1);
2931         }
2932
2933         if (i >= usec_timeout) {
2934                 dev_err(adev->dev, "failed to prime instruction cache\n");
2935                 return -EINVAL;
2936         }
2937
2938         mutex_lock(&adev->srbm_mutex);
2939         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2940                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2941                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2942                         (me_hdr->ucode_start_addr_hi << 30) |
2943                         (me_hdr->ucode_start_addr_lo >> 2) );
2944                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2945                         me_hdr->ucode_start_addr_hi>>2);
2946
2947                 /*
2948                  * Program CP_ME_CNTL to reset given PIPE to take
2949                  * effect of CP_PFP_PRGRM_CNTR_START.
2950                  */
2951                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2952                 if (pipe_id == 0)
2953                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2954                                         ME_PIPE0_RESET, 1);
2955                 else
2956                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2957                                         ME_PIPE1_RESET, 1);
2958                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2959
2960                 /* Clear pfp pipe0 reset bit. */
2961                 if (pipe_id == 0)
2962                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2963                                         ME_PIPE0_RESET, 0);
2964                 else
2965                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2966                                         ME_PIPE1_RESET, 0);
2967                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2968
2969                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2970                         lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2971                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2972                         upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2973         }
2974         soc21_grbm_select(adev, 0, 0, 0, 0);
2975         mutex_unlock(&adev->srbm_mutex);
2976
2977         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2978         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2979         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2980         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2981
2982         /* Invalidate the data caches */
2983         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2984         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2985         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2986
2987         for (i = 0; i < usec_timeout; i++) {
2988                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2989                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2990                         INVALIDATE_DCACHE_COMPLETE))
2991                         break;
2992                 udelay(1);
2993         }
2994
2995         if (i >= usec_timeout) {
2996                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2997                 return -EINVAL;
2998         }
2999
3000         return 0;
3001 }
3002
3003 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3004 {
3005         int r;
3006
3007         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
3008                 return -EINVAL;
3009
3010         gfx_v11_0_cp_gfx_enable(adev, false);
3011
3012         if (adev->gfx.rs64_enable)
3013                 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev);
3014         else
3015                 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev);
3016         if (r) {
3017                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
3018                 return r;
3019         }
3020
3021         if (adev->gfx.rs64_enable)
3022                 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev);
3023         else
3024                 r = gfx_v11_0_cp_gfx_load_me_microcode(adev);
3025         if (r) {
3026                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
3027                 return r;
3028         }
3029
3030         return 0;
3031 }
3032
3033 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev)
3034 {
3035         struct amdgpu_ring *ring;
3036         const struct cs_section_def *sect = NULL;
3037         const struct cs_extent_def *ext = NULL;
3038         int r, i;
3039         int ctx_reg_offset;
3040
3041         /* init the CP */
3042         WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
3043                      adev->gfx.config.max_hw_contexts - 1);
3044         WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
3045
3046         if (!amdgpu_async_gfx_ring)
3047                 gfx_v11_0_cp_gfx_enable(adev, true);
3048
3049         ring = &adev->gfx.gfx_ring[0];
3050         r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev));
3051         if (r) {
3052                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3053                 return r;
3054         }
3055
3056         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3057         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3058
3059         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3060         amdgpu_ring_write(ring, 0x80000000);
3061         amdgpu_ring_write(ring, 0x80000000);
3062
3063         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
3064                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3065                         if (sect->id == SECT_CONTEXT) {
3066                                 amdgpu_ring_write(ring,
3067                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
3068                                                           ext->reg_count));
3069                                 amdgpu_ring_write(ring, ext->reg_index -
3070                                                   PACKET3_SET_CONTEXT_REG_START);
3071                                 for (i = 0; i < ext->reg_count; i++)
3072                                         amdgpu_ring_write(ring, ext->extent[i]);
3073                         }
3074                 }
3075         }
3076
3077         ctx_reg_offset =
3078                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3079         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3080         amdgpu_ring_write(ring, ctx_reg_offset);
3081         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
3082
3083         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3084         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3085
3086         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3087         amdgpu_ring_write(ring, 0);
3088
3089         amdgpu_ring_commit(ring);
3090
3091         /* submit cs packet to copy state 0 to next available state */
3092         if (adev->gfx.num_gfx_rings > 1) {
3093                 /* maximum supported gfx ring is 2 */
3094                 ring = &adev->gfx.gfx_ring[1];
3095                 r = amdgpu_ring_alloc(ring, 2);
3096                 if (r) {
3097                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3098                         return r;
3099                 }
3100
3101                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3102                 amdgpu_ring_write(ring, 0);
3103
3104                 amdgpu_ring_commit(ring);
3105         }
3106         return 0;
3107 }
3108
3109 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
3110                                          CP_PIPE_ID pipe)
3111 {
3112         u32 tmp;
3113
3114         tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
3115         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
3116
3117         WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
3118 }
3119
3120 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
3121                                           struct amdgpu_ring *ring)
3122 {
3123         u32 tmp;
3124
3125         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3126         if (ring->use_doorbell) {
3127                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3128                                     DOORBELL_OFFSET, ring->doorbell_index);
3129                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3130                                     DOORBELL_EN, 1);
3131         } else {
3132                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3133                                     DOORBELL_EN, 0);
3134         }
3135         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
3136
3137         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3138                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
3139         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
3140
3141         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3142                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3143 }
3144
3145 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
3146 {
3147         struct amdgpu_ring *ring;
3148         u32 tmp;
3149         u32 rb_bufsz;
3150         u64 rb_addr, rptr_addr, wptr_gpu_addr;
3151         u32 i;
3152
3153         /* Set the write pointer delay */
3154         WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
3155
3156         /* set the RB to use vmid 0 */
3157         WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
3158
3159         /* Init gfx ring 0 for pipe 0 */
3160         mutex_lock(&adev->srbm_mutex);
3161         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3162
3163         /* Set ring buffer size */
3164         ring = &adev->gfx.gfx_ring[0];
3165         rb_bufsz = order_base_2(ring->ring_size / 8);
3166         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3167         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3168         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3169
3170         /* Initialize the ring buffer's write pointers */
3171         ring->wptr = 0;
3172         WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
3173         WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3174
3175         /* set the wb address wether it's enabled or not */
3176         rptr_addr = ring->rptr_gpu_addr;
3177         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3178         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3179                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3180
3181         wptr_gpu_addr = ring->wptr_gpu_addr;
3182         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3183                      lower_32_bits(wptr_gpu_addr));
3184         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3185                      upper_32_bits(wptr_gpu_addr));
3186
3187         mdelay(1);
3188         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3189
3190         rb_addr = ring->gpu_addr >> 8;
3191         WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
3192         WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3193
3194         WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
3195
3196         gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3197         mutex_unlock(&adev->srbm_mutex);
3198
3199         /* Init gfx ring 1 for pipe 1 */
3200         if (adev->gfx.num_gfx_rings > 1) {
3201                 mutex_lock(&adev->srbm_mutex);
3202                 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
3203                 /* maximum supported gfx ring is 2 */
3204                 ring = &adev->gfx.gfx_ring[1];
3205                 rb_bufsz = order_base_2(ring->ring_size / 8);
3206                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
3207                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
3208                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3209                 /* Initialize the ring buffer's write pointers */
3210                 ring->wptr = 0;
3211                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));
3212                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
3213                 /* Set the wb address wether it's enabled or not */
3214                 rptr_addr = ring->rptr_gpu_addr;
3215                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
3216                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3217                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3218                 wptr_gpu_addr = ring->wptr_gpu_addr;
3219                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3220                              lower_32_bits(wptr_gpu_addr));
3221                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3222                              upper_32_bits(wptr_gpu_addr));
3223
3224                 mdelay(1);
3225                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3226
3227                 rb_addr = ring->gpu_addr >> 8;
3228                 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);
3229                 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));
3230                 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);
3231
3232                 gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3233                 mutex_unlock(&adev->srbm_mutex);
3234         }
3235         /* Switch to pipe 0 */
3236         mutex_lock(&adev->srbm_mutex);
3237         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3238         mutex_unlock(&adev->srbm_mutex);
3239
3240         /* start the ring */
3241         gfx_v11_0_cp_gfx_start(adev);
3242
3243         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3244                 ring = &adev->gfx.gfx_ring[i];
3245                 ring->sched.ready = true;
3246         }
3247
3248         return 0;
3249 }
3250
3251 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3252 {
3253         u32 data;
3254
3255         if (adev->gfx.rs64_enable) {
3256                 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
3257                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
3258                                                          enable ? 0 : 1);
3259                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
3260                                                          enable ? 0 : 1);
3261                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
3262                                                          enable ? 0 : 1);
3263                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
3264                                                          enable ? 0 : 1);
3265                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
3266                                                          enable ? 0 : 1);
3267                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
3268                                                          enable ? 1 : 0);
3269                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
3270                                                          enable ? 1 : 0);
3271                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
3272                                                          enable ? 1 : 0);
3273                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
3274                                                          enable ? 1 : 0);
3275                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
3276                                                          enable ? 0 : 1);
3277                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
3278         } else {
3279                 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
3280
3281                 if (enable) {
3282                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);
3283                         if (!adev->enable_mes_kiq)
3284                                 data = REG_SET_FIELD(data, CP_MEC_CNTL,
3285                                                      MEC_ME2_HALT, 0);
3286                 } else {
3287                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);
3288                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);
3289                 }
3290                 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);
3291         }
3292
3293         adev->gfx.kiq.ring.sched.ready = enable;
3294
3295         udelay(50);
3296 }
3297
3298 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3299 {
3300         const struct gfx_firmware_header_v1_0 *mec_hdr;
3301         const __le32 *fw_data;
3302         unsigned i, fw_size;
3303         u32 *fw = NULL;
3304         int r;
3305
3306         if (!adev->gfx.mec_fw)
3307                 return -EINVAL;
3308
3309         gfx_v11_0_cp_compute_enable(adev, false);
3310
3311         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3312         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3313
3314         fw_data = (const __le32 *)
3315                 (adev->gfx.mec_fw->data +
3316                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3317         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3318
3319         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3320                                           PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3321                                           &adev->gfx.mec.mec_fw_obj,
3322                                           &adev->gfx.mec.mec_fw_gpu_addr,
3323                                           (void **)&fw);
3324         if (r) {
3325                 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3326                 gfx_v11_0_mec_fini(adev);
3327                 return r;
3328         }
3329
3330         memcpy(fw, fw_data, fw_size);
3331
3332         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3333         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3334
3335         gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr);
3336
3337         /* MEC1 */
3338         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);
3339
3340         for (i = 0; i < mec_hdr->jt_size; i++)
3341                 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,
3342                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3343
3344         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3345
3346         return 0;
3347 }
3348
3349 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
3350 {
3351         const struct gfx_firmware_header_v2_0 *mec_hdr;
3352         const __le32 *fw_ucode, *fw_data;
3353         u32 tmp, fw_ucode_size, fw_data_size;
3354         u32 i, usec_timeout = 50000; /* Wait for 50 ms */
3355         u32 *fw_ucode_ptr, *fw_data_ptr;
3356         int r;
3357
3358         if (!adev->gfx.mec_fw)
3359                 return -EINVAL;
3360
3361         gfx_v11_0_cp_compute_enable(adev, false);
3362
3363         mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
3364         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3365
3366         fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
3367                                 le32_to_cpu(mec_hdr->ucode_offset_bytes));
3368         fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
3369
3370         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3371                                 le32_to_cpu(mec_hdr->data_offset_bytes));
3372         fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
3373
3374         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3375                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
3376                                       &adev->gfx.mec.mec_fw_obj,
3377                                       &adev->gfx.mec.mec_fw_gpu_addr,
3378                                       (void **)&fw_ucode_ptr);
3379         if (r) {
3380                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3381                 gfx_v11_0_mec_fini(adev);
3382                 return r;
3383         }
3384
3385         r = amdgpu_bo_create_reserved(adev, fw_data_size,
3386                                       64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
3387                                       &adev->gfx.mec.mec_fw_data_obj,
3388                                       &adev->gfx.mec.mec_fw_data_gpu_addr,
3389                                       (void **)&fw_data_ptr);
3390         if (r) {
3391                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3392                 gfx_v11_0_mec_fini(adev);
3393                 return r;
3394         }
3395
3396         memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
3397         memcpy(fw_data_ptr, fw_data, fw_data_size);
3398
3399         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3400         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
3401         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3402         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
3403
3404         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
3405         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3406         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
3407         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3408         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
3409
3410         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
3411         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
3412         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
3413         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
3414
3415         mutex_lock(&adev->srbm_mutex);
3416         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3417                 soc21_grbm_select(adev, 1, i, 0, 0);
3418
3419                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);
3420                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
3421                      upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));
3422
3423                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
3424                                         mec_hdr->ucode_start_addr_lo >> 2 |
3425                                         mec_hdr->ucode_start_addr_hi << 30);
3426                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
3427                                         mec_hdr->ucode_start_addr_hi >> 2);
3428
3429                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);
3430                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
3431                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3432         }
3433         mutex_unlock(&adev->srbm_mutex);
3434         soc21_grbm_select(adev, 0, 0, 0, 0);
3435
3436         /* Trigger an invalidation of the L1 instruction caches */
3437         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3438         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3439         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
3440
3441         /* Wait for invalidation complete */
3442         for (i = 0; i < usec_timeout; i++) {
3443                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3444                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
3445                                        INVALIDATE_DCACHE_COMPLETE))
3446                         break;
3447                 udelay(1);
3448         }
3449
3450         if (i >= usec_timeout) {
3451                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3452                 return -EINVAL;
3453         }
3454
3455         /* Trigger an invalidation of the L1 instruction caches */
3456         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3457         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
3458         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
3459
3460         /* Wait for invalidation complete */
3461         for (i = 0; i < usec_timeout; i++) {
3462                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3463                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
3464                                        INVALIDATE_CACHE_COMPLETE))
3465                         break;
3466                 udelay(1);
3467         }
3468
3469         if (i >= usec_timeout) {
3470                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3471                 return -EINVAL;
3472         }
3473
3474         return 0;
3475 }
3476
3477 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring)
3478 {
3479         uint32_t tmp;
3480         struct amdgpu_device *adev = ring->adev;
3481
3482         /* tell RLC which is KIQ queue */
3483         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3484         tmp &= 0xffffff00;
3485         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3486         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3487         tmp |= 0x80;
3488         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3489 }
3490
3491 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)
3492 {
3493         /* set graphics engine doorbell range */
3494         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
3495                      (adev->doorbell_index.gfx_ring0 * 2) << 2);
3496         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3497                      (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
3498
3499         /* set compute engine doorbell range */
3500         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3501                      (adev->doorbell_index.kiq * 2) << 2);
3502         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3503                      (adev->doorbell_index.userqueue_end * 2) << 2);
3504 }
3505
3506 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
3507                                   struct amdgpu_mqd_prop *prop)
3508 {
3509         struct v11_gfx_mqd *mqd = m;
3510         uint64_t hqd_gpu_addr, wb_gpu_addr;
3511         uint32_t tmp;
3512         uint32_t rb_bufsz;
3513
3514         /* set up gfx hqd wptr */
3515         mqd->cp_gfx_hqd_wptr = 0;
3516         mqd->cp_gfx_hqd_wptr_hi = 0;
3517
3518         /* set the pointer to the MQD */
3519         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
3520         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3521
3522         /* set up mqd control */
3523         tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
3524         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
3525         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
3526         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
3527         mqd->cp_gfx_mqd_control = tmp;
3528
3529         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3530         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
3531         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3532         mqd->cp_gfx_hqd_vmid = 0;
3533
3534         /* set up default queue priority level
3535          * 0x0 = low priority, 0x1 = high priority */
3536         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
3537         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3538         mqd->cp_gfx_hqd_queue_priority = tmp;
3539
3540         /* set up time quantum */
3541         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
3542         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3543         mqd->cp_gfx_hqd_quantum = tmp;
3544
3545         /* set up gfx hqd base. this is similar as CP_RB_BASE */
3546         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3547         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3548         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3549
3550         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3551         wb_gpu_addr = prop->rptr_gpu_addr;
3552         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3553         mqd->cp_gfx_hqd_rptr_addr_hi =
3554                 upper_32_bits(wb_gpu_addr) & 0xffff;
3555
3556         /* set up rb_wptr_poll addr */
3557         wb_gpu_addr = prop->wptr_gpu_addr;
3558         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3559         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3560
3561         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3562         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3563         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
3564         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3565         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3566 #ifdef __BIG_ENDIAN
3567         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3568 #endif
3569         mqd->cp_gfx_hqd_cntl = tmp;
3570
3571         /* set up cp_doorbell_control */
3572         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3573         if (prop->use_doorbell) {
3574                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3575                                     DOORBELL_OFFSET, prop->doorbell_index);
3576                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3577                                     DOORBELL_EN, 1);
3578         } else
3579                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3580                                     DOORBELL_EN, 0);
3581         mqd->cp_rb_doorbell_control = tmp;
3582
3583         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3584         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
3585
3586         /* active the queue */
3587         mqd->cp_gfx_hqd_active = 1;
3588
3589         return 0;
3590 }
3591
3592 #ifdef BRING_UP_DEBUG
3593 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3594 {
3595         struct amdgpu_device *adev = ring->adev;
3596         struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3597
3598         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3599         WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3600         WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3601
3602         /* set GFX_MQD_BASE */
3603         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3604         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3605
3606         /* set GFX_MQD_CONTROL */
3607         WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3608
3609         /* set GFX_HQD_VMID to 0 */
3610         WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3611
3612         WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY,
3613                         mqd->cp_gfx_hqd_queue_priority);
3614         WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3615
3616         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
3617         WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3618         WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3619
3620         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3621         WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3622         WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3623
3624         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3625         WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3626
3627         /* set RB_WPTR_POLL_ADDR */
3628         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3629         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3630
3631         /* set RB_DOORBELL_CONTROL */
3632         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3633
3634         /* active the queue */
3635         WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3636
3637         return 0;
3638 }
3639 #endif
3640
3641 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)
3642 {
3643         struct amdgpu_device *adev = ring->adev;
3644         struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3645         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3646
3647         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3648                 memset((void *)mqd, 0, sizeof(*mqd));
3649                 mutex_lock(&adev->srbm_mutex);
3650                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3651                 amdgpu_ring_init_mqd(ring);
3652 #ifdef BRING_UP_DEBUG
3653                 gfx_v11_0_gfx_queue_init_register(ring);
3654 #endif
3655                 soc21_grbm_select(adev, 0, 0, 0, 0);
3656                 mutex_unlock(&adev->srbm_mutex);
3657                 if (adev->gfx.me.mqd_backup[mqd_idx])
3658                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3659         } else if (amdgpu_in_reset(adev)) {
3660                 /* reset mqd with the backup copy */
3661                 if (adev->gfx.me.mqd_backup[mqd_idx])
3662                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3663                 /* reset the ring */
3664                 ring->wptr = 0;
3665                 *ring->wptr_cpu_addr = 0;
3666                 amdgpu_ring_clear_ring(ring);
3667 #ifdef BRING_UP_DEBUG
3668                 mutex_lock(&adev->srbm_mutex);
3669                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3670                 gfx_v11_0_gfx_queue_init_register(ring);
3671                 soc21_grbm_select(adev, 0, 0, 0, 0);
3672                 mutex_unlock(&adev->srbm_mutex);
3673 #endif
3674         } else {
3675                 amdgpu_ring_clear_ring(ring);
3676         }
3677
3678         return 0;
3679 }
3680
3681 #ifndef BRING_UP_DEBUG
3682 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev)
3683 {
3684         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3685         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3686         int r, i;
3687
3688         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3689                 return -EINVAL;
3690
3691         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3692                                         adev->gfx.num_gfx_rings);
3693         if (r) {
3694                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3695                 return r;
3696         }
3697
3698         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3699                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3700
3701         return amdgpu_ring_test_helper(kiq_ring);
3702 }
3703 #endif
3704
3705 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3706 {
3707         int r, i;
3708         struct amdgpu_ring *ring;
3709
3710         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3711                 ring = &adev->gfx.gfx_ring[i];
3712
3713                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3714                 if (unlikely(r != 0))
3715                         goto done;
3716
3717                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3718                 if (!r) {
3719                         r = gfx_v11_0_gfx_init_queue(ring);
3720                         amdgpu_bo_kunmap(ring->mqd_obj);
3721                         ring->mqd_ptr = NULL;
3722                 }
3723                 amdgpu_bo_unreserve(ring->mqd_obj);
3724                 if (r)
3725                         goto done;
3726         }
3727 #ifndef BRING_UP_DEBUG
3728         r = gfx_v11_0_kiq_enable_kgq(adev);
3729         if (r)
3730                 goto done;
3731 #endif
3732         r = gfx_v11_0_cp_gfx_start(adev);
3733         if (r)
3734                 goto done;
3735
3736         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3737                 ring = &adev->gfx.gfx_ring[i];
3738                 ring->sched.ready = true;
3739         }
3740 done:
3741         return r;
3742 }
3743
3744 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3745                                       struct amdgpu_mqd_prop *prop)
3746 {
3747         struct v11_compute_mqd *mqd = m;
3748         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3749         uint32_t tmp;
3750
3751         mqd->header = 0xC0310800;
3752         mqd->compute_pipelinestat_enable = 0x00000001;
3753         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3754         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3755         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3756         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3757         mqd->compute_misc_reserved = 0x00000007;
3758
3759         eop_base_addr = prop->eop_gpu_addr >> 8;
3760         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3761         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3762
3763         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3764         tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
3765         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3766                         (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));
3767
3768         mqd->cp_hqd_eop_control = tmp;
3769
3770         /* enable doorbell? */
3771         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3772
3773         if (prop->use_doorbell) {
3774                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3775                                     DOORBELL_OFFSET, prop->doorbell_index);
3776                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3777                                     DOORBELL_EN, 1);
3778                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3779                                     DOORBELL_SOURCE, 0);
3780                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3781                                     DOORBELL_HIT, 0);
3782         } else {
3783                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3784                                     DOORBELL_EN, 0);
3785         }
3786
3787         mqd->cp_hqd_pq_doorbell_control = tmp;
3788
3789         /* disable the queue if it's active */
3790         mqd->cp_hqd_dequeue_request = 0;
3791         mqd->cp_hqd_pq_rptr = 0;
3792         mqd->cp_hqd_pq_wptr_lo = 0;
3793         mqd->cp_hqd_pq_wptr_hi = 0;
3794
3795         /* set the pointer to the MQD */
3796         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3797         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3798
3799         /* set MQD vmid to 0 */
3800         tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
3801         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3802         mqd->cp_mqd_control = tmp;
3803
3804         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3805         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3806         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3807         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3808
3809         /* set up the HQD, this is similar to CP_RB0_CNTL */
3810         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
3811         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3812                             (order_base_2(prop->queue_size / 4) - 1));
3813         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3814                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3815         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3816         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3817         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3818         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3819         mqd->cp_hqd_pq_control = tmp;
3820
3821         /* set the wb address whether it's enabled or not */
3822         wb_gpu_addr = prop->rptr_gpu_addr;
3823         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3824         mqd->cp_hqd_pq_rptr_report_addr_hi =
3825                 upper_32_bits(wb_gpu_addr) & 0xffff;
3826
3827         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3828         wb_gpu_addr = prop->wptr_gpu_addr;
3829         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3830         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3831
3832         tmp = 0;
3833         /* enable the doorbell if requested */
3834         if (prop->use_doorbell) {
3835                 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3836                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3837                                 DOORBELL_OFFSET, prop->doorbell_index);
3838
3839                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3840                                     DOORBELL_EN, 1);
3841                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3842                                     DOORBELL_SOURCE, 0);
3843                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3844                                     DOORBELL_HIT, 0);
3845         }
3846
3847         mqd->cp_hqd_pq_doorbell_control = tmp;
3848
3849         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3850         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
3851
3852         /* set the vmid for the queue */
3853         mqd->cp_hqd_vmid = 0;
3854
3855         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
3856         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3857         mqd->cp_hqd_persistent_state = tmp;
3858
3859         /* set MIN_IB_AVAIL_SIZE */
3860         tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
3861         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3862         mqd->cp_hqd_ib_control = tmp;
3863
3864         /* set static priority for a compute queue/ring */
3865         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3866         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3867
3868         mqd->cp_hqd_active = prop->hqd_active;
3869
3870         return 0;
3871 }
3872
3873 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring)
3874 {
3875         struct amdgpu_device *adev = ring->adev;
3876         struct v11_compute_mqd *mqd = ring->mqd_ptr;
3877         int j;
3878
3879         /* inactivate the queue */
3880         if (amdgpu_sriov_vf(adev))
3881                 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3882
3883         /* disable wptr polling */
3884         WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3885
3886         /* write the EOP addr */
3887         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3888                mqd->cp_hqd_eop_base_addr_lo);
3889         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3890                mqd->cp_hqd_eop_base_addr_hi);
3891
3892         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3893         WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3894                mqd->cp_hqd_eop_control);
3895
3896         /* enable doorbell? */
3897         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3898                mqd->cp_hqd_pq_doorbell_control);
3899
3900         /* disable the queue if it's active */
3901         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3902                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3903                 for (j = 0; j < adev->usec_timeout; j++) {
3904                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3905                                 break;
3906                         udelay(1);
3907                 }
3908                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3909                        mqd->cp_hqd_dequeue_request);
3910                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3911                        mqd->cp_hqd_pq_rptr);
3912                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3913                        mqd->cp_hqd_pq_wptr_lo);
3914                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3915                        mqd->cp_hqd_pq_wptr_hi);
3916         }
3917
3918         /* set the pointer to the MQD */
3919         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3920                mqd->cp_mqd_base_addr_lo);
3921         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3922                mqd->cp_mqd_base_addr_hi);
3923
3924         /* set MQD vmid to 0 */
3925         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3926                mqd->cp_mqd_control);
3927
3928         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3929         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3930                mqd->cp_hqd_pq_base_lo);
3931         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3932                mqd->cp_hqd_pq_base_hi);
3933
3934         /* set up the HQD, this is similar to CP_RB0_CNTL */
3935         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3936                mqd->cp_hqd_pq_control);
3937
3938         /* set the wb address whether it's enabled or not */
3939         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3940                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3941         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3942                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3943
3944         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3945         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3946                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3947         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3948                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3949
3950         /* enable the doorbell if requested */
3951         if (ring->use_doorbell) {
3952                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3953                         (adev->doorbell_index.kiq * 2) << 2);
3954                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3955                         (adev->doorbell_index.userqueue_end * 2) << 2);
3956         }
3957
3958         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3959                mqd->cp_hqd_pq_doorbell_control);
3960
3961         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3962         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3963                mqd->cp_hqd_pq_wptr_lo);
3964         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3965                mqd->cp_hqd_pq_wptr_hi);
3966
3967         /* set the vmid for the queue */
3968         WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3969
3970         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3971                mqd->cp_hqd_persistent_state);
3972
3973         /* activate the queue */
3974         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3975                mqd->cp_hqd_active);
3976
3977         if (ring->use_doorbell)
3978                 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3979
3980         return 0;
3981 }
3982
3983 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)
3984 {
3985         struct amdgpu_device *adev = ring->adev;
3986         struct v11_compute_mqd *mqd = ring->mqd_ptr;
3987         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3988
3989         gfx_v11_0_kiq_setting(ring);
3990
3991         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
3992                 /* reset MQD to a clean status */
3993                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3994                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
3995
3996                 /* reset ring buffer */
3997                 ring->wptr = 0;
3998                 amdgpu_ring_clear_ring(ring);
3999
4000                 mutex_lock(&adev->srbm_mutex);
4001                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4002                 gfx_v11_0_kiq_init_register(ring);
4003                 soc21_grbm_select(adev, 0, 0, 0, 0);
4004                 mutex_unlock(&adev->srbm_mutex);
4005         } else {
4006                 memset((void *)mqd, 0, sizeof(*mqd));
4007                 mutex_lock(&adev->srbm_mutex);
4008                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4009                 amdgpu_ring_init_mqd(ring);
4010                 gfx_v11_0_kiq_init_register(ring);
4011                 soc21_grbm_select(adev, 0, 0, 0, 0);
4012                 mutex_unlock(&adev->srbm_mutex);
4013
4014                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4015                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4016         }
4017
4018         return 0;
4019 }
4020
4021 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)
4022 {
4023         struct amdgpu_device *adev = ring->adev;
4024         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4025         int mqd_idx = ring - &adev->gfx.compute_ring[0];
4026
4027         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4028                 memset((void *)mqd, 0, sizeof(*mqd));
4029                 mutex_lock(&adev->srbm_mutex);
4030                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4031                 amdgpu_ring_init_mqd(ring);
4032                 soc21_grbm_select(adev, 0, 0, 0, 0);
4033                 mutex_unlock(&adev->srbm_mutex);
4034
4035                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4036                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4037         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4038                 /* reset MQD to a clean status */
4039                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4040                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4041
4042                 /* reset ring buffer */
4043                 ring->wptr = 0;
4044                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
4045                 amdgpu_ring_clear_ring(ring);
4046         } else {
4047                 amdgpu_ring_clear_ring(ring);
4048         }
4049
4050         return 0;
4051 }
4052
4053 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)
4054 {
4055         struct amdgpu_ring *ring;
4056         int r;
4057
4058         ring = &adev->gfx.kiq.ring;
4059
4060         r = amdgpu_bo_reserve(ring->mqd_obj, false);
4061         if (unlikely(r != 0))
4062                 return r;
4063
4064         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4065         if (unlikely(r != 0)) {
4066                 amdgpu_bo_unreserve(ring->mqd_obj);
4067                 return r;
4068         }
4069
4070         gfx_v11_0_kiq_init_queue(ring);
4071         amdgpu_bo_kunmap(ring->mqd_obj);
4072         ring->mqd_ptr = NULL;
4073         amdgpu_bo_unreserve(ring->mqd_obj);
4074         ring->sched.ready = true;
4075         return 0;
4076 }
4077
4078 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
4079 {
4080         struct amdgpu_ring *ring = NULL;
4081         int r = 0, i;
4082
4083         if (!amdgpu_async_gfx_ring)
4084                 gfx_v11_0_cp_compute_enable(adev, true);
4085
4086         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4087                 ring = &adev->gfx.compute_ring[i];
4088
4089                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4090                 if (unlikely(r != 0))
4091                         goto done;
4092                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4093                 if (!r) {
4094                         r = gfx_v11_0_kcq_init_queue(ring);
4095                         amdgpu_bo_kunmap(ring->mqd_obj);
4096                         ring->mqd_ptr = NULL;
4097                 }
4098                 amdgpu_bo_unreserve(ring->mqd_obj);
4099                 if (r)
4100                         goto done;
4101         }
4102
4103         r = amdgpu_gfx_enable_kcq(adev);
4104 done:
4105         return r;
4106 }
4107
4108 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
4109 {
4110         int r, i;
4111         struct amdgpu_ring *ring;
4112
4113         if (!(adev->flags & AMD_IS_APU))
4114                 gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4115
4116         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4117                 /* legacy firmware loading */
4118                 r = gfx_v11_0_cp_gfx_load_microcode(adev);
4119                 if (r)
4120                         return r;
4121
4122                 if (adev->gfx.rs64_enable)
4123                         r = gfx_v11_0_cp_compute_load_microcode_rs64(adev);
4124                 else
4125                         r = gfx_v11_0_cp_compute_load_microcode(adev);
4126                 if (r)
4127                         return r;
4128         }
4129
4130         gfx_v11_0_cp_set_doorbell_range(adev);
4131
4132         if (amdgpu_async_gfx_ring) {
4133                 gfx_v11_0_cp_compute_enable(adev, true);
4134                 gfx_v11_0_cp_gfx_enable(adev, true);
4135         }
4136
4137         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
4138                 r = amdgpu_mes_kiq_hw_init(adev);
4139         else
4140                 r = gfx_v11_0_kiq_resume(adev);
4141         if (r)
4142                 return r;
4143
4144         r = gfx_v11_0_kcq_resume(adev);
4145         if (r)
4146                 return r;
4147
4148         if (!amdgpu_async_gfx_ring) {
4149                 r = gfx_v11_0_cp_gfx_resume(adev);
4150                 if (r)
4151                         return r;
4152         } else {
4153                 r = gfx_v11_0_cp_async_gfx_ring_resume(adev);
4154                 if (r)
4155                         return r;
4156         }
4157
4158         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4159                 ring = &adev->gfx.gfx_ring[i];
4160                 r = amdgpu_ring_test_helper(ring);
4161                 if (r)
4162                         return r;
4163         }
4164
4165         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4166                 ring = &adev->gfx.compute_ring[i];
4167                 r = amdgpu_ring_test_helper(ring);
4168                 if (r)
4169                         return r;
4170         }
4171
4172         return 0;
4173 }
4174
4175 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)
4176 {
4177         gfx_v11_0_cp_gfx_enable(adev, enable);
4178         gfx_v11_0_cp_compute_enable(adev, enable);
4179 }
4180
4181 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
4182 {
4183         int r;
4184         bool value;
4185
4186         r = adev->gfxhub.funcs->gart_enable(adev);
4187         if (r)
4188                 return r;
4189
4190         adev->hdp.funcs->flush_hdp(adev, NULL);
4191
4192         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
4193                 false : true;
4194
4195         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
4196         amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
4197
4198         return 0;
4199 }
4200
4201 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev)
4202 {
4203         u32 tmp;
4204
4205         /* select RS64 */
4206         if (adev->gfx.rs64_enable) {
4207                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
4208                 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);
4209                 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
4210
4211                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);
4212                 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);
4213                 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);
4214         }
4215
4216         if (amdgpu_emu_mode == 1)
4217                 msleep(100);
4218 }
4219
4220 static int get_gb_addr_config(struct amdgpu_device * adev)
4221 {
4222         u32 gb_addr_config;
4223
4224         gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
4225         if (gb_addr_config == 0)
4226                 return -EINVAL;
4227
4228         adev->gfx.config.gb_addr_config_fields.num_pkrs =
4229                 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4230
4231         adev->gfx.config.gb_addr_config = gb_addr_config;
4232
4233         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4234                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4235                                       GB_ADDR_CONFIG, NUM_PIPES);
4236
4237         adev->gfx.config.max_tile_pipes =
4238                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4239
4240         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4241                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4242                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4243         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4244                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4245                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4246         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4247                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4248                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4249         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4250                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4251                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4252
4253         return 0;
4254 }
4255
4256 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev)
4257 {
4258         uint32_t data;
4259
4260         data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
4261         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
4262         WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
4263
4264         data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
4265         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
4266         WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
4267 }
4268
4269 static int gfx_v11_0_hw_init(void *handle)
4270 {
4271         int r;
4272         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4273
4274         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4275                 if (adev->gfx.imu.funcs) {
4276                         /* RLC autoload sequence 1: Program rlc ram */
4277                         if (adev->gfx.imu.funcs->program_rlc_ram)
4278                                 adev->gfx.imu.funcs->program_rlc_ram(adev);
4279                 }
4280                 /* rlc autoload firmware */
4281                 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);
4282                 if (r)
4283                         return r;
4284         } else {
4285                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4286                         if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
4287                                 if (adev->gfx.imu.funcs->load_microcode)
4288                                         adev->gfx.imu.funcs->load_microcode(adev);
4289                                 if (adev->gfx.imu.funcs->setup_imu)
4290                                         adev->gfx.imu.funcs->setup_imu(adev);
4291                                 if (adev->gfx.imu.funcs->start_imu)
4292                                         adev->gfx.imu.funcs->start_imu(adev);
4293                         }
4294
4295                         /* disable gpa mode in backdoor loading */
4296                         gfx_v11_0_disable_gpa_mode(adev);
4297                 }
4298         }
4299
4300         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
4301             (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
4302                 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev);
4303                 if (r) {
4304                         dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
4305                         return r;
4306                 }
4307         }
4308
4309         adev->gfx.is_poweron = true;
4310
4311         if(get_gb_addr_config(adev))
4312                 DRM_WARN("Invalid gb_addr_config !\n");
4313
4314         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
4315             adev->gfx.rs64_enable)
4316                 gfx_v11_0_config_gfx_rs64(adev);
4317
4318         r = gfx_v11_0_gfxhub_enable(adev);
4319         if (r)
4320                 return r;
4321
4322         if (!amdgpu_emu_mode)
4323                 gfx_v11_0_init_golden_registers(adev);
4324
4325         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
4326             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
4327                 /**
4328                  * For gfx 11, rlc firmware loading relies on smu firmware is
4329                  * loaded firstly, so in direct type, it has to load smc ucode
4330                  * here before rlc.
4331                  */
4332                 if (!(adev->flags & AMD_IS_APU)) {
4333                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
4334                         if (r)
4335                                 return r;
4336                 }
4337         }
4338
4339         gfx_v11_0_constants_init(adev);
4340
4341         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
4342                 gfx_v11_0_select_cp_fw_arch(adev);
4343
4344         if (adev->nbio.funcs->gc_doorbell_init)
4345                 adev->nbio.funcs->gc_doorbell_init(adev);
4346
4347         r = gfx_v11_0_rlc_resume(adev);
4348         if (r)
4349                 return r;
4350
4351         /*
4352          * init golden registers and rlc resume may override some registers,
4353          * reconfig them here
4354          */
4355         gfx_v11_0_tcp_harvest(adev);
4356
4357         r = gfx_v11_0_cp_resume(adev);
4358         if (r)
4359                 return r;
4360
4361         return r;
4362 }
4363
4364 #ifndef BRING_UP_DEBUG
4365 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev)
4366 {
4367         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4368         struct amdgpu_ring *kiq_ring = &kiq->ring;
4369         int i, r = 0;
4370
4371         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4372                 return -EINVAL;
4373
4374         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
4375                                         adev->gfx.num_gfx_rings))
4376                 return -ENOMEM;
4377
4378         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4379                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
4380                                            PREEMPT_QUEUES, 0, 0);
4381
4382         if (adev->gfx.kiq.ring.sched.ready)
4383                 r = amdgpu_ring_test_helper(kiq_ring);
4384
4385         return r;
4386 }
4387 #endif
4388
4389 static int gfx_v11_0_hw_fini(void *handle)
4390 {
4391         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4392         int r;
4393         uint32_t tmp;
4394
4395         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4396         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4397
4398         if (!adev->no_hw_access) {
4399 #ifndef BRING_UP_DEBUG
4400                 if (amdgpu_async_gfx_ring) {
4401                         r = gfx_v11_0_kiq_disable_kgq(adev);
4402                         if (r)
4403                                 DRM_ERROR("KGQ disable failed\n");
4404                 }
4405 #endif
4406                 if (amdgpu_gfx_disable_kcq(adev))
4407                         DRM_ERROR("KCQ disable failed\n");
4408
4409                 amdgpu_mes_kiq_hw_fini(adev);
4410         }
4411
4412         if (amdgpu_sriov_vf(adev)) {
4413                 gfx_v11_0_cp_gfx_enable(adev, false);
4414                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
4415                 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
4416                 tmp &= 0xffffff00;
4417                 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
4418
4419                 return 0;
4420         }
4421         gfx_v11_0_cp_enable(adev, false);
4422         gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4423
4424         adev->gfxhub.funcs->gart_disable(adev);
4425
4426         adev->gfx.is_poweron = false;
4427
4428         return 0;
4429 }
4430
4431 static int gfx_v11_0_suspend(void *handle)
4432 {
4433         return gfx_v11_0_hw_fini(handle);
4434 }
4435
4436 static int gfx_v11_0_resume(void *handle)
4437 {
4438         return gfx_v11_0_hw_init(handle);
4439 }
4440
4441 static bool gfx_v11_0_is_idle(void *handle)
4442 {
4443         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4444
4445         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
4446                                 GRBM_STATUS, GUI_ACTIVE))
4447                 return false;
4448         else
4449                 return true;
4450 }
4451
4452 static int gfx_v11_0_wait_for_idle(void *handle)
4453 {
4454         unsigned i;
4455         u32 tmp;
4456         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4457
4458         for (i = 0; i < adev->usec_timeout; i++) {
4459                 /* read MC_STATUS */
4460                 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
4461                         GRBM_STATUS__GUI_ACTIVE_MASK;
4462
4463                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4464                         return 0;
4465                 udelay(1);
4466         }
4467         return -ETIMEDOUT;
4468 }
4469
4470 static int gfx_v11_0_soft_reset(void *handle)
4471 {
4472         u32 grbm_soft_reset = 0;
4473         u32 tmp;
4474         int i, j, k;
4475         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4476
4477         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4478         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);
4479         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);
4480         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);
4481         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
4482         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4483
4484         gfx_v11_0_set_safe_mode(adev);
4485
4486         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4487                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4488                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4489                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4490                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4491                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4492                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4493                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4494
4495                                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
4496                                 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
4497                         }
4498                 }
4499         }
4500         for (i = 0; i < adev->gfx.me.num_me; ++i) {
4501                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4502                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4503                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4504                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4505                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4506                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4507                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4508
4509                                 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);
4510                         }
4511                 }
4512         }
4513
4514         WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);
4515
4516         // Read CP_VMID_RESET register three times.
4517         // to get sufficient time for GFX_HQD_ACTIVE reach 0
4518         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4519         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4520         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4521
4522         for (i = 0; i < adev->usec_timeout; i++) {
4523                 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
4524                     !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
4525                         break;
4526                 udelay(1);
4527         }
4528         if (i >= adev->usec_timeout) {
4529                 printk("Failed to wait all pipes clean\n");
4530                 return -EINVAL;
4531         }
4532
4533         /**********  trigger soft reset  ***********/
4534         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4535         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4536                                         SOFT_RESET_CP, 1);
4537         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4538                                         SOFT_RESET_GFX, 1);
4539         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4540                                         SOFT_RESET_CPF, 1);
4541         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4542                                         SOFT_RESET_CPC, 1);
4543         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4544                                         SOFT_RESET_CPG, 1);
4545         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4546         /**********  exit soft reset  ***********/
4547         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4548         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4549                                         SOFT_RESET_CP, 0);
4550         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4551                                         SOFT_RESET_GFX, 0);
4552         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4553                                         SOFT_RESET_CPF, 0);
4554         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4555                                         SOFT_RESET_CPC, 0);
4556         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4557                                         SOFT_RESET_CPG, 0);
4558         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4559
4560         tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);
4561         tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);
4562         WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);
4563
4564         WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);
4565         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);
4566
4567         for (i = 0; i < adev->usec_timeout; i++) {
4568                 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))
4569                         break;
4570                 udelay(1);
4571         }
4572         if (i >= adev->usec_timeout) {
4573                 printk("Failed to wait CP_VMID_RESET to 0\n");
4574                 return -EINVAL;
4575         }
4576
4577         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4578         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4579         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4580         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4581         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4582         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4583
4584         gfx_v11_0_unset_safe_mode(adev);
4585
4586         return gfx_v11_0_cp_resume(adev);
4587 }
4588
4589 static bool gfx_v11_0_check_soft_reset(void *handle)
4590 {
4591         int i, r;
4592         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4593         struct amdgpu_ring *ring;
4594         long tmo = msecs_to_jiffies(1000);
4595
4596         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4597                 ring = &adev->gfx.gfx_ring[i];
4598                 r = amdgpu_ring_test_ib(ring, tmo);
4599                 if (r)
4600                         return true;
4601         }
4602
4603         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4604                 ring = &adev->gfx.compute_ring[i];
4605                 r = amdgpu_ring_test_ib(ring, tmo);
4606                 if (r)
4607                         return true;
4608         }
4609
4610         return false;
4611 }
4612
4613 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4614 {
4615         uint64_t clock;
4616
4617         amdgpu_gfx_off_ctrl(adev, false);
4618         mutex_lock(&adev->gfx.gpu_clock_mutex);
4619         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) |
4620                 ((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL);
4621         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4622         amdgpu_gfx_off_ctrl(adev, true);
4623         return clock;
4624 }
4625
4626 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4627                                            uint32_t vmid,
4628                                            uint32_t gds_base, uint32_t gds_size,
4629                                            uint32_t gws_base, uint32_t gws_size,
4630                                            uint32_t oa_base, uint32_t oa_size)
4631 {
4632         struct amdgpu_device *adev = ring->adev;
4633
4634         /* GDS Base */
4635         gfx_v11_0_write_data_to_reg(ring, 0, false,
4636                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
4637                                     gds_base);
4638
4639         /* GDS Size */
4640         gfx_v11_0_write_data_to_reg(ring, 0, false,
4641                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
4642                                     gds_size);
4643
4644         /* GWS */
4645         gfx_v11_0_write_data_to_reg(ring, 0, false,
4646                                     SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
4647                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4648
4649         /* OA */
4650         gfx_v11_0_write_data_to_reg(ring, 0, false,
4651                                     SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
4652                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
4653 }
4654
4655 static int gfx_v11_0_early_init(void *handle)
4656 {
4657         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4658
4659         adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
4660         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4661                                           AMDGPU_MAX_COMPUTE_RINGS);
4662
4663         gfx_v11_0_set_kiq_pm4_funcs(adev);
4664         gfx_v11_0_set_ring_funcs(adev);
4665         gfx_v11_0_set_irq_funcs(adev);
4666         gfx_v11_0_set_gds_init(adev);
4667         gfx_v11_0_set_rlc_funcs(adev);
4668         gfx_v11_0_set_mqd_funcs(adev);
4669         gfx_v11_0_set_imu_funcs(adev);
4670
4671         gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
4672
4673         return 0;
4674 }
4675
4676 static int gfx_v11_0_late_init(void *handle)
4677 {
4678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4679         int r;
4680
4681         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4682         if (r)
4683                 return r;
4684
4685         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4686         if (r)
4687                 return r;
4688
4689         return 0;
4690 }
4691
4692 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
4693 {
4694         uint32_t rlc_cntl;
4695
4696         /* if RLC is not enabled, do nothing */
4697         rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
4698         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4699 }
4700
4701 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev)
4702 {
4703         uint32_t data;
4704         unsigned i;
4705
4706         data = RLC_SAFE_MODE__CMD_MASK;
4707         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4708
4709         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
4710
4711         /* wait for RLC_SAFE_MODE */
4712         for (i = 0; i < adev->usec_timeout; i++) {
4713                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
4714                                    RLC_SAFE_MODE, CMD))
4715                         break;
4716                 udelay(1);
4717         }
4718 }
4719
4720 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev)
4721 {
4722         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
4723 }
4724
4725 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
4726                                       bool enable)
4727 {
4728         uint32_t def, data;
4729
4730         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
4731                 return;
4732
4733         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4734
4735         if (enable)
4736                 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4737         else
4738                 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4739
4740         if (def != data)
4741                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4742 }
4743
4744 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev,
4745                                        bool enable)
4746 {
4747         uint32_t def, data;
4748
4749         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4750                 return;
4751
4752         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4753
4754         if (enable)
4755                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4756         else
4757                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4758
4759         if (def != data)
4760                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4761 }
4762
4763 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
4764                                            bool enable)
4765 {
4766         uint32_t def, data;
4767
4768         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4769                 return;
4770
4771         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4772
4773         if (enable)
4774                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4775         else
4776                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4777
4778         if (def != data)
4779                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4780 }
4781
4782 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4783                                                        bool enable)
4784 {
4785         uint32_t data, def;
4786
4787         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4788                 return;
4789
4790         /* It is disabled by HW by default */
4791         if (enable) {
4792                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4793                         /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4794                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4795
4796                         data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4797                                   RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4798                                   RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4799
4800                         if (def != data)
4801                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4802                 }
4803         } else {
4804                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4805                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4806
4807                         data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4808                                  RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4809                                  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4810
4811                         if (def != data)
4812                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4813                 }
4814         }
4815 }
4816
4817 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4818                                                        bool enable)
4819 {
4820         uint32_t def, data;
4821
4822         if (!(adev->cg_flags &
4823               (AMD_CG_SUPPORT_GFX_CGCG |
4824               AMD_CG_SUPPORT_GFX_CGLS |
4825               AMD_CG_SUPPORT_GFX_3D_CGCG |
4826               AMD_CG_SUPPORT_GFX_3D_CGLS)))
4827                 return;
4828
4829         if (enable) {
4830                 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4831
4832                 /* unset CGCG override */
4833                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4834                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4835                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4836                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4837                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4838                     adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4839                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4840
4841                 /* update CGCG override bits */
4842                 if (def != data)
4843                         WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4844
4845                 /* enable cgcg FSM(0x0000363F) */
4846                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4847
4848                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4849                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4850                         data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4851                                  RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4852                 }
4853
4854                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4855                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4856                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4857                                  RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4858                 }
4859
4860                 if (def != data)
4861                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4862
4863                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4864                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4865
4866                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4867                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4868                         data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4869                                  RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4870                 }
4871
4872                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4873                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4874                         data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4875                                  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4876                 }
4877
4878                 if (def != data)
4879                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4880
4881                 /* set IDLE_POLL_COUNT(0x00900100) */
4882                 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4883
4884                 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4885                 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4886                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4887
4888                 if (def != data)
4889                         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4890
4891                 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4892                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4893                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4894                 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4895                 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4896                 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4897
4898                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4899                 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4900                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4901
4902                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4903                 if (adev->sdma.num_instances > 1) {
4904                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4905                         data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4906                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4907                 }
4908         } else {
4909                 /* Program RLC_CGCG_CGLS_CTRL */
4910                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4911
4912                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4913                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4914
4915                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4916                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4917
4918                 if (def != data)
4919                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4920
4921                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4922                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4923
4924                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4925                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4926                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4927                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4928
4929                 if (def != data)
4930                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4931
4932                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4933                 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4934                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4935
4936                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4937                 if (adev->sdma.num_instances > 1) {
4938                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4939                         data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4940                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4941                 }
4942         }
4943 }
4944
4945 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4946                                             bool enable)
4947 {
4948         amdgpu_gfx_rlc_enter_safe_mode(adev);
4949
4950         gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
4951
4952         gfx_v11_0_update_medium_grain_clock_gating(adev, enable);
4953
4954         gfx_v11_0_update_repeater_fgcg(adev, enable);
4955
4956         gfx_v11_0_update_sram_fgcg(adev, enable);
4957
4958         gfx_v11_0_update_perf_clk(adev, enable);
4959
4960         if (adev->cg_flags &
4961             (AMD_CG_SUPPORT_GFX_MGCG |
4962              AMD_CG_SUPPORT_GFX_CGLS |
4963              AMD_CG_SUPPORT_GFX_CGCG |
4964              AMD_CG_SUPPORT_GFX_3D_CGCG |
4965              AMD_CG_SUPPORT_GFX_3D_CGLS))
4966                 gfx_v11_0_enable_gui_idle_interrupt(adev, enable);
4967
4968         amdgpu_gfx_rlc_exit_safe_mode(adev);
4969
4970         return 0;
4971 }
4972
4973 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
4974 {
4975         u32 reg, data;
4976
4977         amdgpu_gfx_off_ctrl(adev, false);
4978
4979         reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
4980         if (amdgpu_sriov_is_pp_one_vf(adev))
4981                 data = RREG32_NO_KIQ(reg);
4982         else
4983                 data = RREG32(reg);
4984
4985         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
4986         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
4987
4988         if (amdgpu_sriov_is_pp_one_vf(adev))
4989                 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
4990         else
4991                 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
4992
4993         amdgpu_gfx_off_ctrl(adev, true);
4994 }
4995
4996 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
4997         .is_rlc_enabled = gfx_v11_0_is_rlc_enabled,
4998         .set_safe_mode = gfx_v11_0_set_safe_mode,
4999         .unset_safe_mode = gfx_v11_0_unset_safe_mode,
5000         .init = gfx_v11_0_rlc_init,
5001         .get_csb_size = gfx_v11_0_get_csb_size,
5002         .get_csb_buffer = gfx_v11_0_get_csb_buffer,
5003         .resume = gfx_v11_0_rlc_resume,
5004         .stop = gfx_v11_0_rlc_stop,
5005         .reset = gfx_v11_0_rlc_reset,
5006         .start = gfx_v11_0_rlc_start,
5007         .update_spm_vmid = gfx_v11_0_update_spm_vmid,
5008 };
5009
5010 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
5011 {
5012         u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
5013
5014         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5015                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5016         else
5017                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5018
5019         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
5020
5021         // Program RLC_PG_DELAY3 for CGPG hysteresis
5022         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
5023                 switch (adev->ip_versions[GC_HWIP][0]) {
5024                 case IP_VERSION(11, 0, 1):
5025                         WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
5026                         break;
5027                 default:
5028                         break;
5029                 }
5030         }
5031 }
5032
5033 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
5034 {
5035         amdgpu_gfx_rlc_enter_safe_mode(adev);
5036
5037         gfx_v11_cntl_power_gating(adev, enable);
5038
5039         amdgpu_gfx_rlc_exit_safe_mode(adev);
5040 }
5041
5042 static int gfx_v11_0_set_powergating_state(void *handle,
5043                                            enum amd_powergating_state state)
5044 {
5045         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5046         bool enable = (state == AMD_PG_STATE_GATE);
5047
5048         if (amdgpu_sriov_vf(adev))
5049                 return 0;
5050
5051         switch (adev->ip_versions[GC_HWIP][0]) {
5052         case IP_VERSION(11, 0, 0):
5053         case IP_VERSION(11, 0, 2):
5054         case IP_VERSION(11, 0, 3):
5055                 amdgpu_gfx_off_ctrl(adev, enable);
5056                 break;
5057         case IP_VERSION(11, 0, 1):
5058                 gfx_v11_cntl_pg(adev, enable);
5059                 amdgpu_gfx_off_ctrl(adev, enable);
5060                 break;
5061         default:
5062                 break;
5063         }
5064
5065         return 0;
5066 }
5067
5068 static int gfx_v11_0_set_clockgating_state(void *handle,
5069                                           enum amd_clockgating_state state)
5070 {
5071         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5072
5073         if (amdgpu_sriov_vf(adev))
5074                 return 0;
5075
5076         switch (adev->ip_versions[GC_HWIP][0]) {
5077         case IP_VERSION(11, 0, 0):
5078         case IP_VERSION(11, 0, 1):
5079         case IP_VERSION(11, 0, 2):
5080         case IP_VERSION(11, 0, 3):
5081                 gfx_v11_0_update_gfx_clock_gating(adev,
5082                                 state ==  AMD_CG_STATE_GATE);
5083                 break;
5084         default:
5085                 break;
5086         }
5087
5088         return 0;
5089 }
5090
5091 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)
5092 {
5093         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5094         int data;
5095
5096         /* AMD_CG_SUPPORT_GFX_MGCG */
5097         data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5098         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5099                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5100
5101         /* AMD_CG_SUPPORT_REPEATER_FGCG */
5102         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
5103                 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
5104
5105         /* AMD_CG_SUPPORT_GFX_FGCG */
5106         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
5107                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
5108
5109         /* AMD_CG_SUPPORT_GFX_PERF_CLK */
5110         if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
5111                 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
5112
5113         /* AMD_CG_SUPPORT_GFX_CGCG */
5114         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5115         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5116                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5117
5118         /* AMD_CG_SUPPORT_GFX_CGLS */
5119         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5120                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5121
5122         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5123         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5124         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5125                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5126
5127         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5128         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5129                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5130 }
5131
5132 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5133 {
5134         /* gfx11 is 32bit rptr*/
5135         return *(uint32_t *)ring->rptr_cpu_addr;
5136 }
5137
5138 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5139 {
5140         struct amdgpu_device *adev = ring->adev;
5141         u64 wptr;
5142
5143         /* XXX check if swapping is necessary on BE */
5144         if (ring->use_doorbell) {
5145                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5146         } else {
5147                 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
5148                 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
5149         }
5150
5151         return wptr;
5152 }
5153
5154 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5155 {
5156         struct amdgpu_device *adev = ring->adev;
5157         uint32_t *wptr_saved;
5158         uint32_t *is_queue_unmap;
5159         uint64_t aggregated_db_index;
5160         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
5161         uint64_t wptr_tmp;
5162
5163         if (ring->is_mes_queue) {
5164                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
5165                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
5166                                               sizeof(uint32_t));
5167                 aggregated_db_index =
5168                         amdgpu_mes_get_aggregated_doorbell_index(adev,
5169                                                                  ring->hw_prio);
5170
5171                 wptr_tmp = ring->wptr & ring->buf_mask;
5172                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
5173                 *wptr_saved = wptr_tmp;
5174                 /* assume doorbell always being used by mes mapped queue */
5175                 if (*is_queue_unmap) {
5176                         WDOORBELL64(aggregated_db_index, wptr_tmp);
5177                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
5178                 } else {
5179                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
5180
5181                         if (*is_queue_unmap)
5182                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
5183                 }
5184         } else {
5185                 if (ring->use_doorbell) {
5186                         /* XXX check if swapping is necessary on BE */
5187                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5188                                      ring->wptr);
5189                         WDOORBELL64(ring->doorbell_index, ring->wptr);
5190                 } else {
5191                         WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
5192                                      lower_32_bits(ring->wptr));
5193                         WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
5194                                      upper_32_bits(ring->wptr));
5195                 }
5196         }
5197 }
5198
5199 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5200 {
5201         /* gfx11 hardware is 32bit rptr */
5202         return *(uint32_t *)ring->rptr_cpu_addr;
5203 }
5204
5205 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5206 {
5207         u64 wptr;
5208
5209         /* XXX check if swapping is necessary on BE */
5210         if (ring->use_doorbell)
5211                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5212         else
5213                 BUG();
5214         return wptr;
5215 }
5216
5217 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5218 {
5219         struct amdgpu_device *adev = ring->adev;
5220         uint32_t *wptr_saved;
5221         uint32_t *is_queue_unmap;
5222         uint64_t aggregated_db_index;
5223         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
5224         uint64_t wptr_tmp;
5225
5226         if (ring->is_mes_queue) {
5227                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
5228                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
5229                                               sizeof(uint32_t));
5230                 aggregated_db_index =
5231                         amdgpu_mes_get_aggregated_doorbell_index(adev,
5232                                                                  ring->hw_prio);
5233
5234                 wptr_tmp = ring->wptr & ring->buf_mask;
5235                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
5236                 *wptr_saved = wptr_tmp;
5237                 /* assume doorbell always used by mes mapped queue */
5238                 if (*is_queue_unmap) {
5239                         WDOORBELL64(aggregated_db_index, wptr_tmp);
5240                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
5241                 } else {
5242                         WDOORBELL64(ring->doorbell_index, wptr_tmp);
5243
5244                         if (*is_queue_unmap)
5245                                 WDOORBELL64(aggregated_db_index, wptr_tmp);
5246                 }
5247         } else {
5248                 /* XXX check if swapping is necessary on BE */
5249                 if (ring->use_doorbell) {
5250                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5251                                      ring->wptr);
5252                         WDOORBELL64(ring->doorbell_index, ring->wptr);
5253                 } else {
5254                         BUG(); /* only DOORBELL method supported on gfx11 now */
5255                 }
5256         }
5257 }
5258
5259 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5260 {
5261         struct amdgpu_device *adev = ring->adev;
5262         u32 ref_and_mask, reg_mem_engine;
5263         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5264
5265         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5266                 switch (ring->me) {
5267                 case 1:
5268                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5269                         break;
5270                 case 2:
5271                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5272                         break;
5273                 default:
5274                         return;
5275                 }
5276                 reg_mem_engine = 0;
5277         } else {
5278                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5279                 reg_mem_engine = 1; /* pfp */
5280         }
5281
5282         gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5283                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5284                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5285                                ref_and_mask, ref_and_mask, 0x20);
5286 }
5287
5288 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5289                                        struct amdgpu_job *job,
5290                                        struct amdgpu_ib *ib,
5291                                        uint32_t flags)
5292 {
5293         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5294         u32 header, control = 0;
5295
5296         BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
5297
5298         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5299
5300         control |= ib->length_dw | (vmid << 24);
5301
5302         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5303                 control |= INDIRECT_BUFFER_PRE_ENB(1);
5304
5305                 if (flags & AMDGPU_IB_PREEMPTED)
5306                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
5307
5308                 if (vmid)
5309                         gfx_v11_0_ring_emit_de_meta(ring,
5310                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
5311         }
5312
5313         if (ring->is_mes_queue)
5314                 /* inherit vmid from mqd */
5315                 control |= 0x400000;
5316
5317         amdgpu_ring_write(ring, header);
5318         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5319         amdgpu_ring_write(ring,
5320 #ifdef __BIG_ENDIAN
5321                 (2 << 0) |
5322 #endif
5323                 lower_32_bits(ib->gpu_addr));
5324         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5325         amdgpu_ring_write(ring, control);
5326 }
5327
5328 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5329                                            struct amdgpu_job *job,
5330                                            struct amdgpu_ib *ib,
5331                                            uint32_t flags)
5332 {
5333         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5334         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5335
5336         if (ring->is_mes_queue)
5337                 /* inherit vmid from mqd */
5338                 control |= 0x40000000;
5339
5340         /* Currently, there is a high possibility to get wave ID mismatch
5341          * between ME and GDS, leading to a hw deadlock, because ME generates
5342          * different wave IDs than the GDS expects. This situation happens
5343          * randomly when at least 5 compute pipes use GDS ordered append.
5344          * The wave IDs generated by ME are also wrong after suspend/resume.
5345          * Those are probably bugs somewhere else in the kernel driver.
5346          *
5347          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5348          * GDS to 0 for this ring (me/pipe).
5349          */
5350         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5351                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5352                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
5353                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5354         }
5355
5356         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5357         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5358         amdgpu_ring_write(ring,
5359 #ifdef __BIG_ENDIAN
5360                                 (2 << 0) |
5361 #endif
5362                                 lower_32_bits(ib->gpu_addr));
5363         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5364         amdgpu_ring_write(ring, control);
5365 }
5366
5367 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5368                                      u64 seq, unsigned flags)
5369 {
5370         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5371         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5372
5373         /* RELEASE_MEM - flush caches, send int */
5374         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5375         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
5376                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
5377                                  PACKET3_RELEASE_MEM_GCR_GL2_INV |
5378                                  PACKET3_RELEASE_MEM_GCR_GL2_US |
5379                                  PACKET3_RELEASE_MEM_GCR_GL1_INV |
5380                                  PACKET3_RELEASE_MEM_GCR_GLV_INV |
5381                                  PACKET3_RELEASE_MEM_GCR_GLM_INV |
5382                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
5383                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
5384                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5385                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
5386         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
5387                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
5388
5389         /*
5390          * the address should be Qword aligned if 64bit write, Dword
5391          * aligned if only send 32bit data low (discard data high)
5392          */
5393         if (write64bit)
5394                 BUG_ON(addr & 0x7);
5395         else
5396                 BUG_ON(addr & 0x3);
5397         amdgpu_ring_write(ring, lower_32_bits(addr));
5398         amdgpu_ring_write(ring, upper_32_bits(addr));
5399         amdgpu_ring_write(ring, lower_32_bits(seq));
5400         amdgpu_ring_write(ring, upper_32_bits(seq));
5401         amdgpu_ring_write(ring, ring->is_mes_queue ?
5402                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
5403 }
5404
5405 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5406 {
5407         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5408         uint32_t seq = ring->fence_drv.sync_seq;
5409         uint64_t addr = ring->fence_drv.gpu_addr;
5410
5411         gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
5412                                upper_32_bits(addr), seq, 0xffffffff, 4);
5413 }
5414
5415 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
5416                                    uint16_t pasid, uint32_t flush_type,
5417                                    bool all_hub, uint8_t dst_sel)
5418 {
5419         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
5420         amdgpu_ring_write(ring,
5421                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
5422                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
5423                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
5424                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
5425 }
5426
5427 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5428                                          unsigned vmid, uint64_t pd_addr)
5429 {
5430         if (ring->is_mes_queue)
5431                 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
5432         else
5433                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5434
5435         /* compute doesn't have PFP */
5436         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5437                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5438                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5439                 amdgpu_ring_write(ring, 0x0);
5440         }
5441 }
5442
5443 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5444                                           u64 seq, unsigned int flags)
5445 {
5446         struct amdgpu_device *adev = ring->adev;
5447
5448         /* we only allocate 32bit for each seq wb address */
5449         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5450
5451         /* write fence seq to the "addr" */
5452         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5453         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5454                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5455         amdgpu_ring_write(ring, lower_32_bits(addr));
5456         amdgpu_ring_write(ring, upper_32_bits(addr));
5457         amdgpu_ring_write(ring, lower_32_bits(seq));
5458
5459         if (flags & AMDGPU_FENCE_FLAG_INT) {
5460                 /* set register to trigger INT */
5461                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5462                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5463                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5464                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
5465                 amdgpu_ring_write(ring, 0);
5466                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5467         }
5468 }
5469
5470 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
5471                                          uint32_t flags)
5472 {
5473         uint32_t dw2 = 0;
5474
5475         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5476         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5477                 /* set load_global_config & load_global_uconfig */
5478                 dw2 |= 0x8001;
5479                 /* set load_cs_sh_regs */
5480                 dw2 |= 0x01000000;
5481                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5482                 dw2 |= 0x10002;
5483         }
5484
5485         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5486         amdgpu_ring_write(ring, dw2);
5487         amdgpu_ring_write(ring, 0);
5488 }
5489
5490 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5491 {
5492         unsigned ret;
5493
5494         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5495         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5496         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5497         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5498         ret = ring->wptr & ring->buf_mask;
5499         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5500
5501         return ret;
5502 }
5503
5504 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5505 {
5506         unsigned cur;
5507         BUG_ON(offset > ring->buf_mask);
5508         BUG_ON(ring->ring[offset] != 0x55aa55aa);
5509
5510         cur = (ring->wptr - 1) & ring->buf_mask;
5511         if (likely(cur > offset))
5512                 ring->ring[offset] = cur - offset;
5513         else
5514                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
5515 }
5516
5517 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
5518 {
5519         int i, r = 0;
5520         struct amdgpu_device *adev = ring->adev;
5521         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
5522         struct amdgpu_ring *kiq_ring = &kiq->ring;
5523         unsigned long flags;
5524
5525         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
5526                 return -EINVAL;
5527
5528         spin_lock_irqsave(&kiq->ring_lock, flags);
5529
5530         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
5531                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
5532                 return -ENOMEM;
5533         }
5534
5535         /* assert preemption condition */
5536         amdgpu_ring_set_preempt_cond_exec(ring, false);
5537
5538         /* assert IB preemption, emit the trailing fence */
5539         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
5540                                    ring->trail_fence_gpu_addr,
5541                                    ++ring->trail_seq);
5542         amdgpu_ring_commit(kiq_ring);
5543
5544         spin_unlock_irqrestore(&kiq->ring_lock, flags);
5545
5546         /* poll the trailing fence */
5547         for (i = 0; i < adev->usec_timeout; i++) {
5548                 if (ring->trail_seq ==
5549                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
5550                         break;
5551                 udelay(1);
5552         }
5553
5554         if (i >= adev->usec_timeout) {
5555                 r = -EINVAL;
5556                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
5557         }
5558
5559         /* deassert preemption condition */
5560         amdgpu_ring_set_preempt_cond_exec(ring, true);
5561         return r;
5562 }
5563
5564 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
5565 {
5566         struct amdgpu_device *adev = ring->adev;
5567         struct v10_de_ib_state de_payload = {0};
5568         uint64_t offset, gds_addr, de_payload_gpu_addr;
5569         void *de_payload_cpu_addr;
5570         int cnt;
5571
5572         if (ring->is_mes_queue) {
5573                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5574                                   gfx[0].gfx_meta_data) +
5575                         offsetof(struct v10_gfx_meta_data, de_payload);
5576                 de_payload_gpu_addr =
5577                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5578                 de_payload_cpu_addr =
5579                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5580
5581                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5582                                   gfx[0].gds_backup) +
5583                         offsetof(struct v10_gfx_meta_data, de_payload);
5584                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5585         } else {
5586                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
5587                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5588                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
5589
5590                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
5591                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
5592                                  PAGE_SIZE);
5593         }
5594
5595         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5596         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5597
5598         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5599         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5600         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5601                                  WRITE_DATA_DST_SEL(8) |
5602                                  WR_CONFIRM) |
5603                                  WRITE_DATA_CACHE_POLICY(0));
5604         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
5605         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
5606
5607         if (resume)
5608                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
5609                                            sizeof(de_payload) >> 2);
5610         else
5611                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
5612                                            sizeof(de_payload) >> 2);
5613 }
5614
5615 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
5616                                     bool secure)
5617 {
5618         uint32_t v = secure ? FRAME_TMZ : 0;
5619
5620         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5621         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
5622 }
5623
5624 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5625                                      uint32_t reg_val_offs)
5626 {
5627         struct amdgpu_device *adev = ring->adev;
5628
5629         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5630         amdgpu_ring_write(ring, 0 |     /* src: register*/
5631                                 (5 << 8) |      /* dst: memory */
5632                                 (1 << 20));     /* write confirm */
5633         amdgpu_ring_write(ring, reg);
5634         amdgpu_ring_write(ring, 0);
5635         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5636                                 reg_val_offs * 4));
5637         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5638                                 reg_val_offs * 4));
5639 }
5640
5641 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5642                                    uint32_t val)
5643 {
5644         uint32_t cmd = 0;
5645
5646         switch (ring->funcs->type) {
5647         case AMDGPU_RING_TYPE_GFX:
5648                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5649                 break;
5650         case AMDGPU_RING_TYPE_KIQ:
5651                 cmd = (1 << 16); /* no inc addr */
5652                 break;
5653         default:
5654                 cmd = WR_CONFIRM;
5655                 break;
5656         }
5657         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5658         amdgpu_ring_write(ring, cmd);
5659         amdgpu_ring_write(ring, reg);
5660         amdgpu_ring_write(ring, 0);
5661         amdgpu_ring_write(ring, val);
5662 }
5663
5664 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5665                                         uint32_t val, uint32_t mask)
5666 {
5667         gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5668 }
5669
5670 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5671                                                    uint32_t reg0, uint32_t reg1,
5672                                                    uint32_t ref, uint32_t mask)
5673 {
5674         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5675
5676         gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5677                                ref, mask, 0x20);
5678 }
5679
5680 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,
5681                                          unsigned vmid)
5682 {
5683         struct amdgpu_device *adev = ring->adev;
5684         uint32_t value = 0;
5685
5686         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5687         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5688         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5689         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5690         WREG32_SOC15(GC, 0, regSQ_CMD, value);
5691 }
5692
5693 static void
5694 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5695                                       uint32_t me, uint32_t pipe,
5696                                       enum amdgpu_interrupt_state state)
5697 {
5698         uint32_t cp_int_cntl, cp_int_cntl_reg;
5699
5700         if (!me) {
5701                 switch (pipe) {
5702                 case 0:
5703                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
5704                         break;
5705                 case 1:
5706                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
5707                         break;
5708                 default:
5709                         DRM_DEBUG("invalid pipe %d\n", pipe);
5710                         return;
5711                 }
5712         } else {
5713                 DRM_DEBUG("invalid me %d\n", me);
5714                 return;
5715         }
5716
5717         switch (state) {
5718         case AMDGPU_IRQ_STATE_DISABLE:
5719                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5720                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5721                                             TIME_STAMP_INT_ENABLE, 0);
5722                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5723                                             GENERIC0_INT_ENABLE, 0);
5724                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5725                 break;
5726         case AMDGPU_IRQ_STATE_ENABLE:
5727                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5728                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5729                                             TIME_STAMP_INT_ENABLE, 1);
5730                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5731                                             GENERIC0_INT_ENABLE, 1);
5732                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5733                 break;
5734         default:
5735                 break;
5736         }
5737 }
5738
5739 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5740                                                      int me, int pipe,
5741                                                      enum amdgpu_interrupt_state state)
5742 {
5743         u32 mec_int_cntl, mec_int_cntl_reg;
5744
5745         /*
5746          * amdgpu controls only the first MEC. That's why this function only
5747          * handles the setting of interrupts for this specific MEC. All other
5748          * pipes' interrupts are set by amdkfd.
5749          */
5750
5751         if (me == 1) {
5752                 switch (pipe) {
5753                 case 0:
5754                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5755                         break;
5756                 case 1:
5757                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
5758                         break;
5759                 case 2:
5760                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
5761                         break;
5762                 case 3:
5763                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
5764                         break;
5765                 default:
5766                         DRM_DEBUG("invalid pipe %d\n", pipe);
5767                         return;
5768                 }
5769         } else {
5770                 DRM_DEBUG("invalid me %d\n", me);
5771                 return;
5772         }
5773
5774         switch (state) {
5775         case AMDGPU_IRQ_STATE_DISABLE:
5776                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5777                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5778                                              TIME_STAMP_INT_ENABLE, 0);
5779                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5780                                              GENERIC0_INT_ENABLE, 0);
5781                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5782                 break;
5783         case AMDGPU_IRQ_STATE_ENABLE:
5784                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5785                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5786                                              TIME_STAMP_INT_ENABLE, 1);
5787                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5788                                              GENERIC0_INT_ENABLE, 1);
5789                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5790                 break;
5791         default:
5792                 break;
5793         }
5794 }
5795
5796 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5797                                             struct amdgpu_irq_src *src,
5798                                             unsigned type,
5799                                             enum amdgpu_interrupt_state state)
5800 {
5801         switch (type) {
5802         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5803                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
5804                 break;
5805         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
5806                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
5807                 break;
5808         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5809                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5810                 break;
5811         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5812                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5813                 break;
5814         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5815                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5816                 break;
5817         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5818                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5819                 break;
5820         default:
5821                 break;
5822         }
5823         return 0;
5824 }
5825
5826 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,
5827                              struct amdgpu_irq_src *source,
5828                              struct amdgpu_iv_entry *entry)
5829 {
5830         int i;
5831         u8 me_id, pipe_id, queue_id;
5832         struct amdgpu_ring *ring;
5833         uint32_t mes_queue_id = entry->src_data[0];
5834
5835         DRM_DEBUG("IH: CP EOP\n");
5836
5837         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
5838                 struct amdgpu_mes_queue *queue;
5839
5840                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
5841
5842                 spin_lock(&adev->mes.queue_id_lock);
5843                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
5844                 if (queue) {
5845                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
5846                         amdgpu_fence_process(queue->ring);
5847                 }
5848                 spin_unlock(&adev->mes.queue_id_lock);
5849         } else {
5850                 me_id = (entry->ring_id & 0x0c) >> 2;
5851                 pipe_id = (entry->ring_id & 0x03) >> 0;
5852                 queue_id = (entry->ring_id & 0x70) >> 4;
5853
5854                 switch (me_id) {
5855                 case 0:
5856                         if (pipe_id == 0)
5857                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5858                         else
5859                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
5860                         break;
5861                 case 1:
5862                 case 2:
5863                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5864                                 ring = &adev->gfx.compute_ring[i];
5865                                 /* Per-queue interrupt is supported for MEC starting from VI.
5866                                  * The interrupt can only be enabled/disabled per pipe instead
5867                                  * of per queue.
5868                                  */
5869                                 if ((ring->me == me_id) &&
5870                                     (ring->pipe == pipe_id) &&
5871                                     (ring->queue == queue_id))
5872                                         amdgpu_fence_process(ring);
5873                         }
5874                         break;
5875                 }
5876         }
5877
5878         return 0;
5879 }
5880
5881 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5882                                               struct amdgpu_irq_src *source,
5883                                               unsigned type,
5884                                               enum amdgpu_interrupt_state state)
5885 {
5886         switch (state) {
5887         case AMDGPU_IRQ_STATE_DISABLE:
5888         case AMDGPU_IRQ_STATE_ENABLE:
5889                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5890                                PRIV_REG_INT_ENABLE,
5891                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5892                 break;
5893         default:
5894                 break;
5895         }
5896
5897         return 0;
5898 }
5899
5900 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5901                                                struct amdgpu_irq_src *source,
5902                                                unsigned type,
5903                                                enum amdgpu_interrupt_state state)
5904 {
5905         switch (state) {
5906         case AMDGPU_IRQ_STATE_DISABLE:
5907         case AMDGPU_IRQ_STATE_ENABLE:
5908                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5909                                PRIV_INSTR_INT_ENABLE,
5910                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5911                 break;
5912         default:
5913                 break;
5914         }
5915
5916         return 0;
5917 }
5918
5919 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
5920                                         struct amdgpu_iv_entry *entry)
5921 {
5922         u8 me_id, pipe_id, queue_id;
5923         struct amdgpu_ring *ring;
5924         int i;
5925
5926         me_id = (entry->ring_id & 0x0c) >> 2;
5927         pipe_id = (entry->ring_id & 0x03) >> 0;
5928         queue_id = (entry->ring_id & 0x70) >> 4;
5929
5930         switch (me_id) {
5931         case 0:
5932                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5933                         ring = &adev->gfx.gfx_ring[i];
5934                         /* we only enabled 1 gfx queue per pipe for now */
5935                         if (ring->me == me_id && ring->pipe == pipe_id)
5936                                 drm_sched_fault(&ring->sched);
5937                 }
5938                 break;
5939         case 1:
5940         case 2:
5941                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5942                         ring = &adev->gfx.compute_ring[i];
5943                         if (ring->me == me_id && ring->pipe == pipe_id &&
5944                             ring->queue == queue_id)
5945                                 drm_sched_fault(&ring->sched);
5946                 }
5947                 break;
5948         default:
5949                 BUG();
5950                 break;
5951         }
5952 }
5953
5954 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,
5955                                   struct amdgpu_irq_src *source,
5956                                   struct amdgpu_iv_entry *entry)
5957 {
5958         DRM_ERROR("Illegal register access in command stream\n");
5959         gfx_v11_0_handle_priv_fault(adev, entry);
5960         return 0;
5961 }
5962
5963 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,
5964                                    struct amdgpu_irq_src *source,
5965                                    struct amdgpu_iv_entry *entry)
5966 {
5967         DRM_ERROR("Illegal instruction in command stream\n");
5968         gfx_v11_0_handle_priv_fault(adev, entry);
5969         return 0;
5970 }
5971
5972 #if 0
5973 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5974                                              struct amdgpu_irq_src *src,
5975                                              unsigned int type,
5976                                              enum amdgpu_interrupt_state state)
5977 {
5978         uint32_t tmp, target;
5979         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
5980
5981         target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5982         target += ring->pipe;
5983
5984         switch (type) {
5985         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
5986                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
5987                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
5988                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5989                                             GENERIC2_INT_ENABLE, 0);
5990                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
5991
5992                         tmp = RREG32_SOC15_IP(GC, target);
5993                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
5994                                             GENERIC2_INT_ENABLE, 0);
5995                         WREG32_SOC15_IP(GC, target, tmp);
5996                 } else {
5997                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
5998                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
5999                                             GENERIC2_INT_ENABLE, 1);
6000                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6001
6002                         tmp = RREG32_SOC15_IP(GC, target);
6003                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6004                                             GENERIC2_INT_ENABLE, 1);
6005                         WREG32_SOC15_IP(GC, target, tmp);
6006                 }
6007                 break;
6008         default:
6009                 BUG(); /* kiq only support GENERIC2_INT now */
6010                 break;
6011         }
6012         return 0;
6013 }
6014 #endif
6015
6016 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
6017 {
6018         const unsigned int gcr_cntl =
6019                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
6020                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
6021                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
6022                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
6023                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
6024                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
6025                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
6026                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
6027
6028         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
6029         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
6030         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
6031         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
6032         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
6033         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6034         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
6035         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6036         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
6037 }
6038
6039 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
6040         .name = "gfx_v11_0",
6041         .early_init = gfx_v11_0_early_init,
6042         .late_init = gfx_v11_0_late_init,
6043         .sw_init = gfx_v11_0_sw_init,
6044         .sw_fini = gfx_v11_0_sw_fini,
6045         .hw_init = gfx_v11_0_hw_init,
6046         .hw_fini = gfx_v11_0_hw_fini,
6047         .suspend = gfx_v11_0_suspend,
6048         .resume = gfx_v11_0_resume,
6049         .is_idle = gfx_v11_0_is_idle,
6050         .wait_for_idle = gfx_v11_0_wait_for_idle,
6051         .soft_reset = gfx_v11_0_soft_reset,
6052         .check_soft_reset = gfx_v11_0_check_soft_reset,
6053         .set_clockgating_state = gfx_v11_0_set_clockgating_state,
6054         .set_powergating_state = gfx_v11_0_set_powergating_state,
6055         .get_clockgating_state = gfx_v11_0_get_clockgating_state,
6056 };
6057
6058 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
6059         .type = AMDGPU_RING_TYPE_GFX,
6060         .align_mask = 0xff,
6061         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6062         .support_64bit_ptrs = true,
6063         .vmhub = AMDGPU_GFXHUB_0,
6064         .get_rptr = gfx_v11_0_ring_get_rptr_gfx,
6065         .get_wptr = gfx_v11_0_ring_get_wptr_gfx,
6066         .set_wptr = gfx_v11_0_ring_set_wptr_gfx,
6067         .emit_frame_size = /* totally 242 maximum if 16 IBs */
6068                 5 + /* COND_EXEC */
6069                 7 + /* PIPELINE_SYNC */
6070                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6071                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6072                 2 + /* VM_FLUSH */
6073                 8 + /* FENCE for VM_FLUSH */
6074                 20 + /* GDS switch */
6075                 5 + /* COND_EXEC */
6076                 7 + /* HDP_flush */
6077                 4 + /* VGT_flush */
6078                 31 + /* DE_META */
6079                 3 + /* CNTX_CTRL */
6080                 5 + /* HDP_INVL */
6081                 8 + 8 + /* FENCE x2 */
6082                 8, /* gfx_v11_0_emit_mem_sync */
6083         .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */
6084         .emit_ib = gfx_v11_0_ring_emit_ib_gfx,
6085         .emit_fence = gfx_v11_0_ring_emit_fence,
6086         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6087         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6088         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6089         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6090         .test_ring = gfx_v11_0_ring_test_ring,
6091         .test_ib = gfx_v11_0_ring_test_ib,
6092         .insert_nop = amdgpu_ring_insert_nop,
6093         .pad_ib = amdgpu_ring_generic_pad_ib,
6094         .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
6095         .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
6096         .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,
6097         .preempt_ib = gfx_v11_0_ring_preempt_ib,
6098         .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
6099         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6100         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6101         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6102         .soft_recovery = gfx_v11_0_ring_soft_recovery,
6103         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6104 };
6105
6106 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
6107         .type = AMDGPU_RING_TYPE_COMPUTE,
6108         .align_mask = 0xff,
6109         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6110         .support_64bit_ptrs = true,
6111         .vmhub = AMDGPU_GFXHUB_0,
6112         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6113         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6114         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6115         .emit_frame_size =
6116                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6117                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6118                 5 + /* hdp invalidate */
6119                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6120                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6121                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6122                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6123                 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
6124                 8, /* gfx_v11_0_emit_mem_sync */
6125         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6126         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6127         .emit_fence = gfx_v11_0_ring_emit_fence,
6128         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6129         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6130         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6131         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6132         .test_ring = gfx_v11_0_ring_test_ring,
6133         .test_ib = gfx_v11_0_ring_test_ib,
6134         .insert_nop = amdgpu_ring_insert_nop,
6135         .pad_ib = amdgpu_ring_generic_pad_ib,
6136         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6137         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6138         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6139         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6140 };
6141
6142 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
6143         .type = AMDGPU_RING_TYPE_KIQ,
6144         .align_mask = 0xff,
6145         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6146         .support_64bit_ptrs = true,
6147         .vmhub = AMDGPU_GFXHUB_0,
6148         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6149         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6150         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6151         .emit_frame_size =
6152                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6153                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6154                 5 + /*hdp invalidate */
6155                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6156                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6157                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6158                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6159                 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6160         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6161         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6162         .emit_fence = gfx_v11_0_ring_emit_fence_kiq,
6163         .test_ring = gfx_v11_0_ring_test_ring,
6164         .test_ib = gfx_v11_0_ring_test_ib,
6165         .insert_nop = amdgpu_ring_insert_nop,
6166         .pad_ib = amdgpu_ring_generic_pad_ib,
6167         .emit_rreg = gfx_v11_0_ring_emit_rreg,
6168         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6169         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6170         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6171 };
6172
6173 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)
6174 {
6175         int i;
6176
6177         adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq;
6178
6179         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6180                 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
6181
6182         for (i = 0; i < adev->gfx.num_compute_rings; i++)
6183                 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;
6184 }
6185
6186 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = {
6187         .set = gfx_v11_0_set_eop_interrupt_state,
6188         .process = gfx_v11_0_eop_irq,
6189 };
6190
6191 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {
6192         .set = gfx_v11_0_set_priv_reg_fault_state,
6193         .process = gfx_v11_0_priv_reg_irq,
6194 };
6195
6196 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
6197         .set = gfx_v11_0_set_priv_inst_fault_state,
6198         .process = gfx_v11_0_priv_inst_irq,
6199 };
6200
6201 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
6202 {
6203         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6204         adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;
6205
6206         adev->gfx.priv_reg_irq.num_types = 1;
6207         adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;
6208
6209         adev->gfx.priv_inst_irq.num_types = 1;
6210         adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
6211 }
6212
6213 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
6214 {
6215         if (adev->flags & AMD_IS_APU)
6216                 adev->gfx.imu.mode = MISSION_MODE;
6217         else
6218                 adev->gfx.imu.mode = DEBUG_MODE;
6219
6220         adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
6221 }
6222
6223 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev)
6224 {
6225         adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;
6226 }
6227
6228 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev)
6229 {
6230         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
6231                             adev->gfx.config.max_sh_per_se *
6232                             adev->gfx.config.max_shader_engines;
6233
6234         adev->gds.gds_size = 0x1000;
6235         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
6236         adev->gds.gws_size = 64;
6237         adev->gds.oa_size = 16;
6238 }
6239
6240 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev)
6241 {
6242         /* set gfx eng mqd */
6243         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
6244                 sizeof(struct v11_gfx_mqd);
6245         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
6246                 gfx_v11_0_gfx_mqd_init;
6247         /* set compute eng mqd */
6248         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
6249                 sizeof(struct v11_compute_mqd);
6250         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
6251                 gfx_v11_0_compute_mqd_init;
6252 }
6253
6254 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
6255                                                           u32 bitmap)
6256 {
6257         u32 data;
6258
6259         if (!bitmap)
6260                 return;
6261
6262         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6263         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6264
6265         WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
6266 }
6267
6268 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
6269 {
6270         u32 data, wgp_bitmask;
6271         data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
6272         data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
6273
6274         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6275         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6276
6277         wgp_bitmask =
6278                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
6279
6280         return (~data) & wgp_bitmask;
6281 }
6282
6283 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
6284 {
6285         u32 wgp_idx, wgp_active_bitmap;
6286         u32 cu_bitmap_per_wgp, cu_active_bitmap;
6287
6288         wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev);
6289         cu_active_bitmap = 0;
6290
6291         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
6292                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
6293                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
6294                 if (wgp_active_bitmap & (1 << wgp_idx))
6295                         cu_active_bitmap |= cu_bitmap_per_wgp;
6296         }
6297
6298         return cu_active_bitmap;
6299 }
6300
6301 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
6302                                  struct amdgpu_cu_info *cu_info)
6303 {
6304         int i, j, k, counter, active_cu_number = 0;
6305         u32 mask, bitmap;
6306         unsigned disable_masks[8 * 2];
6307
6308         if (!adev || !cu_info)
6309                 return -EINVAL;
6310
6311         amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
6312
6313         mutex_lock(&adev->grbm_idx_mutex);
6314         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6315                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6316                         mask = 1;
6317                         counter = 0;
6318                         gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff);
6319                         if (i < 8 && j < 2)
6320                                 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(
6321                                         adev, disable_masks[i * 2 + j]);
6322                         bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev);
6323
6324                         /**
6325                          * GFX11 could support more than 4 SEs, while the bitmap
6326                          * in cu_info struct is 4x4 and ioctl interface struct
6327                          * drm_amdgpu_info_device should keep stable.
6328                          * So we use last two columns of bitmap to store cu mask for
6329                          * SEs 4 to 7, the layout of the bitmap is as below:
6330                          *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
6331                          *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
6332                          *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
6333                          *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
6334                          *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
6335                          *    SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
6336                          *    SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
6337                          *    SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
6338                          */
6339                         cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap;
6340
6341                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
6342                                 if (bitmap & mask)
6343                                         counter++;
6344
6345                                 mask <<= 1;
6346                         }
6347                         active_cu_number += counter;
6348                 }
6349         }
6350         gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6351         mutex_unlock(&adev->grbm_idx_mutex);
6352
6353         cu_info->number = active_cu_number;
6354         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
6355
6356         return 0;
6357 }
6358
6359 const struct amdgpu_ip_block_version gfx_v11_0_ip_block =
6360 {
6361         .type = AMD_IP_BLOCK_TYPE_GFX,
6362         .major = 11,
6363         .minor = 0,
6364         .rev = 0,
6365         .funcs = &gfx_v11_0_ip_funcs,
6366 };